Controller, power factor correction circuit, electronic apparatus, and offset setting method

Abstract

To provide a controller in which total harmonic distortion (THD) can be improved.SOLUTION: A controller (700) includes: a first external terminal receiving a first voltage (Vmult) with a full-wave rectified waveform; a second external terminal receiving a first detection voltage (Vis), as a negative voltage, generated by a current flowing through a sense resistor (Ris) connected to a ground potential application terminal; an error amplifier circuit (710) generating a second voltage (V2) by amplifying an error between a second detection voltage (Vs) corresponding to an output voltage (Vdc) and a reference voltage (Vref1); an arithmetic circuit (733) generating a third voltage (V4) by multiplying the first and second voltages; an inverting amplifier (734) generating a fourth voltage (V5) by inverting and amplifying the first detection voltage; and a comparator (735) comparing the third voltage and the fourth voltage.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to a control device. [Background technology]

[0002] A power factor correction circuit brings the power factor close to 1 (that is, 100%) by matching the phases of an AC input voltage and an AC input current (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-60692

[0004] [overview] The power factor correction circuit is required to improve total harmonic distortion (THD).

[0005] In view of the above circumstances, an object of the present disclosure is to provide a control device that can improve THD.

[0006] One aspect of the present disclosure is a control device configured to control a power factor correction circuit having a DC / DC converter, comprising: a first external terminal configured to receive a first voltage having a full-wave rectified waveform; a second external terminal configured to receive a first detection voltage as a negative voltage generated by a current flowing through a sense resistor connected to an application terminal of the ground potential in the power factor correction circuit; an error amplifier circuit configured to amplify an error between a second detection voltage corresponding to an output voltage of the DC / DC converter and a reference voltage, and generate a second voltage; an operational circuit configured to generate a third voltage by multiplying the first voltage and the second voltage; an inverting amplifier configured to invert and amplify the first detection voltage to generate a fourth voltage; a comparator configured to compare the third voltage with the fourth voltage; The power factor correction circuit is configured to drive a switching element in the power factor correction circuit on and off, and to turn off the switching element every time the fourth voltage becomes higher than the third voltage, depending on the output of the comparator. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a circuit diagram showing an example of the configuration of an electronic device. [Figure 2] FIG. 2 is a circuit diagram showing the configuration of a PFC circuit according to a first comparative example. [Figure 3] FIG. 3 is a diagram illustrating an example of an offset voltage generating circuit. [Figure 4] FIG. 4 is a diagram illustrating an example of the first arithmetic circuit. [Figure 5] FIG. 5 is a diagram illustrating an example of the first conversion circuit. [Figure 6] FIG. 6 is a diagram illustrating an example of the second conversion circuit. [Figure 7] FIG. 7 is a diagram illustrating an example of the second arithmetic circuit. [Figure 8] FIG. 8 is a diagram showing an example of waveforms of an AC voltage and an input current. [Figure 9] FIG. 9 is a diagram showing the configuration of a PFC circuit according to a second comparative example. [Figure 10] FIG. 10 is a timing chart showing an example of the operation of the PFC circuit according to the second comparative example. [Figure 11] FIG. 11 is a diagram illustrating a configuration of a PFC circuit according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a timing chart illustrating an example of the operation of the PFC circuit according to an embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram for explaining the offset difference ΔV. [Figure 14] FIG. 14 is a diagram showing a specific example of the configuration of the arithmetic circuit and the inverting amplifier. [Figure 15] FIG. 15 is a diagram showing a configuration related to a process for setting the offset difference ΔV. [Figure 16] FIG. 16 is a timing chart showing an example of measuring the offset voltage V5_offset. [Figure 17] FIG. 17 is a diagram showing a configuration for measuring the offset voltage Voffset. [Figure 18] FIG. 18 is a diagram illustrating a specific configuration example of the offset generating unit.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <Electronic equipment> Fig. 1 is a circuit diagram showing an example configuration of an electronic device. Examples of the electronic device 1 shown in Fig. 1 include home appliances such as televisions, refrigerators, and air conditioners, as well as computers. The electronic device 1 includes a fuse 2, a capacitor 3, a filter 4, a rectifier circuit 5, a capacitor 6, and a power factor correction (PFC) circuit 7. The electronic device 1 further includes a DC / DC converter 8, a microcomputer 9, and a signal processing circuit 10. The electronic device 1 is divided into a primary side and a secondary side that are insulated from each other, with an isolation transformer (not shown) of the DC / DC converter 8 as the boundary.

[0010] The rectifier circuit 5 is, for example, a diode bridge. An AC voltage Vac, such as a commercial AC voltage, is supplied to the rectifier circuit 5 via a fuse 2, a capacitor 3, and a filter 4. The rectifier circuit 5 full-wave rectifies the AC voltage Vac to generate a first voltage Vh. Therefore, the first voltage Vh has a full-wave rectified waveform.

[0011] The first voltage Vh is supplied to the PFC circuit 7 via the capacitor 6. The PFC circuit 7 has a boost-type DC / DC converter (switching regulator) that generates the output voltage Vdc from the first voltage Vh. The PFC circuit 7 improves the power factor by making the phases of the first voltage Vh and the input current Iac substantially coincide.

[0012] The DC / DC converter 8 receives the output voltage Vdc of the PFC circuit 7, steps it down, and supplies it to the microcomputer 9 and the signal processing circuit 10, which are loads.

[0013] The microcomputer 9 integrally controls the entire electronic device 1. The signal processing circuit 10 is a block that performs specific signal processing, and examples thereof include an interface circuit that communicates with an external device, an image processing circuit, and an audio processing circuit. In the actual electronic device 1, it is needless to say that a plurality of signal processing circuits 10 are provided according to the functions thereof.

[0014] The above is the description of the configuration of the electronic device 1. Thus, AC / DC conversion is performed by an electronic device including a rectifier circuit 5 that full-wave rectifies the AC voltage Vac and a PFC circuit 7 that boosts the first voltage Vh after full-wave rectification to generate the output voltage Vdc. Next, the details of the PFC circuit 7 mounted on the electronic device 1 will be described. In the comparative examples described later, for convenience, the symbol "7" of the PFC circuit will be appended with "A" or "B".

[0015] <First Comparative Example> <<PFC Circuit (Positive Voltage Control Type)>> Here, before describing the embodiments of the present disclosure, a comparative example as a comparison will be described. This will make the problems to be solved clearer. FIG. 2 is a circuit diagram showing the configuration of the PFC circuit 7A according to the first comparative example. The PFC circuit 7A has a boost-type DC / DC converter (switching regulator) as described above. Note that, unlike this embodiment, the PFC circuit 7A may have a DC / DC converter other than the boost type. The PFC circuit 7A having the configuration shown in FIG. 2 is a positive voltage control type PFC circuit as will be described later.

[0016] The PFC circuit 7A includes a control device 700A, resistors R1 to R9, capacitors C1 to C6, diodes D1 and D2, inductors L1 and L2, and a switching transistor M1. In this embodiment, the switching transistor M1 is an NMOS transistor (N-channel MOSFET (metal-oxide-semiconductor field-effect transistor)). Note that, although the switching transistor is provided outside the control device in the configuration shown in FIG. 2, it is not limited to this and may be built into the control device.

[0017] The control device 700A is a device that controls the PFC circuit 7A, and has an IC that integrates the internal configuration shown in Fig. 2. The control device 700A has terminals VCC, GND, ZCD, OUT, CS, MULT, EO, and VS as external terminals for establishing electrical connection with the outside.

[0018] A first voltage Vh is applied to one end of resistor R1. The other end of resistor R1 is connected to one end of resistor R2, one end of capacitor C5, and terminal MULT. The other end of resistor R2 and the other end of capacitor C5 are connected to the ground end (the end to which the ground potential is applied). With this configuration, a voltage Vmult, which is the first voltage Vh divided by resistors R1 and R2, is supplied to terminal MULT.

[0019] One end of resistor R1 is connected to one end of inductor L1 and the anode of diode D1. The other end of inductor L1 is connected to the anode of diode D2 and the drain of switching transistor M1. The cathodes of diodes D1 and D2 are connected to one end of capacitor C1. The other end of capacitor C1 is connected to ground, and the gate of switching transistor M1 is connected to terminal OUT via resistor R8, and the source of switching transistor M1 is connected to ground via resistor R9. With this configuration, PFC circuit 7A is equipped with a step-up DC / DC converter (switching regulator). Voltage Vdc, which is the output voltage of the step-up DC / DC converter (switching regulator), is output from one end of capacitor C1.

[0020] Inductor L1 and inductor L2 are magnetically coupled. One end of inductor L2 is connected to terminal ZCD via resistor R7. The other end of inductor L2 is connected to ground. With this configuration, the control device 700A can detect the zero crossing of the current flowing through inductor L1 by monitoring the voltage supplied to terminal ZCD.

[0021] The output voltage Vdc is applied to one end of resistor R3. The other end of resistor R3 is connected to one end of resistor R4, one end of capacitor C2, and terminal VS. The other end of resistor R4 and the other end of capacitor C2 are connected to ground. With this configuration, a detection voltage Vs, which is the output voltage Vdc divided by resistors R3 and R4, is supplied to terminal VS.

[0022] One end of resistor R9 is connected to the source of switching transistor M1, and the other end of resistor R9 is connected to ground. A voltage proportional to the current flowing through switching transistor M1 (the drain current of switching transistor M1) is generated across resistor R9. An RC circuit (low-pass filter) formed by resistor R6 and capacitor C6 removes high-frequency components from the voltage (current detection signal) generated across resistor R9 to generate a detection voltage Vcs, which is supplied to terminal CS. The detection voltage Vcs is a voltage proportional to the current flowing through the switching transistor. Because the detection voltage Vcs is a positive voltage, PFC circuit 7A equipped with control device 700A corresponds to a positive voltage control type PFC circuit.

[0023] One end of resistor R5 and one end of capacitor C3 are connected to terminal EO. The other end of resistor R5 is connected to one end of capacitor C4. The other end of capacitor C3 and the other end of capacitor C4 are connected to ground. A power supply voltage Vcc is supplied to terminal VCC, and terminal GND is connected to ground.

[0024] <<Control device>> The specific configuration of the control device 700A will be described below.

[0025] The control device 700A includes a Zener diode 701, a comparator 702, a bandgap reference voltage circuit 703, a constant voltage circuit 704, and an overheat protection circuit 705. The anode of the Zener diode 701 is connected to the ground terminal, and the cathode of the Zener diode 701 is connected to the terminal VCC.

[0026] The Zener diode 701 clamps the power supply voltage Vcc to a Zener voltage. The inverting input terminal (-) of the comparator 702, the bandgap reference voltage circuit 703, and the constant voltage circuit 704 are connected to the terminal VCC.

[0027] The comparator 702 is a hysteresis comparator that compares the power supply voltage Vcc with a threshold voltage and outputs an undervoltage lockout signal UVLO indicating the comparison result. If the power supply voltage Vcc is equal to or greater than the threshold voltage, the undervoltage lockout signal UVLO goes low (indicating a normal state), and if the power supply voltage Vcc is less than the threshold voltage, the undervoltage lockout signal UVLO goes high (indicating an abnormal state). The threshold voltage used by the comparator 702 transitions between a first threshold voltage Vth1 (e.g., 8 V) and a second threshold voltage Vth2 (e.g., 13 V) depending on the level of the undervoltage lockout signal UVLO.

[0028] The bandgap reference voltage circuit 703 generates a reference voltage using the power supply voltage Vcc and supplies it to the constant voltage circuit 704 .

[0029] The constant voltage circuit 704 generates a constant voltage using the power supply voltage Vcc and a reference voltage, and supplies it to each part of the control device 700A.

[0030] The overheat protection circuit 705 detects the ambient temperature, and if the ambient temperature is equal to or higher than the threshold temperature, outputs a high-level overheat protection signal TSD (a level indicating an abnormal state), and if the ambient temperature is lower than the threshold temperature, outputs a low-level overheat protection signal TSD (a level indicating a normal state).

[0031] The control device 700A further includes a comparator 706, a startup excessive boost reducing circuit 707, a comparator 708, and a comparator 709.

[0032] The comparator 706 compares the detection voltage Vs with a threshold voltage Vth3 (for example, 2.25 [V]) and outputs the comparison result to the startup overboost reduction circuit 707. If the detection voltage Vs is equal to or greater than the threshold voltage Vth3, the output signal of the comparator 706 becomes high level (a level indicating an abnormal state), and if the detection voltage Vs is less than the threshold voltage Vth3, the output signal of the comparator 706 becomes low level (a level indicating a normal state).

[0033] The startup overboost reduction circuit 707 outputs a startup overboost reduction signal OVR. Based on the output signal of the comparator 706 and the output voltage Vcomp of a comparator 715 (described later), when the detection voltage Vs rises to a threshold voltage Vth3 at startup, the startup overboost reduction circuit 707 sets the startup overboost reduction signal OVR to a high level (a level indicating an abnormal state) until a second voltage V2 (described later) drops to a constant voltage Vburst (described later), and sets the startup overboost reduction signal OVR to a low level (a level indicating a normal state) at all other times.

[0034] The comparator 708 compares the detection voltage Vs with a threshold voltage Vth4 (e.g., 0.3 V) and outputs the comparison result, a short-circuit protection signal SP. If the detection voltage Vs is equal to or greater than the threshold voltage Vth4, the short-circuit protection signal SP goes low (indicating a normal state), and if the detection voltage Vs is less than the threshold voltage Vth4, the short-circuit protection signal SP goes high (indicating an abnormal state).

[0035] Comparator 709 is a hysteresis comparator that compares detection voltage Vs with a threshold voltage and outputs a static overvoltage protection signal SOVP indicating the comparison result. If detection voltage Vs is equal to or greater than the threshold voltage, static overvoltage protection signal SOVP goes high (indicating an abnormal state), and if detection voltage Vs is less than the threshold voltage, static overvoltage protection signal SOVP goes low (indicating a normal state). The threshold voltage used by comparator 709 transitions between threshold voltage Vth5 (e.g., 2.6 [V]) and threshold voltage Vth6 (e.g., 2.7 [V]) depending on the level of static overvoltage protection signal SOVP.

[0036] The control device 700A further includes an error amplifier circuit 710, an OR gate 711, an NMOS transistor 712, an arithmetic circuit 713, a Zener diode 714, a comparator 715, and a drive circuit DRV1.

[0037] The error amplifier circuit 710 amplifies the error between the reference voltage Vref1 and the detection voltage Vs, which corresponds to the output voltage Vdc of a step-up DC / DC converter (switching regulator) provided in the PFC circuit 7A, to generate a second voltage V2. The amplification factor of the error amplifier circuit 710 may be 1. The error amplifier circuit 710 supplies the second voltage V2 to a terminal EO and an arithmetic circuit 713.

[0038] The OR gate 711 outputs the logical sum of the undervoltage lockout signal UVLO and the startup overboost reduction signal OVR to the gate of the NMOS transistor 712. The drain of the NMOS transistor 712 is connected to the terminal EO, and the source of the NMOS transistor 712 is connected to the ground terminal. The NMOS transistor 712 is a switch for discharging the second voltage applied to the terminal EO. Therefore, when at least one of the undervoltage lockout signal UVLO and the startup overboost reduction signal OVR is at a high level, the NMOS transistor 712 is turned on, and the second voltage V2 drops.

[0039] The arithmetic circuit 713 generates a third voltage by multiplying the AC voltage (first voltage) Vmult by the second voltage V2, and adds an offset voltage Voffset to the third voltage to generate a fourth voltage V4.

[0040] The fourth voltage V4 is connected to the inverting input terminal of the comparator 715. The cathode of the Zener diode 714 is connected to the inverting input terminal of the comparator 715, and the anode of the Zener diode 714 is connected to the ground terminal. The Zener diode 714 clamps the fourth voltage V4 to a Zener voltage.

[0041] The comparator 715 compares the detection voltage Vcs, which corresponds to the current flowing through the switching transistor M1, with the fourth voltage V4, and outputs a voltage Vcomp indicating the comparison result.

[0042] The drive circuit DRV1 drives the switching transistor M1 on and off, and turns off the switching transistor M1 every time the detection voltage Vcs becomes higher than the fourth voltage V4, in accordance with the voltage Vcomp output from the comparator 715. Note that turning off refers to switching from an on state to an off state. That is, the drive circuit DRV1 turns off the switching transistor M1 based on the voltage Vcomp output from the comparator 715. The configuration of the drive circuit DRV1 is not particularly limited, and any known technology may be used.

[0043] 2 shows an example of the drive circuit DRV1. The drive circuit DRV1 includes a comparator 716, a one-shot circuit 717, a timer 718, an OR gate 719, a flip-flop 720, an AND gate 721, a pre-driver 722, a gate clamp circuit 723, a PMOS transistor (P-channel MOSFET) 724, an NMOS transistor 725, and a resistor 726.

[0044] Comparator 716 is a hysteresis comparator that compares the voltage applied to terminal ZCD with a threshold voltage and outputs the comparison result to one-shot circuit 717. If the voltage applied to terminal ZCD is equal to or greater than the threshold voltage, the output signal of comparator 716 becomes low level, and if the voltage applied to terminal ZCD is less than the threshold voltage, the output signal of comparator 716 becomes high level. The threshold voltage used by comparator 716 transitions between threshold voltage Vth7 (e.g., 0.67 [V]) and threshold voltage Vth8 (e.g., 0.9 [V]) depending on the level of the output signal of comparator 716.

[0045] When the output signal of the comparator 716 goes high, the one-shot circuit 717 supplies a one-shot pulse to the first input terminal of the OR gate 719 .

[0046] When the timer 718 has timed out a certain period of time, it supplies a high-level signal to the second input terminal of the OR gate 719. The timer 718 is reset every time the pre-driver 722 receives a high-level signal from the AND gate 721.

[0047] An OR gate 719 supplies the logical sum of the output signal of the one-shot circuit 717 and the output of the timer 718 to a set terminal (S) of an RS flip-flop 720. A voltage Vcomp, which is the output of the comparator 715, is supplied to a reset terminal (R) of the RS flip-flop 720. The output (Q) of the RS flip-flop 720 transitions to a high level at each positive edge of the voltage applied to the set terminal (S), and transitions to a low level at each positive edge of the voltage applied to the reset terminal (R).

[0048] The AND gate 721 supplies the pre-driver 722 with the logical product of the inverted signal of the undervoltage lockout signal UVLO, the output signal of the RS flip-flop 720, the inverted signal of the static overvoltage protection signal SOVP, the inverted signal of the short-circuit protection signal SP, the inverted signal of the overheat protection signal TSD, and the PFC off signal PFCOFF_H, which will be described later.

[0049] The pre-driver 722 complementarily drives the PMOS transistor 724 and the NMOS transistor 725 on / off based on the output of the AND gate 721. Specifically, when the output of the AND gate 721 is high, the pre-driver 722 turns the PMOS transistor 724 on and the NMOS transistor 725 off, thereby setting the voltage at the terminal OUT to a high level and turning the switching transistor M1 on. On the other hand, when the output of the AND gate 721 is low, the pre-driver 722 turns the PMOS transistor 724 off and the NMOS transistor 725 on, thereby setting the voltage at the terminal OUT to a low level and turning the switching transistor M1 off.

[0050] The source of the PMOS transistor 724 is connected to a gate clamp circuit 723, and the drain of the PMOS transistor 724 is connected to the drain of the NMOS transistor 725, the terminal OUT, and one end of a resistor 726. The source of the NMOS transistor 725 is connected to the ground terminal and the other end of the resistor 726. The gate clamp circuit 723 generates a high-level voltage that is applied to the terminal OUT from the power supply voltage Vcc. The gate clamp circuit 723 clamps the high-level voltage applied to the terminal OUT to a constant voltage, so that the high-level voltage applied to the terminal OUT does not exceed the gate-source breakdown voltage of the switching transistor M1 when the power supply voltage Vcc rises.

[0051] The control device 700A has a comparator 727 and a terminal PFCOFF as an external terminal. A non-inverting input terminal of the comparator 727 is connected to the terminal PFCOFF. The comparator 727 compares the control signal Poff input to the terminal PFCOFF with a threshold voltage Vth9, and outputs a PFC off signal PFCOFF_H. The PFC off signal PFCOFF_H is input to an AND gate 721. As a result, when the control signal Poff is at a low level, the PFC off signal PFCOFF_H is at a low level, and when the control signal Poff is at a high level, the PFC off signal PFCOFF_H is at a high level. When the control signal Poff is at a low level, the PFC circuit 7A (control device 700A) is placed in a standby state.

[0052] <<Arithmetic circuit>> This concludes the description of the configuration of the PFC circuit 7A. Next, we will describe the internal configuration of the arithmetic circuit 713. First, we will describe a specific example configuration of the offset voltage generating circuit 713A provided in the arithmetic circuit 713.

[0053] 3 shows an example of the offset voltage generating circuit 713A. The offset voltage generating circuit 713A includes a constant current generating circuit 713A1, a first current generating circuit 713A2, and a resistor R10.

[0054] The constant current generating circuit 713A1 includes a current mirror circuit formed by PMOS transistors M2 and M3 and a current source IS1. The constant voltage Vdd output from the constant voltage circuit 704 is applied to the source and back gate of the PMOS transistor M2 and the source and back gate of the PMOS transistor M3. The gate and drain of the PMOS transistor M2 and the gate of the PMOS transistor M3 are connected to one end of the current source IS1. The other end of the current source IS1 is connected to ground. The drain of the PMOS transistor M3 and one end of a resistor R10 are connected to a node ND1. The other end of the resistor R10 is connected to ground. The constant current generating circuit 713A1 generates a constant current I0 and supplies it to the node ND1. The value of the constant current I0 is not particularly limited. For example, if the constant current output by the current source IS1 is 1 μA and the current mirror ratio is 6:1, the value of the constant current I0 is 167 nA.

[0055] The first current generating circuit 713A2 includes an operational amplifier OP1, a drain-type current mirror circuit formed by PMOS transistors M4 and M5, an NMOS transistor M6, a resistor R11, and a drain-type current mirror circuit formed by NMOS transistors M7 and M8. The constant voltage Vdd output from the constant voltage circuit 704 is applied to the source and back gate of the PMOS transistor M4 and the source and back gate of the PMOS transistor M5. The gate and drain of the PMOS transistor M4 and the gate of the PMOS transistor M5 are connected to the drain of the NMOS transistor M6.

[0056] The source and back gate of the NMOS transistor M6 are connected to one end of a resistor R11 and the inverting input terminal of an operational amplifier OP1. The other end of the resistor R11 is connected to ground. A voltage Vmult is supplied to a first non-inverting input terminal of the operational amplifier OP1, and a constant voltage of, for example, 2.5 V is supplied to a second non-inverting input terminal of the operational amplifier OP1. The output terminal of the operational amplifier OP1 is connected to the gate of the NMOS transistor M6. The operational amplifier OP1 outputs a signal obtained by amplifying the difference between the voltage supplied to its inverting input terminal and the voltage Vmult plus the constant voltage of, for example, 2.5 V.

[0057] The drain of the PMOS transistor M5 is connected to the drain and gate of the NMOS transistor M7 and the gate of the NMOS transistor M8. The source and back gate of the NMOS transistor M7 and the source and back gate of the NMOS transistor M8 are connected to the ground terminal. The drain of the NMOS transistor M8 is connected to the node ND1. The first current generating circuit 713A2 generates a first current I1 and draws the first current I1 from the node ND1. The first current I1 varies depending on the voltage (AC voltage) Vmult. Specifically, the first current I1 increases as the voltage Vmult increases. In the example shown in FIG. 3, the first current I1 increases linearly as the voltage Vmult increases.

[0058] A current obtained by subtracting the first current I1 from the constant current I0, i.e., a differential current (I0-I1), flows from node ND1 to resistor R10. The product of the differential current (I0-I1) and the resistance value of resistor R10 is the offset voltage Voffset. Therefore, the offset voltage Voffset varies depending on the voltage Vmult. Specifically, the offset voltage Voffset decreases as the voltage Vmult increases. In the example shown in FIG. 3, the offset voltage Voffset decreases linearly as the voltage Vmult increases.

[0059] The range of the offset voltage Voffset is not particularly limited, but in the example shown in FIG. 3, for example, if the value of the constant current I0 is 167 [nA] as described above, the current mirror ratio of the discharge current mirror circuit in the first current generating circuit 713A2 is 10:1, the resistance value of the resistor R11 which is a current source connected to the discharge current mirror circuit is 2 [MΩ], the drain current mirror ratio in the first current generating circuit 713A2 is 1:1, and the resistance value of the resistor R10 is 161.2 [kΩ], then the offset voltage Voffset is variable within a range of 6.9 [mV] to 26.8 [mV].

[0060] If the design value of the minimum value of the offset voltage Voffset is set to, for example, 6.9 [mV] as in the above example, the actual minimum value of the offset voltage Voffset due to variations in the circuit constants can be made equal to or greater than zero.

[0061] 3, if the minimum value of the offset voltage Voffset becomes smaller than zero, the offset voltage generation circuit 713A will not operate normally, and therefore it is desirable that the minimum value of the offset voltage Voffset be equal to or greater than zero. Note that it is also possible to configure the circuit so that no malfunction occurs when the minimum value of the offset voltage Voffset becomes smaller than zero, and therefore it is also possible to set the minimum value of the offset voltage Voffset to be smaller than zero.

[0062] Furthermore, the offset voltage generating circuit 713A may be provided with a trimming element for adjusting the circuit constants, thereby suppressing variations in the circuit constants and setting the minimum design value of the offset voltage Voffset to zero or close to zero. An example of such a trimming element is at least one fuse provided in a parallel circuit of multiple resistors to adjust the resistance of a resistor that serves as a current source connected to the discharge current mirror circuit in the first current generating circuit 713A2. The fuse can be blown, for example, by laser trimming.

[0063] The above is a description of the configuration of the offset voltage generation circuit 713A. Next, a description will be given of a specific configuration example of the circuits other than the offset voltage generation circuit 713A of the arithmetic circuit 713. In addition to the offset voltage generation circuit 713A, the arithmetic circuit 713 includes a first arithmetic circuit 713B, a first conversion circuit 713C, a second conversion circuit 713D, and a second arithmetic circuit 713E.

[0064] FIG. 4 shows an example of the first arithmetic circuit 713B. The first arithmetic circuit 713B includes resistors R12 to R15 and an operational amplifier OP2. A second voltage V2 is applied to one end of the resistor R12. The other end of the resistor R12 and one end of the resistor R13 are connected to the non-inverting input terminal of the operational amplifier OP2. The other end of the resistor R13 is connected to ground. A constant voltage Vburst is applied to one end of the resistor R14. The other end of the resistor R14 and one end of the resistor R15 are connected to the inverting input terminal of the operational amplifier OP2. The other end of the resistor R15 is connected to the output terminal of the operational amplifier OP2. The first arithmetic circuit 713B outputs a voltage (V2-Vburst) obtained by subtracting the constant voltage Vburst from the second voltage V2.

[0065] 5 shows an example of a first conversion circuit 713C. The first conversion circuit 713C includes an operational amplifier OP3, a resistor R16, and an NPN bipolar transistor M9. A voltage (V2-Vburst) is applied to the non-inverting input terminal of the operational amplifier OP3. One end of the resistor R16 is connected to the inverting input terminal and output terminal of the operational amplifier OP3. The other end of the resistor R16 is connected to the ground terminal. The collector and base of the NPN bipolar transistor M9 are connected to the power supply terminal of the operational amplifier OP3. The emitter of the NPN bipolar transistor M9 is connected to the ground terminal. The first conversion circuit 713C converts the voltage (V2-Vburst) into a current (I2-Iburst) and outputs the current (I2-Iburst) as the base current of the NPN bipolar transistor M9.

[0066] FIG. 6 shows an example of a second conversion circuit 713D. The second conversion circuit 713D includes an operational amplifier OP4, a resistor R17, and an NPN bipolar transistor M10. A voltage Vmult is applied to the non-inverting input terminal of the operational amplifier OP4. One end of the resistor R17 is connected to the inverting input terminal and output terminal of the operational amplifier OP4. The other end of the resistor R17 is connected to ground. The collector and base of the NPN bipolar transistor M10 are connected to the power supply terminal of the operational amplifier OP4. The emitter of the NPN bipolar transistor M10 is connected to ground. The second conversion circuit 713D converts the voltage Vmult into a current Imult and outputs the current Imult as the base current of the NPN bipolar transistor M10.

[0067] 7 shows an example of the second arithmetic circuit 713E. The second arithmetic circuit 713E includes resistors R18 to R24, a current source IS2, NPN bipolar transistors M11 to M20, PMOS transistors M21 and M22, NMOS transistors M23 and M24, a PNP bipolar transistor M25, and a NOT gate NG1.

[0068] The constant voltage Vdd output from the constant voltage circuit 704 is applied to one end of each of resistors R18 to R22, the collector of NPN bipolar transistor M12, the source and backgate of PMOS transistor M21, the source and backgate of PMOS transistor M22, and the emitter of PNP bipolar transistor M25. The other end of resistor R18 is connected to the collector of NPN bipolar transistor M11. The emitter of NPN bipolar transistor M11 is connected to one end of current source IS2 and the base of NPN bipolar transistor M15. The other end of current source IS2 is connected to ground.

[0069] The base and emitter of NPN bipolar transistor M12 are connected to the base of PNP bipolar transistor M25 and the collector of NPN bipolar transistor M13. The emitter of NPN bipolar transistor M13 is connected to the collector of NPN bipolar transistor M15. The emitter of NPN bipolar transistor M15 is connected to the emitter of NPN bipolar transistor M16. The other end of resistor R19 is connected to the collector of NPN bipolar transistor M14. The emitter of NPN bipolar transistor M14 is connected to the base of NPN bipolar transistor M11 and the collector of NPN bipolar transistor M16.

[0070] The other end of resistor R20 is connected to the collector of NPN bipolar transistor M17. The emitter of NPN bipolar transistor M17 is connected to the base of NPN bipolar transistor M16 and the collector of NPN bipolar transistor M18. The emitter of NPN bipolar transistor M18 is connected to ground. The base of NPN bipolar transistor M18 is connected to the base and collector of NPN bipolar transistor M10 in the second conversion circuit 713D. NPN bipolar transistors M10 and M18 form a current mirror circuit.

[0071] The other end of resistor R21 is connected to the collector of NPN bipolar transistor M19. The emitter of NPN bipolar transistor M19 is connected to the base of NPN bipolar transistor M17 and the collector of NPN bipolar transistor M20. The emitter of NPN bipolar transistor M20 is connected to the ground terminal. The base of NPN bipolar transistor M20 is connected to the base and collector of NPN bipolar transistor M9 in the first conversion circuit 713C. NPN bipolar transistors M9 and M20 form a current mirror circuit.

[0072] The other end of the resistor R22 is connected to one end of a resistor R23, the base of an NPN bipolar transistor M13, the base of an NPN bipolar transistor M14, and the base of an NPN bipolar transistor M19. The other end of the resistor R23 is connected to the ground terminal.

[0073] The gate and drain of the PMOS transistor M21 are connected to the gate of the PMOS transistor M22. The PMOS transistors M21 and M22 form a current mirror circuit. The drain of the PMOS transistor M22 is connected to the drain of the NMOS transistor M23 and the input terminal of the NOT gate. An enable signal EN is supplied to the gate of the NMOS transistor M23. The source and back gate of the NMOS transistor M23 are connected to the ground terminal. The output terminal of the NOT gate is connected to the gate of the NMOS transistor M24. The source and back gate of the NMOS transistor M24 are connected to the ground terminal. The drain of the NMOS transistor M24 is connected to one end of a resistor R24. The other end of the resistor R24 ​​is connected to the collector of a PNP bipolar transistor M25 and one end of a resistor R10. The other end of the resistor R10 is connected to the ground terminal.

[0074] The second arithmetic circuit 713E multiplies the current (I2-Iburst) by the current Imult and outputs the result of this multiplication, an output current Iout, to a resistor R10. The resistor R10 converts the output current Iout into a voltage (K×Vmult(V2-Vburst)). The constant K is determined by the ratio between the resistance value of the resistor R16 in the first conversion circuit 713C and the resistance value of the resistor R10, and the ratio between the resistance value of the resistor R17 in the second conversion circuit 713D and the resistance value of the resistor R10. The current I3 output by the current source IS2 in the second arithmetic circuit 713E is a current proportional to the peak value (maximum value) of the voltage Vmult. The second arithmetic circuit 713E can be switched between an enabled state and a disabled state by an enable signal EN.

[0075] The resistor R10 shown in Fig. 7 is the same as the resistor R10 provided in the offset voltage generating circuit 713A shown in Fig. 3. Therefore, an offset voltage Voffset is also applied to the resistor R10. Therefore, the fourth voltage V4 generated in the resistor R10 as the voltage across the resistor R10 is expressed by the following equation. V4=K×Vmult(V2-Vburst)+Voffset

[0076] Here, in order to explain the effect of the PFC circuit 7A, a circuit obtained by removing the offset voltage generating circuit 713A from the PFC circuit 7A will be compared with the PFC circuit 7A.

[0077] In a circuit in which the offset voltage generating circuit 713A is removed from the PFC circuit 7A, the on-time of the switching transistor M1 is shortened when the first voltage Vh is near 0 [V] due to the operation of the drive circuit DRV1. Therefore, when the first voltage Vh is near 0 [V], the capacitor 6 provided on the output side of the rectifier circuit 5 cannot be sufficiently discharged, and as a result, the current output from the rectifier circuit 5 is temporarily stopped, causing distortion in the input current Iac (see the dotted line in FIG. 8).

[0078] On the other hand, in the PFC circuit 7A, when the first voltage Vh is near 0 [V], the offset voltage Voffset increases and the fourth voltage V4 also increases, so that the on-time of the switching transistor M1 is lengthened by the operation of the drive circuit DRV1. Therefore, when the first voltage Vh is near 0 [V], the capacitor 6 provided on the output side of the rectifier circuit 5 can be sufficiently discharged, resulting in a smooth current output from the rectifier circuit 5 and suppressed distortion of the input current Iac (see the solid line in FIG. 8). In other words, the control device 700A can suppress the THD of the PFC circuit 7A.

[0079] It should be noted that since it is not necessary to increase the offset voltage Voffset when the first voltage Vh is not near 0 V, it is desirable to make the offset voltage Voffset variable as in the above-described embodiment. However, it is also possible to fix the offset voltage Voffset by allowing the addition of unnecessary offset voltage Voffset when the first voltage Vh is not near 0 V.

[0080] <Second Comparative Example> 9 is a diagram showing the configuration of a PFC circuit 7B according to a second comparative example. The PFC circuit 7B differs from the first comparative example in that it does not include an inductor L2, but includes a sense resistor Ris and a control device 700B. The control device 700B also includes a terminal IS instead of a terminal CS as an external terminal.

[0081] One end of the sense resistor Ris is connected to the ground terminal. The other end of the sense resistor Ris is connected to one end of a resistor R6. The other end of the resistor R6 is connected to a terminal IS. When the switching transistor M1 is in the on state, a current Is flows through the sense resistor Ris from the ground side, and the detection voltage Vis generated at the terminal IS becomes a negative voltage. Therefore, the PFC circuit 7B shown in FIG. 9 corresponds to a negative voltage control type PFC circuit.

[0082] The control device 700B has an error amplifier circuit 710, a comparator 730, an OSC (oscillator) 731, a comparator 732, and a drive circuit DRV2. The control device 700B also has terminals VS, EO, IS, and OUT as external terminals.

[0083] As in the first comparative example, the detection voltage Vs generated at the terminal VS and the reference voltage Vref1 are input to an error amplifier circuit 710, and a voltage V2 is output from the error amplifier circuit 710. The voltage V2 and the detection voltage Vis are input to a comparator 732, and the output of the comparator 732 is input to the reset terminal of a flip-flop 720 in the drive circuit DRV2. The detection voltage Vis and a negative reference voltage Vth10 are input to a comparator 730, and the output of the comparator 730 is input to OSC 731. The oscillation signal Vosc output from OSC 731 is connected to the set terminal of the flip-flop 720 and the Q output terminal.

[0084] An example of operation of the PFC circuit 7B configured as above is shown in the timing chart of Fig. 10. In Fig. 10, from the top, examples of the waveforms of the detection voltage Vis, the oscillation signal Vosc, and the voltage at the terminal OUT are shown.

[0085] When the switching transistor M1 is in the off state, the current Is decreases, the detection voltage Vis rises toward 0 V, and at timing Ta, when it exceeds the reference voltage Vth10 (for example, -10 mV), this is detected by the comparator 730, and the oscillation signal Vosc is raised to a high level by the OSC 731. This causes the voltage at the terminal OUT to rise to a high level, and the switching transistor M1 is turned on. Turning on refers to switching from an off state to an on state.

[0086] As a result, the current Is increases and the detection voltage Vis decreases. Then, when a predetermined ON width time Ton elapses before the detection voltage Vis reaches voltage V2 (=negative voltage), the oscillation signal Vosc falls to low level by the OSC 731 (timing Tb). This causes the Q output of the flip-flop 720 to fall to low level, the voltage at the terminal OUT falls to low level, and the switching transistor M1 is turned off.

[0087] As a result, the current Is decreases, the detection voltage Vis rises toward 0 V, and when it exceeds the reference voltage Vth10 at timing Ta, this is detected by the comparator 730, and the oscillation signal Vosc is raised to high level by the OSC 731 (timing Tc), causing the voltage at the terminal OUT to rise to high level and turning on the switching transistor M1.

[0088] As a result, the current Is increases and the detection voltage Vis decreases. When the detection voltage Vis reaches the voltage V2 before the ON width time Ton has elapsed, the comparator 732 detects this and resets the flip-flop 720, causing the Q output to go low. This causes the voltage at the terminal OUT to fall to low, and the switching transistor M1 is turned off (timing Td).

[0089] As described above, in the configuration of the second comparative example (FIG. 9), in the negative voltage control type PFC circuit 7B, it is possible to control the turn-off of the switching transistor M1 without using the voltage Vmult as in the first comparative example. However, by not using the voltage Vmult (terminal MULT), the configuration does not improve THD as in the first comparative example.

[0090] <Embodiments of the present disclosure> In view of the above-described problems, this embodiment provides a configuration that improves THD in a negative voltage control PFC circuit. Fig. 11 is a diagram showing the configuration of a PFC circuit 7 according to an embodiment of the present disclosure. The PFC circuit 7 includes a control device 700.

[0091] The control device 700 has a terminal MULT as an external terminal. In the PFC circuit 7, as in the first comparative example, the voltage Vh is divided by resistors R1 and R2 to generate a voltage Vmult, and the voltage Vmult is applied to the terminal MULT. The control device 700 has an error amplifier circuit 710, an arithmetic circuit 733, an inverting amplifier 734, a comparator 735, and a drive circuit DRV. The PFC circuit 7 also has an inductor L2 and a resistor R7 as in FIG. 2 described above, and the control device 700 has a terminal ZCD and a comparator 716 as in FIG. 2. The logic unit 736 in the control device 700 controls the set terminal of the flip-flop 720 based on the output of the comparator 716.

[0092] As in the first comparative example, the voltage V2 output from the error amplifier circuit 710 and the voltage Vmult are input to the arithmetic circuit 733. In the arithmetic circuit 733, as in the first comparative example, V4=K×Vmult(V2-Vburst)+Voffset The voltage V4 is calculated by the following equation.

[0093] The inverting amplifier 734 is a circuit that inverts and amplifies the negative detection voltage Vis to convert it into a positive detection voltage V5. The voltage V4 is input to the inverting input terminal of the comparator 735, and the detection voltage V5 is input to the non-inverting input terminal. The output of the comparator 735 is input to the reset terminal of the flip-flop 720 in the drive circuit DRV.

[0094] Fig. 12 is a timing chart showing an example of operation of the PFC circuit 7 according to this embodiment. Fig. 12 shows, from the top to the bottom, example waveforms of the detection voltage Vis, the detection voltage V5, the voltage at the terminal OUT, the inductor current IL flowing through the inductor L1, and the voltage at the terminal ZCD.

[0095] At timing t1, the voltage at the terminal OUT rises to a high level and the switching transistor M1 is turned on, whereupon the inductor current IL increases, the detection voltage Vis drops from 0 V, and the positive detection voltage V5 rises accordingly. When the detection voltage V5 exceeds the voltage V4, the flip-flop 720 is reset, the voltage at the terminal OUT falls to a low level, and the switching transistor M1 is turned off (timing t2).

[0096] As a result, the inductor current IL decreases, and the voltage at the terminal ZCD rises. Furthermore, the detection voltage Vis rises toward 0V, and the detection voltage V5 falls. The comparator 716 monitors the auxiliary winding voltage (the voltage of the inductor L2) from the terminal ZCD, and when the inductor current IL crosses zero, the voltage at the terminal ZCD falls, which is detected by the comparator 716 (timing t3). Upon detecting the zero cross of the inductor current IL, the logic unit 736 sets the flip-flop 720, causing the voltage at the terminal OUT to rise to a high level, and turning on the switching transistor M1 (timing t4).

[0097] FIG. 12 shows V4 with and without offset voltage Voffset. FIG. 12 also shows offset voltage V5_offset (e.g., 200 mV), which is the value of detection voltage V5 when detection voltage Vis=0 V. As shown in FIG. 13, when voltage Vmult is 0 V, the value of voltage V4 calculated by calculation circuit 733 is Voffset, and it is necessary to ensure an offset difference ΔV expressed as ΔV=Voffset−V5_offset. If the offset difference ΔV is ensured, when voltage Vh is close to 0 V, i.e., when Vmult is close to 0 V, the on-width of switching transistor M1 becomes longer, thereby improving THD.

[0098] 14 is a diagram showing a specific example of the configuration of the arithmetic circuit 733 and the inverting amplifier 734. The arithmetic circuit 733 has an arithmetic processing section 733A, an offset generating section 733B, and a resistor 733C.

[0099] The arithmetic processing unit 733 outputs the output current Iout to the resistor 733C, similar to the second arithmetic circuit 713E (FIG. 7) of the first comparative example. The offset generating unit 733B outputs the offset current Ioffset to the resistor 733C. The output current Iout and the offset current Ioffset are combined and flow through the resistor 733C. The voltage generated across the resistor 733C is output as the voltage V4.

[0100] That is, the resistance value of resistor 733C is R, V4 = R × (Iout + Ioffset) =R×Iout+R×Ioffset =K×Vmult(V2-Vburst)+Voffset This becomes:

[0101] As described above, it is necessary to ensure the offset difference ΔV, but due to variations between products, a setting process is required to set the offset difference ΔV to a desired value. Such a setting method will be described below.

[0102] FIG. 15 is a diagram showing a configuration related to a process for setting the offset difference ΔV. The control device 700 shown in FIG. 11 is a semiconductor device having a chip on which the internal configuration shown in FIG. 11 is integrated. FIG. 15 shows that the arithmetic circuit 733, the inverting amplifier 734, the comparator 735, and the drive circuit DRV are integrated in the chip CHP described above. The chip CHP is provided with pads, including an EO pad P1, a MULT pad P2, an IS pad P3, and a test pad P4. The EO pad P1, the MULT pad P2, and the IS pad P3 are connected to the terminals EO, MULT, and IS of the control device 700 by bonding wires, respectively. The test pad P4 is not connected to an external terminal by a bonding wire.

[0103] Furthermore, in the chip CHP, a switch SW1 is provided between the output terminal of the arithmetic circuit 733 and the inverting input terminal of the comparator 735, and a switch SW2 is provided between the test pad P4 and the inverting input terminal of the comparator 735. During normal use as the control device 700, the switch SW1 is in the on state and the switch SW2 is in the off state.

[0104] The setting process is performed in the chip CHP state. In the first process, as shown in Figure 15, switch SW1 is set to the OFF state, SW2 is set to the ON state, and a test voltage Vtest is applied to the test pad P4 with 0V applied to the IS pad P3. The test voltage Vtest is swept upward from 0V. The voltage at the OUT terminal is monitored, and the value of Vtest is measured when the voltage level at the OUT terminal switches. This makes it possible to measure the voltage V5 when the detection voltage Vis = 0V, i.e., the offset voltage V5_offset. Figure 16 shows an example waveform when measuring the offset voltage V5_offset. When Vtest is swept and reaches V5 when the detection voltage Vis = 0V, the voltage level at the OUT terminal switches.

[0105] Next, in the second step, as shown in Fig. 16, both switches SW1 and SW2 are turned on, and the voltage generated at test pad P4 is measured with 0V applied to MULT pad P2. This makes it possible to measure the value of V4 when Vmult = 0V, i.e., the offset voltage Voffset. At this time, the measurement is performed by the offset generator 733 shown in Fig. 14 using the offset current Ioffset as a reference value.

[0106] Then, in the third step, the offset current Ioffset is adjusted (repaired) by the offset generating unit 733B so that the offset difference ΔV becomes a desired value based on the offset voltages V5_offset and Voffset measured as described above. This allows the offset difference ΔV to be set to a desired value.

[0107] Fig. 18 is a diagram showing a specific example of the configuration of the offset generation unit 733B. The offset generation unit 733B shown in Fig. 18 has current mirrors CM1 to CM3.

[0108] The current mirror CM1 is configured to mirror the reference current Iref using PMOS transistors on the input and output sides. The current mirror CM1 also includes a PMOS transistor PM1 whose source is connected to the drain of the output PMOS transistor, a fuse F1 connected to the high-potential side (upper side) of the gate of the PMOS transistor PM1, and a pull-down resistor Rp1 connected to the low-potential side (lower side) of the gate of the PMOS transistor PM1. The PMOS transistor PM1 switches the current mirror CM1 between enabled and disabled depending on whether the fuse F1 is blown.

[0109] The current mirror CM2 is configured to mirror the reference current Iref using PMOS transistors on the input and output sides.

[0110] The current mirror CM3 is configured to mirror the reference current Iref using PMOS transistors on the input and output sides. The current mirror CM3 also has a fuse F3 connected to the drain of the PMOS transistor on the output side. The current mirror CM3 is disabled or enabled depending on whether the fuse F3 is blown.

[0111] As shown in Figure 18, one current mirror CM2, three current mirrors CM1, and three current mirrors CM3 are provided. Note that the number of current mirrors is not limited to this. A state in which none of the fuses F1 and F3 are cut is the reference state, and the offset current Ioffset generated in this state is the reference value. In this case, the current mirror CM1 is disabled (the PMOS transistor PM1 is off) and the current mirror CM3 is enabled, so the currents mirrored by the current mirrors CM2 and CM3 are combined to become the offset current Ioffset.

[0112] When fuse F1 is cut during repair, current mirror CM1 corresponding to the cut fuse F1 becomes active (PMOS transistor PM1 is on), and the current mirrored by current mirror CM1 is added to the current mirrored by current mirrors CM2 and CM3, increasing the offset current Ioffset from the reference value.

[0113] When fuse F3 is blown during repair, current mirror CM3 corresponding to the blown fuse F3 is disabled, and the offset current Ioffset is reduced from the reference value. In this way, repairs can be made by increasing or decreasing the offset current Ioffset by blowing fuses F1 and F3.

[0114] It is also possible to provide a switch instead of a fuse and repair the offset current Ioffset by turning the switch on and off using a logic circuit.

[0115] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0116] <Additional Notes> As described above, one aspect of the present disclosure is a control device (700) configured to control a power factor correction circuit (7) having a DC / DC converter, a first external terminal (MULT) configured to receive a first voltage (Vmult) having a full-wave rectified waveform; a second external terminal (IS) configured to receive a first detection voltage (Vis) as a negative voltage generated by a current flowing through a sense resistor (Ris) connected to an application terminal of the ground potential in the power factor correction circuit; an error amplifier circuit (710) configured to amplify an error between a second detection voltage (Vs) corresponding to an output voltage (Vdc) of the DC / DC converter and a reference voltage (Vref1) to generate a second voltage (V2); an arithmetic circuit (733) configured to generate a third voltage (V4) by multiplying the first voltage and the second voltage; an inverting amplifier (734) configured to invert and amplify the first detection voltage to generate a fourth voltage (V5); a comparator (735) configured to compare the third voltage with the fourth voltage; The power factor correction circuit is configured to drive a switching element in the power factor correction circuit on and off, and to turn off the switching element every time the fourth voltage becomes higher than the third voltage according to the output of the comparator (first configuration).

[0117] In addition, the first configuration may be configured to include an adjustment unit (733B) configured to be able to adjust an offset difference, which is the difference between the third voltage obtained when the first voltage = 0V and the fourth voltage obtained when the first detection voltage = 0V (second configuration).

[0118] In the second configuration, the arithmetic circuit (733) an arithmetic processing unit (733A) configured to receive the first voltage and the second voltage and output an output current (Iout); an offset generating unit (733B) configured to variably generate an offset current (Ioffset) as the adjusting unit; A resistor (733C) configured so that a current obtained by combining the output current and the offset current flows may also be provided (third configuration).

[0119] In the third configuration, the offset generation unit (733B) includes a first current mirror (CM1), a second current mirror (CM2), a third current mirror (CM3), a first selection unit (F1) configured to select whether the first current mirror is enabled or disabled, and a second selection unit (F3) configured to select whether the third current mirror is enabled or disabled; The offset current may be obtained by combining the currents output from the first current mirror, the second current mirror, and the third current mirror (fourth configuration).

[0120] In addition, in the above fourth configuration, the first selection unit and the second selection unit may be fuses (F1, F3), and the first current mirror and the third current mirror may be enabled / disabled depending on whether the fuses are cut or not (fifth configuration).

[0121] In the fifth configuration, each of the first current mirror, the second current mirror, and the third current mirror has an input-side PMOS transistor and an output-side PMOS transistor, the first current mirror includes a first PMOS transistor (PM1) whose source is connected to the drain of the output-side PMOS transistor, the fuse (F1) connected to a high potential side of the gate of the first PMOS transistor, and a pull-down resistor (Rp1) connected to a low potential side of the gate of the first PMOS transistor; The third current mirror may have a configuration in which the fuse (F3) is connected to the drain of the output-side PMOS transistor (sixth configuration).

[0122] In addition, in any one of the third to sixth configurations, a chip (CHP) for integrating circuits is provided, The chip is The arithmetic processing unit (733A), The offset generation unit (733B), The inverting amplifier (734); The comparator (735); a first pad (P2) for applying the first voltage; a second pad (P3) for applying the first detection voltage; A test pad (P4) may be connected to the output terminal of the arithmetic processing unit, the output terminal of the offset generating unit, and the input terminal of the comparator (seventh configuration).

[0123] Moreover, a power factor correction circuit (7) according to an aspect of the present disclosure includes a control device having any one of the first to seventh configurations (eighth configuration).

[0124] Also, an electronic device (1) according to one aspect of the present disclosure includes a rectifier circuit (5) configured to full-wave rectify an AC voltage (Vac); and a power factor correction circuit (7) of an eighth configuration configured to receive the output voltage (Vh) of the rectifier circuit (ninth configuration).

[0125] Furthermore, one aspect of the present disclosure is an offset setting method carried out in a manufacturing process of a control device having the seventh configuration, a first step of sweeping a test voltage (Vtest) to be applied to the test pad while applying a voltage of 0 V to the second pad, and measuring the test voltage when the output level of the comparator switches; a second step of measuring the voltage of the test pad while applying a voltage of 0 V to the first pad; and a third step of adjusting the offset difference using the adjustment unit based on the measurement results of the first step and the second step (tenth configuration). [Industrial Applicability]

[0126] The present disclosure can be used in AC / DC converters for various applications. [Explanation of symbols]

[0127] 1 Electronic equipment 2 fuses 3. Capacitors 4 Filters 5 Rectifier circuit 6 capacitors 7, 7A, 7B PFC circuit 8 DC / DC converters 9 Microcomputer 10 Signal processing circuit 700, 700A, 700B control device 701 Zener diode 702 Comparator 702 Control device 703 Bandgap Reference Voltage Circuit 704 Constant Voltage Circuit 705 Overheat protection circuit 706 Comparator 707 Start-up overvoltage reduction circuit 708 Comparator 709 Comparator 710 Error Amplifier Circuit 711 OR Gate 712 NMOS transistor 713 Arithmetic circuit 713A Offset Voltage Generation Circuit 713A1 Constant current generation circuit 713A2 1st current generation circuit 713B 1st calculation circuit 713C 1st conversion circuit 713D Second Conversion Circuit 713E 2nd arithmetic circuit 714 Zener diode 715 Comparator 716 Comparator 717 One-shot circuit 718 Timer 719 OR Gate 720 flip-flops 721 AND Gate 722 Pre-driver 723 Gate clamp circuit 724 PMOS transistors 725 NMOS transistor 726 Resistance 727 Comparator 730 Comparator 731 Oscillator 732 Comparator 733 Arithmetic circuit 733A Processing Unit 733B Offset Generation Unit 733C resistance 734 Inverting Amplifier 735 Comparator 736 Logic Section C1~C6 capacitors CHP chips CM1~CM3 current mirror D1, D2 diodes DRV, DRV1, DRV2 drive circuit F1, F3 fuses L1 inductor L2 inductor M1 Switching transistor P1 EO Pad P2 MULT Pad P3 IS Pad P4 Test Pad PM1 PMOS transistor R1~R9 Resistors Ris Sense resistor Rp1 pull-down resistor SW1 and SW2 switches

Claims

1. 1. A control device configured to control a power factor correction circuit having a DC / DC converter, comprising: a first external terminal configured to receive a first voltage having a full-wave rectified waveform; a second external terminal configured to receive a first detection voltage as a negative voltage generated by a current flowing through a sense resistor connected to an application terminal of the power factor correction circuit to which a ground potential is applied; an error amplifier circuit configured to amplify an error between a second detection voltage corresponding to an output voltage of the DC / DC converter and a reference voltage, and generate a second voltage; an operational circuit configured to generate a third voltage by multiplying the first voltage and the second voltage; an inverting amplifier configured to invert and amplify the first detection voltage to generate a fourth voltage; a comparator configured to compare the third voltage with the fourth voltage; a drive circuit configured to drive a switching element in the power factor correction circuit on and off, and to turn off the switching element every time the fourth voltage becomes higher than the third voltage in accordance with an output of the comparator; A control device comprising:

2. 2. The control device according to claim 1, further comprising an adjustment unit configured to adjust an offset difference that is a difference between the third voltage obtained when the first voltage = 0 V and the fourth voltage obtained when the first detection voltage = 0 V.

3. The arithmetic circuit comprises: a calculation processing unit configured to receive the first voltage and the second voltage and output an output current; an offset generating unit configured to variably generate an offset current as the adjusting unit; a resistor configured to pass a current obtained by combining the output current and the offset current; The control device of claim 2 , further comprising:

4. The offset generation unit a first current mirror; and a second current mirror; and a third current mirror; and a first selection unit configured to select whether the first current mirror is enabled or disabled; a second selection unit configured to select whether the third current mirror is enabled or disabled; and 4. The control device according to claim 3, wherein the offset current is a combination of currents output from the first current mirror, the second current mirror, and the third current mirror.

5. 5. The control device according to claim 4, wherein the first selection unit and the second selection unit are fuses, and whether the first current mirror and the third current mirror are enabled or disabled is selected depending on whether the fuses are cut or not.

6. each of the first current mirror, the second current mirror, and the third current mirror has an input-side PMOS transistor and an output-side PMOS transistor; the first current mirror includes a first PMOS transistor having a source connected to the drain of the output-side PMOS transistor, the fuse connected to a high potential side of the gate of the first PMOS transistor, and a pull-down resistor connected to a low potential side of the gate of the first PMOS transistor; The control device according to claim 5 , wherein the third current mirror has the fuse connected to the drain of the output-side PMOS transistor.

7. a chip for integrating a circuit; The chip is the arithmetic processing unit; the offset generation unit; the inverting amplifier; the comparator; a first pad for applying the first voltage; a second pad for applying the first detection voltage; a test pad connected to an output terminal of the arithmetic processing unit, an output terminal of the offset generating unit, and an input terminal of the comparator; The control device of claim 3 , further comprising:

8. A power factor correction circuit comprising the control device according to any one of claims 1 to 7.

9. a rectifier circuit configured to full-wave rectify an AC voltage; An electronic device comprising: a power factor correction circuit according to claim 8 configured to receive the output voltage of the rectifier circuit.

10. 8. An offset setting method carried out in a manufacturing process of the control device according to claim 7, comprising: a first step of sweeping a test voltage to be applied to the test pad while applying a voltage of 0 V to the second pad, and measuring the test voltage when the level of the output of the comparator changes; a second step of measuring the voltage of the test pad while applying a voltage of 0 V to the first pad; a third step of adjusting the offset difference using the adjustment unit based on the measurement results of the first step and the second step; An offset setting method including:

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