Transistor

Abstract

To suppress the decrease in potential of a gate of a pull-up transistor.SOLUTION: A first transistor included in a driving circuit has a first terminal electrically connected to a second wire, a second terminal electrically connected to a first wire, and a gate electrically connected to a second circuit and a first terminal of a third transistor. A second transistor has a first terminal electrically connected to the first wire, a second terminal electrically connected to a sixth wire, and a gate electrically connected to a gate of a first circuit and the third transistor. The third transistor has a second terminal electrically connected to the sixth wire. The first circuit is electrically connected to a third wire, a fourth wire, a fifth wire, and the sixth wire. The second circuit is electrically connected to the first wire, the second wire, and the sixth wire.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] Semiconductor device, display device, liquid crystal display device, driving method thereof, or manufacturing method thereof In particular, the present invention relates to a semiconductor device, a display device, and a display device having a driver circuit formed on the same substrate as a pixel portion. The present invention relates to a liquid crystal display device or a driving method thereof, or the semiconductor device and the display device. or an electronic device having the liquid crystal display device. [Background technology]

[0002] In recent years, display devices have been actively developed due to the increase in large display devices such as LCD TVs. In particular, transistors made of non-single-crystal semiconductors are used to form a pixel portion. The technology of configuring drive circuits such as gate drivers on the board is expected to significantly reduce costs and improve reliability. Development is underway actively to contribute significantly to the

[0003] A transistor formed of a non-single-crystal semiconductor has an increased threshold voltage or a decreased mobility. If the deterioration of this transistor progresses, the drive circuit may not operate properly. Therefore, Patent Document 1 describes a The patent discloses a shift register that can suppress the deterioration of transistors. In Figure 7 of Reference 1, two transistors are used to suppress the degradation of the transistor characteristics. One transistor is connected to the output terminal of the flip-flop and VSS (hereinafter referred to as the negative power supply). The other transistor is connected between the output of the flip-flop and the wiring that supplies the The flip-flop is connected between the input terminal and the gate of the pull-up transistor. During the period when the output signal of the amplifier is at the L level, these two transistors are turned on alternately. When one of the transistors is turned on, VSS is flipped When the other transistor is turned on, the pull-up transistor The VSS supplied to the gate of the flip-flop is connected to the output of the flip-flop through the other transistor. This can prevent the transistor from deteriorating. Since VSS is always supplied to the output terminal of the flip-flop, the output signal of the flip-flop This makes it easier to maintain the L level. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-50502 Summary of the Invention [Problem to be solved by the invention]

[0005] In the configuration shown in Patent Document 1, during the period when the output signal of the flip-flop is at H level, The other transistor is turned on for a short time, The output terminal of the flip-flop is connected to the pull-up resistor for a short time. The gate potential of the flip-flop transistor is at a high potential, and the output terminal of the flip-flop The potential of the gate of the pull-up transistor is low. The objective is to increase the potential of the

[0006] Alternatively, if the potential at the gate of the pull-up transistor drops, the pull-up transistor An object of one embodiment of the present invention is to prevent a malfunction of a shift register. do.

[0007] Or the pull-up transistor will turn on and the shift register will operate normally. Even if the voltage is increased, the potential of the gate of the pull-up transistor will still decrease. In one embodiment, the potential difference (Vgs) between the gate and source of the pull-up transistor is increased. The goal is to make it easier to listen.

[0008] Or, when the Vgs of the pull-up transistor becomes smaller, the ON An object of one embodiment of the present invention is to reduce the size of a display device. Another object of one embodiment of the present invention is to provide a display device with high resolution.

[0009] Or, when the Vgs of the pull-up transistor becomes smaller, the output signal of the flip-flop The rise time or fall time of the pixel is increased. This prevents writing of incorrect signals (for example, video signals to pixels belonging to a different row) to the display. The goal is to raise the rank.

[0010] Or, if the Vgs of the pull-up transistor becomes smaller, the The channel width of the pull-up transistor needs to be increased. When the channel width of the other transistor is increased, the channel width of the other transistor also needs to be increased. Another object of the present invention is to reduce the layout area of ​​a display device. The objective is to narrow the frame.

[0011] Alternatively, when the channel width of a transistor is increased, the distance between the gate and source of the transistor increases. One aspect of the present invention is to improve the yield. Another object of one embodiment of the present invention is to reduce costs.

[0012] Alternatively, as the channel width of the transistor increases, the parasitic capacitance of the shift register increases. One aspect of the present invention is to provide a method for reducing distortion or delay in a signal input to a shift register. Another object of one embodiment of the present invention is to reduce power consumption. To improve this, a circuit that supplies signals or voltages to the shift register is used. Therefore, it is necessary to use a circuit having a large current capacity. Another object of one embodiment of the present invention is to reduce the size of a display device. The title is:

[0013] The above description of the problems does not preclude the existence of other problems. [Means for solving the problem]

[0014] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, and a third transistor. a driver circuit having a first circuit and a second circuit, and a pixel having a liquid crystal element; The first terminal of the transistor functions as a signal line or a clock signal line. The second terminal is electrically connected to the wiring of the first terminal, and the second terminal is a signal line, a gate line, a scanning line, or an output signal line. The gate is electrically connected to the first wiring having a function as a line, and the gate is connected to the second circuit and the third a first terminal of the first transistor electrically connected to the first terminal of the second transistor; The first terminal is electrically connected to the first wiring, and the second terminal functions as a power supply line or a ground line. The gate of the third transistor is electrically connected to the sixth wiring. The third transistor has a second terminal electrically connected to the sixth wiring. The second circuit includes a third wiring having a function as a signal line or a clock signal line, a fourth wiring having a function as a signal line, a fifth wiring having a function as a signal line, and The first circuit is electrically connected to the first wiring, the second wiring, and the sixth wiring. The liquid crystal display device is electrically connected to the

[0015] In one embodiment of the present invention, the first transistor is connected to a potential of the gate of the first transistor. In response, a bootstrap circuit that controls the timing at which a signal on the second wiring is supplied to the first wiring is It may also function as a transistor.

[0016] In one aspect of the present invention, the second transistor is connected to an output signal of the first circuit or A switch that controls the conduction state between the sixth wiring and the first wiring according to the potential of the gate of the transistor. It may also function as a switch.

[0017] In one embodiment of the present invention, the third transistor is connected to the sixth transistor in response to an output signal of the first circuit. The gate of the first transistor is connected to the wiring of the first transistor. It may also be the case.

[0018] In one aspect of the present invention, the first circuit is configured to: By controlling the timing of supplying the voltage of the sixth wiring to the gate of the second transistor, a function of increasing, decreasing, or maintaining the potential of the gate of the second transistor; The gate of the transistor may be in a floating state.

[0019] In one aspect of the present invention, the second circuit receives a signal supplied to the third wiring, a signal supplied to the fourth wiring, The gate of the first transistor is turned on or off in response to a signal supplied to the fifth wiring. controlling the timing of supplying the signal to the fourth wiring or the voltage to the sixth wiring; A function of increasing, decreasing, or maintaining the potential of the gate of the first transistor, or It may also function as a control circuit that sets the potential of the gate of the transistor in a floating state. .

[0020] In one embodiment of the present invention, the first circuit includes a fourth transistor, a fifth transistor, a third transistor, a fourth transistor, a fifth transistor, a fifth transistor, a sixth ... a sixth transistor and a seventh transistor, and the fourth transistor is connected to a first terminal is electrically connected to the second wiring, and the second terminal is electrically connected to the gate of the second transistor. The fifth transistor has a first terminal electrically connected to the sixth wiring and a second terminal electrically connected to the sixth wiring. The terminal is electrically connected to the gate of the second transistor, and the gate is electrically connected to the first wiring. The sixth transistor has a first terminal electrically connected to the second wiring and a second The terminal is electrically connected to the gate of the fourth transistor, and the gate is electrically connected to the second wiring. The seventh transistor has a first terminal electrically connected to the sixth wiring and a second terminal electrically connected to the sixth wiring. The terminal is electrically connected to the gate of the fourth transistor, and the gate is electrically connected to the first wiring. It may be connected.

[0021] In one embodiment of the present invention, the second circuit includes an eighth transistor, a ninth transistor, a a tenth transistor, an eleventh transistor, and a twelfth transistor; The transistor has a first terminal electrically connected to the fourth wiring and a second terminal electrically connected to the first transistor. The gate of the transistor is electrically connected to the third wiring, and the gate is electrically connected to the ninth wiring. The transistor has a first terminal electrically connected to the gate of the first transistor and a second terminal electrically connected to the gate of the second transistor. The terminal is electrically connected to the fourth wiring, the gate is electrically connected to the fourth wiring, and the tenth The transistor has a first terminal electrically connected to the gate of the first transistor and a second terminal electrically connected to the gate of the second transistor. The terminal of the first transistor is electrically connected to the sixth wiring, the gate is electrically connected to the fifth wiring, and the first The first transistor has a first terminal electrically connected to the first wiring and a second terminal electrically connected to the sixth wiring. The twelfth transistor is electrically connected to the wiring, and the gate is electrically connected to the fifth wiring. The first terminal of the capacitor is electrically connected to the first wiring, and the second terminal is electrically connected to the sixth wiring. The gate may be electrically connected to the third wiring.

[0022] In one aspect of the present invention, the driving circuit may be formed on the same substrate as the pixels. .

[0023] In one embodiment of the present invention, the channel width of the first transistor is It may be larger than the channel width of the third transistor.

[0024] The switch can be of various types. For example, an electrical switch There are various types of switches, such as switches and mechanical switches. In other words, anything that can control the flow of current is sufficient. For example, a transistor (e.g., a bipolar transistor) can be used as a switch. transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal diode, MIS (Metal Insulator Semiconductor) conductor diode, diode-connected transistor, etc. Alternatively, a logic circuit that combines these can be used as a switch.

[0025] An example of a mechanical switch is a digital micromirror device (DMD). There are switches that use MEMS (microelectromechanical systems) technology. do.

[0026] In addition, both N-channel and P-channel transistors are used to An S-type switch may be used as the switch.

[0027] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) Therefore, the predetermined connection relationship For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applied to the connections shown in the drawings or text. This also includes things other than relationships.

[0028] For example, if A and B are electrically connected, the electrical connection between A and B can be The elements that function as One or more diodes (e.g., diodes) may be connected between A and B. Alternatively, When A and B are functionally connected, a circuit (e.g. For example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits , step-down circuits, level shifter circuits that change the potential level of signals, voltage sources, current sources , switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, etc.), operational amplifiers , differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, One or more control circuits may be connected between A and B. For example, Even if there is another circuit between them, if the signal output from A is transmitted to B, then A and B are are considered to be functionally connected.

[0029] When it is explicitly stated that A and B are electrically connected, it means that A and B are electrically connected. When A and B are electrically connected (i.e., when another element or circuit is placed between A and B), A and B are functionally connected (i.e., there is no other connection between A and B) and B are functionally connected (i.e., there is no other connection between A and B). When A and B are connected functionally through a circuit) and when A and B are connected directly ( In other words, A and B are connected without any other element or circuit between them. In other words, when explicitly stating that something is electrically connected, it simply means that it is connected. is the same as if it were expressly stated only that it is

[0030] Note that a display element, a display device which is a device having a display element, a light-emitting element, a device having a light-emitting element The light emitting device can have various forms and various elements. For example, the display element, display device, light-emitting element or light-emitting device may be an EL (electroluminescent EL elements (EL elements containing organic and inorganic materials, organic EL elements, inorganic EL elements), LE D (white LED, red LED, green LED, blue LED, etc.), transistor (responding to current transistors that emit light when exposed to light, electron-emitting devices, liquid crystal devices, electronic ink, electrophoretic devices, graphene Rating light bulb (GLV), plasma display (PDP), digital microphone Chromatic mirror device (DMD), piezoelectric ceramic display, carbon nanotube, Displays whose contrast, brightness, reflectance, transmittance, etc. change due to electromagnetic effects, such as It can have a medium.

[0031] The liquid crystal element is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystal. It is an element that consists of a pair of electrodes and liquid crystal. The optical modulation action of the liquid crystal is as follows: Controlled by the electric field applied to the liquid crystal (including the horizontal electric field, vertical electric field, or diagonal electric field) The liquid crystal element is controlled by nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, Discotic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal , polymer liquid crystal, polymer dispersed liquid crystal (PDLC), ferroelectric liquid crystal, antiferroelectric liquid crystal, main chain liquid crystal Examples include side-chain polymer liquid crystals, plasma-addressed liquid crystals (PALCs), and banana-shaped liquid crystals. The liquid crystal driving method is Twisted Nematic (TN). mode, STN (Super Twisted Nematic) mode, IPS (In- Plane-Switching mode, FFS (Fringe Field Switching) mode tching) mode, MVA (Multi-domain Vertical Alignment gnment) mode, PVA(Patterned Vertical Alignm) ent) mode, ASV (Advanced Super View) mode, ASM ( Axially Symmetrically aligned Micro-cell) mode , OCB (Optically Compensated Birefringence) ) mode, ECB (Electrically Controlled Birefringence ngence) mode, FLC (Ferroelectric Liquid Crystal tal) mode, AFLC(AntiFerroelectric Liquid Cr systal mode, PDLC (Polymer Dispersed Liquid Crystal Crystal mode, guest host mode, Blue Phase mode However, the present invention is not limited to this, and the liquid crystal element and its driving method can be used. A variety of different types can be used.

[0032] The light source may be an electroluminescent, cold cathode fluorescent lamp, hot cathode fluorescent lamp, LED, or laser. However, the light source is not limited to these, and may be a laser light source, a mercury lamp, or the like. A variety of materials can be used.

[0033] The structure of the transistor can take various forms and is not limited to a specific structure. For example, a multi-gate structure with two or more gate electrodes can be applied. When the gate structure is used, the channel regions are connected in series, so multiple transistors are connected in series. The configuration is connected to:

[0034] As another example, a structure in which gate electrodes are arranged above and below the channel can be applied. do.

[0035] A structure in which a gate electrode is disposed above a channel region, and a structure in which a gate electrode is disposed below a channel region The structure in which the channel region is divided into multiple regions is also available. a structure in which the channel regions are connected in parallel, or a structure in which the channel regions are connected in series Furthermore, the channel region (or a part thereof) can be provided with a source electrode or a drain electrode. Alternatively, a structure in which an LDD region is provided can be applied.

[0036] Note that it is not explicitly stated that B is formed on A, or that B is formed on A. In the case of the above, it is not limited to B being formed on A in direct contact with it. This also includes cases where A and B are not in agreement, i.e., where another object is present between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). , etc.).

[0037] Therefore, for example, it is not possible to explicitly state that layer B is formed on top of layer A (or on top of layer A). When described, it means that layer B is formed directly on layer A, and layer A is formed on layer B. Another layer (such as layer C or layer D) is formed directly on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be formed as follows: It may be a single layer or multiple layers.

[0038] Furthermore, the same applies to cases where it is explicitly stated that B is formed above A. It is not limited to B being directly on A, and there is another object between A and B. For example, if layer B is formed above layer A, In this case, there are two cases: when layer B is formed directly on top of layer A, and when layer B is formed directly on top of layer A. Another layer (such as layer C or layer D) is formed on top of it, and layer B is formed directly on top of it. It should be noted that other layers (such as layers C and D) may be used as single layers. It may be a multi-layer structure.

[0039] In addition, B is formed on A, B is formed on A, or B is formed above A. When explicitly stating that "B" is formed, this also includes the case where B is formed diagonally above. .

[0040] The same applies to the case where B is below A, or B is below A.

[0041] In addition, it is preferable that anything explicitly stated as singular be in the singular. However, it is not limited to this, and plurals are also possible. It is preferable that the items described in the table be plural. However, this is not limited to this. It is also possible for the term to be singular.

[0042] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0043] The diagrams are merely diagrams showing ideal examples, and are not limited to the shapes or values ​​shown in the diagrams. For example, variations in shape due to manufacturing technology, variations in shape due to errors, and noise Variations in signals, voltages, or currents due to timing differences, or variations in signals, voltages, Alternatively, it is possible to include variations in current.

[0044] Note that technical terms may be used to describe specific embodiments or examples. Many, but not limited to:

[0045] In addition, undefined terms (including scientific and technical terms such as technical terms or academic terms) are generally It can be used as a meaning equivalent to the general meaning understood by a person of ordinary skill in the art. The terms defined herein shall be construed in a manner consistent with the background of the relevant art. is preferred.

[0046] It should be noted that the terms first, second, third, etc., refer to various elements, members, regions, layers, and sections as distinct from one another. Therefore, the words "first," "second," "third," etc. are used to distinguish between elements, parts, etc. It is not intended to limit the number of materials, regions, layers, areas, etc. It is possible to replace "second" or "third" etc. [Effects of the Invention]

[0047] According to one embodiment of the present invention, the potential of the gate of a transistor can be increased. According to one embodiment of the present invention, a malfunction can be prevented. Alternatively, one embodiment of the present invention can increase the Vgs of the transistor. Alternatively, one embodiment of the present invention can reduce the channel width of a transistor. Alternatively, one embodiment of the present invention can suppress or reduce deterioration of a transistor. Alternatively, one embodiment of the present invention can reduce the layout area. Alternatively, one aspect of the present invention is to use a flip-flop, a shift register, or a scanning line driver. Shortening the fall time or rise time of the output signal of a driving circuit such as a driving circuit Alternatively, according to one embodiment of the present invention, the display device can be enlarged. According to one embodiment of the present invention, a display device can have high resolution. Alternatively, one aspect of the present invention is to provide a method for providing an accurate signal to a pixel. Alternatively, in one embodiment of the present invention, display quality can be improved. Alternatively, one embodiment of the present invention can increase yield. Alternatively, one aspect of the present invention is to provide a shift register having an input terminal. Alternatively, one aspect of the present invention is to reduce distortion or delay of the signal to be transmitted. Alternatively, one embodiment of the present invention can reduce the current capacity of an external circuit. Alternatively, one aspect of the present invention is to reduce the size of an external circuit or the external circuit. The size of the display device having the path can be reduced. [Brief explanation of the drawings]

[0048] [Figure 1] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart illustrating a driving method thereof; [Figure 2] 1A to 1C are schematic diagrams illustrating a method for driving a semiconductor device. [Figure 3] 1A to 1C are schematic diagrams illustrating a method for driving a semiconductor device. [Figure 4] 10 is a timing chart illustrating a method for driving a semiconductor device. [Figure 5] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 6] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 7] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 8] 1A and 1B are a circuit diagram of a semiconductor device and a timing chart illustrating a driving method thereof; [Figure 9] 1A to 1C are schematic diagrams illustrating a method for driving a semiconductor device. [Figure 10]FIG. 1 is a circuit diagram of a semiconductor device. [Figure 11] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 12] 1A to 1C are circuit diagrams of a semiconductor device and schematic diagrams illustrating a driving method thereof. [Figure 13] 1A to 1C are schematic diagrams illustrating a method for driving a semiconductor device. [Figure 14] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 15] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 16] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 17] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 18] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 19] Circuit diagram of a shift register. [Figure 20] 10 is a timing chart illustrating a method for driving a shift register. [Figure 21] 10 is a timing chart illustrating a method for driving a shift register. [Figure 22] Circuit diagram of a shift register. [Figure 23] FIG. 1 is a system block diagram of a display device. [Figure 24] 1A and 1B illustrate a structure of a display device. [Figure 25] 1A and 1B are a circuit diagram of a signal line driver circuit and a timing chart illustrating a driving method thereof; [Figure 26] 1A and 1B are a circuit diagram of a pixel and a timing chart illustrating a driving method thereof; [Figure 27] Circuit diagram of a pixel. [Figure 28] FIG. 1 is a circuit diagram of a semiconductor device. [Figure 29] 1A and 1B are a top view and a cross-sectional view of a display device. [Figure 30] FIG. 1 is a cross-sectional view of a transistor. [Figure 31] Layout diagram of a shift register. [Figure 32] Layout diagram of a shift register. [Figure 33] 1A to 1C illustrate electronic devices. [Figure 34]1A to 1C illustrate electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0049] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention may be embodied in many different ways without departing from the spirit and scope thereof. It will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention. It should not be construed as being limited to the description of the embodiment. In the drawings, the same reference numerals are used to indicate the same parts or the same components. A detailed description of the parts having various functions will be omitted.

[0050] Note that the content (or even a part of the content) described in one embodiment may be used in conjunction with that embodiment. Other content (or even part of content) described in the above, and / or one or more other implementations The content (or part of the content) described in the form of You can do things like:

[0051] The contents described in the embodiments are explained in detail in each embodiment using various drawings. This refers to the content that is stated or the content that is stated using the text in the specification.

[0052] In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, , and many more diagrams can be constructed.

[0053] (Embodiment 1) In this embodiment, an example of a semiconductor device will be described. For example, it is used in a shift register, a gate driver, a source driver, or a display device. Note that the semiconductor device is referred to as a flip-flop or a driver circuit. It is possible.

[0054] First, an example of a semiconductor device of this embodiment will be described with reference to FIG. 1A shows a circuit 100. Note that the circuit 100 may be used as a semiconductor device, a driver circuit, or a flip-chip device. It can be shown as a p-flop.

[0055] The circuit 100 includes a transistor 101 (also referred to as a first transistor), a transistor 102 (also referred to as a second transistor), and a transistor 103 (also referred to as a third transistor). 2 (also referred to as a second transistor), and transistor 103 (also referred to as a third transistor). ), a circuit 104 (also referred to as a first circuit), and a circuit 105 (also referred to as a second circuit). The circuit 104 has terminals 104a, 104b, 104c, and 104d. The circuit 105 has a plurality of terminals, such as a terminal 105a, a terminal 105b, a terminal 105c, and a terminal The terminal 105 has a plurality of terminals, namely, a terminal 105d, a terminal 105e, and a terminal 105f. However, the present invention is not limited to the above, and any of these transistors or circuits may be omitted. Alternatively, various elements such as a capacitance element, a resistance element, or a diode, or any of these It is possible to replace it with a circuit that combines any of the elements. Various elements such as a transistor, a capacitance element, a resistance element, or a diode, or It is possible to add a new circuit that combines any of these elements. Depending on the configuration of the circuit 104 and the circuit 105, terminals may be added or omitted. It is possible.

[0056] As an example, the transistors 101 to 103 are N-channel transistors. In a channel type transistor, the potential difference between the gate and source (Vgs) is the threshold voltage (V th), the transistor is turned on. The transistors 101 to 103 can be P-channel transistors. , when the potential difference (Vgs) between the gate and source is lower than the threshold voltage (Vth), This shall be done.

[0057] As an example, as shown in FIG. 28(A), the circuit 104 is a two-input AND and NOT This combinational logic circuit is a logic circuit that combines one input signal and the other. The other input signal (for example, the signal on the wiring 113) is inverted. However, the present invention is not limited to this, and the circuit 104 may be implemented as shown in FIG. As shown in FIG. 8(B), a two-input NOR can be used. As the circuit, various circuits can be used.

[0058] For example, the circuit 104 and the circuit 105 each include one or more transistors. The polarities of these transistors are transistors 101 to 103. By making the polarity of the transistors the same, This can reduce the number of steps, improve yield, improve reliability, or reduce costs. However, the circuit 104 and the circuit 105 are not limited to this, and may be an N-channel transistor and a P-channel transistor. In other words, the circuits 104 and 105 can have a can be a CMOS circuit.

[0059] As an example, the terminals 104a to 104c function as input terminals, and the terminal 104d functions as As an example, the terminals 105a to 105d function as output terminals. 105e and 105f function as input terminals, and terminals 105e and 105f function as output terminals. However, this is not limited to the above.

[0060] It should be noted that the circuit 104 and / or the circuit 105 may have more terminals. Alternatively, the circuit 104 and / or the circuit 105 may omit some of the terminals. be.

[0061] Next, an example of the connections in the circuit 100 will be described. The first terminal of the transistor 101 is connected to a wiring 112, and the second terminal of the transistor 101 is connected to a wiring 111. The first terminal of the transistor 102 is connected to the wiring 116. The second terminal of the transistor 103 is connected to the wiring 111. 6, and the second terminal of transistor 103 is connected to the gate of transistor 101. The gate of the transistor 103 is connected to the gate of the transistor 102. A terminal 104a of the circuit 104 is connected to the wiring 112, and a terminal 104b of the circuit 104 is connected to the wiring 113. 11, and the terminal 104c of the circuit 104 is connected to the wiring 116. The terminal 104d is connected to the gate of the transistor 102. The terminal 105a of the circuit 105 is , the terminal 105b of the circuit 105 is connected to the wiring 114, and the terminal 105c of the circuit 105 is connected to the wiring 114. A terminal 105c of the circuit 105 is connected to the wiring 115, and a terminal 105d of the circuit 105 is connected to the wiring 11 6, and the terminal 105e of the circuit 105 is connected to the gate of the transistor 101. A terminal 105f of the circuit 105 is connected to a wiring 111. However, this is not limitative and other Various connection configurations are possible.

[0062] Note that the gate of the transistor 101, the second terminal of the transistor 103, or the The connection point of the terminal 105e of the transistor 105 is indicated as node A. The terminal 104d of the circuit 104 or the connection point of the gate of the transistor 103 is connected to the node B. Note that the node A and the node B can be represented as wiring or terminals.

[0063] The wiring 111, the wiring 112, the wiring 113, the wiring 114, the wiring 115, and the wiring 116 can be designated as a terminal.

[0064] As already mentioned, new terminals are added to the circuit 104 and / or the circuit 105. In such a case, the terminal may be connected to various wires or various elements. It is possible to continue.

[0065] It should be noted that any of the wirings 111 to 116 may be omitted and / or new wiring may be added. is possible.

[0066] Next, an example of the signals or voltages input to or output from the wirings 111 to 116 will be described. As an example, a signal OUT is output from the wiring 111. The signal OUT is H In many cases, the output signal of the circuit 100 is a digital signal having a high level and a low level. Functions as a select signal, transfer signal, start signal, reset signal, gate signal, or scan signal For example, a signal IN1 is input to the wiring 112. The signal IN1 is often a digital signal and can function as a clock signal. It is possible. As an example, a signal IN2 is input to the wiring 113. N2 is the inverted signal of signal IN1 or a signal that is 180° out of phase with signal IN1. In many cases, the wiring 114 can function as an inverted clock signal. The signal IN3 is assumed to be input as a digital signal. It can also function as a start signal or vertical synchronization signal. If 00 is used in a shift register or display device, signal IN3 is It can function as a transfer signal from a row (stage) or a signal to select another row (for example, the previous row). As an example, a signal IN4 is input to the wiring 115. 4 is often a digital signal and can function as a reset signal. Alternatively, if circuit 100 is used in a shift register or display device, signal IN4 may be The wiring 116 can function as a signal for selecting the next row (for example, the next row). As an example, a voltage V1 is input. The voltage V1 is a signal OUT at a low level. It may be approximately equal to the value of the signal IN1, the signal IN2, the signal IN3, or the signal IN4. It can often function as a ground voltage, a power supply voltage, or a negative power supply voltage. However, the wirings 111 to 116 are not limited to this, and various other signals, currents, or It is possible to input various voltages. For example, the wiring 112, the wiring 113, the wiring 114 and / or the wiring 115 may be supplied with a voltage such as voltage V1 or voltage V2. Alternatively, the wiring 116 may be connected to the signal OUT, the signal IN1, the signal IN2, the signal IN3, or Signals such as signal IN4 can be input to the wiring 111 and the wiring 11. 2. Signals or voltages are applied to the wiring 113, wiring 114, wiring 115, and / or wiring 116. It is possible to leave these wires floating without inputting

[0067] The term "generally" refers to errors due to noise, process variations, and the manufacturing process of the element. This includes various errors such as errors due to variations in process and / or measurement errors.

[0068] The wiring 111 (also referred to as a first wiring) is a signal line, a gate line, a scanning line, or an output signal line. The wiring 112 (also referred to as a second wiring) can function as a signal line or The wiring 113 (also referred to as the third wiring) can function as a clock signal line. The wiring 114 (fourth The wiring 115 (also referred to as the fifth wiring) can function as a signal line. The wiring 116 (also referred to as the sixth wiring) can function as a signal line. ) can function as a power supply line or a ground line. However, it is not limited to this. In addition, the wirings 111 to 116 can also function as various other wirings. For example, a voltage is supplied to the wiring 112, the wiring 113, the wiring 114, and / or the wiring 115. In this case, these wirings can function as power supply lines. When a signal is input, the wiring 116 can function as a signal line. Alternatively, the wiring 114 and / or the wiring 115 may be used as a signal line, a gate line, or the like, similarly to the wiring 111. , scanning lines, or output signal lines.

[0069] It is possible to input a multi-phase clock signal to the circuit 100. For example, n( When referring to a clock signal with n phases (n is a natural number), the n-phase clock signal has a period of 1 It is a set of n clock signals that are shifted by 1 / n periods. Any two of these can be input to wiring 112 and wiring 113, respectively.

[0070] It is possible to use a balanced clock signal as the signal IN1 or the signal IN2. It is also possible to use unbalanced (also called unbalanced) clock signals. In one cycle, the period when the signal is at H level and the period when the signal is at L level are equal. Equilibrium means that the period during which the signal is at the H level differs from the period during which the signal is at the L level within one cycle. .

[0071] As an example, let V1 be the potential of the L level signal and V2 be the potential of the H level signal. And, V2>V1. And, when we refer to voltage V2, it means The voltage V2 is approximately equal to the H level of the signal. However, it is not limited to this. The potential of the L-level signal can be lower than V1 or higher than V1. Alternatively, the potential of the H-level signal may be lower than V2. , it is possible that it is higher than V2.

[0072] Next, examples of functions of the transistors 101 to 103 and the circuits 104 and 105 will be described. I will explain.

[0073] The transistor 101 outputs an H-level signal IN1 to the wiring 111 in response to the potential of the node A. By controlling the timing of the supply, the timing when the signal OUT becomes H level can be controlled. It has the function of controlling the The transistor 102 can function as an output signal of the circuit 104 or a node. By controlling the conduction state between the wiring 116 and the wiring 111 according to the potential of the node B, It has a function of controlling the timing of supplying voltage V1 to line 111 and functions as a switch. The transistor 103 receives an output signal from the circuit 104 or a voltage at the node B. By controlling the conduction state between the wiring 116 and the node A according to the potential, the node A is supplied with a current. It has the function of controlling the timing of supplying pressure V1 and can function as a switch is.

[0074] The circuit 104 outputs the signal IN3 or the voltage V1 to the node B in response to the signal OUT or the signal IN1. By controlling the timing of supplying the voltage, the voltage of the node B can be increased, decreased or maintained. It has a function to maintain the node B or a function to make the node B floating, and can function as a control circuit. The circuit 104 controls the potential of the node B to It is possible to have a function of controlling the conduction state of the transistor 102 and the transistor 103. For example, when the signal IN2 becomes low, the circuit 104 outputs the voltage V1 or the low-level signal By supplying IN2 to node B, the potential of node B is decreased. As another example, when the signal OUT becomes H level, the circuit 104 outputs a voltage V1 or a voltage V2 of L level. By supplying a signal to node B, the potential of node B is decreased. For example, when the signal OUT is at L level and the signal IN2 becomes H level, the voltage V2 Alternatively, by supplying a high-level signal IN2 to the node B, the potential of the node B is increased. It has the function of

[0075] The circuit 105 outputs a signal I to the node A in response to the signal IN2, the signal IN3, or the signal IN4. By controlling the timing of supplying N3 or voltage V1, the potential of node A is increased. , decrease, or maintain the voltage of the node A, or make the node A floating. Alternatively, the circuit 105 may function as a By controlling the timing of supplying the voltage V1 to the wiring 111 in response to the signal IN4, The potential of the wiring 111 is reduced or maintained, or the wiring 111 is brought into a floating state. For example, when the signal IN2 or the signal IN3 becomes H level, the circuit 105 By supplying a signal IN3 of a low level or a voltage V2 to node A, the potential of node A is As another example, the circuit 105 has a function of raising the voltage when the signal IN2 or the signal IN4 is H. When the voltage V1 or the L level signal is supplied to the node A or the wiring 111, This has the function of decreasing the potential of the node A or the potential of the wiring 111.

[0076] However, the present invention is not limited to this, and the transistors 101 to 103 and the circuits 104 to 105 may be These elements or circuits may have various other functions. It is possible that the function is not provided.

[0077] Next, the operation of the semiconductor device of FIG. 1(A) will be described with reference to FIGS. 1(B), 2(A), and 2(B). ), 2(C), 3(A) and 3(B). FIG. 1(B) is an example of a timing chart for explaining the operation of the device. The potential Va of the signals IN1, IN2, IN3, and IN4 and the node A during the operation period , the potential Vb of the node B, and the signal OUT. One operating period in the chart includes periods T1, T2, T3, T4, and T5. FIG. 2A is an example of a schematic diagram of the operation of the semiconductor device in FIG. 1A during the period T1. FIG. 2B is an example of a schematic diagram of the operation of the semiconductor device in FIG. 1A during the period T2. FIG. 2C is an example of a schematic diagram of the operation of the semiconductor device in FIG. 1A during the period T3. FIG. 3A is an example of a schematic diagram of the operation of the semiconductor device in FIG. 1A during the period T4. FIG. 3B is an example of a schematic diagram of the operation of the semiconductor device in FIG. 1A during the period T5. be.

[0078] As an example, when the signal IN3 becomes H level, the semiconductor device of FIG. The operation in period T1, the operation in period T2, and the operation in period T3 are performed in this order. After that, the semiconductor device of FIG. 1A remains in the ON state until the signal IN3 becomes H level again. The operation in the period T4 and the operation in the period T5 are repeated in sequence. However, the semiconductor device of FIG. 1A may operate in various ways in the periods T1 to T5. It is possible to do this in any order.

[0079] First, during a period T1, the signal IN1 goes to the L level, and the signal IN2 goes to the H level. Signal IN3 goes high and signal IN4 goes low. Therefore, the circuit 105 starts to increase the potential of the node A. At this time, the signal IN1 goes low. As this signal reaches the threshold, circuit 104 begins to decrease the potential at node B to V1. As a result, the transistor 102 and the transistor 103 are turned off, and the wiring 116 and the wiring The wiring 116 and the node A are brought into a non-conductive state. The potential of the node A is equal to the potential of the wiring 112 (V1) and the threshold voltage of the transistor 101 (Vth1 When the sum of V1 and Vth101 is reached (V1 + Vth101), transistor 101 turns on. Then, the wiring 112 and the wiring 111 are brought into a conductive state, and the signal IN1 at L level is The signal is supplied from the wiring 112 to the wiring 111 through the transistor 101. Since the potential of the node 1 becomes V1, the signal OUT becomes L level. The potential of node A continues to rise. Then, the circuit 105 raises the potential of node A to a certain extent. When the voltage rises to the value of V1+Vth101 (at least V1+Vth101), the signal to node A Or the voltage supply is stopped. Therefore, the node A is at the potential (for example, V1+Vth1) at this time. The player will become levitating while maintaining their current level (01 or higher).

[0080] Note that during the period T1, the circuit 105 applies the voltage V1 or an L-level signal to the wiring 111. However, the circuit 105 is not limited to this. By not supplying a signal or the like, the circuit 105 and the wiring 111 are brought into a non-conductive state. is possible.

[0081] Next, during a period T2, the signal IN1 goes to the H level, and the signal IN2 goes to the L level. The signal IN3 goes low and the signal IN4 remains low. In many cases, a signal is not supplied to node A, so node A is The potential (V1+Vth101 or more) is maintained and the transistor remains floating. Since the transistor 101 remains on, the wiring 112 and the wiring 111 remain in a conductive state. At this time, the signal IN1 rises from L level to H level, so that the voltage of the wiring 111 The potential starts to rise from V1. Then, since node A is in a floating state, The potential rises due to the parasitic capacitance between the gate and the second terminal of the transistor 101 . This is the so-called bootstrap operation. In this way, the potential of node A becomes V2+Vth10 The potential of the wiring 111 rises to 1+α (α is a positive number). Then, the potential of the wiring 111 rises to H level. The potential of the signal O rises to V2, so the signal OUT goes to H level. Since UT becomes H level, the circuit 104 applies a voltage V1 or a signal of L level to the node B. Therefore, the potential of node B is maintained at V1 by supplying 2 and the transistor 103 remain off, so that the wiring 116 and the wiring 111 are not electrically connected. The wiring 116 and the node A remain in a non-conductive state.

[0082] Note that during the period T2, the circuit 104 does not supply a signal or a voltage to the node B. By this, it is possible to put the circuit 104 and the node B into a non-conductive state. 104 can make the node B floating. In this case, the node B is still floating. state, the potential of node B is often maintained at V1.

[0083] Note that during the period T2, the circuit 105 does not supply a signal or a voltage to the wiring 111. This makes it possible to bring the circuit 105 and the wiring 111 into a non-conductive state. Without being limited to this, the circuit 105 may supply a voltage V2 or an H-level signal to the wiring 111. It is possible to do this.

[0084] Next, during a period T3, the signal IN1 goes to the L level, the signal IN2 goes to the H level, The signal IN3 remains at L level, and the signal IN4 goes to H level. Since the potential of node A becomes V1, the circuit 105 decreases the potential of node A to V1. Since the transistor 101 is turned off, the wiring 112 and the wiring 111 are not electrically connected to each other. Here, the potential of node A is controlled by a voltage or signal supplied via circuit 105. Therefore, the timing at which the transistor 101 is turned off is the timing at which the signal IN1 becomes L level. In other words, when the transistor 101 is on, In this case, the signal IN1 at the L level is applied to the wiring 11 2 to the wiring 111 through the transistor 101. Since the voltage V is V1, the signal OUT goes low. At this time, the signal IN1 is low, so Then, the circuit 104 supplies a low level signal IN2 or a low level voltage V1 to the node B. Therefore, the potential of the node B is maintained at V1. Since 103 remains off, the wiring 116 and the wiring 111 remain in a non-conductive state. The wiring 116 and the node A remain in a non-conductive state.

[0085] During the period T3, the circuit 104 does not supply a signal or a voltage to the node B. By this, it is possible to put the circuit 104 and the node B into a non-conducting state. 104 can make the node B floating. In this case, the node B is still floating. state, the potential of node B is often maintained at V1.

[0086] Note that during the period T2, the circuit 105 supplies the voltage V1 or an L-level signal to the wiring 111. Alternatively, the circuit 105 can supply a voltage, a signal, or the like to the wiring 111. By not providing the wiring 111, the circuit 105 and the wiring 111 can be brought out of electrical continuity. do.

[0087] Next, during a period T4, the signal IN1 goes to the H level, the signal IN2 goes to the L level, The signal IN3 remains at L level, and the signal IN4 goes to L level. Since the signal IN1 remains at the H level while the signal IN2 remains at the H level, the circuit 104 By supplying voltage V2 to node B, the potential of node B is raised to V2. Then, the transistor 102 and the transistor 103 are turned on, and the wiring 11 6 and the wiring 111 are brought into electrical continuity, and the wiring 116 and the node A are brought into electrical continuity. , the voltage V1 is supplied from the wiring 116 to the wiring 111 via the transistor 102, The potential of the wiring 111 is maintained at V1. The voltage V1 is applied from the wiring 116 to the transistor Since the voltage V is supplied to node A via 103, the potential of node A is maintained at V1. Therefore, the signal OUT remains at the L level.

[0088] Note that the circuit 105 supplies a voltage V1 or an L-level signal to the wiring 111 or the node A. Alternatively, the circuit 105 may transmit a voltage or a signal to the wiring 111 or the node. By not supplying a voltage to node A, it is possible to put the circuit 105 and node A into a non-conductive state. Therefore, the circuit 105 and the wiring 111 can be brought out of electrical continuity.

[0089] Next, during a period T5, the signal IN1 goes to the L level, the signal IN2 goes to the H level, The signal IN3 remains at the L level, and the signal IN4 remains at the L level. Since the signal IN1 or voltage V1 is at the L level, the circuit 104 supplies the signal IN1 or voltage V1 at the L level to the node B. By supplying V, the potential at node B is decreased to V1. Since the transistor 102 and the transistor 103 are turned off, the wiring 116 and the wiring 111 are not conductive. The wiring 116 and the node A are brought into a non-conductive state. If a signal of V1 or L level is supplied to the wiring 111 or the node A, Alternatively, the potential of the node A is maintained at V1. Even if no supply is made to the line 111 or the node A, the potential of the line 111 or the node A is V 1 because the wiring 111 and the node A are in a floating state. This is because the potential (V1) at 4 is maintained. Thus, the signal OUT remains at the L level. This becomes:

[0090] The operation of the semiconductor device in FIG. In the period T2, the potential of the node A can be prevented from decreasing. During the period T2, the potential of the wiring 111 rises to a certain value until the potential of the wiring 111 rises to a certain value. 11 was in a conducting state. Therefore, the potential of node A decreased. However, as shown in FIG. In the semiconductor device of A), the node A and the wiring 111 are not in a conductive state during the period T2. Therefore, the potential of the node A can be prevented from decreasing. It is possible to prevent a decrease in Vgs of the transistor 101. Or, the potential of node A may be reduced too much to prevent malfunction. Alternatively, a decrease in Vgs of the transistor 101 can be prevented. Therefore, the channel width (W) of the transistor 101 can be reduced. Alternatively, the Vgs of the transistor 101 can be increased. Therefore, the on-resistance of the transistor 101 can be reduced. This reduces the fall time or rise time of the signal OUT, or delays the signal OUT. It is possible to reduce this.

[0091] Alternatively, in the semiconductor device of FIG. 1A, the polarity of all the transistors may be changed to N-channel or P-channel. Therefore, the number of processes can be reduced, the yield can be improved, and reliability can be improved. In particular, all transistors are N-channel. In the case of the monocrystalline type, the semiconductor layer of the transistor can be made of non-single-crystal semiconductor, microcrystalline semiconductor, or organic semiconductor. Therefore, it is possible to reduce the number of steps and improve the yield. This may improve the quality, reliability or reduce costs, but is not limited to these. First, the semiconductor device of FIG. 1A has a P-channel transistor and an N-channel transistor. It is possible to have a CMOS circuit composed of transistors. A single crystal semiconductor or a polycrystalline semiconductor can be used for the semiconductor layer of the transistor.

[0092] Alternatively, in the semiconductor device of FIG. 1A, during at least one of the periods T4 and T5, Therefore, the transistors 101 to 103 are turned off during one operation period. Since the transistor is not always on during operation, there are problems with the transistor such as an increase in threshold voltage or a decrease in mobility. In particular, the semiconductor layer of a transistor can be made of a non-single crystal. When a semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used, However, in the semiconductor device shown in FIG. 1(A), the transistor This can suppress the deterioration of transistor characteristics, so it is suitable for use as a non-single layer in transistors. It is easy to use a crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. However, the semiconductor layer is not limited to this, and may be a polycrystalline semiconductor or a single crystal semiconductor. It is possible to use.

[0093] Note that the period T2 is designated as the selection period, and the other periods (period T1, period T3, period T4, and Periods T1, T2, and T5 can be designated as non-selection periods. The periods T3, T4, and T5 are respectively referred to as a set period, an output period, a reset period, and a first This can be referred to as the non-selection period and the second non-selection period.

[0094] In the example of the timing chart of FIG. 1(B), the signals IN1 and IN2 are balanced. As already mentioned, the signal IN1 and the signal The signal IN2 can be unbalanced. In this example, the time when the signal IN1 (or signal IN2) becomes H level and the time when the signal IN1 (or signal IN2) becomes H level are IN2) are at L level for approximately the same time, that is, when the time when signals IN1 and IN Although the duty ratio of the second pulse is approximately 50%, the present invention is not limited to this. The duty ratio of the signal IN1 and the signal IN2 can be 50% or more; 4A shows that the signal IN1 and the signal IN2 are non-uniform. Timing when the duty ratio of signals IN1 and IN2 is not 50% In the timing chart of FIG. 4A, in the period T2, the signal I When N1 goes high, the voltage at node A rises due to the bootstrap operation, and the signal OUT becomes H level. After that, signal IN1 becomes L level. At the same time, or with a slight delay, the potential at node A decreases to V1. In other words, the transition occurs simultaneously with or a little later than the signal IN1 becoming L level. However, in the timing chart of FIG. 4(A), the signal IN4 The potential of node A remains high until the signal IN1 goes high or until the signal IN2 goes high. In other words, even after the signal IN1 becomes low level, the transistor 101 remains on. Therefore, the wiring 112 and the wiring 111 remain in a conductive state, and the L level signal IN1 is supplied from the wiring 112 to the wiring 111 via the transistor 101. Since the channel width (W) of the transistor 101 is large in most cases, the potential of the wiring 111 is Therefore, the fall time of the signal OUT can be shortened.

[0095] In FIG. 4(A), one period of signal IN1 is denoted as period Tck. And, the period during which signal IN1 is at the H level within one period is denoted as period Tck(H), and the period during which signal IN1 is at the L level within one period is denoted as period Tck(L). Similarly, one period of signal IN2 is denoted as period Tckb. And, the period during which signal IN2 is at the H level within one period is denoted as period Tckb(H), and the period during which signal IN2 is at the L level within one period is denoted as period Tckb(L). The relationship between period Tck and period Tckb, the relationship between period Tck(H) and period Tckb(H), and the relationship between period Tck(L) and period Tckb(L) are often Tck≒Tckb, Tck(H)≒Tckb(H), and Tck(L)≒Tckb(L), respectively. However, it is not limited to this. Among them, the period during which signal IN1 is at the H level is denoted as period Tck(H), and the period during which signal IN 1 is at the L level is denoted as period Tck(L). Similarly, one period of signal IN2 is denoted as period Tckb. And, the period during which signal IN2 is at the H level within one period is denoted as period Tckb (H), and the period during which signal IN2 is at the L level within one period is denoted as period Tckb(L) is shown. The relationship between period Tck and period Tckb, the relationship between period Tck(H) and period Tckb(H), and the relationship between period Tck(L) and period Tckb(L) are often Tck≒Tckb, Tck(H)≒Tckb(H), and Tck(L)≒Tckb(L), respectively. However, it is not limited to this. However, it is not limited to this.

[0096] In FIG. 4(A), the relationship between period Tck(H) and period Tck(L) is preferably Tck( H)<Tck(L). Similarly, the relationship between period Tckb(H) and period Tckb (L) is preferably Tckb(H)<Tckb(L). By doing so, as described above, the falling time of signal OUT can be shortened. However, it is not limited to this, and it is possible that Tck(H)>Tck(L), and it is possible that Tc kb(H)>Tckb(L). However, it is not limited to this, and it is possible that Tck(H)>Tck(L), and it is possible that Tckb(H)>Tckb(L).

[0097] As shown in the timing chart of FIG. 4(A), it is possible to set signal OUT to the L level during period T2. To achieve this, during period T2, signal IN 4 is set to the H level. Then, the circuit 100 in FIG. 1(A) forcibly operates during period T3, or During period T2, signal IN4 is set to the H level. Then, the circuit 100 in FIG. 1(A) forcibly operates during period T3, or First, the signal IN4 goes to H level, so the circuit 105 , the node A and the wiring 111 are supplied with a voltage V1 or a signal at an L level. The potentials of the node A and the wiring 111 are decreased to V1. Then, the signal OUT becomes L level, and the signal IN1 remains H level. Therefore, the circuit 104 supplies the H-level signal IN1 to the node B, as in the period T4. As a result, the potential of the node B is set to V2. Since the starter 103 is turned on, the wiring 116 and the wiring 111 are brought into a conductive state, and the wiring 116 and the wiring 111 are brought into a conductive state. Therefore, the voltage V1 is applied from the wiring 116 to the transistor 102. The potential of the wiring 111 is maintained at V1. V1 is supplied to node A from wiring 116 through transistor 103, so that node A At this time, the potential of node A is V1, so the potential of transistor 101 is turned off. Therefore, the wiring 112 and the wiring 111 are not electrically connected. The period during which the signal OUT is at H level is shorter than the period during which the signal IN1 is at H level. As a result, the time when the signal IN1 is at H level and the time when the signal OUT is at H level can be shortened. The driving frequency is slower than when the time to reach the peak is roughly the same. It is possible to reduce power consumption.

[0098] For example, among the transistors 101 to 103 or Among the transistors included in the semiconductor device, the transistor 101 has the largest channel width. This reduces the on-resistance of the transistor 101. Therefore, the rise time or fall time of the signal OUT can be shortened. However, the channel width of the transistor 101 is not limited to this. It is possible for the MOSFET to be smaller than either of the transistors.

[0099] When referring to the channel width of a transistor, this is expressed as the W / L (W: channel This can be rephrased as the ratio of the channel width (L: channel length).

[0100] For example, the channel width of the transistor 102 is It is preferable that the length is larger than the width because the wiring 111 is connected to the gate line or the pixel. Therefore, the load on the wiring 111 is often larger than the load on the node A. The transistor 102 has a function of supplying a voltage V1 to the wiring 111. This is because the transistor 103 has the function of supplying the voltage V1 to the node A. However, the channel width of the transistor 102 is not limited to this. It is possible that the width of the channel is smaller than the width of the channel.

[0101] As an example, in the transistor 101, a parasitic capacitance between the gate and the second terminal is is preferably larger than the parasitic capacitance between the gate and the first terminal, because the period At T2, the voltage of node A tends to become higher due to the bootstrap operation. Therefore, a conductive layer that functions as a gate and a conductive layer that functions as a source or drain are Preferably, the area of ​​the conductive layer overlapping the second terminal side is larger than that of the first terminal side. However, it is not limited to this.

[0102] It is possible to divide the wiring into multiple wirings. The same signal or voltage can be input, or different signals or voltages can be input. Alternatively, the multiple wirings can be connected to the same wiring or the same element. Alternatively, the multiple wires may be connected to separate wires or separate elements. In the example of FIG. 5(A), the wiring 112 is divided into a plurality of wirings 112A to 112B. 1 shows a configuration in which the wiring 116 is divided into a plurality of wirings 116A to 116D. The first terminal of the transistor 101 is connected to the wiring 112A and the terminal 104 of the circuit 104. The first terminal of the transistor 102 is connected to a wiring 116A. The first terminal of the transistor 103 is connected to the wiring 116B, and the second terminal of the circuit 104 is connected to the wiring 116C. 104c is connected to a wiring 116C, and a terminal 105d of the circuit 105 is connected to a wiring 116D. However, the present invention is not limited to this, and the wiring 111, the wiring 113, the wiring 114, and / or The wiring 115 can be divided into multiple wirings. Alternatively, the wiring 112 and the wiring 116 can be It is possible to divide only one of the above into multiple wirings.

[0103] In FIG. 5A, the wirings 112A to 112B correspond to the wiring 112 in FIG. Therefore, it is possible to input the signal IN1 to the wirings 112A to 112B. The wirings 112A to 112B can function as signal lines or clock signal lines. However, the present invention is not limited to this, and the wirings 112A to 112B may be supplied with a voltage V1 or a voltage V2. Any voltage can be supplied, and the wirings 112A to 112B function as power supply lines. Alternatively, the wirings 112A and 112B may carry different signals or different voltages. Alternatively, various other signals can be input to the wirings 112A to 112B. It is possible to input a signal, a different voltage, or a different current.

[0104] In FIG. 5A, the wirings 116A to 116D correspond to the wiring 116 in FIG. Therefore, it is possible to supply the voltage V1 to the wirings 116A to 116D. The lines 116A to 116D can function as power supply lines. The wirings 116A to 116D are not connected to the signal OUT or the signals IN1 to IN4. Signals can be input, and the wirings 116A to 116D function as signal lines. Alternatively, different voltages or different signals may be applied to the wirings 116A to 116D. Alternatively, various other signals can be input to the wirings 116A to 116D. , various voltages, or various currents can be input.

[0105] Note that in FIG. 5A, the wirings 116A and 116B are For example, a signal that becomes an L level can be input to the wiring 116A and the wiring 11 In this case, as shown in FIG. 5(B), the signal IN2 can be input to the input terminal 6B. The first terminal of the transistor 102 and the first terminal of the transistor 103 are connected to the wiring 113 Thus, the transistor 102 and the transistor 10 3 can be reverse biased, so that transistor 102 and transistor 1 However, the present invention is not limited to this, and the deterioration of the characteristics of the wiring 116A and the wiring 116B can be mitigated. A signal IN2 is input to one of the wirings 116A and 116B, and only one of the wirings 116A and 116B is connected. It can be connected to the wiring 113. Alternatively, it can be connected to the wiring 116A and / or the wiring 116B. 16B can be input with the signal OUT, the signal IN3, the signal IN4, or other signals. In this case, the first terminal of the transistor 103 and / or the first terminal of the transistor 10 The first terminal of the second transistor can be connected to the wiring 111, the wiring 114, or the wiring 115. Alternatively, the signal OUT, the signal IN2, the signal It is possible to input the signal IN3, the signal IN4, or other signals. The terminal 104c of the circuit 104 and / or the terminal 105d of the circuit 105 are connected to the wiring 111 and the wiring 112. 13, wiring 114, or wiring 115.

[0106] As shown in FIG. 6A, a capacitor is provided between the gate and the second terminal of the transistor 101. By doing so, in the period T2, During the bootstrap operation, the potential of node A can be increased. Since the Vgs of the transistor 101 becomes large, the fall time or rise time of the signal OUT becomes large. However, the present invention is not limited to this, and the capacitance element 121 may be It is possible to use a transistor as a MOS capacitor. In this case, the MOS capacitor To increase the capacitance of the transistor used, the gate of the transistor is connected to node A. and the first terminal or the second terminal of the transistor is connected to the wiring 111. It is preferable.

[0107] 6(A), in FIGS. 5(A) and 5(B), the gate of the transistor 101 is A capacitor 121 can be newly connected between the first terminal and the second terminal. A transistor having a first terminal and a second terminal connected to the wiring 111 and a gate connected to the node A. It is possible to add a new transistor.

[0108] As shown in FIG. 6B, the first terminal is connected to the wiring 111, and the second terminal is connected to the A transistor 122 is newly added, the gate of which is connected to the wiring 112. The polarity of the transistor 122 is the same as that of the transistors 101 to 103. It is preferable that the ion channel is N-channel, and in many cases, it is N-channel. However, it is not limited to this. The polarity of the transistor 122 can be a P-channel type. 2 controls the timing at which the node A and the wiring 111 are brought into a conductive state in response to the signal IN2. The transistor 122 has a function of switching on and off, and can function as a switch. During time T4, it is turned on, bringing node A and the wiring 111 into a conductive state.

[0109] As in FIG. 6(B), the first end The first terminal is connected to the wiring 111, the second terminal is connected to the node A, and the gate is connected to the wiring 112. It is possible to add a new transistor 122 connected to the input.

[0110] As shown in FIG. 6C, the transistor 103 can be omitted. In this case, node A is often in a floating state during period T4. Therefore, the transistor 102 can be omitted. In this case, in the period T4, In many cases, the wiring 111 is in a floating state. By omitting either 103 or 104, the number of transistors can be reduced. This makes it possible to reduce the layout area and improve the yield.

[0111] As in FIG. 6(C), in FIGS. 5(A) to 5(B) and 6(A) to 6(B), The transistor 102 or the transistor 103 can be omitted. In (B), it is preferable to omit either the transistor 102 or the transistor 103. This is because in FIG. 6B, the node A and the wiring 111 are in a conductive state during the period T4. Therefore, the node A or the wiring 111 is not in a floating state.

[0112] As shown in FIG. 7A, the transistor 102 is connected to one terminal (hereinafter also referred to as the positive electrode). The first terminal of the first transistor is connected to the wiring 111, and the second terminal (hereinafter also referred to as the negative terminal) is connected to the node B. Alternatively, the transistor 103 can be replaced with a diode 102a. One terminal (hereinafter also referred to as the positive terminal) is connected to node A, and the other terminal (hereinafter also referred to as the negative terminal) is connected to node B. This can be replaced with a diode 103a connected to node B. In this case, the circuit 104 decreases the potential of the node B to V1 during the period T4. During periods T1, T2, and T5, the potential of node B is increased to V2. However, the present invention is not limited to this, and the transistors 102 and 103 may be It is possible to replace only one of the diodes with a diode. and / or a diode 103a can be newly added.

[0113] As in FIG. 7(A), in FIGS. 5(A) to 5(B) and 6(A) to 6(C), The transistor 102 has one terminal connected to the wiring 111 and the other terminal connected to the node B. Alternatively, the transistor 10 can be replaced by a diode 102a connected to the 3 is a diode with one terminal connected to node A and the other terminal connected to node B. Alternatively, the diode 102a and / or the diode 103a may be replaced. A new diode 103a can be added.

[0114] Although not shown, FIGS. 1(A), 5(A) to 5(B), 6(A) to 6(C), and In 7(A), the transistor 102 or the transistor 103 is diode-connected. In this case, the first terminal of the transistor 102 is connected to the node B, The second terminal of the transistor 102 is connected to the wiring 111. The first terminal of the transistor 103 is connected to a node B or a wiring 111. The second terminal of the transistor 103 is connected to node B, and the second terminal of the transistor 104 is connected to node A. The gate of the inverter 103 is connected to the node A or the node B. However, this is not limiting. Only one of the transistors 102 and 103 can be diode-connected. be.

[0115] As shown in FIG. 7B, the terminal 104b of the circuit 104 is connected to the node A. By doing so, during the period T2, the terminal 104b of the circuit 104 This prevents an L-level signal from being input to the node B, so the potential of node B is maintained at V1. Therefore, the potential of the node B rises instantaneously, and the transistor 102 and the transistor This can prevent the transistor 103 from turning on.

[0116] As with FIG. 7(B), FIGS. 5(A) to 5(B), 6(A) to 6(C), and 7(A) In this case, the terminal 104b of the circuit 104 can be connected to the node A.

[0117] As shown in FIG. 7C, the circuit 105 can be omitted.

[0118] As with FIG. 7(C), FIGS. 5(A) to 5(B), 6(A) to 6(C), and 7(A) In the cases 1 to 3, the circuit 105 can also be omitted.

[0119] As shown in FIG. 28B, the terminal 104a of the circuit 104 is connected to the wiring 113. However, the terminal 104a of the circuit 104 is not limited to this. It is possible to connect to various wirings, terminals, or nodes. Similarly, in Figs. 5(A)-(B), 6(A)-(C), and 7(A)-(B), A terminal 104 a of the circuit 104 can be connected to a wiring 113 .

[0120] As shown in FIG. 8A, the transistors 101 to 103 are P-channel transistors. It is possible to use transistors 101p, 102p, and The transistors 101, 102, and 103p are respectively 8B, the transistor 103 corresponds to the P-channel type. When the polarity of the transistor is P-channel, a voltage V2 is supplied to the wiring 116, and the signals OUT and Signal IN1, signal IN2, signal IN3, signal IN4, the potential of node A, and the potential of node B It should be noted that the timing is reversed compared to the timing chart of FIG. 1(B).

[0121] Note that in FIG. 8A, the polarities of the transistors included in the circuit 104 and the circuit 105 are However, it is not limited to this, and the circuit 104 and the circuit The polarity of the transistor included in the path 105 can be an N-channel type.

[0122] 8(A) and 8(B), as well as FIGS. 5(A) to 5(B) and 6(A) to 6(C), 7A to 7C, the transistors 101 to 103 are P-channel It is possible to use a type transistor.

[0123] (Embodiment 2) In this embodiment, a specific example of the circuit 104 described in Embodiment 1 will be described. The circuit 104 can be referred to as a semiconductor device, a driver circuit, or a gate driver. The contents described in the first embodiment will not be described here. can be freely combined with the contents described in this embodiment.

[0124] First, an example of the circuit 104 will be described with reference to FIG. The circuit 104 includes a transistor 201 (also referred to as a fourth transistor), a transistor 202 (also referred to as a fifth transistor), and transistor 203 (also referred to as a sixth transistor). 204 (also referred to as a seventh transistor). However, the present invention is not limited to this, and any of these transistors may be omitted. Any of these transistors may be used as a capacitance element, a resistance element, or a diode. It can be replaced by various elements or circuits that combine any of these elements. Alternatively, various elements such as transistors, capacitors, resistors, or diodes can be used. It is possible to add new elements or circuits that combine any of these elements. It is possible.

[0125] As an example, the transistors 201 to 204 are N-channel transistors. In addition, when the transistors 101 to 103 described in the first embodiment are N-channel type, It is preferable that the transistors 201 to 204 are N-channel type. The transistor may be an N-channel type, but is not limited to this. 201 to 204 can be of the P-channel type.

[0126] Next, an example of the connection relationship of the circuit 104 will be described. is connected to the wiring 112, and the second terminal of the transistor 201 is connected to the node B. The first terminal of the transistor 202 is connected to the wiring 116. The second terminal of the transistor 202 is connected to the node B, and the gate of the transistor 202 is connected to the wiring 111. A first terminal of the transistor 203 is connected to the wiring 112. The second terminal of the transistor 201 is connected to the gate of the transistor 203. The first terminal of the transistor 204 is connected to a wiring 116. The second terminal of the transistor 204 is connected to the gate of the transistor 201. The gate of the transistor 204 is connected to the wiring 111. However, this is not limitative and other Various connection configurations are possible.

[0127] Note that the gate of the transistor 201, the second terminal of the transistor 203, or the The connection point of the second terminal of the stator 204 is shown as node C. Note that node C is not considered to be a wiring or a terminal. It is possible to show.

[0128] Note that the wiring 111, the wiring 112, and the wiring 116 may be formed using various types of wiring, as described in Embodiment 1. It is possible to input various signals, various voltages, or various currents. The signal OUT described in the first embodiment is input to the wiring 111. As an example, the signal IN1 described in the first embodiment is input to the signal 112. As an example, the voltage V1 described in the first embodiment is supplied to the line 116. However, it is not limited to this.

[0129] Next, an example of the functions of the transistors 201 to 204 will be described. 201 controls the timing of supplying the signal IN2 to the node B according to the potential of the node C. It has the function of functioning as a bootstrap transistor or switch. The transistor 202 changes the potential of the wiring 111 in response to the potential of the wiring 111 (signal OUT). By controlling the conduction state between the node 6 and the node B, the voltage V1 is supplied to the node B. The transistor has the function of controlling the switching and can function as a switch. 203 has the function of raising the potential of node C and then putting node C into a floating state. The transistor 204 can function as a diode. By controlling the conduction state between the wiring 116 and the node C in response to the signal OUT, It has the function of controlling the timing of supplying voltage V1 to node C and functions as a switch. However, the present invention is not limited to this, and the transistors 201 to 204 may also be These elements or circuits may have a variety of functions, or may be It is possible that the integrating element does not have

[0130] Next, the operation of the circuit 104 will be described with reference to FIGS. 1(B), 9(B), 9(C), 9(D), This will be explained with reference to Figures 9(E) and 9(F). Figure 9(B) shows the circuit during period T1. 9C is a schematic diagram of an example of the operation of the circuit 104 during the period T2. 9D is an example of a schematic diagram of the operation of the circuit 104 in the period T3. FIG. 9E is an example of a schematic diagram of the operation of the circuit 104 in the period T4. 9(F) is an example of a schematic diagram of the operation of the circuit 104 during the period T5.

[0131] For convenience, the operation during period T2 will be described first. During period T2, signal IN2 is H The signal OUT becomes H level, and the signal OUT becomes H level. The transistor 202 and the transistor 204 are turned on. Then, the wiring 116 and the node B are connected. This brings the wiring 116 and the node C into a conductive state. 16 is supplied to node B via transistor 202, so the potential of node B is V1 Then, the voltage V1 is applied from the wiring 116 to the node C through the transistor 204. The potential of node C at this time is The operation point of the transistor 203 and the transistor 204 is determined as follows. The potential of the node C is the sum (V1 +Vth201) is lower than the value of Vth201. Therefore, the transistor 201 is turned off. Therefore, the wiring 112 and the node B are not electrically connected to each other.

[0132] Next, in a period T3, the signal IN1 goes to the L level, and the signal OUT goes to the L level. OUT becomes L level, so the transistor 202 and the transistor 203 are turned off. Therefore, the wiring 116 and the node B are brought into a non-conductive state, and the wiring 116 and the node C are brought into a non-conductive state. Then, the signal IN1 goes to the L level, and the transistor 203 turns off. Then, the node C is in a floating state, and the potential in the period T2 is maintained. Thus, transistor 201 remains off.

[0133] Next, during a period T4, the signal IN1 becomes H level, and the signal OUT remains at L level. Since the signal OUT remains at the L level, the transistors 202 and 203 Therefore, the wiring 116 and the node B remain in a non-conductive state, and the wiring 1 16 remains non-conductive with node C. At this time, signal IN1 goes high. Then, the transistor 203 is turned on, and the wiring 112 and the node C are brought into electrical continuity. Therefore, the signal IN1 at H level is supplied from the wiring 112 to the node C via the transistor 203. , the potential at node C starts to rise. After that, the potential at node C becomes V1+V When the potential becomes th201, the transistor 201 turns on. Therefore, the signal IN1 at the H level is transmitted from the wiring 112 to the transistor B. The voltage at node B starts to rise as a result of the voltage being supplied to node B via capacitor 201. The potential of the node C is changed from the potential (V2) of the H-level signal IN1 to the threshold voltage of the transistor 203. When the voltage (Vth203) is subtracted from the value (V2-Vth203), the transistor 203 is turned off, and therefore the wiring 112 and the node C are in a non-conductive state. Since node C is in a floating state, the potential of node C is The parasitic capacitance between the device and the power supply continues to rise due to capacitive coupling, i.e., bootstrap operation. If the potential of this node C becomes higher than V2+Vth201, The potential at node B rises to V2.

[0134] Next, during the period T5 or T1, the signal IN1 becomes L level, and the signal OUT becomes L level. Since the signal OUT remains at the L level, the transistor 202 and the transistor Therefore, the wiring 116 and the node B remain in a non-conductive state. The signal IN1 is at the L level, and the wiring 116 and the node C remain in a non-conductive state. Then, the transistor 203 turns off, and the wiring 112 and the node C are not connected. Therefore, node C is in a floating state, so V2 + Vth201 As a result, transistor 201 remains on, The line 112 and the node B remain in a conductive state. 12 is supplied to node B via transistor 201, so the potential of node B is V1 At this time, the node C is in a floating state, so the gate of the transistor 201 and the The potential often decreases due to capacitive coupling of parasitic capacitance between the terminals of the During period T4, the potential of node C decreases by the amount that was increased by the bootstrap operation. This is often the case.

[0135] The circuit 104 in FIG. 9A has been described above. The circuit 104 in FIG. By using the trapping action, the potential of node B can be raised to V2. Therefore, the V of the transistor 102 and the transistor 103 described in the first embodiment As a result, the transistor 102 and the transistor 10 Since the channel width of 3 can be reduced, the layout area can be reduced. Alternatively, even if the threshold voltages of the transistors 102 and 103 increase, Alternatively, the transistor 102 and the transistor Since the on-resistance of the resistor 103 is reduced, the potential of the node A and the potential of the wiring 111 are increased to V1 This can make it easier to maintain.

[0136] Alternatively, in the circuit 104 of FIG. 9A, the polarity of all the transistors is set to N-channel or P-channel. Therefore, the number of processes can be reduced, the yield can be improved, and reliability can be improved. In particular, all transistors are N-channel. In the case of the monocrystalline type, the semiconductor layer of the transistor can be made of non-single-crystal semiconductor, microcrystalline semiconductor, or organic semiconductor. Therefore, it is possible to reduce the number of steps and improve the yield. This may improve the quality, reliability or reduce costs, but is not limited to these. First, the circuit 104 in FIG. 9A includes a P-channel transistor and an N-channel transistor. It is possible to have a CMOS circuit composed of transistors. A single crystal semiconductor or a polycrystalline semiconductor can be used for the semiconductor layer of the transistor.

[0137] Alternatively, in the circuit 104 of FIG. 9A, during at least one of the periods T4 and T5, Therefore, the transistors 202 to 204 are turned off during one operation period. Since the transistor is not always on during operation, there are problems with the transistor such as an increase in threshold voltage or a decrease in mobility. In the periods T4 and T5, the deterioration of the characteristics of the node can be suppressed. C repeats the increase and decrease of the potential. This leads to deterioration of transistor characteristics such as an increase in threshold voltage or a decrease in mobility. In particular, the semiconductor layer of a transistor can be formed using a non-single-crystal semiconductor, a microcrystalline semiconductor, or the like. When a crystalline semiconductor, organic semiconductor, or oxide semiconductor is used, the characteristics of the transistor However, in the semiconductor device shown in FIG. Since this can suppress deterioration of characteristics, non-single crystal semiconductors are used as the semiconductor layer of transistors. It becomes easy to use a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. However, the semiconductor layer may be formed using a polycrystalline semiconductor or a single-crystal semiconductor. is possible.

[0138] For example, the channel width of the transistor 203 is It is preferable that the width is smaller than the width of the transistor 203 during the period T2. This is to lower the potential of node C when transistor 204 is turned on. For example, the channel length of transistor 203 is However, it is not limited to this, and the length of the transistor 203 is preferably shorter than the channel length. The channel width can be greater than the channel width of transistor 204; or The channel length of the transistor 203 is smaller than the channel length of the transistor 204. It is possible to do this.

[0139] As an example, the channel width of the transistor 204 is It is preferable that the width is smaller than the width because the load on node B is larger than the load on node C. For the same reason, the channel width of the transistor 203 is It is preferable that the channel width of the transistor 201 is smaller than that of the transistor 201. However, it is not limited to this. The channel width of transistor 204 is greater than the channel width of transistor 202. Alternatively, the channel width of the transistor 203 may be set to be equal to or smaller than the channel width of the transistor 201. It is possible for the width of the loop to be larger than the loop width.

[0140] As an example, the channel width of the transistor 201 and the channel width of the transistor 202 are It is preferable that the values ​​are approximately equal to each other because the values ​​of the transistors 201 and 202 are 02 because they both control the potential of node C and are transistors of the same polarity. However, the present invention is not limited to this, and the channel width of the transistor 201 is It can be larger or smaller than the channel width.

[0141] As an example, the transistor 201, the transistor 202, the transistor 203, or The channel width of the transistor 204 is the same as that of the transistor 101 and the transistor 204 described in the first embodiment. It is preferable that the channel width of the transistor 102 or the channel width of the transistor 103 be smaller. However, the present invention is not limited to this, and the channel width of any one of the transistors 201 to 204 may be The channel of transistor 101, transistor 102, or transistor 103 of 1(A) It is possible for the width of the loop to be larger than the loop width.

[0142] As an example, similar to the transistor 101 described in the first embodiment, In 01, the parasitic capacitance between the gate and the second terminal is It is preferable that the capacitance is larger than the capacitance of the node C during the period T4. This is because the gate voltage is likely to be high due to the gate strap operation. The area where the conductive layer that functions as a source or a drain overlaps with the conductive layer that functions as a second It is preferable that the terminal side is larger than the first terminal side. However, this is not limitative. stomach.

[0143] It is possible to input a signal whose L level potential is lower than V1 to the terminal 104b. In this way, a reverse bias is applied to the transistor 202 and the transistor 204. Therefore, the deterioration of the characteristics of the transistors 202 and 204 can be reduced. Alternatively, a signal whose H level potential is lower than V2 can be input to the terminal 104b. Thus, the transistor 202 and the transistor 204 are turned on. Since Vgs can be reduced at this time, the transistor 202 and the transistor In this case, the deterioration of the characteristics of the wiring 111 can be suppressed. A signal whose potential is lower than V1, a signal whose H level potential is lower than V2, or a signal whose L level potential is lower than V3 It is possible to input a signal whose H level potential is lower than V1 and whose H level potential is lower than V2. However, the present invention is not limited to this, and the terminal 104b may be connected to a wiring other than the wiring 111. The wiring is connected to a signal whose L level potential is lower than V1 and a signal whose H level potential is lower than V2. or a signal whose L level potential is lower than V1 and whose H level potential is lower than V2 It is possible to input

[0144] As in the first embodiment, the wiring can be divided into multiple wirings. The same signal or voltage can be input to the multiple wirings, or different signals or Alternatively, the plurality of wirings may be connected to the same wiring or the same element. The plurality of wirings may be connected to separate wirings or separate elements. In one example of FIG. 10(A), the wiring 111 is connected to wirings 111A to 111B. The wiring 112 is divided into a plurality of wirings 112C to 112D. In this case, the wiring 116 is divided into a plurality of wirings 116E to 116F. The gate of the transistor 204 is connected to the wiring 111A. The gate of the transistor 202 is connected to the wiring 111B. The first terminal and the gate of the transistor 203 are connected to the wiring 112D. The first terminal of the transistor 202 is connected to the wiring 116E. The first terminal of the capacitor 204 is connected to the wiring 116F. However, the present invention is not limited to this. Only one or two of the wirings 111, 112, and 116 are divided into multiple wirings. Alternatively, the gate and the first terminal of the transistor 203 may be connected to separate In this case, the gate of transistor 203 is The output and the first terminal can be connected to different wires.

[0145] In FIG. 10A, the wirings 111A to 111B correspond to the wiring 111 in FIG. 9A. Therefore, like the wiring 111, the signal OUT is input to the wirings 111A to 111B. The wirings 111A and 111B can function as signal lines. However, the present invention is not limited to this, and the wirings 111A to 111B may be supplied with a voltage V1 or a voltage V2. The wirings 111A and 111B function as power supply lines. Alternatively, the wirings 111A and 111B may be provided with separate signals or separate voltages. Alternatively, various other signals can be input to the wirings 111A to 111B. It is possible to input a signal, a different voltage, or a different current.

[0146] In FIG. 10A, the wirings 112C to 112D correspond to the wiring 112 in FIG. 9A. Therefore, like the wiring 112, the signal IN1 is input to the wirings 112C to 112D. The wirings 112C to 112D can function as signal lines. However, the present invention is not limited to this, and the wirings 112C to 112D may be supplied with a voltage V1 or a voltage V2. The wirings 112C to 112D function as power supply lines. Alternatively, the wirings 112C to 112D may be provided with separate signals or separate voltages. Alternatively, various other signals can be input to the wirings 112C to 112D. It is possible to input a signal, a different voltage, or a different current.

[0147] In FIG. 10A, the wirings 116E to 116F correspond to the wiring 116 in FIG. 9A. Therefore, similar to the wiring 116, the voltage V1 is supplied to the wirings 116E to 116F. The wirings 116E to 116F can function as power supply lines. However, the present invention is not limited to this, and the wirings 116E to 116F may be connected to the signal OUT or the signal I. By inputting signals such as N1 to IN4, the wirings 116E to 116F function as signal lines. Alternatively, the wirings 116E to 116F may be connected to different voltages or Alternatively, the wirings 116E to 116F may be connected to other It is possible to input various signals, various voltages, or various currents.

[0148] In FIG. 10A, the wirings 116E and 116F are connected in the period T2. For example, a signal that becomes an L level can be input to the wiring 116E and the wiring 116F. In this case, the signal IN2 can be input to the wiring 116E and the wiring 116F. The line 116F can be connected to the wiring 113 described in the first embodiment. As a result, a reverse bias is applied to the transistor 202 and the transistor 204. Therefore, the deterioration of the characteristics of the transistors 202 and 204 can be reduced. However, the present invention is not limited to this, and a signal may be transmitted to only one of the wiring 116E and the wiring 116F. In this case, only one of the wiring 116E and the wiring 116F can be used. can be connected to the wiring 113. Alternatively, the wiring 116E and / or the wiring It is possible to input the signal IN3 or the signal IN4 to the wiring 116F. 116E and / or the wiring 116F are the wiring 114 or the wiring 11 described in the first embodiment. 5 can be connected.

[0149] In FIG. 10A, the signal IN2 can be input to the wiring 112D. In this case, the gate and the first terminal of the transistor 203 are connected to the wiring 113. By doing so, the potential of the node C is at the H level during the period T3. The threshold voltage (Vth203) of the transistor 203 is subtracted from the potential (V2) of the signal IN2 of the After that, during a period T4, the signal IN1 becomes the H level. Therefore, the voltage at node C becomes V2-Vth203 by the bootstrap operation. Therefore, the potential of the node C increases, and the V As a result, the output signal of the circuit 104 (potential of the node B) The fall time and rise time can be shortened. However, the wiring 112D is not limited to this, and the following may be provided: It is possible to provide a voltage V2.

[0150] As shown in FIG. 10B, a transistor 201 is connected between the gate and the second terminal thereof. It is possible to newly connect a capacitor 221. By doing so, the capacitor 221 shown in FIG. Similarly, the potential of the node C can be increased. However, this is not limited to this, and the potential of the node C can be increased as shown in FIG. As in A), the first terminal and the second terminal of the capacitance element 221 are connected to the node B, A transistor whose gate is connected to node C can be used as a MOS capacitor. do.

[0151] 10B, the gate of the transistor 201 and the A capacitor 221 can be newly connected between the first terminal and the second terminal. A transistor having a first terminal and a second terminal connected to a node B and a gate connected to a node C. It is possible to connect a new controller.

[0152] Note that, as shown in FIG. 10C, the transistor 204 can be omitted. Alternatively, as shown in FIG. 10(D), the transistor 202 can be omitted. By doing so, the number of transistors can be reduced. However, this is not limited to this, and Both transistor 202 and transistor 204 may be omitted.

[0153] As in FIG. 10(C) or FIG. 10(D), in FIG. 10(A) to (B), Transistor 202 and / or transistor 204 may be omitted.

[0154] As shown in FIG. 10(E), the transistor 202 is connected to one terminal (hereinafter also referred to as the positive terminal). The other terminal (hereinafter also referred to as a negative electrode) is connected to the wiring 111. Alternatively, the transistor 203 can be replaced with a diode 202a. One terminal (hereinafter referred to as the positive terminal) is connected to node C, and the other terminal (hereinafter referred to as the negative terminal) is connected to node C. The diode 203a connected to the wiring 111 can be substituted for the diode 203b. In this case, the terminal 104b of the circuit 104 receives the inverted signal of the signal OUT or the potential of the node A. To achieve this, the wiring 111 or Node A is an inverter circuit, a NAND circuit, or a NOR circuit that inverts the input signal. It can be connected to the terminal 104b of the circuit 104 via a circuit having a function of outputting the However, the present invention is not limited to this, and the transistor 202 and the transistor 204 may be the same. Alternatively, the diode 202a and / or Alternatively, a diode 203a can be newly added.

[0155] As in FIG. 10(E), the transistor 202 is also shown in FIGS. 10(A) to 10(D). , a diode 2 having one terminal connected to the node B and the other terminal connected to the wiring 111; Alternatively, the transistor 203 can be replaced with a The other terminal is connected to the wiring 111. Alternatively, the diode 202a and / or the diode 203a may be New ones can be added.

[0156] Although not shown, in FIGS. 10(A) to 10(E), the first terminal of the transistor 202 The first terminal of the transistor 201 is connected to the wiring 111, the second terminal of the transistor 202 is connected to the node B, and the The gate of the transistor 202 is connected to the wiring 111 or the node B. The transistor 202 can be diode-connected. The first terminal of the transistor 204 is connected to the wiring 111, and the second terminal of the transistor 204 is connected to the node C. The gate of the transistor 204 is connected to the wiring 111 or the node C. In this case, the transistor 204 can be diode-connected. However, this is not a limitation. Only one of the transistors 202 and 204 is diode-connected. is possible.

[0157] As shown in FIG. 10(F), the transistors 201 to 204 are P-channel transistors. In particular, transistors 101 to 103 in FIG. When P-channel transistors are used, the transistors 201 to 204 It is preferable to use a P-channel transistor as the transistor 201p. The transistor 202p, the transistor 203p, and the transistor 204p are transistors. Supports Transistor 201, Transistor 202, Transistor 203, and Transistor 204 It is a P-channel type.

[0158] As in FIG. 10(F), in FIGS. 10(A) to 10(E), the transistors 201 to A P-channel transistor can be used as 204 .

[0159] As already described, the circuit 104 included in the circuit 100 described in Embodiment 1 may be replaced with The configuration of the circuit 104 described in the embodiment can be used. 9A is used as the circuit 104 included in the circuit 100 in FIG. 7C. However, the present invention is not limited to this, and the configurations shown in Figs. 9(A), 10(A), and 10(B) are also possible. (B), FIG. 10(C), FIG. 10(D), FIG. 10(E), FIG. 10(F), or a combination thereof The combined circuit 104 is shown in FIGS. 1(A), 5(A), 5(B), 6(A), and 6 (B), FIG. 6(C), FIG. 7(A), FIG. 7(B), FIG. 8(A), or a combination thereof In this case, the circuit 104 included in the circuit 100 can be used.

[0160] (Embodiment 3) In this embodiment, a specific example of the circuit 105 will be described. It is possible to refer to the device, the driver circuit, or the gate driver. The contents described in the second embodiment will not be described here. The content described in the second embodiment can be freely combined with the content described in this embodiment.

[0161] First, an example of the circuit 105 will be described with reference to FIG. In the circuit 105, a transistor 301 (also referred to as an eighth transistor) a transistor 302 (also referred to as a ninth transistor), a transistor 303 (also referred to as a tenth transistor), a transistor 304 (also referred to as an eleventh transistor), and a transistor 305 (also referred to as the twelfth transistor). However, the present invention is not limited to this. It is possible to omit any of the transistors. Any of these may be used as various elements such as a capacitance element, a resistance element, or a diode. It is possible to replace it with a circuit that combines any of the elements. Various elements such as a transistor, a capacitance element, a resistance element, or a diode, or It is possible to add a new circuit that combines any of these elements.

[0162] As an example, the transistors 301 to 305 are N-channel transistors. The transistors 101 to 103 described in the first embodiment and the transistor When the transistors 201 to 204 are N-channel type, the transistors 301 to 305 are , and preferably N-channel type. In this way, all transistors have the same polarity. However, the present invention is not limited to this, and the transistors 301 to 305 may be P-channel It is possible for the type

[0163] Next, an example of the connections in the circuit 105 in FIG. 12A will be described. A first terminal of the transistor 301 is connected to the wiring 114, and a second terminal of the transistor 302 is connected to the node A, and the gate of the transistor 301 is connected to the wiring 114. A first terminal of the transistor 302 is connected to the wiring 114, and a second terminal of the transistor 302 is connected to the The gate of the transistor 302 is connected to the wiring 113. A first terminal of the transistor 303 is connected to the wiring 116, and a second terminal of the transistor 303 is connected to the wiring 116. The gate of the transistor 303 is connected to the node A, and the gate of the transistor 304 is connected to the wiring 115. The first terminal of the transistor 304 is connected to the wiring 116, and the second terminal of the transistor 304 is connected to the wiring 116. The gate of the transistor 304 is connected to the wiring 111, and the gate of the transistor 304 is connected to the wiring 115. The first terminal of the transistor 305 is connected to the wiring 116. The terminal of the transistor 302 is connected to the wiring 111, and the gate of the transistor 305 is connected to the wiring 113. However, the present invention is not limited to this, and various other connection configurations are possible.

[0164] Note that the wiring 113, the wiring 114, the wiring 115, and the wiring 116 may have the same structure as described in Embodiment 1. As described above, various signals, voltages, or currents can be input. For example, the signal IN2 described in the first embodiment is input to the wiring 113. For example, the signal IN3 described in the first embodiment is input to the wiring 114. For example, the signal IN4 shown in FIG. 1B or FIG. 3A is transmitted to the wiring 115. As an example, a voltage V1 is supplied to the wiring 116. However, it is not limited to this.

[0165] Next, an example of the functions of the transistors 301 to 305 will be described. 301 indicates the timing at which the signal IN2 at H level is supplied to the node A in response to the signal IN3. Alternatively, the transistor 301 can be controlled to function as a diode. By controlling the conduction state between the wiring 114 and the node A in accordance with the potential of the node A, , and has the function of controlling the timing of supplying signal IN3 to node A. 02 controls the conduction state between the wiring 114 and the node A in response to the signal IN2. It has the function of controlling the timing of supplying signal IN3 to node A, and acts as a switch. The transistor 303 is connected to the wiring 116 in response to the signal IN4. By controlling the conduction state with node A, it has the function of supplying voltage V1 to node A. The transistor 304 is turned on in response to the signal IN4. By controlling the conduction state between the wiring 116 and the wiring 111, the voltage V1 is applied to the wiring 116. 11 and can function as a switch. 05 controls the conduction state between the wiring 116 and the wiring 111 in response to the signal IN2. 111, and can function as a switch. However, the transistors 301 to 305 are not limited to these, and may have various other functions. Alternatively, these elements or circuits may have the functions described above. It is possible to do this.

[0166] Next, the operation of the circuit 105 will be described with reference to FIGS. 1(B), 12(B), 12(C), and 13( 13(A), 13(B), and 13(C). FIG. 13(B) shows the period T1 12C is an example of a schematic diagram of the operation of the circuit 105 in the period T2. 13A is a schematic diagram of an example of the operation of the circuit 105 during a period T3. 13B is an example of a schematic diagram of the operation of the circuit 105 in the period T4. FIG. 13C is an example of a schematic diagram of the operation of the circuit 105 in the period T5. be.

[0167] First, in the period T1, the signal IN2 becomes H level, the signal IN3 becomes H level, and the signal Signal IN4 becomes L level. Signal IN3 becomes H level, so transistor 301 is turned on. At the same time, the signal IN2 goes high, so that the transistors 302 and Then, the wiring 114 and the node A are brought into a conductive state, and the signal IN 3 is supplied from the wiring 114 to the node A through the transistor 301 and the transistor 302. Therefore, the potential of the node A starts to rise. is turned on, the voltage V1 is applied from the wiring 116 to the wiring 11 through the transistor 305. Therefore, the potential of the wiring 111 becomes V1. At this time, the signal IN4 is supplied to the L level. Therefore, the transistor 303 and the transistor 304 are turned off. 116 and the node A are brought into a non-conductive state, and the wiring 116 and the wiring 111 are brought into a non-conductive state. After that, the potential of the node A changes from the potential of the wiring 114 (V2) to the threshold voltage of the transistor 301. When the voltage (Vth301) is subtracted from the value (V2-Vth301), the transistor Similarly, the potential of the node A changes from the potential of the wiring 113 (V2) to the potential of the transistor 301. The value obtained by subtracting the threshold voltage (Vth302) of the first transistor 302 from the voltage (V2-Vth302) is Therefore, the transistor 302 is turned off. Therefore, there is no electrical continuity between the wiring 114 and the node A. Here, as an example, when the potential of node A becomes V2-Vth301, , the transistor 301 and the transistor 302 are turned off. A is in a floating state while the potential is maintained at V2-Vth301.

[0168] Next, in the period T2, the signal IN3 becomes L level, the signal IN4 becomes L level, and the signal The signal IN5 remains at the L level. Since the signal IN3 becomes the L level, the transistor 301 At the same time, the signal IN2 goes low, so the transistor 302 The transistor 303 remains off, and the wiring 114 and the node A are The non-conductive state remains, and the wiring 116 and the wiring 111 are in a non-conductive state. Since the signal IN4 remains at the L level, the transistors 303 and 304 are turned off. Therefore, the wiring 116 and the node A remain in a non-conductive state, and the wiring 116 and the wiring 111 remain in a non-conductive state.

[0169] Next, during the period T3, the signal IN2 becomes H level and the signal IN3 remains L level. Since the signal IN3 remains at the L level, the transistor 30 Then, the signal IN2 goes high, so the transistor 302 , and the transistor 304 is turned on. Then, electrical continuity is established between the wiring 114 and the node A. Therefore, the signal IN3 at the L level is supplied from the wiring 114 to the node A via the transistor 302. Similarly, the wiring 116 and the wiring 111 are in a conductive state, so that the voltage V1 is supplied to the wiring 116. The signal is supplied from the line 116 to the wiring 111 via the transistor 305. Since the signal 4 goes to H level, the transistor 303 and the transistor 304 are turned on. Then, the wiring 116 and the node A are brought into a conductive state, and the voltage V1 is transferred from the wiring 116. The signal is supplied to node A via transistor 303. Similarly, the wiring 116 and the wiring 111 are connected. Since the transistor 304 is turned on, the voltage V1 is applied from the wiring 116 to the wiring 111. Therefore, the potential of the node A decreases to V1, and the potential of the wiring 111 decreases. The value is reduced to V1.

[0170] Next, during the period T4, the signal IN2 becomes L level, and the signal IN3 remains L level. Since the signal IN3 remains at the L level, the transistor 30 Then, the signal IN2 goes low, so the transistor 302 , and the transistor 305 is turned off. Therefore, there is no electrical continuity between the wiring 114 and the node A. This causes a non-conductive state between the wiring 116 and the wiring 111. At the same time, the signal IN4 becomes L level. Therefore, the transistor 303 and the transistor 304 are turned off. 116 and the node A are brought into a non-conductive state, and the wiring 116 and the wiring 111 are brought into a non-conductive state. In this manner, during the period T4, a signal or a current is transmitted from the circuit 105 to the node A or the wiring 111. In many cases, pressure is not supplied.

[0171] Next, during the period T5, the signal IN2 becomes H level and the signal IN3 remains L level. Since the signal IN4 remains at the L level, the transistor Therefore, the wiring 116 and the node A are not connected to each other. The signal IN3 is turned on, and the wiring 116 and the wiring 111 are turned off. Since the signal IN2 remains at the L level, the transistor 301 remains off. becomes H level, the transistor 302 and the transistor 305 are turned on. Then, the wiring 114 and the node A are brought into electrical continuity, and the signal IN3 at the L level is applied to the wiring 114. 4 is supplied to node A via transistor 302. Therefore, the potential of node A is Similarly, the wiring 116 and the wiring 111 are in a conductive state, so that the voltage V1 is supplied from the wiring 116 to the wiring 111 through the transistor 305. The potential of 11 is maintained at V1.

[0172] The circuit 105 in FIG. 12A has been described above. The polarity of all the transistors can be either N-channel or P-channel. Therefore, it is possible to reduce the number of processes, improve yield, improve reliability, or reduce costs. In particular, when all transistors are N-channel type, the semiconductor layer of the transistors Therefore, a non-single-crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. This makes it possible to reduce the number of processes, improve yield, improve reliability, or reduce costs. However, the present invention is not limited to this, and the circuit 105 of FIG. CMOS circuits consisting of N-channel transistors and N-channel transistors Alternatively, a semiconductor layer of the transistor may be formed of a single crystal semiconductor or A polycrystalline semiconductor can be used.

[0173] Alternatively, in the circuit 105 of FIG. 12A, during at least one of the periods T4 and T5, Therefore, the transistors 301 to 305 are turned off during one operation period. Since the transistor is not always on during the period, there are no problems with transistors such as an increase in threshold voltage or a decrease in mobility. In particular, the semiconductor layer of a transistor can be made of non-single crystal. When a crystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used, However, in the circuit 105 of FIG. Since it is possible to suppress the deterioration of transistor characteristics, it is suitable as a semiconductor layer for transistors. It is easy to use a non-single-crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. However, the semiconductor layer is not limited to this, and may be a polycrystalline semiconductor or a single crystal semiconductor. It is possible to use the body.

[0174] For example, the channel width of the transistor 305 is Alternatively, the channel width of the transistor 304 is preferably larger than the width of the transistor 304. Therefore, it is preferable that the channel width of the wiring 11 is larger than that of the transistor 303. The load of node 1 is often larger than the load of node A, so that a signal or a voltage is applied to the wiring 111. The driving capability of the transistor that supplies a signal or voltage to node A is This is because the driving capability of the transistor 305 is often larger than that of the transistor 306. The transistor 304 has a function of supplying a signal or a voltage to the wiring 111. The transistor 302 and the transistor 303 have a function of supplying a signal or voltage to the node A. However, the channel width of the transistor 305 is not limited to this. The channel width of transistor 304 can be smaller than that of transistor 302. The channel width can be smaller than the channel width of transistor 303, for example. This is because the node A is connected to the first terminal of the transistor 101 described in the first embodiment. This is because noise is easily generated by the parasitic capacitance between the gate and the The transistor 101 may be turned on by noise, and the potential of the wiring 111 may increase. Because there is.

[0175] For example, the channel width of the transistor 303 is Alternatively, the channel width of the transistor 304 is preferably larger than the width of the transistor 304. It is preferable that the channel width of the transistor 305 is larger than that of the transistor 305. Therefore, the influence of noise generated in the node A and the wiring 111 can be reduced. However, the channel width of the transistor 303 is not limited to the above. Alternatively, the channel width of transistor 304 can be smaller than the width of transistor 304. It is possible that the width of the channel of the resistor 305 is smaller than the width of the channel of the resistor 305 .

[0176] The terminals 105a and 105c receive a signal whose L level potential is lower than V1. In this way, a reverse bias is applied to the transistors 302 to 305. This makes it possible to reduce the deterioration of the characteristics of the transistors 302 to 305. Alternatively, the terminal 105a and the terminal 105c are connected to a signal whose H level potential is lower than V2. Thus, when the transistors 302 to 305 are on, Since Vgs can be reduced, deterioration of the characteristics of the transistors 302 to 305 can be suppressed. In this case, the wiring 113 and the wiring 115 are connected to a low-level potential V 1, a signal whose H level potential is lower than V2, or a signal whose L level potential is V1 It is possible to input a signal whose H level potential is lower than V1 and whose H level potential is lower than V2. However, the present invention is not limited to this, and an L-level potential may be applied to one of the terminals 105a and 105c. 1, a signal whose H level potential is lower than V2, or a signal whose L level potential is V1 It is possible to input a signal whose H level potential is lower than V2. In this case, a signal having an L level potential lower than V1 is applied to one of the wirings 113 and 115. A signal whose L level potential is lower than V2, or whose L level potential is lower than V1 and whose H level potential is Alternatively, a signal whose potential is lower than V2 can be input to the terminal 105a. A signal having an L-level potential lower than V1 is connected to a wiring other than the wiring 113. , a signal whose H level potential is lower than V2, or whose L level potential is lower than V1, and It is possible to input a signal whose H level potential is lower than V2. c is connected to a wiring other than the wiring 115, and the wiring has a potential of L level lower than V1. signal, a signal whose H level potential is lower than V2, or a signal whose L level potential is lower than V1, In addition, it is possible to input a signal whose H level potential is lower than V2.

[0177] The terminal 105d is at the L level during the periods T1, T3, and T4. For example, the signal IN2 can be input to the terminal 105d. In this case, the terminal 105d can be connected to the wiring 113. By doing so, the transistor 303, the transistor 304, or the transistor Since a reverse bias can be applied to the transistor 305, the transistor 303 and the transistor This can alleviate the deterioration of the characteristics of the resistor 304 or the transistor 305.

[0178] As in the first or second embodiment, the wiring can be divided into a plurality of wirings. The same signal or voltage can be input to the multiple wirings. Alternatively, the plurality of wirings may be connected to the same The wires may be connected to the same element, or the wires may be separate wires or In the example shown in FIG. 14A, the wiring 113 is a wiring The wiring 114 is divided into a plurality of wirings 113A to 113B, and the wiring 114 is divided into wirings 114A to 114B. The wiring 115 is divided into a plurality of wirings 115A to 115B. In this case, the wiring 116 is divided into a plurality of wirings 116G to 116I. The gate of the transistor 302 is connected to the wiring 113A. The gate of the transistor 305 is connected to the wiring 113B. The first terminal of the transistor 302 is connected to the wiring 113C. The first terminal and the gate of the transistor 301 are connected to the wiring 114B. The gate of the transistor 303 is connected to the wiring 115A, and the gate of the transistor 304 is connected to the wiring 115B. The gate of the transistor 303 is connected to the wiring 115B. The first terminal of the transistor 303 is connected to the wiring 116G. The first terminal of the transistor 304 is connected to the wiring 116H, and the second terminal of the transistor 305 is connected to the wiring 116H. The first terminal of the wiring 113 is connected to the wiring 116I. , wiring 114, wiring 115, and wiring 116, only one, two, or three of them are plural. It is possible to divide the wiring into

[0179] In FIG. 14A, the wirings 113A to 113B are the same as the wiring 113 in FIG. 12A. Therefore, like the wiring 113, the signal IN2 is input to the wirings 113A to 113B. The wirings 113A and 113B can function as signal lines. However, the present invention is not limited to this, and the wirings 113A to 113B may be supplied with a voltage V1 or a voltage V 2, and the wirings 113A and 113B function as power supply lines. Alternatively, the wirings 113A to 113B may carry separate signals or separate Alternatively, various other voltages can be input to the wirings 113A to 113B. It is possible to input a signal, a different voltage, or a different current.

[0180] In FIG. 14A, the wirings 114A to 114B are the same as the wiring 114 in FIG. 12A. Therefore, like the wiring 114, the signal IN3 is input to the wirings 114A to 114B. The wirings 114A and 114B can function as signal lines. However, the present invention is not limited to this, and the wirings 114A to 114B may be supplied with a voltage V1 or a voltage V 2, and the wirings 114A and 114B function as power supply lines. Alternatively, the wirings 114A to 114B may carry separate signals or separate Alternatively, various other voltages can be input to the wirings 114A to 114B. It is possible to input a signal, a different voltage, or a different current.

[0181] In FIG. 14A, the wirings 115A to 115B are the same as the wiring 115 in FIG. 12A. Therefore, like the wiring 115, the signal IN4 is input to the wirings 115A to 115B. The wirings 115A and 115B can function as signal lines. However, the present invention is not limited to this, and the wirings 115A to 115B may be supplied with a voltage V1 or a voltage V 2, and the wirings 115A and 115B function as power supply lines. Alternatively, the wirings 115A to 115B may carry separate signals or separate Alternatively, various other voltages can be input to the wirings 115A to 115B. It is possible to input a signal, a different voltage, or a different current.

[0182] In FIG. 14A, the wirings 116G to 116I are the same as the wiring 116 in FIG. 12A. Therefore, similar to the wiring 116, the voltage V1 is supplied to the wirings 116G to 116I. The wirings 116G to 116I can function as power supply lines. However, the present invention is not limited to this, and the wirings 116G to 116I may be connected to a signal OUT or a signal By inputting signals such as IN1 to IN4, the wirings 116G to 116I are signal lines Alternatively, the wirings 116G to 116I may be connected to separate voltages, Alternatively, separate signals can be supplied to the wirings 116G to 116I. It is also possible to input various signals, various voltages, or various currents to the input terminals.

[0183] In FIG. 14A, the wirings 116G and 116H are connected in the period T3. For example, a signal that becomes an L level can be input to the wiring 116G and the wiring 116G. In this case, the signal IN2 can be input to the wiring 116G and the wiring 116H. The line 116H can be connected to the wiring 112 described in the first and second embodiments. By doing so, the transistor 303 and the transistor 304 are reverse biased. This allows the application of a bias to the transistors 303 and 304. However, the present invention is not limited to this, and the wiring 116G and the wiring 116G can suppress the deterioration of the characteristics. It is possible to input the signal IN2 to only one of the wirings 116G and 116H. and / or the signal OUT or the signal IN3 can be input to the wiring 116H. In this case, the wiring 116G and / or the wiring 116H are the same as those in the first and second embodiments. It can be connected to the wiring 111 or the wiring 114 described in the second embodiment.

[0184] In FIG. 14A, the wiring 116I is connected to the wiring 116I during the periods T1, T3, and T5. For example, the signal 116I can be input to the signal In this case, the wiring 116I is the same as in the first and second embodiments. It is possible to connect the wiring 112 described in the second embodiment. This allows a reverse bias to be applied to the transistor 305, The deterioration of characteristics can be suppressed, but the present invention is not limited to this.

[0185] As shown in FIG. 14B, the transistors 303 and 304 are omitted. This allows the number of transistors to be reduced. This can reduce the layout area or improve the yield. However, the present invention is not limited to this, and only one of the transistors 303 and 304 may be omitted. It is possible to omit it.

[0186] 14B, the transistor 303 and / or In this case, the transistor 304 can be omitted.

[0187] As shown in FIG. 14C, the transistor 305 can be omitted. In this way, the number of transistors can be reduced, which leads to a reduction in layout area, or It is possible to improve the yield, etc. However, the present invention is not limited to this.

[0188] As in FIG. 14(C), the transistor 305 is also shown in FIGS. 14(A) and 14(B). It is possible to omit

[0189] As shown in FIG. 15A, the transistor 302 can be omitted. In this way, the number of transistors can be reduced, which leads to a reduction in layout area, or It is possible to improve the yield, etc. However, the present invention is not limited to this.

[0190] As in FIG. 15(A), the transistor 302 is also shown in FIGS. 14(A) to 14(C). It can be omitted.

[0191] As shown in FIG. 15B, the transistor 301 can be omitted. In this way, the number of transistors can be reduced, which leads to a reduction in layout area, or It is possible to improve the yield, etc. However, the present invention is not limited to this.

[0192] As in FIG. 15(B), in FIGS. 14(A) to 14(C) and FIG. 15(A), The transistor 301 can be omitted.

[0193] As shown in FIG. 16A, the transistor 303 is connected to one terminal (hereinafter also referred to as the positive terminal). The other terminal (hereinafter also referred to as a negative electrode) is connected to the wiring 115. Alternatively, the transistor 304 can be replaced with a diode 303a. One terminal (hereinafter also referred to as the positive terminal) is connected to the wiring 111, and the other terminal (hereinafter also referred to as the negative terminal) is connected to the wiring 112. ) can be replaced with the diode 304a connected to the wiring 115. However, the present invention is not limited to this, and one of the transistors 303 and 304 may be die-coupled. Alternatively, the diode 303a and / or the diode It is possible to add a new node 304a.

[0194] As in FIG. 16(A), in FIGS. 14(A) to 14(C) and 15(A) to 15(B), In this case, one terminal of the transistor 303 is connected to the node A and the other terminal is connected to the wiring 11. 5. Alternatively, the transistor One terminal of the capacitor 304 is connected to the wiring 111, and the other terminal is connected to the wiring 115. Alternatively, the diodes 303a and 304a can be replaced with the diodes 303a and 304b. Or, a new diode 304a can be added.

[0195] Although not shown, FIGS. 14(A) to 14(C), 15(A) to 15(B), and 16(A) ), the first terminal of the transistor 303 is connected to the wiring 115, and the second terminal of the transistor 303 is connected to the wiring 115. A second terminal of transistor 303 is connected to node A, and a gate of transistor 304 is connected to node A. By doing so, it is possible to connect the transistor 303 in a diode-connected state. Alternatively, the first terminal of the transistor 304 is connected to the wiring 115, and the The second terminal of the transistor 304 is connected to the wiring 111. By doing so, it is possible to make the transistor 304 diode-connected. However, without being limited to this, one of the transistors 303 and 304 may be a diode. It is possible to make it a connection.

[0196] As shown in FIG. 16B, the transistor 305 is connected to one terminal (hereinafter also referred to as the positive terminal). The negative terminal is connected to the wiring 111, and the negative terminal is connected to the wiring 113. However, the present invention is not limited to this and may be substituted with a diode 305a. A new diode 305a can be added.

[0197] As in FIG. 16(B), FIGS. 14(A) to 14(C), 15(A) to 15(B), and 1 6(A), the transistor 305 is connected to a wiring 111 and the other terminal (hereinafter also referred to as the negative electrode) is connected to the wiring 113. Alternatively, the diode 305a can be replaced with a new diode 305a. It is possible to do this.

[0198] Although not shown, FIGS. 14(A) to 14(C), 15(A) to 15(B), and 16(A) In ) to )B, the first terminal of the transistor 305 is connected to the wiring 113, and the The second terminal of the transistor 305 is connected to the wiring 111, and the gate of the transistor 305 is connected to the wiring 112. 111, the transistor 305 can be diode-connected. However, it is not limited to this.

[0199] As shown in FIG. 17A, the gate of the transistor 301 is connected to the wiring 117. For this purpose, the circuit 105 may have a new terminal 105g. The wiring 117 is connected to the gate of the transistor 301 via the terminal 105g. The wiring 117 is connected to the power supply line. A voltage V2 is supplied to the wiring 117. However, the present invention is not limited to this, and the first terminal of the transistor 301 may be The gate of the transistor 301 may be connected to the wiring 114. Alternatively, a signal at an H level is input to the wiring 117 during the period T2. The wiring 117 can function as a signal line. A signal IN2 can be input to the line 117, which is connected to the line 113. Alternatively, the wiring 117 may be connected to various other signals, voltages, or Various currents can be input.

[0200] As in FIG. 17(A), FIGS. 14(A) to 14(C), 15(A) to 15(B), and 1 6(A) to (B), the gate of the transistor 301 or the The first terminal can be connected to the wiring 117 .

[0201] As shown in FIG. 17B, a transistor 306 and a transistor 307 are newly added. As an example, transistor 306 and transistor 30 7 is often of the same polarity as the transistors 301 to 305 and is an N-channel type. The first terminal of the transistor 306 is connected to the wiring 116. The second terminal of the transistor 306 is connected to the node A, and the gate of the transistor 306 is connected to the wiring 118. The first terminal of the transistor 307 is connected to the wiring 116. The second terminal of the transistor 307 is connected to the wiring 111, and the gate of the transistor 307 is connected to the wiring 112. 118. As an example, a signal IN5 is input to the wiring 118. The wiring 118 can function as a signal line. The transistor 306 receives the signal I The conduction state between the wiring 116 and the node A is controlled depending on the potential of N5 or the wiring 115. By this, it has the function of controlling the timing when voltage V1 is supplied to node A, and the switch The transistor 307 can function as a By controlling the conduction state between the wiring 116 and the wiring 111 according to the potential of the It has a function of controlling the timing when V1 is supplied to the wiring 111 and functions as a switch. For example, the signal IN5 may function as an all-stage reset signal. However, this is not limited to this, and one of the transistors 306 and 307 may be used. Only new entries can be added.

[0202] As in FIG. 17(B), FIGS. 14(A) to 14(C), 15(A) to 15(B), and 16( In A) to (B) and FIG. 17(A), the transistor 306 and / or the transistor A first terminal of the transistor 306 is connected to the The second terminal of the transistor 306 is connected to the wiring 116, and the second terminal of the transistor 306 is connected to the node A. The gate of the transistor 306 is connected to the wiring 118. The second terminal of the transistor 307 is connected to the wiring 111. The gate of the transistor 307 is connected to the wiring 118 .

[0203] As shown in FIG. 17C, the transistors 301 to 305 are P-channel transistors. In particular, the transistor 101 described in Embodiment 1 can be used. The transistors 201 to 204 described in the second embodiment are P-channel transistors. When transistors are used, the transistors 301 to 305 are P-channel type. It is preferable to use transistors such as transistor 301p, transistor 302p, The transistor 303p, the transistor 304p, and the transistor 305p are Transistor 301, transistor 302, transistor 303, transistor 304, Compatible with Transistor 305.

[0204] As in FIG. 17(C), FIGS. 14(A) to 14(C), 15(A) to 15(B), and 16( 17A to 17B, the transistors 301 to 305 are also Therefore, a P-channel transistor can be used.

[0205] As already described, the circuit 105 included in the circuit 100 described in Embodiment 1 may be replaced with The configuration of the circuit 105 described in the embodiment can be used. For example, the circuit 105 included in the circuit 100 in FIG. 1A may be replaced with the circuit 105 in FIG. 18(B) shows an example of the configuration of the case where the The circuit 105 included in the circuit 100 is an example of the circuit 105 in FIG. 12A. When an example of the circuit 104 in FIG. 9A is used as the circuit 104 included in the circuit 100 in FIG. However, the present invention is not limited to this configuration, and other configurations may be used, such as those shown in FIGS. 12(A), 14(A), and 14(B). ,Fig. 14(C),Fig. 15(A),Fig. 15(B),Fig. 16(A),Fig. 16(B),Fig. 17( 17(A), 17(B), 17(C), or a combination thereof. 1(A), Fig. 5(A), Fig. 5(B), Fig. 6(A), Fig. 6(B), Fig. 6(C), Fig. 7(A) 7B, 8A, or a combination thereof. It can be used for 05.

[0206] (Fourth embodiment) In this embodiment, an example of a shift register will be described. The system can include the semiconductor device according to the first to third embodiments. The soft resistor may refer to a semiconductor device or a gate driver. The contents described in the first to third embodiments will not be described here. The contents described in the third embodiment can be freely combined with the contents described in this embodiment. do.

[0207] First, an example of a shift register will be described with reference to FIG. 0 is a multiple flip-flop called flip-flops 401_1 to 401_N (N is a natural number). It has a loop.

[0208] The flip-flops 401_1 to 401_N are the same as those in the first to third embodiments, respectively. 19 corresponds to the semiconductor device described in the section 1. In the example of FIG. 1_N, the semiconductor device shown in FIG. 1(A) is used. However, this is not limited to this. The flip-flops 401_1 to 401_N are the same as those of the semiconductor device of FIG. In addition, the semiconductor devices described in the first to third embodiments, or various other semiconductor devices or It is possible to use a circuit.

[0209] Next, the connection relationship of the shift register will be described. 1_1 to 411_N, which are connected to wiring 412, wiring 413, wiring 414, and wiring 415. Then, in the flip-flop 401_i (i is any one of 1 to N), the wiring 1 11 is connected to the wiring 411_i, and the wiring 112 is connected to one of the wiring 412 and the wiring 413. The wiring 113 is connected to the other of the wiring 412 and the wiring 413, and the wiring 114 is connected to the wiring 41 1_i-1, the wiring 115 is connected to the wiring 411_i+1, and the wiring 116 is connected to the wiring 416. Here, the odd-numbered flip-flops and the even-numbered flip-flops are connected In the above, the connection destinations of the wiring 112 and the wiring 113 are often reversed. In the flip-flop of the stage, the wiring 112 is connected to the wiring 412, and the wiring 113 is connected to the wiring When the wiring 112 is connected to the wiring 413 in the flip-flops of the even number stages, 3, and the wiring 113 is often connected to the wiring 412. In the flip-flop, the wire 112 is connected to the wire 413, and the wire 113 is connected to the wire 412. When the flip-flops are connected, the wiring 112 is connected to the wiring 412 in the even-numbered stages. In many cases, the wiring 113 is connected to the wiring 413. However, this is not limiting and other Various connection configurations are possible.

[0210] In the flip-flop 401_1, the wiring 114 may be connected to the wiring 414. In the flip-flop 401_N, the wiring 115 is connected to the wiring 415. This is often the case.

[0211] The wirings 411_1 to 411_N are the wirings described in the first to third embodiments, respectively. The wiring 412 corresponds to the wiring 112 or the wiring 111 described in the first to third embodiments. The wiring 413 corresponds to the wiring 113. The wiring 414 corresponds to the wiring 113 described in the first to third embodiments. The wiring 415 corresponds to the wiring 115 described in the first to third embodiments. The wiring 416 corresponds to the wiring 116 described in the first to third embodiments.

[0212] Next, the wirings 411_1 to 411_N, the wiring 412, the wiring 413, the wiring 414, and the wiring 415 An example of a signal or voltage input to or output from the wiring 411 will be described. For example, signals GOUT_1 to GOUT_N are output from the inputs 1 to 411_N, respectively. The signals GOUT_1 to GOUT_N are output from the flip-flops 401_1 to 401_N, respectively. The signals GOUT_1 to GOUT_N are output signals of the Corresponding to the signal OUT described in the first to third embodiments, the signal includes an output signal, a selection signal, a transfer signal, and a start signal. It can function as a start signal, a reset signal, a gate signal, or a scan signal. As an example, a signal GCK is input to the wiring 412. This corresponds to the signal IN1 or IN2 described in the first to third embodiments, and is used as a clock signal. For example, the signal GCKB is input to the wiring 413. The signal GCKB is the signal IN1 or the signal IN2 described in the first to third embodiments. The wiring 414 corresponds to the IN2 and can function as an inverted clock signal. As an example, it is assumed that the signal GSP is input. It corresponds to the signal IN3 described in form 3 and functions as a start signal or a vertical synchronization signal. As an example, the signal GRE is input to the wiring 415. The signal GRE corresponds to the signal IN4 described in the first to third embodiments, and is a reset signal. The wiring 416 can function as a voltage V1, for example. However, the present invention is not limited to this, and the wirings 411_1 to 411_N, the wiring 412, the wiring 413, wiring 414, wiring 415, and / or wiring 416 may also carry various other signals. For example, the wiring 412, the wiring 413, and the wiring 414 can be connected to each other. 3. A voltage such as voltage V1 or voltage V2 is supplied to the wiring 414 and / or wiring 415. Alternatively, the signals GOUT_1 to GOUT_N and the signal Signals such as GCK, signal GCKB, signal GSP, or signal GRE can be input. Alternatively, the wirings 411_1 to 411_N, the wiring 412, the wiring 413, the wiring 414, Without inputting a signal or voltage to the wiring 415 and / or the wiring 416, It is possible to make the

[0213] The wirings 411_1 to 411_N are used as signal lines, gate lines, scanning lines, or output signal lines. The wiring 412 can function as a signal line or a clock signal line. The wiring 413 can function as a signal line or a clock signal line. The wiring 414 can function as a signal line. The wiring 415 can function as a signal line. The wiring 416 can function as a power supply line or a ground line. However, the present invention is not limited to this, and the wirings 411_1 to 411_N, wiring The line 412, the wiring 413, the wiring 414, the wiring 415, and / or the wiring 416 may be various other For example, the wiring 412, the wiring 413, the wiring 414, and the wiring 415 can function as various wirings. 4 and / or wiring 415, these wirings are used as power supply lines. Alternatively, when a signal is input to the wiring 416, the wiring 416 can function as a signal line.

[0214] As already mentioned, the shift register can be supplied with a multiphase clock signal or an unbalanced clock signal. A lock signal can be input.

[0215] The wiring 412, the wiring 413, the wiring 414, the wiring 415, and the wiring 416 are connected to the circuit 4. The circuit 420 receives a signal or voltage from the shift register 40. 0 to control the shift register 400. The present embodiment has a control circuit, a controller, or the like. As an example, the circuit 420 includes wiring 412, wiring 413, wiring 414, wiring 415, and wiring 416, which respectively transmits a signal GCK, a signal GCKB, a signal GSP, a signal GRE, and a voltage V However, the circuit 420 is not limited to this and may be configured to provide a shift register 4 00, as well as various other circuits (for example, a signal line driving circuit, a scanning line driving circuit, and / or It is possible to supply signals or voltages to the individual elements (e.g., the pixel) to control these circuits. .

[0216] Note that the circuit 420 includes, for example, a circuit 421 and a circuit 422. The circuit 421 generates power supply voltages such as a positive power supply voltage, a negative power supply voltage, a ground voltage, and a reference voltage. The circuit 42 has a function of supplying a power to the power supply circuit or a regulator. 2 is a clock signal, an inverted clock signal, a start signal, a reset signal, and / or a It has the function of generating various signals such as video signals and functions as a timing generator. However, the circuit 420 can be implemented by the circuit 421 and the circuit 422. In addition to the circuit 22, various circuits or elements may be included. For example, the circuit 42 0 is an oscillator, a level shift circuit, an inverter circuit, a buffer circuit, a DA conversion circuit, AD conversion circuit, operational amplifier, shift register, look-up table, coil, transistor The circuit may include a resistor, a capacitive element, a resistive element, and / or a frequency divider.

[0217] Next, the operation of the shift register in FIG. 19 will be explained with reference to the timing chart in FIG. 20. FIG. 20 is an example of a timing chart for explaining the operation of the shift register. FIG. 20 shows the signals GSP, GRE, GCK, GCKB, and GOU. T_1, signal GOUT_i-1, signal GOUT_i, signal GOUT_i+1, and signal G OUT_N. Note that the same operations as those of the semiconductor devices of the first to third embodiments are also shown. Where necessary, the explanation will be omitted.

[0218] The operation of the flip-flop 401_i will be described. First, when the signal GOUT_i-1 is H, Then, the flip-flop 401_i starts its operation in the period T1. Then, the signal GOUT_i becomes L level. Then, the signals GCK and GCKB are inverted. Then, the flip-flop 401_i starts its operation in the period T2, and the signal GOU T_i becomes H level. The signal GOUT_i is reset to the flip-flop 401_i-1. The signal is input to the flip-flop 401_i+1 as a start signal. Therefore, the flip-flop 401_i-1 starts its operation in the period T3. , the flip-flop 401_i+1 starts operation in the period T1. Then, the signal The GCK and GCKB signals are inverted again. Then, the flip-flop 401_i+1 The operation in the period T2 starts, and the signal GOUT_i+1 becomes H level. _i+1 is input to the flip-flop 401_i as a reset signal. , the flip-flop 401_i starts operating in the period T3, so that the signal GOUT_ After that, the signal GOUT_i-1 goes low until it goes high again. The flip-flop 401_i is inverted every time the signals GCK and GCKB are inverted during the period T4. The operation in period T1 and the operation in period T5 are repeated.

[0219] In addition, in the flip-flop 401_1, instead of the output signal of the previous stage flip-flop, Then, the signal GSP is input from the circuit 420 via the wiring 414. When it becomes H level, the flip-flop 401_1 starts operation in the period T1.

[0220] In addition, in the flip-flop 401_N, instead of the output signal of the next stage flip-flop, The signal GRE is input from the circuit 420 via the wiring 415. When it becomes H level, the flip-flop 401_N starts operation in the period T3.

[0221] The operation of the shift register of this embodiment has been described above. By using the semiconductor device according to the first to third embodiments, It is possible to obtain the same advantages as the device.

[0222] As will be described in the first to third embodiments, the relationship between the signal GCK and the signal GCKB For example, as shown in the timing chart of FIG. In this way, the period when the signals GCK and GCKB are at the H level is the same as the period when the signals GCK and GCKB are at the L level. By doing so, the signals GOUT_1 to GOUT Even if delay or distortion occurs in N, the period during which these signals are at H level is prevented. Therefore, when the shift register of this embodiment is used in a display device, This can prevent multiple rows from being selected at the same time. In the signal GCK and / or the signal GCKB, the period during which the signal is at the H level is the period during which the signal is at the L level. It is possible to do this for longer than that.

[0223] As will be described in the first to third embodiments, it is possible to use a multiphase clock signal. For example, as shown in the timing chart of FIG. 21(B), In this case, the signals GOUT_1 to GOUT In N, the period when a certain stage is at H level is the period when the stages before and after it are at H level. Therefore, when this embodiment is used in a display device, In this case, multiple rows are selected at the same time, which reduces the video signal to the pixels in other rows. This makes it possible to use the signal as a precharge voltage.

[0224] In FIG. 21(B), it is preferable that M≦8. More preferably, it is preferable that M≦6. It is more preferable that M≦4. When the register is used in a scanning line driving circuit of a display device, if M is too large, multiple This is because several kinds of video signals are written to the pixel. This is because the period during which the signal is input becomes longer, which may result in a decrease in display quality.

[0225] As in FIG. 21(B), the timing chart in FIG. 21(A) also includes a multi-phase clock. A lock signal can be used.

[0226] The wiring 415 can be shared with other wirings or can be omitted. 415 may be shared with wiring 412, wiring 413, wiring 414, or wiring 416. In this case, the wiring 415 is omitted, and the wiring The line 115 may be connected to the wiring 412, the wiring 413, the wiring 414, or the wiring 416. As another example, the wiring 415 can be omitted. In the flip-flop 401_N, as in FIG. 14B, the transistor included in the circuit 105 The transistor 303 and the transistor 304 can be omitted.

[0227] Depending on the configuration of the flip-flops 401_1 to 401_N, new wiring may be added. For example, as shown in FIG. 17(A) or FIG. 17(B), the voltage V2 or If you need a signal that can function as a reset signal for all stages, you will need to add a new wiring. The newly added wiring can be used to transmit signals from the circuit 420 or can be supplied with a voltage or the like.

[0228] As shown in FIG. 22, the flip-flops 401_1 to 401_N are each It is possible to add a transistor 431. The polarity of the transistor 431 is It is preferable that the polarity is the same as 101, and it is often an N-channel type. Without being limited thereto, the transistor 431 can be a P-channel type. In the flip-flop 401_i, a first terminal of the transistor 431 is connected to the wiring 112. The second terminal of the transistor 431 is connected to the wiring 417_i. The gate of the flip-flop 401_i is connected to the node A. The line 111 is connected to the wiring 411_i, and the wiring 112 is connected to one of the wiring 412 and the wiring 413. The wiring 113 is connected to the other of the wiring 412 and the wiring 413, and the wiring 114 is connected to the other of the wiring 412 and the wiring 413. The wiring 115 is connected to the wiring 411_i+1, and the wiring 11 6 is connected to the wiring 416. By doing so, the wirings 411_1 to 411_N are Even when a load such as a pixel or gate line is connected, the next stage flip-flop is driven. Therefore, there is no distortion or delay in the transfer signal for the shift register. The influence of delay can be reduced. However, the present invention is not limited to this. 11_i−1. Alternatively, the wiring 115 can be connected to the wiring 417_i+ Alternatively, the potential of the wirings 417_1 to 417_N can be set to V1. It is possible to add a new transistor to maintain the current.

[0229] In FIG. 22, the signals GCK and GCKB are unbalanced in the same manner as in FIG. 21(A). Alternatively, similar to FIG. 21(B), a multi-phase clock signal can be used. It is possible.

[0230] (Embodiment 5) In this embodiment, an example of a display device will be described.

[0231] First, an example of a system block of a liquid crystal display device will be described with reference to FIG. 23(A). The liquid crystal display device includes a circuit 5361, a circuit 5362, a circuit 5363_1, a circuit 5363_2, a circuit 5363_3, a circuit 5363_4, a circuit 5363_5, a circuit 5363_6, a circuit 5363_7, a circuit 5363_8, a circuit 5363_9, a circuit 5363_10, a circuit 5 2, a pixel portion 5364, a circuit 5365, and a lighting device 5366. In the figure, a plurality of wirings 5371 are arranged extending from a circuit 5362, and a plurality of wirings 5372 are arranged in a circuit. The wiring 5363_1 and the wiring 5363_2 are arranged to extend from each other. The intersections of the line 5371 and the wirings 5372 each have a display element such as a liquid crystal element. Pixels 5367 corresponding to the pixel area are arranged in a matrix.

[0232] The circuit 5361 is connected to the circuit 5362, the circuit 5363_1, the circuit 5364, the circuit 5365, and the circuit 5366 in response to the video signal 5360. 363_2 and the circuit 5365, and has a function of supplying a signal, a voltage, a current, or the like to the controller, control circuit, timing generator, power supply circuit, regulator, etc. In this embodiment, as an example, the circuit 5361 can function as a 362, a start signal for the signal line driver circuit (SSP), a clock signal for the signal line driver circuit ( SCK), inverted clock signal for signal line driver circuit (SCKB), data for video signal (DA TA), and a latch signal (LAT). Then, a start signal for the scanning line driving circuit (G SP), clock signal for the scanning line driving circuit (GCK), and clock signal for the inverted scanning line driving circuit Alternatively, the circuit 5361 may supply a signal (GCKB) to the circuit 5365. The circuit is intended to provide a backlight control signal (BLC), but is not limited to this. 5361 also transmits various other signals, various voltages, or various currents to a circuit 5362, a circuit The signal can be supplied to a circuit 5363_1, a circuit 5363_2, and a circuit 5365.

[0233] The circuit 5362 receives signals (e.g., SSP, SCK, SCKB) supplied from the circuit 5361. , DATA, LAT) to output video signals to multiple wirings 5371. The circuit 5363_1 and the circuit 536_2 can function as a signal line driver circuit. 3_2 runs in response to the signals (GSP, GCK, GCKB) supplied from the circuit 5361. It has a function of outputting scanning signals to a plurality of wirings 5372 and functions as a scanning line driver circuit. The circuit 5365 performs the following in response to the signal (BLC) supplied from the circuit 5361: By controlling the amount of power supplied to the lighting device 5366 or the time, the lighting device It has the function of controlling the brightness (or average brightness) of 5366 and can function as a power supply circuit. It is possible.

[0234] When video signals are input to the multiple wirings 5371, the multiple wirings 5371 The wirings 53 can function as lines, video signal lines, source lines, or the like. When a scanning signal is input to 72, the plurality of wirings 5372 are signal lines, scanning lines, or gate lines. It can function as a line, etc., but is not limited to this.

[0235] Note that the same signal is input from the circuit 5361 to the circuits 5363_1 and 5363_2. In this case, the circuit 5363_1 outputs scan signals to the wirings 5372 and the circuit 5363 The timing of the scanning signals output from the _2 to the multiple wirings 5372 is approximately the same. Therefore, the loads driven by the circuits 5363_1 and 5363_2 are reduced. Therefore, the display device can be made larger. Alternatively, the circuits 5363_1 and 5363_2 may have high resolution. Since the channel width of the transistor can be reduced, a display device with a narrow frame can be obtained. However, the present invention is not limited to this, and the circuit 5361 can be implemented by a circuit 5363_1 and a circuit 536 It is possible to supply separate signals to 3_2.

[0236] Note that one of the circuit 5363_1 and the circuit 5363_2 can be omitted.

[0237] In addition, in the pixel portion 5364, wiring such as a capacitance line, a power supply line, and a scanning line can be newly arranged. The circuit 5361 can output a signal or a voltage to these wirings. Alternatively, a circuit similar to the circuit 5363_1 or the circuit 5363_2 may be newly added. This newly added circuit outputs signals such as scanning signals to the newly added wiring. It is possible.

[0238] The pixel 5367 can have a light-emitting element such as an EL element as a display element. In this case, as shown in FIG. 23(B), the display element can emit light, so that the circuit 5 365 and the lighting device 5366 can be omitted. In order to supply power, a plurality of wirings 5373 that can function as power supply lines are provided in the pixel portion 53 64. The circuit 5361 distributes a power supply voltage called voltage (ANO). The wiring 5373 is connected to each color element of the pixel. It can be connected to all pixels in common.

[0239] Note that in FIG. 23B, as an example, the circuit 5361 includes a circuit 5363_1 and a circuit 536 3_2. The circuit 5361 is a circuit for a scanning line driver circuit. Start signal (GSP1), clock signal for scanning line driving circuit (GCK1), and inverse scanning A signal such as a clock signal (GCKB1) for the line driving circuit is supplied to the circuit 5363_1. The circuit 5361 outputs a start signal (GSP2) for the scanning line driving circuit, Clock signal (GCK2), clock signal for inverted scanning line driver circuit (GCKB2), etc. In this case, the circuit 5363_1 supplies the signal to the circuit 5363_2. 72, and the circuit 5363_2 scans only the odd-numbered wirings among the plurality of wirings 5372. That is, only the wirings in the even rows can be scanned. Since the driving frequency of the circuit 5363_2 can be reduced, power consumption can be reduced. Alternatively, the area in which one stage of flip-flops can be laid out can be increased. Therefore, the display device can be made high-definition. However, the present invention is not limited to this. As in FIG. 23A, the circuit 5361 can be The same signal can be output to the circuit 5363_1 and the circuit 5363_2.

[0240] 23B, the circuit 5361 in FIG. 23A is the same as the circuit 5363 in FIG. It is possible to provide separate signals to the circuit 5363_1 and the circuit 5363_2.

[0241] An example of the system block of the display device has been described above.

[0242] Next, an example of the configuration of the display device will be described with reference to FIGS. 24(A), (B), (C), (D), and ( Please refer to E) for further explanation.

[0243] In FIG. 24A, a circuit (for example, a circuit 5364) having a function of outputting a signal to the pixel portion 5364 is shown. 362, a circuit 5363_1, and a circuit 5363_2 are formed on the same substrate as the pixel portion 5364. The circuit 5361 is formed on a substrate different from the pixel portion 5364. This reduces the number of external components, thereby reducing costs. Since the number of signals or voltages input to the board 5380 is reduced, the board 5380 and the external components can be The number of connections can be reduced, which can improve reliability and yield. can.

[0244] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is a TAB (Ta Flexible PCB (Flexible Printed Circuit) Alternatively, the substrate may be , the pixel part 5364 is mounted on the same substrate 538 by the COG (Chip on Glass) method. It is possible to implement it in 0.

[0245] When the circuit is formed on a substrate different from the pixel portion 5364, the substrate is formed on a single crystal semiconductor. Therefore, it is possible to form a transistor using the substrate. The circuit has the advantages of improved drive frequency, improved drive voltage, and reduced output signal variation. You can get the points.

[0246] A signal, voltage, or current is input from an external circuit via an input terminal 5381. This is often the case.

[0247] In FIG. 24(B), circuits with low drive frequencies (for example, circuit 5363_1, circuit 5363_ 2) is formed on the same substrate 5380 as the pixel portion 5364. The circuit 5362 is formed on a substrate different from that of the pixel portion 5364. The transistors make it possible to configure circuits formed on the substrate 5380. The semiconductor layer of the transistor may be made of a non-single-crystal semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, It is possible to use an organic semiconductor, an oxide semiconductor, or the like. This allows for larger size, a reduction in the number of steps, cost reduction, and an improvement in yield.

[0248] As shown in FIG. 24C, a part of the circuit 5362 (circuit 5362a) is connected to the pixel section 53 The remaining circuit 5362 (circuit 5362b) is formed on the same substrate 5380 as the pixel section 564. The circuit 5362a can be formed on a different substrate from the circuit 364. Circuits that can be configured using transistors (e.g., shift registers, selectors, The circuit 5362b has high mobility and characteristic variations. A circuit (e.g., a shift register) that is preferably constructed using transistors with low They often have a built-in amplifier (e.g., a phase shifter, a latch circuit, a buffer circuit, a DA conversion circuit, an AD conversion circuit, etc.) By doing so, as in FIG. 24(B), a non-single layer can be used as the semiconductor layer of the transistor. A crystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used. This makes it possible to further reduce the number of external parts.

[0249] In FIG. 24(D), a circuit (for example, a circuit 5364) having a function of outputting a signal to the pixel portion 5364 is shown. 362, circuit 5363_1, and circuit 5363_2, etc.), and controlling these circuits A circuit having a function (for example, a circuit 5361) is formed on a substrate different from that of the pixel portion 5364. This makes it possible to form the pixel section and its peripheral circuits on separate substrates. Therefore, the yield can be improved.

[0250] As in FIG. 24(D), in FIGS. 24(A) to 24(C), the circuit 5363_1 and The circuit 5363_2 can be formed on a substrate different from that of the pixel portion 5364.

[0251] In FIG. 24(E), a part of the circuit 5361 (circuit 5361a) is on the same substrate as the pixel portion 5364. 5380, and the remaining circuit 5361 (circuit 5361b) is formed separately from the pixel portion 5364. The circuit 5361a is formed on a substrate. The circuit 5361a is formed by a transistor with low mobility. In some cases, the device has a circuit that can be switched (for example, a switch, a selector, a level shift circuit, etc.). The circuit 5361b uses transistors with high mobility and small variations. A circuit (for example, a shift register, a timing generator, an These often include a resistor, regulator, or analog buffer.

[0252] 24(A) to 24(D), the circuit 5361a and the pixel section 5364 are mounted on the same substrate. The circuit 5361b can be formed on a substrate different from that of the pixel portion 5364.

[0253] The display device of this embodiment has been described above. Therefore, the semiconductor device or shift register according to the first to fourth embodiments can be used. In this case, the circuit 5363_1, the circuit 5363_2, and the pixel portion are formed on the same substrate. By forming the transistors on the substrate, the polarity of all the transistors formed on the substrate is changed to N-channel type. Alternatively, it can be a P-channel type, which reduces the number of processes and improves yield. In particular, the reliability of all transistors can be improved or the cost can be reduced. When the transistor is of N-channel type, the semiconductor layer of the transistor is made of a non-single crystal semiconductor, a microcrystalline It is possible to use a crystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like. This allows for the enlargement of display devices, reduction in costs, and improvement in yield.

[0254] Note that a non-single-crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like may be used as the semiconductor layer. The transistors used as the gate electrodes suffer from degradation of characteristics such as an increase in threshold voltage or a decrease in mobility. However, the semiconductor devices or shift registers according to the first to fourth embodiments are Since the deterioration of transistor characteristics can be suppressed, the life of the display device can be extended. can.

[0255] As a part of the circuit 5362, the semiconductor device of the first to fourth embodiments or the shift For example, the circuit 5362a can be implemented by using a register similar to that in the first to third embodiments. The semiconductor device of the fourth aspect may have a shift register.

[0256] (Embodiment 6) In this embodiment, an example of a signal line driver circuit will be described. It can be referred to as a conductor device or a signal generating circuit.

[0257] An example of a signal line driver circuit will be described with reference to FIG. A plurality of circuits 502_1 to 502_N (N is a natural number), a circuit 500, and a circuit 5 01. Each of the circuits 502_1 to 502_N includes a transistor 503_ The transistor 503 has a plurality of transistors 1 to 503_k (k is a natural number). _1 to 503_k are assumed to be N-channel type. However, this is not limited to this. The transistors 503_1 to 503_k can be P-channel type, and can be CMOS It is possible to use a switch of this type.

[0258] The connection relationship of the signal line driver circuit will be described using the circuit 502_1 as an example. The first terminals of the transistors 503_1 to 503_k are connected to the wiring 505_1. The second terminals of the transistors 03_1 to 503_k are connected to the wirings S1 to Sk, respectively. The gates of the transistors 503_1 to 503_k are connected to the wirings 504_1 to 504_k, respectively. For example, the first terminal of the transistor 503_1 is connected to the wiring 505_1. The second terminal of the transistor 503_1 is connected to the wiring S1. The port is connected to the wiring 504_1.

[0259] The circuit 500 transmits signals to the circuits 502_1 to 502_k via the wirings 504_1 to 504_k. N, and can function as a shift register, decoder, etc. This signal is often a digital signal and can function as a selection signal. The wirings 504_1 to 504_k can function as signal lines. be.

[0260] The circuit 501 has a function of outputting signals to circuits 502_1 to 502_N, and is a video signal generator. For example, the circuit 501 can function as a At the same time, a signal is supplied to the circuit 502_1 via the wiring 505_2. The signal is often an analog signal and functions as a video signal. The wirings 505_1 to 505_N can function as signal lines. It is possible to do this.

[0261] The circuits 502_1 to 502_N select to which wiring the output signal of the circuit 501 is to be output. For example, the circuit 502 has a function of selecting a _1 indicates which of the wirings S1 to Sk the signal output from the circuit 501 to the wiring 505_1 is connected to. It has the function to select whether to output to

[0262] The transistors 503_1 to 503_k are connected to the wiring 5 in response to the output signal of the circuit 500. 05_1 and the wiring S1 to Sk, and functions as a switch. do.

[0263] Next, the operation of the signal line driver circuit of FIG. 25(A) will be explained with reference to the timing chart of FIG. 25(B). 25B shows a signal 514_1 input to a wiring 504_1. , a signal 514_2 input to the wiring 504_2, a signal 514_k input to the wiring 504_k, _k, a signal 515_1 input to the wiring 505_1, and a signal 515_2 input to the wiring 505_2. An example of No. 515_2 is shown below.

[0264] One operation period of the signal line driving circuit corresponds to one gate selection period in the display device. One gate selection period is the period during which pixels belonging to a certain row are selected and a video signal is written to the pixel. This refers to the period during which it is possible to

[0265] One gate selection period is divided into periods T0, T1, and Tk. is a period for simultaneously applying a precharge voltage to pixels belonging to a selected row. The periods T1 to Tk can function as precharge periods. This is the period for writing video signals to pixels belonging to the selected row, and functions as a write period. It is possible to do this.

[0266] For convenience, the operation of the signal line driver circuit will be described using the operation of the circuit 502_1 as an example.

[0267] First, in a period T0, the circuit 500 applies an H-level signal to the wirings 504_1 to 504_k. Then, the transistors 503_1 to 503_k are turned on, and the wiring 505 At this time, the circuit 501 is in a state where the wiring 505_1 and the wirings S1 to Sk are electrically connected to each other. Since the precharge voltage Vp is supplied to the transistor 5 The signals are output to the wirings S1 to Sk via the signals 03_1 to 503_k. The charge voltage Vp is written to the pixels belonging to the selected row, so that the The corresponding pixels are precharged.

[0268] Next, in the period T1, the circuit 500 outputs an H-level signal to the wiring 504_1. Then, the transistor 503_1 is turned on, and the wiring 505_1 and the wiring S1 are brought into a conductive state. Then, the wiring 505_1 and the wirings S2 to Sk are in a non-conductive state. If the circuit 501 outputs a signal Data (S1) to the wiring 505_1, the signal D The ata (S1) is output to the wiring S1 through the transistor 503_1. The signal Data(S1) is supplied to the pixels in the selected row among the pixels connected to the wiring S1. It is written in simple terms.

[0269] Next, in the period T2, the circuit 500 outputs an H-level signal to the wiring 504_2. Then, the transistor 503_2 is turned on, and the wiring 505_2 and the wiring S2 are brought into a conductive state. Then, the wiring 505_1 and the wiring S1 are brought into a non-conductive state, and the wiring 505_1 and The wirings S3 to Sk remain in a non-conductive state. At this time, the circuit 501 outputs the signal Data( S2) is output to the wiring 505_1, the signal Data (S2) is In this way, the signal Data (S2) is output to the wiring S2 via the data input terminal 503_2. Of the pixels connected to line S2, those belonging to the selected row are written.

[0270] After that, until the period Tk, the circuit 500 outputs a high-level signal to the wirings 504_1 to 504_k. Since the signals are output in sequence, the signals are output in the same manner as in the periods T1 and T2, from the period T3 to the period Tk. 00 outputs H-level signals to the wirings 504_3 to 504_k in order. The transistors 503_3 to 503_k are turned on in turn, so that the transistors 503_1 to 503_k are turned on in turn. Therefore, the signal output from the circuit 501 is transmitted to the wirings S1 to Sk in order. In this way, signals can be written in order to the pixels in the selected row. becomes.

[0271] An example of the signal line driver circuit has been described above. Since the circuit has a function as a connector, the number of signals or the number of wirings can be reduced. Alternatively, a voltage for precharging before writing a video signal to the pixel (period T0) is written to the pixel, the time required to write the video signal can be shortened. This allows for larger display devices and higher resolution display devices. It is possible to omit period T0 and not precharge the pixels.

[0272] If k is too large, the time it takes to write to the pixel becomes too short, so the time it takes to write to the pixel of the video signal becomes too short. Writing may not finish in time, so it is preferable that k≦6. More preferably, k≦3. Further preferably, k=2. It's nice.

[0273] In particular, if the color components of a pixel are divided into n (n is a natural number), it is possible to set k=n. For example, if the color components of a pixel are divided into three components, red (R), green (G), and blue (B), , k=3. In this case, one gate selection period includes a period T0, a period T1, , period T2, and period T3. In periods T1, T2, and T3, It is possible to write video signals to red (R), green (G), and blue (B) pixels. However, the order of the periods T1, T2, and T3 is not limited to this, and can be set arbitrarily. It is possible to do this.

[0274] In particular, a pixel has n (n is a natural number) sub-pixels (hereinafter also referred to as sub-pixels or sub-pixels). For example, if a pixel is divided into two sub-pixels, then k=n. In this case, one gate selection period is the period T In the period T1, one of the two sub-pixels In the period T1, a video signal is written to the other of the two sub-pixels. It is possible to do this.

[0275] In addition, since the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are often low, The circuit 500 and the circuits 502_1 to 502_N may be formed on the same substrate as the pixel portion. In this way, it is possible to reduce the number of connections between the substrate on which the pixel section is formed and the external circuit. This allows for improved yield and reliability. As shown in 4(C), the scanning line driver circuit is also formed on the same substrate as the pixel section, This significantly reduces the number of connections to external circuits.

[0276] The circuit 500 may be a semiconductor device or a shift register according to any one of the first to fourth embodiments. In this case, the polarities of all the transistors in the circuit 500 can be changed to It can be made into either an N-channel type or a P-channel type. Therefore, the number of processes can be reduced. This can improve yield or reduce costs.

[0277] It should be noted that not only the circuit 500 but also all the transistors included in the circuits 502_1 to 502_N The polarity of the transistor can be either N-channel or P-channel. 00, and when the circuits 502_1 to 502_N are formed on the same substrate as the pixel portion, the number of steps This can reduce the number of transistors, improve the yield, or reduce the cost. By making the polarity of the transistor N-channel, the semiconductor layer of the transistor can be made non-single-crystal. A crystalline semiconductor, an amorphous semiconductor, a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like can be used. This is because the driving frequencies of the circuit 500 and the circuits 502_1 to 502_N are This is because it is often low.

[0278] (Embodiment 7) In this embodiment, a pixel configuration and pixel operation applicable to a liquid crystal display device will be described. explain.

[0279] 26A shows an example of a pixel. The pixel 5420 includes a transistor 5421, a liquid crystal element The first terminal of the transistor 5421 is connected to a first terminal of the transistor 5422 and a second terminal of the capacitor 5423. is connected to a wiring 5431, and the second terminal of the transistor 5421 is connected to a liquid crystal element 5422. one electrode of the transistor 5421 and one electrode of the capacitor 5423 are connected to the gate of the transistor 5421. The other electrode of the liquid crystal element 5422 is connected to an electrode 5434. The other electrode of the capacitor 5423 is connected to a wiring 5433 .

[0280] For example, a video signal can be input to the wiring 5431. For example, a scan signal, a selection signal, or a gate signal can be input to the input terminal 2. For example, a constant voltage can be supplied to the wiring 5433. For example, 434 may be supplied with a constant voltage. The wiring 5431 is not fixed, and a precharge voltage is supplied to the wiring 5431, so that the The writing time can be shortened. Alternatively, a signal can be input to the wiring 5433. By this, it is possible to control the voltage applied to the liquid crystal element 5422. By inputting a signal to the electrode 5434, frame inversion driving can be realized. It is Noh.

[0281] The wiring 5431 can function as a signal line, a video signal line, or a source line. The wiring 5432 can function as a signal line, a scan line, or a gate line. The wiring 5433 can function as a power supply line or a capacitor line. 4 can function as a common electrode or a counter electrode, but is not limited to this. If a voltage is supplied to the wiring 5431 and the wiring 5432, these wirings are power supply lines. Alternatively, when a signal is input to the wiring 5433, the wiring 5433 can function as a signal line.

[0282] The transistor 5421 controls electrical continuity between the wiring 5431 and one electrode of the liquid crystal element 5422. By controlling the timing of writing a video signal to the pixel, The capacitor 5423 can function as a switch. The potential difference between the electrode and the wiring 5433 is maintained, and the voltage applied to the liquid crystal element 5422 is The capacitor has a function of keeping the capacitance constant, and functions as a storage capacitor. However, the invention is not limited to this.

[0283] FIG. 26B is a timing chart for explaining the operation of the pixel of FIG. 26A. 26B shows an example of a signal 5442_j (j is a natural number), a signal 5442_j+1 , a signal 5441_i (i is a natural number), a signal 5441_i+1, and a voltage 5442 are shown. FIG. 26(B) shows the k-th (k is a natural number) frame and the k+1-th frame. Note that the signals 5442_j, ​​5442_j+1, 5441_i, and 5441_i +1 and a voltage 5442 are signals input to the wiring 5432 in the jth row, and the j+1th row a signal input to the wiring 5432 in the i-th column, a signal input to the wiring 5431 in the i+1-th column, 5 is an example of a signal input to the wiring 5431 and a voltage supplied to the wiring 5432.

[0284] The operation of the pixel 5420 belonging to the jth row and the ith column will be described. When this occurs, the transistor 5421 is turned on. Since the signal 5441_j is connected to one electrode of the transistor 5422, The signal is input to one electrode of the liquid crystal element 5422 through a capacitor 5423. At this time, the potential difference between the potential of one electrode of the liquid crystal element 5422 and the potential of the wiring 5433 is maintained. Therefore, the liquid crystal element 542 remains in the ON state until the signal 5442_j becomes H level again. The voltage applied to the liquid crystal element 5422 is constant. It expresses gradation.

[0285] In FIG. 26B, positive and negative signals are alternately arranged for each row selection period. This shows an example of input to the line 5431. A positive signal is a signal whose potential is equal to or greater than a reference value (for example, A negative signal is a signal whose potential is higher than the reference value. (for example, the potential of the electrode 5434). The signal input to the wiring 5431 can have the same polarity during one frame period. do.

[0286] In addition, in FIG. 26(B), the polarity of the signal 5441_i and the polarity of the signal 5441_i+1 are different. However, the present invention is not limited to this example, and the polarity and The polarity of signal 5441_i+1 may be the same.

[0287] 26B shows a period in which the signal 5442_j is at H level and a period in which the signal 5442_j is at H level. This is an example of a case where the period when +1 is at H level does not overlap. However, this is not limited to this. As shown in FIG. 26(C), there is a period in which the signal 5442_j is at H level and a period in which the signal 5442_j is at H level. 42_j+1 is at H level. In this case, the period when the wiring 543 It is preferable that signals of the same polarity are supplied to all the inputs during one frame. By using the signal 5441_j written to the pixel in the jth row, the pixel in the j+1th row is This allows the time required to write a video signal to the pixel to be shortened. Therefore, the display device can be made high-definition. Alternatively, the same wiring 5431 can be used in one frame period. Since a polarity signal is input, power consumption can be reduced.

[0288] It should be noted that the pixel configuration of FIG. 27(A) and the timing chart of FIG. 26(C) can be combined. In this way, dot inversion driving can be realized. The pixel 5420(i, j) is connected to the wiring 5431_i. j+1) is connected to the wiring 5431_i+1. In this way, the i-th row is connected to the wiring 5431_i and the wiring 5431_i+1 alternately. The pixels belonging to the eye are written with positive and negative polarity signals alternately, row by row. However, the present invention is not limited to this, and the dot inversion driving can be realized. The pixels are arranged in a plurality of rows (for example, two or three rows) alternately with the wiring 5431_i and the wiring 5431 _i+1.

[0289] It is possible to use a sub-pixel structure as the pixel configuration. 27(a) and 27(b) show the configuration in which a pixel is divided into two sub-pixels. Figure 27(B) shows a subpixel structure called 1S+2G, and Figure 27(C) shows a subpixel structure called 2S+1 The subpixel structure shown is called G. Subpixel 5420A and subpixel 5420B are The transistor 5421A and the transistor 5421B correspond to the pixel 5420. The liquid crystal element 5422A and the liquid crystal element 5422B correspond to the liquid crystal element The capacitors 5423A and 5423B correspond to the capacitors 5423 The wiring 5431A and the wiring 5431B correspond to the wiring 5431. 32A and wiring 5432B correspond to wiring 5432.

[0290] The pixel configuration and the pixel driving method of this embodiment have been described above. A pixel and a semiconductor device, a shift register, a display device, or a signal processing device according to any one of the first to sixth embodiments By combining it with a signal line drive circuit, various benefits can be obtained. For example, when a subpixel structure is used as a pixel, the signal required to drive the display device is This increases the number of gate lines or source lines. As a result, the number of connections between the substrate on which the pixel unit is formed and the external circuitry may increase significantly. However, even if the number of gate lines increases, as shown in the fifth embodiment, the scanning line driving circuit can be connected to the pixel Therefore, the substrate on which the pixel section is formed and the substrate on which the outer section are formed can be formed on the same substrate. This allows the use of sub-pixel structure pixels without significantly increasing the number of connections to external circuits. Alternatively, even if the number of source lines increases, the signal line driver circuit of the sixth embodiment may be mounted on the same substrate as the pixel section. Therefore, the substrate on which the pixel part is formed and the external circuit can be easily connected. A pixel with a sub-pixel structure can be used without significantly increasing the number of connections.

[0291] Alternatively, when inputting a signal to a capacitance line, the number of connections between the substrate on which the pixel unit is formed and the external circuit is Therefore, the semiconductor device according to the first to fourth embodiments is provided on the capacitance line. The signals can be supplied using conductor devices or shift registers. The semiconductor device or shift register of the first to fourth embodiments is formed on the same substrate as the pixel section. Therefore, the number of connections between the substrate on which the pixel section is formed and the external circuit can be significantly reduced. Therefore, a signal can be input to the capacitance line without increasing the capacitance.

[0292] Alternatively, when AC driving is used, the time required to write a video signal to a pixel becomes shorter. As a result, there may not be enough time to write the video signal to the pixels. Similarly, when using pixels with a subpixel structure, the time required to write a video signal to the pixel is short. As a result, there may not be enough time to write the video signal to the pixel. Therefore, it is possible to write a video signal to the pixel by using the signal line driver circuit of the sixth embodiment. In this case, a precharge voltage is applied to the pixel before writing a video signal to the pixel. , the video signal can be written to the pixel in a short time. As shown in (B), the period in which one row is selected can overlap with the period in which another row is selected. By this, it is possible to use a video signal of another row as a voltage for precharging. .

[0293] (Embodiment 8) In this embodiment, an example of a cross-sectional structure of a display device will be described with reference to FIGS. Please refer to C) for explanation.

[0294] 29A is an example of a top view of a display device. A pixel portion 5393 is formed. An example of the driver circuit 5392 is a scanning line driver circuit. , or a signal line driver circuit.

[0295] FIG. 29(B) shows an example of the cross section AB of FIG. 29(A). 5400, a conductive layer 5401 formed on the substrate 5400, and An insulating layer 5402 is formed to cover the conductive layer 5401 and the insulating layer 5402. and a semiconductor layer 5403b formed on the semiconductor layer 5403a. a conductive layer 5404 formed on the semiconductor layer 5403b and on the insulating layer 5402; an insulating layer 5405 having an opening formed on the edge layer 5402 and on the conductive layer 5404; a conductive layer 5406 formed on the insulating layer 5405 and in the opening of the insulating layer 5405; an insulating layer 5408 disposed on the layer 5405 and on the conductive layer 5406; a liquid crystal layer 5407 formed on the insulating layer 5408; 5 shows a conductive layer 5409 formed over the conductive layer 5409 and a substrate 5410 formed over the conductive layer 5409 .

[0296] The conductive layer 5401 can function as a gate electrode. The conductive layer 5404 can function as a gate insulating film. The insulating layer 5405 can function as an electrode, an electrode of a capacitor, or the like. The conductive layer 5406 can function as a wiring, a pixel electrode, or a planarization film. The insulating layer 5408 can function as a polarizer or a reflector. The conductive layer 5409 can function as a counter electrode or a common electrode. It is possible.

[0297] Here, a parasitic capacitance may occur between the driver circuit 5392 and the conductive layer 5409. As a result, the output signal of the driver circuit 5392 or the potential of each node may be rounded or delayed. Or, the power consumption will increase. However, as shown in Figure 29(B), As shown in FIG. 5B, an insulating layer 5408 that can function as a sealant is formed on the driver circuit 5392. By forming the conductive layer 5409, the parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 is reduced. This is because the dielectric constant of the sealing material is lower than that of the liquid crystal layer. Therefore, the output signal of the driver circuit 5392 or the potential of each node is Alternatively, the power consumption of the driver circuit 5392 can be reduced. This can be done.

[0298] As shown in FIG. 29C, a film that functions as a sealant is provided on a part of the driver circuit 5392. In this case, an insulating layer 5408 can be formed. The parasitic capacitance generated between the driver circuit 5392 and the conductive layer 5409 can be reduced. Therefore, it is possible to reduce the distortion or delay of the output signal of the driver circuit 5392 or the potential of each node. However, it is not limited to this, and a film that functions as a sealant can be provided on the driver circuit 5392. It is possible that the insulating layer 5408 is not formed.

[0299] The display element is not limited to a liquid crystal element, and may be any of various display elements such as an EL element or an electrophoretic element. It is possible to use a display element.

[0300] In the above, an example of the cross-sectional structure of the display device has been described in the present embodiment. and the semiconductor device or shift register according to any one of the first to fourth embodiments. For example, a semiconductor layer of a transistor may be formed of a non-single-crystal semiconductor or an amorphous semiconductor. When a microcrystalline semiconductor, an organic semiconductor, an oxide semiconductor, or the like is used, the channel of the transistor However, as in this embodiment, the parasitic capacitance of the drive circuit is If the thickness can be reduced, the channel width of the transistor can be reduced. Since the outer area can be reduced, the frame of the display device can be made narrower. This allows the display device to have high definition.

[0301] (Embodiment 9) In this embodiment, examples of the structure of a transistor are shown in FIGS. ) will be referred to for explanation.

[0302] FIG. 30A shows an example of the structure of a top-gate transistor. This is an example of the structure of a bottom-gate transistor. 1 is an example of a structure of a transistor manufactured by

[0303] FIG. 30(A) shows a substrate 5260, an insulating layer 5261 formed on the substrate 5260, The insulating layer 5261 is formed on the insulating layer 5261, and includes a region 5262a, a region 5262b, a region 5262c, and a region A semiconductor layer 5262 having regions 5262d and 5262e, and a semiconductor layer 5262 having a thickness of 100 μm. The insulating layer 5263 is formed as shown in FIG. 5, and the insulating layer 5264 is formed on the semiconductor layer 5262 and the insulating layer 5263. a conductive layer 5264 formed over the insulating layer 5263 and the conductive layer 5264 and having an opening; an insulating layer 5265 formed on the insulating layer 5265 and in the opening of the insulating layer 5265; a layer 5266, a conductive layer 5267 formed on the conductive layer 5266 and on the insulating layer 5265, and having an opening; An insulating layer 5267 and a conductive layer formed on the insulating layer 5267 and in the opening of the insulating layer 5267 5268, and an insulating layer having an opening formed on the insulating layer 5267 and the conductive layer 5268. The insulating layer 5269 is formed on the insulating layer 5269 and in the opening of the insulating layer 5269. 270 and a conductive layer 5271 formed on the insulating layer 5269 and on the light-emitting layer 5270. show.

[0304] FIG. 30B shows a substrate 5300, a conductive layer 5301 formed on the substrate 5300, An insulating layer 5302 formed to cover the conductive layer 5301, and a conductive layer 5301 and an insulating layer 5302 A semiconductor layer 5303a formed on the semiconductor layer 302 and a semiconductor layer 5303b formed on the semiconductor layer 5303a A conductor layer 5303b and a conductive layer formed on the semiconductor layer 5303b and on the insulating layer 5302 a layer 5304, an insulating layer having an opening formed on the insulating layer 5302 and the conductive layer 5304; A border layer 5305 and a conductive layer 5306 formed on the insulating layer 5305 and in the openings of the insulating layer 5305. 306, a liquid crystal layer 5307 disposed on the insulating layer 5305 and on the conductive layer 5306; A conductive layer 5308 formed on the liquid crystal layer 5307 is shown.

[0305] FIG. 30C shows a semiconductor substrate 5352 having a region 5353 and a region 5355, and a semiconductor An insulating layer 5356 formed on the semiconductor substrate 5352 and a an insulating layer 5354 formed on the insulating layer 5356; a conductive layer 5357 formed on the insulating layer 5356; 4. An insulating layer 535 having an opening formed on the insulating layer 5356 and the conductive layer 5357. 8 and a conductive layer 5359 formed on the insulating layer 5358 and in the opening of the insulating layer 5358. In this way, transistors are formed in each of the regions 5350 and 5351.

[0306] The insulating layer 5261 can function as a base film. The insulating layer 5263, the insulating layer 5302, and the insulating layer 5303 function as an isolation layer (for example, a field oxide film). The insulating layer 5356 can function as a gate insulating film. The insulating layer 5301 and the conductive layer 5357 can function as gate electrodes. The insulating layer 5265, the insulating layer 5267, the insulating layer 5305, and the insulating layer 5358 are interlayer films or flat films. The conductive layer 5266, the conductive layer 5304, and the conductive layer 5305 can function as a conductive film. 359 can function as a wiring, an electrode of a transistor, an electrode of a capacitor, or the like. The conductive layer 5268 and the conductive layer 5306 can be used as a pixel electrode, a reflective electrode, or the like. The insulating layer 5269 can function as a bank. The conductive layer 5271 and the conductive layer 5308 can function as a counter electrode, a common electrode, or the like. It is possible to do this.

[0307] Examples of the substrate 5260 and the substrate 5300 include a glass substrate, a quartz substrate, and a silicon substrate. (or single crystal substrate), SOI substrate, plastic substrate, metal substrate, stainless steel substrate, Substrate with steel foil, tungsten substrate, tungsten foil Examples of the glass substrate include a barium borosilicate glass substrate and a flexible substrate. Examples of flexible substrates include polyethylene terephthalate (PET) and aluminoborosilicate glass. Polyethylene naphthalate (PET), polyethylene naphthalate (PEN), polyether sulfonate Plastics such as polyethylene terephthalate (PES), or flexible synthetic resins such as acrylic. Other examples include laminated films (polypropylene, polyester, vinyl, polypropylene, etc.) vinyl fluoride, vinyl chloride, etc.), paper containing fibrous materials, base film (polyester, Polyamide, inorganic vapor deposition film, paper, etc.

[0308] The semiconductor substrate 5352 is, for example, a single-crystal Si substrate having n-type or p-type conductivity. However, it is not limited to this, and a plate similar to the substrate 5260 can be used. The region 5353 can be formed by, for example, introducing impurities into the semiconductor substrate 5352. For example, if the semiconductor substrate 5352 is a p-type conductive region, If the region 5353 has n-type conductivity, it functions as an n-well. On the other hand, when the semiconductor substrate 5352 has an n-type conductivity, the region 5353 has a p-type conductivity. The region 5355 has, for example, a region where impurities are not introduced into the semiconductor substrate 5 352 and functions as a source region or a drain region. The conductive substrate 5352 may have an LDD region formed therein.

[0309] Examples of the insulating layer 5261 include silicon oxide (SiOx), silicon nitride (SiNx), and oxynitride. Silicon oxide (SiOxNy)(x>y), silicon nitride (SiNxOy)(x>y) The insulating layer 5261 has a two-layer structure. For example, a silicon nitride film is provided as the first insulating layer, and a silicon nitride film is provided as the second insulating layer. A silicon oxide film can be provided as an insulating film. The insulating layer 5261 is provided in a three-layer structure. For example, a silicon oxide film is provided as the first insulating film and a silicon dioxide film is provided as the second insulating film. It is possible to provide a silicon nitride film as the first insulating film and a silicon oxide film as the third insulating film.

[0310] An example of the semiconductor layer 5262, the semiconductor layer 5303a, and the semiconductor layer 5303b is a non-single layer. Crystalline semiconductors (amorphous silicon, polycrystalline silicon, microcrystalline silicon, etc.) , single crystal semiconductor, compound semiconductor or oxide semiconductor (ZnO, InGaZnO, SiG e, GaAs, IZO, ITO, SnO, TiO, AlZnSnO(AZTO)), organic Examples include semiconductors and carbon nanotubes.

[0311] For example, the region 5262a is an intrinsic semiconductor layer 5262 to which no impurities are added. However, a small amount of impurity is added to the region 5262a. The impurity added to the region 5262a can be added to the region 5262b, 5262c, 5262d, or 5262e. The regions 5262b and 5262d are preferably lightly doped with impurities. This region functions as an LDD (Lightly Doped Drain) region. However, the area 5262b and the area 5262d can be omitted. The regions 5262c and 5262e are regions in which impurities are added to the semiconductor layer 5262 at high concentration. The region functions as a source region or a drain region.

[0312] The semiconductor layer 5303b is a semiconductor layer to which phosphorus or the like is added as an impurity element. It has n-type conductivity.

[0313] When an oxide semiconductor or a compound semiconductor is used for the semiconductor layer 5303a, The semiconductor layer 5303b can be omitted.

[0314] An example of the insulating layer 5263, the insulating layer 5302, and the insulating layer 5356 is silicon oxide (Si Ox), silicon nitride (SiNx), silicon oxynitride (SiOxNy)(x>y), silicon nitride oxide Films containing oxygen or nitrogen, such as silicon (SiNxOy) (x>y), or their laminated structures There are various types of structures.

[0315] Conductive layer 5264, conductive layer 5266, conductive layer 5268, conductive layer 5271, conductive layer 5301, A conductive layer 5304, a conductive layer 5306, a conductive layer 5308, a conductive layer 5357, and a conductive layer 535 Examples of the conductive film 9 include a single-layer conductive film and a laminated structure thereof. Examples include aluminum (Al), tantalum (Ta), titanium (Ti), and molybdenum. (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni) , platinum (Pt), gold (Au), silver (Ag), copper (Cu), manganese (Mn), cobalt ( Co), niobium (Nb), silicon (Si), iron (Fe), palladium (Pd), carbon ( C), scandium (Sc), zinc (Zn), phosphorus (P), boron (B), arsenic (As) , Gallium (Ga), Indium (In), Tin (Sn), Oxygen (O), Zirconium (Z r), cerium (Ce), or Examples of such compounds include compounds containing one or more elements selected from the above group. In the case of the above, an alloy containing one or more elements selected from the above group (indium tin oxide (I TO), indium zinc oxide (IZO), indium tin oxide with silicon oxide (ITS O), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (CTO), aluminium Odim (Al-Nd), aluminum tungsten (Al-Ta), aluminum zirconium (Al -Zr), aluminum titanium (Al-Ti), aluminum cerium (Al-Ce), magnesium Silver (Mg-Ag), Molybdenum Niobium (Mo-Nb), Molybdenum Tungsten (Mo- W), molybdenum-tantalum (Mo-Ta) alloy materials, and one or more selected from the above group or compounds of nitrogen with multiple elements (titanium nitride, tantalum nitride, molybdenum nitride, etc.) nitride film), or a compound of one or more elements selected from the above group with silicon (thin film). tungsten silicide, titanium silicide, nickel silicide, aluminum silicon, molybdenum Other examples include carbon nanotubes, organic Nanotube materials include nanotubes, inorganic nanotubes, or metallic nanotubes. .

[0316] Silicon (Si) is doped with n-type impurities (such as phosphorus) or p-type impurities (such as boron). It is possible to include

[0317] When copper is used as a conductive layer, it is recommended to use a laminated structure to improve adhesion. is preferred.

[0318] The conductive layer in contact with the oxide semiconductor or silicon may be formed using molybdenum or titanium. It is preferable to use

[0319] By using an alloy material of neodymium and aluminum as the conductive layer, This makes it less likely for the nium to cause hillocks.

[0320] When a semiconductor material such as silicon is used as the conductive layer, The material can be formed simultaneously with the semiconductor layer of the transistor.

[0321] In addition, ITO, IZO, ITSO, ZnO, Si, SnO, CTO, or carbon nanotubes Since the tubes and the like have light-transmitting properties, these materials can be used for the pixel electrode, the counter electrode, or the common electrode. It can be used in light-transmitting parts such as electrodes.

[0322] In addition, by using a low resistance material (such as aluminum) to form a laminated structure, The resistance of the wire can be reduced.

[0323] In addition, a low heat-resistant material (such as aluminum) may be replaced with a high heat-resistant material (such as molybdenum). By using a laminated structure sandwiching low heat resistant materials (such as tantalum, titanium, neodymium, etc.), This makes it possible to improve the heat resistance of wiring, electrodes, etc. while taking advantage of the advantages of the material.

[0324] In addition, materials that react with other materials and change their properties are replaced with materials that do not react easily with those other materials. For example, ITO and aluminum can be used to sandwich or cover the When connecting the ITO and aluminum, neodymium alloy, titanium, molybdenum For example, when connecting silicon and aluminum, Neodymium alloy, titanium, or molybdenum can be sandwiched between silicon and aluminum. It is Noh. These materials are also used for wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. It is possible to do this.

[0325] An insulating layer 5265, an insulating layer 5267, an insulating layer 5269, an insulating layer 5305, and an insulating layer 535 An example of the insulating film 8 is a single-layer insulating film or a laminated structure of these insulating films. Examples include silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride ( Oxygen-containing silicon nitride (SiOxNy) (x>y), silicon oxynitride (SiNxOy) (x>y) Nitrogen-containing films, carbon-containing films such as DLC (diamond-like carbon), or siloxane San resin, epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene Examples of the material include organic materials such as acrylic and the like.

[0326] An example of the light-emitting layer 5270 is an organic EL element or an inorganic EL element. An example of the element is a hole injection layer made of a hole injection material, a hole transport layer made of a hole transport material, a light-emitting layer made of a light-emitting material; an electron transport layer made of an electron transport material; A single layer structure of an electron injection layer, or a layer in which a plurality of materials among these materials are mixed, or These include laminated structures.

[0327] Note that an insulating layer functioning as an alignment film is provided over the insulating layer 5305 and the conductive layer 5306. It is possible to form an insulating layer or the like that functions as a protrusion.

[0328] Note that a color filter, a black matrix, or a protrusion may be formed on the conductive layer 5308. An insulating layer or the like that functions as an alignment film can be formed under the conductive layer 5308. It is possible to form an insulating layer that acts as a barrier.

[0329] In the cross-sectional structure of FIG. 30(A), the insulating layer 5269, the light-emitting layer 5270, and the conductive layer 5271 is omitted, and the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 30(B) are formed on the insulating layer 526. 7 and conductive layer 5268.

[0330] In the cross-sectional structure of FIG. 30(B), the liquid crystal layer 5307 and the conductive layer 5308 are omitted. 30(A) is formed on the insulating layer 530. 5 and on the conductive layer 5306.

[0331] In the cross-sectional structure of FIG. 30(C), the insulating layer 5358 and the conductive layer 5359 are 30(A), an insulating layer 5269, a light-emitting layer 5270, and a conductive layer 5271 are formed. Alternatively, the liquid crystal layer 5307 and the conductive layer 5308 shown in FIG. 30(B) may be formed as an insulating layer. It can be formed on 5267 and on conductive layer 5268.

[0332] In this embodiment, an example of the structure of a transistor has been described. The transistor can be applied to the first to eighth embodiments. In the above (B), the semiconductor layer is a non-single-crystal semiconductor, a microcrystalline semiconductor, an organic semiconductor, or When an oxide semiconductor or the like is used, the transistor may deteriorate. In the semiconductor device, the shift register, or the display device according to the first to eighth embodiments, the transistor This is advantageous because it can suppress deterioration of the star.

[0333] (Embodiment 10) In this embodiment, a layout diagram (hereinafter also referred to as a top view) of a shift register will be described. In this embodiment, as an example, the layer of the shift register described in the fourth embodiment is The contents explained in this embodiment are the same as those in the fourth embodiment. In addition to the shift registers described above, the semiconductor devices and shift registers according to the first to ninth embodiments are also The layout diagram of this embodiment is It should be noted that this is just an example and is not limiting.

[0334] The layout diagram of this embodiment will be described with reference to FIGS. 31 and 32. FIG. 32 shows an example of a layout diagram of a part of a shift register. 4 shows a layout diagram of the flip-flop 401_i.

[0335] The transistors or wirings shown in FIGS. 31 and 32 are formed by a conductive layer 601, a semiconductor layer 60 2, a conductive layer 603, a conductive layer 604, and a contact hole 605. However, the present invention is not limited to this, and other conductive layers, insulating films, or other contact holes may be newly formed. For example, a contact for connecting the conductive layer 601 and the conductive layer 603 can be formed. It is possible to add new holes.

[0336] The conductive layer 601 can include a portion that functions as a gate electrode or a wiring. The conductor layer 602 may include a portion that functions as a semiconductor layer of a transistor. The conductive layer 603 may include a portion that functions as a wiring, a source, or a drain. The conductive layer 604 may include a portion that functions as a transparent electrode, a pixel electrode, or a wiring. The contact hole 605 has the function of connecting the conductive layer 601 and the conductive layer 604. Alternatively, the conductive layer 603 and the conductive layer 604 are connected to each other.

[0337] In the example of FIG. 31, the wiring 412 has an opening 611, and the wiring 413 has an opening 612. In this way, the wiring 412 and the wiring 413 have openings, and thus the parasitic Capacitance can be reduced. Also, damage to transistors caused by electrostatic discharge can be prevented. However, the present invention is not limited to this, and the opening 611 can be formed in the same manner as the wiring 416. Alternatively, the opening 612 can be omitted. As with the wiring 413, an opening can be provided.

[0338] In the example of FIG. 31, an opening is formed at a part of the intersection between the wiring 412 or the wiring 413 and another wiring. By providing this, the cross capacitance of the wiring can be reduced. It is possible to reduce the noise level, or reduce the delay or distortion of signals.

[0339] In the example of FIG. 31, a conductive layer 604 is formed on a part of the conductive layer 603 of the wiring 416. The conductive layer 604 is connected to the conductive layer 606 via a contact hole 605. 03. This reduces the wiring resistance, which reduces the voltage drop. However, the present invention is not limited to this, and the present invention can also be applied to the reduction of signal delay or distortion. The conductive layer 604 and the contact hole 605 can be omitted. As in the wiring 416, in the wiring 412 or the wiring 413, a part of the conductive layer 603 A conductive layer 604 is formed on the conductive layer 603, and the conductive layer 604 is connected to the conductive layer 603. It is possible.

[0340] In the example of FIG. 31, the width of the wiring 412, the width of the wiring 413, and the width of the wiring 414 are The widths of the 16 wirings are shown as wiring width 621, wiring width 622, and width 623, respectively. The width of 611, the length of opening 611, the width of opening 612, and the length of opening 612 are respectively , width 624, length 625, width 626, length 627.

[0341] In many cases, the signals input to the wiring 412 and the wiring 413 are inverted signals. Therefore, the wiring resistance or parasitic capacitance of the wiring 412 is equal to the wiring resistance or parasitic capacitance of the wiring 413. Therefore, the wiring 412 is preferably set to be approximately equal to the wiring Preferably, the opening 611 includes a portion that is approximately equal to the line width 622. Alternatively, the opening 611 may be an opening The width 626 of the opening 612 or the length 627 of the opening 612 may be approximately equal to the width 626 of the opening 612. However, it is not limited to this, and the wiring width 621, the wiring width 622, the width of the opening 611, 624, the width 624 of the opening 611, the length 625 of the opening 611, or the length 625 of the opening 612 627 can be set to various values. For example, the intersection of the wire 412 with other wires The difference capacitance is assumed to be larger than the intersection capacitance between the wiring 413 and other wirings. By reducing the wiring resistance of the wiring 412 and the wiring 413, It is possible to set the delay or accent of the The wiring 412 may include a portion that is larger than the wiring width 622. 611 may include a portion that is smaller than the width 626 of the opening 612; or The opening 611 may include a portion that is shorter than the length 627 of the opening 612. On the other hand, the intersection capacitance between the wiring 412 and the other wiring is smaller than the intersection capacitance between the wiring 413 and the other wiring. In this case, the wiring 412 may include a portion that is smaller than the wiring width 622. Alternatively, opening 611 may include a portion that is greater than width 626 of opening 612. Alternatively, opening 611 may include a portion that is longer than length 627 of opening 612. It is Noh.

[0342] When the wiring 416 does not have an opening, the wiring 416 has a wiring width 621 or a wiring width 62 It is preferable that the wiring 416 includes a portion smaller than 2 because the wiring 416 does not have an opening. Therefore, the wiring resistance of the wiring 416 is small. 16 may include a portion that is larger than the line width 621 or the line width 622.

[0343] In the example of FIG. 32, transistors 101, 102, 103, and Transistor 201, transistor 202, transistor 203, transistor 204, Transistor 301, transistor 302, transistor 303, transistor 304, and and / or the conductive layer 601 and the conductive layer 603 of the second terminal of the transistor 305 The overlapping area is smaller than the overlapping area between the conductive layer 601 and the conductive layer 603 of the first terminal. By doing so, the gate of the transistor 101 or the wiring 401 Alternatively, the concentration of the electric field on the second terminal can be suppressed. Therefore, deterioration or destruction of the transistor can be suppressed. .

[0344] An example of a layout diagram of a shift register has been described above. However, as already mentioned, The layout diagram of this embodiment is an example, and the present invention is not limited to this.

[0345] Note that a semiconductor layer 602 is formed in the area where the conductive layer 601 and the conductive layer 603 overlap. By doing so, the parasitic capacitance between the conductive layer 601 and the conductive layer 603 can be reduced. For the same reason, the conductive layer A semiconductor layer 602 or a conductive layer 603 is formed in the area where the conductive layer 604 overlaps with the semiconductor layer 601. It is possible.

[0346] A conductive layer 604 is formed on a part of the conductive layer 601. It is possible to connect with the conductive layer 604 through the hole 605. This can reduce the wiring resistance. and a conductive layer 604 are formed, and the conductive layer 601 is connected to the corresponding substrate through a contact hole 605. The conductive layer 603 is connected to the conductive layer 604 through another contact hole 605. It is possible to connect with the conductive layer 604. By doing so, the wiring resistance can be further reduced. can be further reduced.

[0347] The conductive layer 604 is formed on a part of the conductive layer 603. It is possible to connect with the conductive layer 604 through the hole 605. This can reduce the wiring resistance.

[0348] Note that the conductive layer 601 or the conductive layer 603 is formed under a part of the conductive layer 604. 604 is connected to the conductive layer 601 or the conductive layer 603 through a contact hole 605. By doing so, the wiring resistance can be reduced. .

[0349] As described in the first embodiment, the transistor 101 has a gate and a first terminal. The parasitic capacitance between the gate and the second terminal of the transistor 101 is made larger than the parasitic capacitance. As shown in FIG. 32, a first electrode of the transistor 101 can be formed by The width of the conductive layer 603 that can be formed is shown as width 631, and the second electrode of the transistor 101 The width of the conductive layer 603 that can function as a It is possible for the width to be larger than the width 632. By doing so, As such, the parasitic capacitance between the gate and the first terminal of the transistor 101 is larger than the parasitic capacitance between the gate and the first terminal of the transistor 101. It is possible to increase the parasitic capacitance between the gate and the second terminal of the capacitor 101. , but is not limited to this.

[0350] (Embodiment 11) In this embodiment, an example of an electronic device will be described.

[0351] 33(A) to 33(H) and 34(A) to 34(D) are diagrams showing electronic devices. These electronic devices include a housing 5000, a display unit 5001, a speaker 5003, an LED Lamp 5004, operation keys 5005 (including operation switches or power switches), connection terminals Child 5006, sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, number of rotations, distance, Light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, (including functions to measure flow rate, humidity, gradient, vibration, odor or infrared rays), 5008, etc.

[0352] FIG. 33(A) shows a mobile computer, which includes, in addition to the above, a switch 5009, It may have an infrared port 5010, etc. FIG. 33(B) shows a portable device equipped with a recording medium. A type of image reproducing device (for example, a DVD reproducing device), which, in addition to the above, also has a second display 33C shows a GOG In addition to the above, the display includes a second display unit 5002, a support unit 5012, The game machine may have earphones 5013, etc. Figure 33(D) shows a portable game machine. In addition to the above, it can have a recording medium reading unit 5011, etc. In addition to the components described above, the projector includes a light source 5033, a projection lens 5034, etc. FIG. 33(F) shows a portable gaming machine, which, in addition to the above, has a second display unit 33G shows a television receiver. In addition to the components described above, the image sensor may also include a tuner, an image processor, etc. 33(H) is a portable television receiver, which, in addition to the above, is capable of transmitting and receiving signals. 34(A) is a display, and the above-mentioned In addition to the above, it may have a support stand 5018, etc. Figure 34(B) shows a camera. In addition to the above, an external connection port 5019, a shutter button 5015, an image receiving unit 5016, etc. FIG. 34(C) is a computer, and In addition, there are a pointing device 5020, an external connection port 5019, a reader / writer 5 021, etc. FIG. 34(D) shows a mobile phone, which can have the above-mentioned 2, an antenna 5014, a 1-segment partial reception service tuner for mobile phones and mobile terminals It may have a lens, etc.

[0353] The electronic devices shown in FIGS. 33(A) to 33(H) and 34(A) to 34(D) are various For example, various information (still images, videos, text images, etc.) Function to display on the display, touch panel function, calendar, date or time, etc. Functions, functions to control processing by various software (programs), wireless communication functions, The ability to connect to various computer networks using wireless communication functions, The function of transmitting or receiving various data using the program or The data can be read out and displayed on the display unit. In electronic devices with displays, one display is used primarily to display image information, and another is used A function that mainly displays text information on one display unit, or a function that takes parallax into account on multiple displays By displaying an image, it is possible to have a function of displaying a three-dimensional image. In electronic devices with an image receiving unit, there are functions for taking still images, taking videos, and The function to automatically or manually correct the captured image, and to save the captured image to a recording medium (external or camera). It can have functions such as saving the captured image to a built-in memory, displaying the captured image on the display, etc. Note that the electronic devices shown in FIGS. 33(A) to 33(H) and 34(A) to 34(D) The functions that can be possessed by the are not limited to these, and the function can have various functions.

[0354] The electronic device described in this embodiment has a display unit for displaying some information. The electronic device of this embodiment and the semiconductor device of any one of the first to ninth embodiments are characterized in that: By combining it with a device, a shift register, or a display device, the reliability and yield can be improved. This allows for improved resolution, cost reduction, larger display area, and higher resolution display area. .

[0355] Next, application examples of the semiconductor device will be described.

[0356] FIG. 34(E) shows an example in which a semiconductor device is integrated with a building. ) includes a housing 5022, a display unit 5023, a remote control device 5024 as an operation unit, and a speaker 5025. 025, etc. The semiconductor device is a wall-mounted type that is integrated with the building, and the installation space is limited. It can be installed without requiring a large space.

[0357] FIG. 34(F) shows another example in which a semiconductor device is provided inside a building as an integral part of the building. The display panel 5026 is attached to the unit bath 5027 as a unit. The display panel 5026 becomes viewable.

[0358] In this embodiment, a wall and a unit bath are used as examples of buildings. The manner in which the semiconductor device is installed is not limited to this, and the semiconductor device can be installed in various buildings.

[0359] Next, an example in which the semiconductor device is integrated with a moving object will be described.

[0360] FIG. 34G shows an example in which the semiconductor device is provided in an automobile. 5028 is attached to the body 5029 of the automobile, and is The information entered can be displayed on demand. It may be possible.

[0361] FIG. 34(H) is a diagram showing an example in which a semiconductor device is integrated with a passenger airplane. FIG. 34(H) shows a passenger plane with a display panel 5031 mounted on a ceiling 5030 above the seats. The display panel 5031 is attached to the ceiling 50. 30 and the hinge part 5032 are attached together, and the extension and contraction of the hinge part 5032 This allows passengers to view the display panel 5031. The display panel 5031 is operated by passengers. It has the function of displaying information by

[0362] In this embodiment, the moving body is exemplified by an automobile body and an airplane body. However, this is not limited to motorcycles, four-wheeled vehicles (including cars, buses, etc.), trains (monorails, etc.), It can be installed on a variety of things, including buildings, railways, ships, etc. [Explanation of symbols]

[0363] 100 circuits 101 Transistor 102 transistor 103 Transistor 104 circuits 105 circuits 106 circuits 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 116 Wiring 117 Wiring 118 Wiring 121 Capacitor element 122 transistors 201 Transistor 202 Transistor 203 Transistor 204 Transistor 221 Capacitor element 301 Transistor 302 Transistor 303 Transistor 304 Transistor 305 Transistor 306 Transistor 307 Transistor 400 Shift Registers 401 Flip-Flop 411 Wiring 412 Wiring 413 Wiring 414 Wiring 415 Wiring 416 Wiring 417 Wiring 420 circuits 421 circuits 422 circuits 431 Transistor 500 circuits 501 circuits 502 circuits 503 Transistor 504 Wiring 505 Wiring 514 signal 515 Signal 540 pixels 601 Conductive layer 602 Semiconductor layer 603 Conductive layer 604 Conductive layer 605 Contact Hole 611 Opening 612 Opening 621 Wiring width 622 Wiring width 623 width 624 width 626 width 631 width 632 width 101p transistor 102a diode 102p transistor 103a diode 103p transistor 104a terminal 104b terminal 104c terminal 104d terminal 105a terminal 105b terminal 105c terminal 105d terminal 105e terminal 105f terminal 105g terminal 111A wiring 112A wiring 112B wiring 112C wiring 112D Wiring 113A wiring 113B wiring 114A wiring 114B wiring 115A wiring 115B wiring 116A wiring 116B wiring 116C wiring 116D Wiring 116E wiring 116F wiring 116G wiring 116H Wiring 116I wiring 201p transistor 202a diode 202p transistor 203a diode 203p transistor 204p transistor 301p transistor 302p transistor 3030 transistor 303a diode 303p transistor 304a diode 304p transistor 305a diode 305p transistor 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED lamp 5005 Operation key 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 pointing device 5021 Reader / Writer 5022 Housing 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Panel 5027 Unit bath 5028 Display Panel 5029 Car Body 5030 Ceiling 5031 Display Panel 5032 Hinge part 5033 Light source 5034 Projection lens 5260 board 5261 Insulation layer 5262 Semiconductor layer 5263 Insulation layer 5264 Conductive layer 5265 Insulation layer 5265 Insulating film 5266 Conductive layer 5267 Insulation layer 5268 Conductive layer 5269 Insulation layer 5269 Insulating film 5270 luminous layer 5271 Conductive layer 5273 Insulation layer 5300 board 5301 Conductive layer 5302 Insulation layer 5304 Conductive layer 5305 Insulation layer 5306 Conductive layer 5307 Liquid crystal layer 5308 Conductive layer 5321 Transistor 5350 area 5351 area 5352 Semiconductor substrate 5353 area 5354 Insulation layer 5355 area 5356 Insulation layer 5357 Conductive layer 5358 Insulation layer 5359 Conductive layer 5360 video signal 5361 Circuit 5362 Circuit 5362 Wiring 5363 Circuit 5364 Pixel section 5365 Circuit 5366 Lighting equipment 5367 pixels 5371 Wiring 5372 Wiring 5373 Wiring 5380 PCB 5381 input terminal 5391 Circuit Board 5392 drive circuit 5393 Pixel section 5400 board 5401 Conductive layer 5402 Insulation layer 5404 Conductive layer 5405 Insulation layer 5406 Conductive layer 5408 Insulation layer 5409 Conductive layer 5410 PCB 5420 pixels 5421 Transistor 5421 Wiring 5422 Liquid crystal element 5423 Capacitor 5431 Wiring 5432 Wiring 5433 Wiring 5434 Electrode 5441 Signal 5442 signal 5262a area 5262b area 5262c area 5262d area 5262e area 5303a Semiconductor layer 5303b Semiconductor layer 5361a circuit 5361b circuit 5362a circuit 5362b circuit 5403a Semiconductor layer 5403b Semiconductor layer 5420A Subpixel 5420B subpixel 5421A Transistor 5421B Transistor 5422A Liquid Crystal Element 5422B Liquid Crystal Element 5423A Capacitive Element 5423B Capacitive Element 5431A Wiring 5431B Wiring 5432A Wiring 5432B Wiring

Claims

[Claim 1] A substrate; a first conductive layer having a region located above the substrate and functioning as a gate electrode; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating film; a semiconductor layer having a region located above the first insulating layer and having a channel formation region; a second conductive layer having a region located above the semiconductor layer and functioning as a source electrode or a drain electrode; a second insulating layer having a region located above the second conductive layer.

Images