Manufacturing method of wiring board

Abstract

To improve yield in manufacturing of a wiring board.SOLUTION: A manufacturing method of a wiring board according to an embodiment includes steps of: preparing a glass substrate having one or a plurality of product areas; and forming a build-up portion by laminating a conductor layer 12 and an insulating layer 11 over the product areas. The thickness of the glass substrate is 0.5 mm or more and 2.0 mm or less, and includes alternately laminating three or more conductor layers 12 and three or more insulating layers 11. The shape of each product area is rectangular in which a dimension of each side is 80 mm or more and 240 mm or less, and laminating the conductor layer 12 includes forming a resist layer having a resist pattern, forming a minimum value of the width of the wiring included in a conductor pattern to 2 μm or less, and forming a minimum value of an interval of a wiring to 2 μm or less, and forming a resist layer includes exposing the resist layer by a direct imaging exposure.SELECTED DRAWING: Figure 3J

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a wiring board. [Background technology]

[0002] Patent Document 1 discloses a method for manufacturing a wiring substrate including a second wiring substrate and a first wiring substrate. The first wiring substrate is formed by laminating an insulating resin and a wiring layer on a support substrate including a glass substrate. The wiring layer on the insulating resin is formed by filling a conductor into openings in a resist pattern. After the first wiring substrate is bonded to the second wiring substrate, the support substrate is peeled off. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-4926 Summary of the Invention [Problem to be solved by the invention]

[0004] In the method for manufacturing a wiring board disclosed in Patent Document 1, warping may occur in the support substrate, insulating resin, and wiring layer when laminating the insulating resin and wiring layer on the support substrate. Defects may occur in the formation of the wiring layer pattern. The yield in manufacturing the wiring board may be reduced. [Means for solving the problem]

[0005] A method for manufacturing a wiring board of the present invention includes: preparing a glass substrate having one side with one or more product areas and another side opposite the one side; and forming a build-up portion on only the one side by stacking conductor layers and insulating layers across the one or more product areas. The glass substrate has a thickness of 0.5 mm to 2.0 mm, stacking the conductor layers and insulating layers includes alternately stacking three or more conductor layers and three or more insulating layers, each product area having a rectangular shape with each side measuring 80 mm to 240 mm in plan view, stacking the conductor layers includes forming a resist layer having a resist pattern and forming a conductor pattern according to the resist pattern, stacking the conductor layers includes forming the conductor pattern with a minimum width of 2 μm or less and a minimum spacing between the wires of 2 μm or less, and forming the resist layer having the resist pattern includes exposing the resist layer by direct imaging exposure.

[0006] According to the embodiment of the present invention, the degree of warpage that may occur in the process of forming the build-up portion is suppressed, and wiring boards can be manufactured efficiently with a high yield. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view showing an example of a wiring substrate manufactured by a manufacturing method according to an embodiment of the present invention. [Figure 2] FIG. 10 is a cross-sectional view showing another example of a wiring substrate manufactured by the manufacturing method of one embodiment of the present invention. [Figure 3A] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3B] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3C] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3D] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3E] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3F] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3G] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3H] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3I] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3J] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3K] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3L] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3M] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3N] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3O] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; [Figure 3P] 1A to 1C are diagrams showing an example of a method for manufacturing a wiring board according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0008] A method for manufacturing a wiring board according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view showing wiring board 1, which is an example of a wiring board manufactured by a manufacturing method according to an embodiment. Note that wiring board 1 is merely one example of a wiring board to be manufactured. The layered structure of the manufactured wiring board and the number of conductor layers and insulating layers are not limited to the layered structure of wiring board 1 shown in FIG. 1 and the number of conductor layers and insulating layers included in wiring board 1. Furthermore, the drawings referred to are not intended to show the exact proportions of the components, but are drawn to facilitate understanding of the features of the present invention.

[0009] The wiring board 1 has a layered structure including a buildup portion made up of a plurality of alternately stacked conductor layers and insulating layers. The buildup portion that constitutes the wiring board 1 has two surfaces (a first surface 1F and a second surface 1B opposite to the first surface 1F) that are perpendicular to the thickness direction. The buildup portion of a wiring board manufactured by the wiring board manufacturing method of one embodiment includes at least a buildup portion 10, as shown in FIG. 1 . The surface (first surface 10F) of the buildup portion 10 constitutes the first surface 1F.

[0010] Buildup section 10 has a second surface 10B as the surface opposite to first surface 10F. As shown in FIG. 1 , wiring board 1 may further include buildup sections 20, 30 on the second surface 10B side of buildup section 10, which are composed of insulating layers and conductor layers that are alternately stacked. Hereinafter, in the description of wiring board 1, buildup section 10 will also be referred to as first buildup section 10, buildup section 20 will also be referred to as second buildup section 20, and buildup section 30 will also be referred to as third buildup section 30.

[0011] The second buildup section 20 has a first surface 20F and a second surface 20B that is the surface opposite to the first surface 20F. The third buildup section 30 has a first surface 30F and a second surface 30B that is the surface opposite to the first surface 30F. As shown in the figure, when the wiring board 1 has the second buildup section 20 and the third buildup section 30 in addition to the first buildup section 10, the first surface 20F of the second buildup section 20 is disposed so as to face the second surface 10B of the first buildup section 10, and the first surface 30F of the third buildup section 30 is disposed so as to face the second surface 20B of the second buildup section 20.

[0012] When the wiring board 1 has a second buildup section 20 and a third buildup section 30 in addition to the first buildup section 10, the second side 1B of the wiring board 1 can be formed by the surface (second side 30B) of the third buildup section 30. Note that when the third buildup section 30 is not formed and the buildup section of the wiring board is formed by the first buildup section 10 and the second buildup section 20, the second side 1B can be formed by the surface (second side 20B) of the second buildup section 20. Furthermore, as will be described later with reference to FIG. 2, when the second buildup section 20 and the third buildup section 30 are not formed and the buildup section of the wiring board 1 is formed by the first buildup section 10, the second side 1B can be formed by the surface (second side 10B) of the first buildup section 10. The wiring board 1 is formed as a coreless wiring board that does not include a core layer.

[0013] The first buildup section 10 includes relatively fine wiring and can have relatively dense circuit wiring. The first buildup section 10 has insulating layers (first insulating layers) 11 and conductor layers (first conductor layers) 12 that are alternately stacked. In a wiring board manufactured by the wiring board manufacturing method of one embodiment, the first buildup section 10 includes at least three insulating layers 11 and at least three conductor layers 12. In the illustrated example, the first buildup section 10 includes five insulating layers 11 and six conductor layers 12.

[0014] The conductor layers 12 facing each other across one insulating layer 11 are connected by via conductors (first via conductors) 13. The conductor layers 12 are patterned to have a predetermined conductor pattern. The first surface 10F of the first buildup section 10 is composed of the surface (top surface) of the conductor layer 12 and the surface (top surface) of the insulating layer 11 exposed from the pattern of the conductor layer 12. The second surface 10B of the first buildup section 10 is composed of the surface (bottom surface) of the insulating layer 11 and the surfaces (bottom surface and side surface) of the conductor layer 12. In the illustrated example, the conductor layer 12 constituting the first surface 10F is formed in a pattern including a plurality of conductor pads 12p.

[0015] 1, the first surface 10F of the first buildup section 10, i.e., the first surface 1F side of the buildup section constituting the wiring board 1, will be referred to as the "top" or "upper side," and the second surface 1B side of the wiring board 1 will be referred to as the "bottom" or "lower side." Furthermore, in each component, the surface facing the first surface 1F side will also be referred to as the "top surface," and the surface facing the second surface 1B side will also be referred to as the "bottom surface."

[0016] In the illustrated example, the conductor pad 12p is the uppermost surface of the first buildup section 10, i.e., the outermost surface of the wiring board 1, and constitutes a component mounting surface of the wiring board 1 to which external electronic components can be connected. The component mounting surface of the wiring board 1 may have multiple component mounting areas. For example, as shown in the example of FIG. 1, two component mounting areas may be formed corresponding to the areas where electronic components E1 and E2 are to be mounted. When mounting external electronic components on the wiring board 1 in the illustrated example, the exposed upper surface of the conductor pad 12p may be electrically and mechanically connected to the external electronic component via, for example, a conductive bonding material (not shown) such as solder between the upper surface and the connection pad of the external electronic component. In this case, a plating layer (not shown) including, for example, a nickel layer and a tin layer may be formed in advance on the upper surface of the conductor pad 12p. Examples of electronic components E1 and E2 that can be mounted on the wiring board 1 include active components such as semiconductor integrated circuit devices and transistors.

[0017] The insulating layer 11 of the first buildup section 10 may be formed using an insulating resin such as an epoxy resin or a phenol resin. The insulating layer 11 may contain any of fluororesin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), and modified polyimide resin (MPI). As will be described in detail later with reference to FIGS. 3A to 3P, the material constituting the insulating layer 11 is selected so that the difference in thermal expansion coefficient between it and the glass substrate on which the first buildup section 10 is formed falls within a predetermined range. For example, a resin material with a thermal expansion coefficient of 25 ppm / °C or less is preferably selected as the material constituting the insulating layer 11.

[0018] Examples of conductors constituting the conductor layer 12 and the via conductors 13 include copper and nickel, and copper is preferably used. For ease of viewing, the conductor layer 12 and the via conductors 13 are shown as single layers in Fig. 1, but the conductor layer 12 and the via conductors 13 may have a multi-layer structure. For example, the conductor layer 12 and the via conductors 13 may have a two-layer structure including a metal film layer (e.g., a sputtering film layer or an electroless plating film layer) and a plating film layer (e.g., an electrolytic plating film layer).

[0019] The via conductors 13, which penetrate the insulating layer 11 in the thickness direction, are formed by filling through holes 11a penetrating the insulating layer 11 with a conductor. In the example of FIG. 1, the via conductors 13 are integrally formed with the conductor layer 12 provided below them. Therefore, the via conductors 13 and the conductor layer 12 may be formed using the same metal film layer and plating film layer. The through holes 11a are formed so that the aspect ratio of the via conductors 13 (height from the upper surface of the lower conductor layer 12 to which the via conductors 13 are connected to the lower surface of the upper conductor layer 12 / diameter of the via conductors 13 on the upper surface of the lower conductor layer 12) is, for example, approximately 0.5 or more and approximately 1.0 or less. The via diameter of the via conductors 13 (diameter of the via conductors 13 on the upper surface of the lower conductor layer 12 to which the via conductors 13 are connected) is approximately 10 μm. Although the term "diameter" is used, the planar shape of the via conductors 13 is not necessarily limited to a circle. The "diameter" means the distance between the longest two points on the outer periphery of the via conductor 13 in a horizontal cross section.

[0020] The conductor layer 12 constituting the first buildup section 10 may have fine wiring FW, which is high-density wiring with a relatively small wiring width and inter-wiring distance (wiring spacing). The fine wiring FW may have the smallest wiring width and inter-wiring distance among the wiring constituting the wiring board 1. The fine wiring FW included in the first buildup section 10 may have a wiring width smaller than the wiring width of wiring that may be included in the conductor layer 22 of the second buildup section 20 (described below) and the wiring that may be included in the conductor layer 32 of the third buildup section 30. The fine wiring FW included in the first buildup section 10 may have a wiring spacing smaller than the wiring spacing (inter-wiring distance) of wiring that may be included in the conductor layer 22 of the second buildup section 20 (described below) and the wiring that may be included in the conductor layer 32 of the third buildup section 30.

[0021] Specifically, for example, the minimum wiring width of the fine wiring FW is 2 μm or less, and the minimum wiring spacing is 2 μm or less. Having the fine wiring FW in the first buildup section 10 may provide wiring with more appropriate characteristics corresponding to the electrical signals that can be carried by the wiring in the first buildup section 10. From a similar perspective, the aspect ratio of the fine wiring FW that can be included in the conductor layer 12 is, for example, 2.0 or more and 4.0 or less. As will be described in detail later with reference to FIGS. 3A to 3P, a wiring board 1 including such relatively fine wiring FW is formed more accurately.

[0022] When the conductor layer 12 is formed to include the fine wiring FW as described above, it may be preferable that the via conductors 13 connecting the opposing conductor layers 12 with the insulating layer 11 interposed therebetween are also formed at a fine pitch. Small diameter through holes 11a for the via conductors 13 may be formed in the insulating layer 11. Therefore, although the insulating layer 11 may contain an inorganic filler such as fine particles made of silica (SiO2), alumina, or mullite, it may be preferable that the insulating layer 11 does not contain an inorganic filler so that small diameter through holes 11a can be easily formed.

[0023] In the first buildup section 10 including the conductor layer 12 including the fine wiring FW, the thickness of the insulating layer 11 is, for example, about 7.5 μm to 10 μm. In this case, the insulating layer 11 preferably does not include a core material (reinforcing material) made of glass fiber, aramid fiber, or the like. The thickness of the conductor layer 12 is, for example, 7 μm or less.

[0024] Similar to the first buildup section 10, the second buildup section 20 has insulating layers (second insulating layers) 21 and conductor layers (second conductor layers) 22 that are alternately stacked. The insulating layers 21 have via conductors 23 formed therein that penetrate each insulating layer 21 and connect the conductor layers that face each other with each insulating layer 21 interposed therebetween. Each conductor layer 22 is patterned to have a predetermined conductor pattern. Similar to the first buildup section 10, the third buildup section 30 has insulating layers (third insulating layers) 31 and conductor layers (third conductor layers) 32 that are alternately stacked. The insulating layers 31 have via conductors 33 formed therein that penetrate each insulating layer 31 and connect the conductor layers that face each other with each insulating layer 31 interposed therebetween. Each conductor layer 32 is patterned to have a predetermined conductor pattern.

[0025] The insulating layer 21 constituting the second buildup section 20 and the insulating layer 31 constituting the third buildup section 30 may be formed using an insulating resin similar to that of the insulating layer 11. The insulating layers 21 and 31 may contain a core material (reinforcing material) made of glass fiber or aramid fiber. In the illustrated example, the insulating layer 31 of the third buildup section 30 contains a core material made of glass fiber. The insulating layers 21 and 31 may further contain an inorganic filler (not shown) made of fine particles such as silica (SiO2), alumina, or mullite. The conductor layer 22 of the second buildup section 20, the conductor layer 32 of the third buildup section 30, and each of the via conductors 23 and 33, like the conductor layer 12 and the via conductor 13, may be formed using any metal such as copper or nickel.

[0026] As described above, the wiring width and spacing of the wiring included in the conductor layer 22 of the second buildup section 20 and the conductor layer 32 of the third buildup section 30 may be larger than the wiring width and spacing of the wiring included in the conductor layer 12 of the first buildup section 10. For example, the minimum wiring width of the wiring included in the conductor layer 22 is approximately 4 μm, and the minimum wiring spacing is approximately 6 μm. Furthermore, the thickness of the insulating layers 21 and 31 is formed to be thicker than the thickness of the insulating layer 11, and the thickness of the insulating layer 21 may be, for example, approximately 20 μm to 30 μm. The thickness of the insulating layer 31 may be, for example, not less than 100 μm and not more than 200 μm.

[0027] The thickness of the conductor layers 22 and 32 is greater than that of the conductor layer 12, and may be, for example, 10 μm or greater. The thickness of the conductor layer 32 may be, for example, about 20 μm. The via diameter of the via conductor 23 formed in the insulating layer 21 (the diameter of the via conductor 23 on the upper surface of the lower conductor layer 22 to which the via conductor 23 is connected) is, for example, about 50 μm. The via diameter of the via conductor 33 formed in the insulating layer 31 (the diameter of the via conductor 33 on the upper surface of the conductor layer 32) is, for example, about 100 μm.

[0028] Like the conductor layer 12 and the via conductor 13, the conductor layers 22, 32 and the via conductors 23, 33 may have a multi-layer structure, for example, a two-layer structure including a metal film layer and a plating film layer. The second buildup section 20 and the third buildup section 30 do not include a fine wiring pattern such as the fine wiring FW of the first buildup section 10. In such a case, the metal film layer of the two-layer structure forming the conductor layer 22 and the via conductor 23 and the conductor layer 32 and the via conductor 33 may be an electroless plated film layer (e.g., an electroless copper plated film layer) formed by an electroless plated film, and the plating film layer may be an electrolytic plated film layer (e.g., an electrolytic copper plated film layer) formed by an electrolytic plated film.

[0029] 1, the wiring board 1 further includes a solder resist layer SR formed on a second surface 1B that is composed of the surfaces of the insulating layer 31 and the conductor layer 32. The solder resist layer SR is formed using, for example, a photosensitive polyimide resin or an epoxy resin. An opening SRa is formed in the solder resist layer SR, and the conductor pads 32p of the conductor layer 32 in the third buildup section 30 are exposed through the opening SRa.

[0030] The second surface 1B of the wiring board 1, which is the surface opposite to the component mounting surface of the wiring board 1, can be a connection surface that is connected to an external element when the wiring board 1 itself is mounted on an external element such as an external wiring board (e.g., the motherboard of an electrical device). The conductor pad 32p can be connected to an external board, electrical component, or mechanical component. In plan view, the wiring board 1 has a rectangular shape with each side measuring 80 mm or more and 240 mm or less. Here, "plan view" means viewing an object with a line of sight parallel to the thickness direction of the wiring board 1.

[0031] 2 shows a wiring board 1a as another example of a wiring board manufactured by the wiring board manufacturing method of the embodiment. The wiring board 1a includes a first buildup portion 10 having a first surface 10F and a second surface 10B, and a solder resist layer SR covering the second surface 10B. A conductor layer 12 is exposed through an opening SRa formed in the solder resist layer SR. That is, the first surface 1F of the wiring board 1a is formed by the first surface 10F of the first buildup portion 10, and the second surface 1B of the wiring board 1a is formed by the second surface 10B of the first buildup portion 10. If a wiring board manufactured by the wiring board manufacturing method of the embodiment does not include a buildup portion other than the first buildup portion 10, it may have the configuration of the wiring board 1a shown in the figure.

[0032] Next, with reference to FIGS. 3A to 3P, a method for manufacturing a wiring board according to an embodiment will be described, taking the case of manufacturing the wiring board 1 shown in FIG. 1 as an example. Unless otherwise specified, each component formed in the manufacturing method described below may be formed using the material exemplified as the material of the corresponding component in the description of the wiring board 1 in FIG. 1. In the following description of the method for manufacturing the wiring board 1, the side closer to the core material GS1 constituting the first support substrate SP1 on whose surface the first buildup section 10 is formed will be referred to as the "bottom" or "lower side," and the side farther from the core material GS1 will be referred to as the "top" or "upper side." Therefore, the surface of each component constituting the wiring board 1 that faces the first support substrate SP1 will be referred to as the "lower surface," and the surface facing away from the first support substrate SP1 will also be referred to as the "upper surface."

[0033] First, as shown in FIG. 3A, a first support substrate SP1 is prepared. The first support substrate SP1 has two surfaces perpendicular to its thickness direction: a first surface SP1a and a second surface SP1b opposite the first surface SP1a. The first support substrate SP1 includes a core material GS1 having one surface GS1A and another surface GS1B opposite the first surface GS1A. In addition to the core material GS1, the first support substrate SP1 also includes a first metal film layer ML1 laminated on the surface of the one surface GS1A of the core material GS1, and a second metal film layer ML2 laminated on the metal film layer ML1 via an adhesive layer AL1. The core material GS1 is a glass substrate made of a glass material, and therefore is also referred to as a glass substrate GS1. The first and second metal film layers ML1 and ML2 are metal film layers formed by, for example, electroless plating or sputtering. In the illustrated example, the second surface SP1b of the first support substrate SP1 is formed by the other surface GS1B of the core material GS1.

[0034] 3A and 3B to 3P illustrate an example in which one wiring substrate is formed on the first surface SP1a of the first support substrate SP1, and a method for manufacturing a wiring substrate will be described below. However, multiple wiring substrates may be formed on the first support substrate SP1. Specifically, the first surface SP1a of the first support substrate SP1 has one or more continuous product areas, and a laminate (build-up portion) including one wiring substrate is formed in each product area. The formed laminate is divided into each product area to manufacture the wiring substrates.

[0035] The glass substrate GS1 constituting the first support substrate SP1 is made of a glass material whose thermal expansion coefficient satisfies a predetermined relationship with that of the insulating layer 11 (see FIGS. 3C to 3J) laminated on the first support substrate SP1. Preferably, the material used for the glass substrate GS1 is a material whose difference in thermal expansion coefficient between the material constituting the glass substrate GS1 and the material constituting the insulating layer 11 is 13 ppm / °C or less. The glass material used for the glass substrate GS1 may have a thermal expansion coefficient of, for example, 8 ppm / °C or more. Specifically, the glass material used for the glass substrate GS1 may be, for example, borosilicate glass or soda-lime glass. The first and second metal film layers ML1 and ML2 are each depicted as a single layer in the illustration, but may include multiple layers. For example, the first and second metal film layers ML1 and ML2 may each have a two-layer structure composed of a titanium layer and a copper layer. The adhesive layer AL1 may contain, for example, an azobenzene-based polymer adhesive that can be attached and detached by light irradiation.

[0036] The formation of the first buildup section 10, which will be described later with reference to FIGS. 3B to 3J, is performed only on the upper side of one surface GS1A of the glass substrate GS1. During the formation of the first buildup section 10, stress is generated in the first support substrate SP1, causing the first support substrate SP1 to warp convexly toward the second surface SP1b due to the difference in thermal expansion coefficient between the first support substrate SP1 and the first buildup section 10. If the first support substrate SP1 warps, the first support substrate SP1 will also warp during the formation process, making it difficult to form fine wiring with accurate widths and wiring spacing in the first conductor layer 12. Therefore, it is desirable for the first support substrate SP1 to warp only slightly during the process of forming the first buildup section 10. From the perspective of suppressing warpage, it is preferable for the glass substrate GS1 constituting the first support substrate SP1 to have a certain thickness or greater.

[0037] On the other hand, exposure of the resist layer RL1, which will be described later with reference to FIG. 3E, is preferably performed with the first support substrate SP1 mounted on the suction table TA of the exposure apparatus. The first support substrate SP1 is suctioned and fixed to the suction table TA. It is believed that warpage of the first support substrate SP1 is corrected by suctioning the first support substrate SP1 to the suction table TA. Here, "correcting" warpage can include not only eliminating warpage but also reducing warpage. From the perspective of warpage correction, a glass substrate GS1 having a thickness of a certain level or less that allows it to be deformed by suction is preferred.

[0038] Therefore, from the viewpoints of suppressing the occurrence of warpage and facilitating correction of warpage, the method for manufacturing a wiring board according to the embodiment uses a glass plate having a thickness of 0.5 mm or more and 2.0 mm or less as the glass substrate GS1. By using a glass substrate GS1 having a thickness in this range, it is possible to suppress the occurrence of warpage during the formation of the first buildup section 10. Moreover, it is possible to form the first conductor layer 12 while appropriately correcting the warpage. Therefore, as will be described later, it is believed that it is possible to manufacture a wiring board 1 including fine wiring with accurate widths and wiring spacing.

[0039] Next, as shown in FIG. 3B, a conductor layer 12 having a plurality of conductor pads 12p is formed on the first surface SP1a of the first support substrate SP1. In forming the conductor layer 12 in contact with the first support substrate SP1, for example, a plating resist is formed on the metal film layer ML2, and openings corresponding to the formation areas of the pattern of the conductor pads 12p are formed in the plating resist by, for example, photolithography. Next, a plating film layer 122 is formed in the openings by electrolytic plating using the metal film layer ML2 as a seed layer. After the plating film layer 122 is formed, the plating resist is removed, resulting in the state shown in FIG. 3B.

[0040] Next, as shown in FIG. 3C , an insulating layer 11 is laminated to cover the upper and side surfaces of the conductor layer 12 and the first surface SP1a of the first support substrate SP1 exposed from the conductor pattern of the conductor layer 12. The insulating layer 11 is formed by thermocompression bonding a resin film. A material having a thermal expansion coefficient that differs from that of the glass substrate GS1 by 13 ppm / °C or less is used to form the insulating layer 11. Therefore, warping that may occur due to the difference in thermal expansion coefficient between the glass substrate GS1 and the insulating layer 11 during the process of forming the insulating layer 11 on the glass substrate GS1 and the process of forming the conductor layer 12 on the insulating layer 11, which will be described later with reference to FIGS. 3D to 3H, can be further suppressed. As described above, the thermal expansion coefficient of the glass substrate GS1 is, for example, 8 ppm / °C or more. Therefore, a resin material having a thermal expansion coefficient of 25 ppm / °C or less can be preferably used as the resin material constituting the first insulating layer 11.

[0041] For example, an insulating resin such as an epoxy resin or a phenol resin can be used for the insulating layer 11. Fluorine resin, liquid crystal polymer (LCP), fluoroethylene resin (PTFE), polyester resin (PE), or modified polyimide resin (MPI) may also be used. The insulating layer 11 is formed to have a thickness of about 7.5 μm to 10 μm.

[0042] Next, through holes 11a are formed in the insulating layer 11 at positions where the via conductors 13 (see FIG. 3G) will be formed by irradiating the insulating layer 11 with, for example, carbon dioxide laser light or excimer laser light. As described above, in the wiring board manufacturing method of the embodiment, the degree of warping that may occur due to the difference in thermal expansion coefficient between the glass substrate GS1 and the insulating layer 11 is relatively small, and the surface of the insulating layer 11 has relatively good flatness. Therefore, it is considered that the through holes 11a can be formed relatively accurately at positions corresponding to the locations where the via conductors 13 are to be formed. The through holes 11a can be formed so that the ratio of the depth of the through holes 11a to the diameter of the through holes 11a is approximately 0.5 or more and approximately 1.0 or less. Here, the "depth of the through holes 11a" refers to the shortest distance between the top surface of the conductor layer 12 and the top surface of the insulating layer 11, and the "diameter of the through holes 11a" refers to the distance between the longest two points on the periphery of the through holes 11a in a planar view on the top surface of the insulating layer 11. The through holes 11a can be formed to have a diameter of approximately 10 μm.

[0043] Although not shown, the formation of the through holes 11a by irradiation with a laser such as a carbon dioxide laser beam may be performed by irradiating the laser while the upper surface of the insulating layer 11 is protected by covering it with a protective film such as a polyethylene terephthalate (PET) film. After the formation of the through holes 11a, a desmearing process may be performed to prevent a decrease in adhesion and an increase in resistance components during the formation of the conductor layer 12 due to processing-induced deformation products generated at the bottom of the through holes 11. The desmearing process may preferably be a dry desmearing process using plasma gas. The desmearing process may also be performed while protecting the surface of the insulating layer 11 with a protective film such as a polyethylene terephthalate (PET) film formed on the surface of the insulating layer 11.

[0044] 3D, a metal film layer 121 is formed on the inner wall of the through hole 11a and on the surface of the insulating layer 11 by electroless plating, sputtering, or the like. Preferably, the metal film layer 121 may be a sputtering film formed by sputtering. Note that, if a protective film is provided on the surface of the insulating layer 11 during the formation of the through hole 11a and / or the desmear treatment, the protective film may be peeled off and removed before the formation of the metal film layer 121.

[0045] Next, as shown in FIG. 3E, a dry film resist containing, for example, a photosensitive epoxy resin is adhered to the metal film layer 121, forming a resist layer RL1 in contact with the upper surface of the metal film layer 121. The resist layer RL1 is then exposed to light. In the wiring substrate manufacturing method of the embodiment, direct imaging exposure, which provides relatively high resolution, is performed in the process of exposing the resist layer RL1. In direct imaging exposure, the first support substrate SP1 is placed on, for example, an adsorption table TA of an exposure device. A plurality of through holes TH are formed in the surface of the flat adsorption table TA on which the first support substrate SP1 is placed. The first support substrate SP1 is sucked through the through holes SH by driving the pump P. As described above, the glass substrate GS1 constituting the first support substrate SP1 may have a thickness of 0.5 mm or more and 2.0 mm or less. Therefore, warping of the first support substrate SP1 is suppressed, and even if warping occurs, the warping can be corrected during exposure for forming the first conductor layer 12. In this state, the resist layer RL1 on the metal film layer 121 is directly irradiated with irradiation light L. As a light source for the irradiation light L, for example, a semiconductor laser with a wavelength of 350 nm to 410 nm or an ultra-high pressure mercury lamp can be used. The irradiation light L is scanned in accordance with a drawing pattern corresponding to the conductor pattern of the first conductor layer 12 to be formed on the insulating layer 11 (see FIG. 3H). The exposure amount can be determined by the illuminance of the exposure light source and the scanning speed of the irradiation light L.

[0046] In the wiring board manufacturing method of the embodiment, each product area on the first surface SP1a of the first support substrate SP1 has a rectangular shape with each side measuring 80 mm or more and 240 mm or less in plan view. Therefore, the stack (build-up portion) formed across one or more product areas on the first surface SP1a of the first support substrate SP1 has a rectangular shape with each side measuring at least 80 mm or more in plan view. When a relatively large stack is manufactured in this way, exposure using a photomask that limits the area that can be exposed in a single exposure in forming the resist layer RL1 requires repeated exposure of different areas, which may increase the number of steps in the exposure process. In contrast, direct imaging exposure simplifies the exposure process because the entire area of ​​the wiring board is scanned with irradiation light in a single exposure, which may improve the yield of wiring board manufacturing.

[0047] 3F, a resist pattern corresponding to the conductor pattern of the conductor layer 12 (see FIG. 3H) to be formed on the insulating layer 11 is formed on the resist layer RL1. Specifically, after the above-mentioned step of exposing the resist layer RL1 is completed, the resist layer RL1 is developed with a developer made of an aqueous sodium carbonate solution, which may contain, for example, a surfactant, an antifoaming agent, a small amount of an organic solvent to promote development, and the like, to form openings RL1o. When wiring FW (see FIG. 3H) is included as the conductor pattern of the conductor layer 12 to be formed on the insulating layer 11, the openings RL1o corresponding to the wiring FW can be formed so that the minimum width of the opening is 2 μm or less and the minimum spacing between the openings is 2 μm or less.

[0048] As described above, in the wiring board manufacturing method of the embodiment, the glass substrate GS1 constituting the first support substrate SP1 can have a thickness of 0.5 mm or more and 2.0 mm or less. Potential warpage of the first support substrate SP1 is suppressed and corrected. Furthermore, the difference between the thermal expansion coefficient of the glass substrate GS1 and the thermal expansion coefficient of the insulating layer 11 is relatively small, at 13 ppm / °C or less. Therefore, the degree of warpage that may occur in the first support substrate SP1 and the insulating layer 11 during the wiring board manufacturing process is relatively small. Therefore, the resist layer RL1 is considered to have good flatness at the time of exposure of the resist layer RL1, as described with reference to FIG. 3E. The irradiated light L is considered to scan the resist layer RL1 on the insulating layer 11 according to a drawing pattern that more accurately corresponds to the conductor pattern of the first conductor layer 12 (see FIG. 3H) to be formed. Therefore, the opening RL1o formed in the resist layer RL1 by development more accurately corresponds to the conductor pattern of the first conductor layer 12 (see FIG. 3H) to be formed.

[0049] 3G, a plating film layer 122 is formed in the opening RL1o of the resist layer RL1 by electrolytic plating using the metal film layer 121 as a power supply layer. The inside of the through hole 11a is completely filled with the electrolytic plating film 122, and the via conductor 13 is formed.

[0050] Next, the resist layer RL1 is removed using an alkaline stripping solution, and then the portions of the metal film layer 121 not covered by the plating film layer 122 are removed by etching. As a result, as shown in FIG. 3H, a conductor layer 12 having a two-layer structure consisting of the metal film layer 121 and the plating film layer 122 and having fine wiring FW is formed. The conductor layer 12 may be formed to a thickness of, for example, 7 μm or less. The fine wiring FW may be formed so that the minimum wiring width is 2 μm or less, the minimum wiring spacing is 2 μm or less, and the aspect ratio is, for example, 2.0 or more and 4.0 or less. As described above with reference to FIG. 3F, by forming openings RL1o in the resist layer RL1 that relatively accurately correspond to the conductor pattern to be formed, it is believed that the conductor layer 12 having such fine wiring FW can be formed more accurately.

[0051] Next, as shown in FIG. 3I, a desired number of insulating layers 11 and conductor layers 12, as well as via conductors 13 penetrating each insulating layer 11, are formed on the insulating layers 11 using a method similar to the method for forming the insulating layers 11, conductor layers 12, and via conductors 13 described above. In the wiring board manufacturing method of the embodiment, at least three insulating layers 11 and at least three conductor layers 12 are formed on the first support substrate SP1. As the number of insulating layers 11 and conductor layers 12 stacked on the first support substrate SP1 increases, the degree of warping due to the difference in thermal expansion coefficients between the insulating layers 11 and the glass substrate GS1 may increase. However, in the wiring board manufacturing method of the embodiment, the thickness of the glass substrate GS1 is 0.5 mm or more and 2.0 mm or less. Therefore, when the first support substrate SP1 is sucked toward the suction table TA of the exposure apparatus (see FIG. 3E), the warping of the first support substrate SP1 can be corrected. Furthermore, the difference in thermal expansion coefficient between each insulating layer 11 and the glass substrate GS1 is relatively small, at 13 ppm / °C or less, and the warpage that occurs can be suppressed to a relatively small extent even if the number of stacked insulating layers 11 increases. Therefore, when a plurality of insulating layers 11 and a plurality of conductor layers 12 are formed on the support substrate SP1, the above-mentioned accurate formation of the through holes 11a and accurate formation of the conductor layers 12 can be realized.

[0052] Next, as shown in FIG. 3J, the uppermost insulating layer 11 and conductor layer 12 of the insulating layer 11 and conductor layer 12 of the first buildup section 10 are formed on top of the conductor layer 12. The formation of the first buildup section 10 on the first surface SP1a of the first support substrate SP1 is completed. As shown in the figure, the uppermost conductor layer 12, which does not include the fine wiring FW, may be formed by a method similar to the formation of the insulating layer 11 and the conductor layer 12 on the insulating layer 11 described above (a method including direct imaging exposure of a resist layer). Alternatively, it may be formed by a method including forming a resist pattern by exposure of a resist layer using a photomask. After the first buildup section 10 is formed, the flatness of the surface of the first buildup section 10 facing the first support substrate SP1 (i.e., the surface in contact with the first surface SP1a of the first support substrate SP1) is, for example, ±2.5 μm or less.

[0053] In the method for manufacturing a wiring board according to the embodiment, in forming the plurality of conductor layers 12 constituting the first buildup section 10, any of the conductor layers 12 formed on the insulating layer 11 may be formed by a method including direct imaging exposure to a resist layer. Therefore, for example, in the illustrated example, the lowermost conductor layer 12 in the first buildup section 10 that does not include the fine wiring FW (the conductor layer 12 in contact with the first support substrate SP1) may also be formed by a method including formation of a resist pattern by exposure using a photomask to a resist layer, or may also be formed by a method including direct imaging exposure.

[0054] Next, as shown in FIG. 3K, the lowermost insulating layer 21 of the second buildup section 20 (see FIG. 3N) is laminated on the uppermost insulating layer 11 and conductor layer 12 of the first buildup section 10. The thickness of the insulating layer 21 may be different from the thickness of the insulating layer 11 that constitutes the first buildup section 10. The insulating layer 21 may be formed to have a thickness of, for example, approximately 20 μm to 30 μm. The insulating layer 21 may be made of an insulating resin similar to the insulating resin that constitutes the insulating layer 11. A film 21F made of a resin such as polyethylene terephthalate is laminated on the insulating layer 21 and is peelably adhered to the insulating layer 21.

[0055] Next, as shown in FIG. 3L, the first buildup section 10 with the insulating layer 21 and film 21F attached is attached to both of the two main surfaces (surfaces perpendicular to the thickness direction) of the second support substrate SP2 via the first support substrate SP1. The main surfaces of the second support substrate SP2 and the second surface SP1b of the first support substrate SP1 are joined via an adhesive layer AL2 made of any adhesive. The second support substrate SP2 may be, for example, a glass substrate similar to the core material GS1 of the first support substrate SP1. Alternatively, the second support substrate SP2 may be made of a copper clad laminate (CCL) including an insulating layer and copper foils thermocompression-bonded to both surfaces of the insulating layer.

[0056] Next, as shown in FIG. 3M, film 21F is peeled off from insulating layer 21. Subsequently, through holes 21a are formed in insulating layer 21 by, for example, laser light irradiation, and via conductors 23 having a two-layer structure of a metal film layer 221 and a plating film layer 222 and a conductor layer 22 on insulating layer 21 are formed by a so-called semi-additive method. That is, metal film layer 221 is formed in through holes 21a and on the surface of insulating layer 21 by, for example, electroless plating, and a plating resist (not shown) having openings corresponding to the conductor pattern to be formed in conductor layer 22 is provided on metal film layer 221. Then, plating film layer 222 is formed in the openings of the plating resist by electrolytic plating using metal film layer 221 as a power supply layer, and via conductors 23 are formed in through holes 21a. Thereafter, plating resist is removed, and further, exposed portions of metal film layer 221 that are not covered by plating film layer 222 are removed by etching. Conductor layer 22 can be formed to have a thickness of, for example, 10 μm or more. The conductor layer 22 can be formed to have wiring with a minimum wiring width of about 4 μm and a minimum wiring spacing of about 6 μm, for example. In forming the conductor layer 22, the above-mentioned direct imaging exposure may be used to form openings in the plating resist, or exposure using a photomask may also be used.

[0057] 3M and the following reference figures 3N to 3P show the stack formed on one surface of the second support substrate SP2, and do not show stacks that may be formed on the opposite surface. However, the stacks are simultaneously formed on the opposite surface of the second support substrate SP2 in the manner and number shown.

[0058] 3N, the above-described steps of forming insulating layers 21, conductor layers 22, and via conductors 23 are then repeated to form a desired number of insulating layers 21 and conductor layers 22, as well as via conductors 23 that penetrate each insulating layer 21. This completes the formation of second buildup section 20 on first buildup section 10. Note that in FIG. 3N and the subsequent FIGS. 3O and 3P, metal film layers and plating film layers are not depicted, and conductor layers 12 and 22 are depicted as single layers, as in FIG. 1.

[0059] 1 is manufactured, the second buildup section 20 is formed on the first support substrate SP1 via the first buildup section 10, following lamination of the first buildup section 10 on the first support substrate SP1. The second buildup section 20 is formed directly on the first buildup section 10, which has a relatively small degree of warpage that may occur, and it is believed that the second buildup section 20 can also be formed to have good flatness.

[0060] Next, as shown in FIG. 3O, the insulating layer 31, the conductor layer 32, and the via conductor 33 penetrating the insulating layer 31 of the third buildup section 30 are formed on the uppermost insulating layer 21 and conductor layer 22 of the second buildup section 20 using a method similar to the method for forming the insulating layer 21, the conductor layer 22, and the via conductor 23. The insulating resin forming the insulating layer 31 can be a prepreg containing an insulating resin such as epoxy resin or BT resin impregnated into a reinforcing material (core material) made of glass fiber. As shown in the figure, the third buildup section 30 is formed, including two insulating layers 31 and two conductor layers 32. Next, a solder resist layer SR is formed by forming a photosensitive epoxy resin or polyimide resin layer on the surfaces of the insulating layer 31 and the conductor layer 32. Then, openings SRa exposing the conductor pads 32p are formed using photolithography.

[0061] Next, as shown in FIG. 3P, the first support substrate SP1 and the second support substrate SP2 are removed from the laminate including the first buildup section 10. To remove the first support substrate SP1 from the first buildup section 10, the adhesive layer AL1 is softened by, for example, irradiating it with laser light, and then the second metal film layer ML2 of the first support substrate SP1 is peeled off from the adhesive layer AL1. The lower surface of the second metal film layer ML2 below the conductor pad 12p is exposed. Although not shown in FIG. 3P, the removal of the first support substrate SP1 is similarly performed on the surface of the second support substrate SP2 opposite to the surface shown in the figure. Next, the second metal film layer ML2 is removed by etching. The lower surfaces of the conductor pads 12p and the insulating layer 11 are exposed. The laminate, which may include multiple wiring substrates, is divided into product areas and formed into individual, independent wiring substrates. The wiring substrate 1 shown in FIG. 1 is completed.

[0062] The method for manufacturing a wiring board according to the embodiment is not limited to the method described with reference to FIGS. 3A to 3P, and the conditions and order of steps may be arbitrarily changed. Furthermore, certain steps may be omitted, or other steps may be added. The method for manufacturing a wiring board according to the embodiment includes at least preparing a glass substrate having a thickness of 0.5 mm or more and 2.0 mm or less, and alternately stacking three or more conductor layers and three or more insulating layers on only one side of the glass substrate. Each product area has a rectangular shape with each side measuring 80 mm or more and 240 mm or less in a plan view. The stacking of the conductor layers may include forming a resist pattern by direct imaging exposure. For example, a solder resist layer having openings exposing the conductor pads 12p may be formed on the conductor pads 12p and the insulating layer 11 exposed after the second metal film layer ML2 is removed by etching. Furthermore, conductor bumps connecting to the conductor pads 12p may be formed in the openings of the solder resist layer. A plating layer including a nickel layer and a tin layer may be formed on the surface of the conductor bump. The second and third buildup sections may not be formed, or a fourth buildup section may be formed in addition to the second and third buildup sections. [Explanation of symbols]

[0063] 1, 1a Wiring board 10 First build-up section 20 Second build-up section 30 Third Build-up Section 11 Insulating layer (first insulating layer) 12 Conductor layer (first conductor layer) 21 Insulating layer (second insulating layer) 22 Conductor layer (second conductor layer) 31 Insulating layer (third insulating layer) 32 Conductor layer (third conductor layer) 121, 221 metal film layer 122, 222 plating film layer 12p, 32p contact pads FW wiring (fine wiring) GS1 Core material (glass substrate) GS1A One side GS1B The other side RL1 resist layer SP1 1st support board SP2 2nd support board SR solder resist layer SRa aperture TA suction table TH through hole

Claims

1. providing a glass substrate having one side with one or more product areas and another side opposite the one side; forming a build-up portion by stacking a conductor layer and an insulating layer on only the one surface across the one or more product areas; A method for manufacturing a wiring substrate, comprising: The thickness of the glass substrate is 0.5 mm or more and 2.0 mm or less, stacking the conductor layers and the insulating layers includes alternately stacking three or more conductor layers and three or more insulating layers; The shape of each of the product areas is a rectangle with each side measuring 80 mm or more and 240 mm or less in plan view, laminating the conductor layer includes forming a resist layer having a resist pattern and forming a conductor pattern according to the resist pattern; laminating the conductor layers includes forming the conductor pattern so that the minimum width of the wiring included in the conductor pattern is 2 μm or less and the minimum spacing between the wiring is 2 μm or less; Forming the resist layer having the resist pattern includes exposing the resist layer by direct imaging exposure.

2. 2. The method for manufacturing a wiring board according to claim 1, wherein exposing the resist layer includes correcting warpage of the glass substrate.

3. 2. The method for manufacturing a wiring board according to claim 1, wherein the difference between the thermal expansion coefficient of the glass substrate and the thermal expansion coefficient of each of the insulating layers is 13 ppm / ° C. or less.

4. 2. The method for manufacturing a wiring board according to claim 1, wherein the coefficient of thermal expansion of the glass substrate is 8 ppm / ° C. or more.

5. 2. The method for manufacturing a wiring board according to claim 1, wherein the glass substrate includes borosilicate glass or soda lime glass.

6. 2. The method for manufacturing a wiring board according to claim 1, further comprising forming a build-up portion including an insulating layer having a thickness different from that of the insulating layer on the side of the build-up portion opposite the glass substrate.

Images