Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing ringing.SOLUTION: The semiconductor device includes a semiconductor layer having a first plane and a second plane and including a first trench provided on a side of the first plane, a first field plate electrode in the first trench, a gate electrode in a gate trench, a first electrode provided on a side of the first plane with respect to the semiconductor layer and electrically connected to the first field plate electrode, a second electrode provided on a side of the second plane with respect to the semiconductor layer, and a connection portion provided between the first electrode and the first field plate electrode, electrically connected to the first electrode and the first field plate electrode, and having an electric resistance higher than an electric resistance of the first field plate electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Vertical transistors, in which the gate electrode is buried in a trench in the semiconductor layer, are used to reduce the size or improve performance of transistors. In vertical transistors, there is a trade-off between the drain-source breakdown voltage (hereinafter simply referred to as "breakdown voltage") and on-resistance. In other words, increasing the impurity concentration in the drift region to reduce on-resistance reduces the breakdown voltage. Conversely, decreasing the impurity concentration in the drift region to improve breakdown voltage increases the on-resistance.

[0003] One way to improve the trade-off between breakdown voltage and on-resistance is to install a field plate electrode inside the trench of a vertical transistor. By changing the electric field distribution in the drift region with the field plate electrode, it is possible to increase the impurity concentration in the drift region while maintaining the breakdown voltage. Therefore, it is possible to reduce the on-resistance while maintaining the breakdown voltage.

[0004] When the field plate electrode is electrically connected to the source electrode of the vertical transistor, a snubber circuit is formed between the source electrode and the drain electrode, in which the electrical resistance between the source electrode and the field plate electrode and the capacitance between the field plate electrode and the semiconductor layer are connected in series. By providing the snubber circuit, ringing during the off-state of the vertical transistor can be suppressed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2023-43340 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a semiconductor device capable of suppressing ringing. [Means for solving the problem]

[0007] A semiconductor device according to an embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a first trench provided on the side of the first surface, a gate trench provided on the side of the first surface and surrounding the first trench, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a first field plate electrode provided in the first trench; a gate insulating layer, a gate electrode provided in the gate trench, a gate insulating layer provided between the gate electrode and the semiconductor layer, a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region and the first field plate electrode, a second electrode provided on the second surface side of the semiconductor layer and electrically connected to the first semiconductor region, and a connection part provided between the first electrode and the first field plate electrode, electrically connected to the first electrode and the first field plate electrode, and having an electrical resistance higher than that of the first field plate electrode. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 1 is a schematic plan view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a comparative example. [Figure 4] FIG. 10 is a schematic plan view of a semiconductor device according to a comparative example. [Figure 5] 5A to 5C are explanatory diagrams illustrating the operation and effect of the semiconductor device according to the first embodiment. [Figure 6] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Figure 7] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a modified example of the second embodiment. [Figure 9] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 10] FIG. 11 is a schematic cross-sectional view of a semiconductor device according to a modified example of the third embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment. [Figure 14] FIG. 10 is a schematic top view of a semiconductor device according to a fifth embodiment. [Figure 15] FIG. 13 is a schematic top view of a semiconductor device according to a first modified example of the fifth embodiment. [Figure 16] FIG. 13 is a schematic top view of a semiconductor device according to a second modified example of the fifth embodiment. [Figure 17] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a sixth embodiment. [Figure 18] FIG. 10 is a schematic plan view of a semiconductor device according to a sixth embodiment. [Figure 19] FIG. 13 is a schematic cross-sectional view of a semiconductor device according to a seventh embodiment. [Figure 20] FIG. 13 is a schematic plan view of a semiconductor device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0010] In the following description, n+ , n, n - and p + , p, p - When the notation is used, these notations indicate the relative high and low of the impurity concentration. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + shape, n - The shape is simply n-type, p-type + shape, p - The shape is sometimes simply referred to as p-shape.

[0011] Note that n-type impurities are so-called donors, and p-type impurities are so-called acceptors. In this specification, the term "impurities" means either a donor or an acceptor, or both.

[0012] The impurity concentration of a semiconductor device can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration of a semiconductor device can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). Distances such as the width and depth of an impurity region of a semiconductor device can be determined by, for example, SIMS. Distances such as the width and depth of an impurity region of a semiconductor device can also be determined from, for example, an SCM image.

[0013] The depth of a trench, the thickness of an insulating layer, etc. of a semiconductor device can be measured on an image obtained by, for example, a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0014] The electrical resistivity of a member of a semiconductor device can be determined, for example, by identifying the material of the member and determining the resistivity as a characteristic value of the material.

[0015] The electrical resistance of a semiconductor device component can be determined by direct measurement using a probe needle, or by calculation using the electrical resistivity of the identified material and the identified shape of the component, for example.

[0016] The material can be identified by, for example, Energy Dispersive X-ray Spectroscopy (EDX), and the shape can be identified by, for example, SEM images or TEM images.

[0017] (First embodiment) The semiconductor device of the first embodiment is a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including: a first trench provided on the first surface side; a gate trench provided on the first surface side and surrounding the first trench; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface; and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a first field plate electrode provided in the first trench; the gate insulating layer provided between the gate electrode and the semiconductor layer; a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region and the first field plate electrode; a second electrode provided on the second surface side of the semiconductor layer and electrically connected to the first semiconductor region; and a connection portion provided between the first electrode and the first field plate electrode, electrically connected to the first electrode and the first field plate electrode, and having an electrical resistance higher than that of the first field plate electrode.

[0018] The semiconductor device of the first embodiment is a vertical transistor in which a gate electrode and a field plate electrode are buried in a trench. The semiconductor device of the first embodiment is a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device of the first embodiment is a MOSFET 100.

[0019] In this specification, a trench is a groove-type or recessed structure that the semiconductor layer itself has, and a structure other than the semiconductor layer can be provided inside the trench. The trench is a part of the semiconductor layer.

[0020] The following description will be given taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type, taking as an example an n-channel MOSFET in which electrons are carriers.

[0021] Fig. 1 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Fig. 2 is a schematic plan view of the semiconductor device of the first embodiment. Fig. 2 is a plan view of the first plane (F1 in Fig. 1) of Fig. 1. Fig. 1 is a cross-section taken along line AA' of Fig. 2.

[0022] The MOSFET 100 includes a silicon layer 10 (semiconductor layer), a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, a first field plate electrode 20, a first field plate insulating layer 22, a connection portion 24, a contact portion 26, and an interlayer insulating layer 28 (first insulating layer).

[0023] The source electrode 12 includes a first contact plug portion 12a, a second contact plug portion 12b, and a surface layer portion 12c.

[0024] The silicon layer 10 includes a gate trench 30, a first field plate trench 31 (first trench), and a + n-type drain region 35 - a p-type drift region 36 (first semiconductor region), a p-type body region 37 (second semiconductor region), and+ a source region 38 (third semiconductor region) of p + The mold contact area 39 is included.

[0025] The silicon layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1). The second surface F2 faces the first surface F1.

[0026] The first direction and the second direction are parallel to the first plane F1. The second direction is a direction intersecting the first direction. The second direction is, for example, a direction perpendicular to the first direction. Furthermore, the third direction is a direction perpendicular to the first plane F1. The third direction is a direction perpendicular to the first direction and the second direction.

[0027] Hereinafter, the term "depth" refers to the depth based on the first plane F1, that is, the distance in the third direction based on the first plane F1.

[0028] The silicon layer 10 is made of single-crystal silicon (Si). The surface of the silicon layer 10 is inclined at an angle of 0 to 8 degrees with respect to the (100) plane, for example.

[0029] n + A n-type drain region 35 is provided in the silicon layer 10. The drain region 35 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The concentration of the n-type impurities in the drain region 35 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0030] n - A mold drift region 36 is provided in the silicon layer 10. The drift region 36 is provided between the drain region 35 and the first face F1. The drift region 36 is provided on the drain region 35.

[0031] The drift region 36 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the drift region 36 is, for example, 1×10 15 cm -3 More than 1×10 18 cm -3 The drift region 36 is, for example, + The epitaxially grown layer is formed on the drain region 35 of the semiconductor substrate by epitaxial growth.

[0032] The thickness of the drift region 36 in the third direction is, for example, not less than 7 μm and not more than 15 μm.

[0033] A p-type body region 37 is provided in the silicon layer 10. The body region 37 is provided between the drift region 36 and the first face F1.

[0034] The body region 37 is provided between two adjacent first field plate trenches 31. The body region 37 is provided between the gate trench 30 and the first field plate trench 31.

[0035] When the MOSFET 100 is in an on-state, a channel is formed in the body region 37 in contact with the gate insulating layer 18 .

[0036] The body region 37 contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration of the body region 37 is, for example, 1×10 16 cm -3 More than 1×10 18 cm -3 The following is the result.

[0037] n + A source region 38 of the type is provided in the silicon layer 10. The source region 38 is provided between the body region 37 and the first face F1.

[0038] The source region 38 is provided between two adjacent first field plate trenches 31. The source region 38 is provided between the gate trench 30 and the first field plate trench 31.

[0039] The source region 38 contains n-type impurities. The n-type impurities are, for example, phosphorus (P) or arsenic (As). The n-type impurity concentration of the source region 38 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0040] p + A mold contact region 39 is provided in the silicon layer 10. The contact region 39 is provided between the body region 37 and the first face F1.

[0041] The contact region 39 contains p-type impurities. The p-type impurities are, for example, boron (B). The p-type impurity concentration of the contact region 39 is higher than the p-type impurity concentration of the body region 37. The p-type impurity concentration of the contact region 39 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0042] The gate trench 30 is provided in the silicon layer 10. The gate trench 30 is provided on the first face F1 side of the silicon layer 10. The gate trench 30 is a groove formed in the silicon layer 10.

[0043] The gate trench 30 surrounds the first field plate trench 31. The gate trench 30 has a mesh shape on the first face F1.

[0044] The gate electrode 16 is disposed within the gate trench 30. A gate insulating layer 18 is disposed between the gate electrode 16 and the silicon layer 10.

[0045] The gate electrode 16 is a conductor, such as a metal, a metal nitride, a metal carbide, or a metal-semiconductor compound.

[0046] The gate electrode 16 includes, for example, polycrystalline silicon. The gate electrode 16 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The gate electrode 16 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0047] The first field plate trench 31 is provided in the silicon layer 10. The first field plate trench 31 is provided on the first face F1 side of the silicon layer 10. The first field plate trench 31 is a groove formed in the silicon layer 10.

[0048] 2, the first field plate trenches 31 are provided in a dot pattern on the first face F1. The first field plate trenches 31 are surrounded by the gate trenches 30. The first field plate trenches 31 are deeper than the gate trenches 30.

[0049] The first field plate electrode 20 is provided in the first field plate trench 31 .

[0050] The first field plate electrode 20 is electrically connected to the source electrode 12 .

[0051] The first field plate electrode 20 includes polycrystalline silicon. The first field plate electrode 20 is, for example, polycrystalline silicon containing impurities. The first field plate electrode 20 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The first field plate electrode 20 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0052] The impurity concentration of the first field plate electrode 20 is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3When the first field plate electrode 20 is made of n-type polycrystalline silicon, the n-type impurity concentration of the first field plate electrode 20 is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3 When the first field plate electrode 20 is made of p-type polycrystalline silicon, the p-type impurity concentration of the first field plate electrode 20 is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3 The following is the result.

[0053] The first field plate insulating layer 22 is provided between the first field plate electrode 20 and the silicon layer 10. The first field plate insulating layer 22 is provided between the first field plate electrode 20 and the drift region 36. The first field plate insulating layer 22 is, for example, silicon oxide.

[0054] The connection portion 24 is provided between the source electrode 12 and the first field plate electrode 20. The connection portion 24 electrically connects the source electrode 12 and the first field plate electrode 20. The connection portion 24 is provided in the first field plate trench 31.

[0055] The electrical resistance of the connection portion 24 is higher than the electrical resistance of the first field plate electrode 20. The electrical resistance of the connection portion 24 is, for example, 100 times or more and 10,000 times or less than the electrical resistance of the first field plate electrode 20.

[0056] The connection portion 24 includes polycrystalline silicon. The connection portion 24 is, for example, polycrystalline silicon containing impurities. The connection portion 24 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The connection portion 24 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0057] The impurity concentration of the polycrystalline silicon of the connection portion 24 is lower than the impurity concentration of the polycrystalline silicon of the first field plate electrode 20. The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, 1 / 100 or less of the impurity concentration of the polycrystalline silicon of the first field plate electrode 20.

[0058] The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, 1×10 11 cm -3 More than 1×10 17 cm -3 When the connection portion 24 is made of n-type polycrystalline silicon, the n-type impurity concentration of the connection portion 24 is, for example, 1×10 11 cm -3 More than 1×10 17 cm -3 When the connection portion 24 is made of p-type polycrystalline silicon, the p-type impurity concentration of the connection portion 24 is, for example, 1×10 11 cm -3 More than 1×10 17 cm -3 The following is the result.

[0059] The contact portion 26 is provided between the source electrode 12 and the connection portion 24. The contact portion 26 electrically connects the source electrode 12 and the connection portion 24.

[0060] The contact portion 26 is in contact with the source electrode 12. The contact portion 26 is in contact with the second contact plug portion 12b of the source electrode 12. The contact portion 26 is in contact with the connection portion 24. The contact portion 26 is provided in the first field plate trench 31.

[0061] The contact portion 26 includes polycrystalline silicon. The contact portion 26 is, for example, polycrystalline silicon containing impurities. The contact portion 26 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The contact portion 26 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0062] The impurity concentration of the polycrystalline silicon of the contact portion 26 is higher than the impurity concentration of the polycrystalline silicon of the connection portion 24. The impurity concentration of the polycrystalline silicon of the contact portion 26 is, for example, 100 times or more and 1,000,000 times or less than the impurity concentration of the polycrystalline silicon of the connection portion 24.

[0063] The impurity concentration of the polycrystalline silicon of the contact portion 26 is higher than the impurity concentration of the polycrystalline silicon of the first field plate electrode 20, for example.

[0064] The impurity concentration of the polycrystalline silicon in the contact portion 26 is, for example, 1×10 20 cm -3 More than 1×10 22 cm -3 When the contact portion 26 is made of n-type polycrystalline silicon, the n-type impurity concentration of the contact portion 26 is, for example, 1×10 20 cm -3 More than 1×10 22 cm -3 When the contact portion 26 is made of p-type polycrystalline silicon, the p-type impurity concentration of the connection portion 24 is, for example, 1×10 20 cm -3 More than 1×10 22 cm -3 The following is the result.

[0065] By providing the contact portion 26, for example, the contact resistance of the second contact plug portion 12b can be reduced.

[0066] The interlayer insulating layer 28 is provided between the source electrode 12 and the silicon layer 10. The interlayer insulating layer 28 is provided between the source electrode 12 and the first field plate electrode 20. The interlayer insulating layer 28 is provided between the source electrode 12 and the gate electrode 16.

[0067] The interlayer insulating layer 28 is an insulator, such as silicon oxide.

[0068] The source electrode 12 is provided on the first face F1 side of the silicon layer 10. The source electrode 12 is provided on the first face F1 of the silicon layer 10.

[0069] The source electrode 12 is electrically connected to the source region 38 and the contact region 39. The source electrode 12 is electrically connected to the first field plate electrode 20.

[0070] The source electrode 12 includes a first contact plug portion 12a, a second contact plug portion 12b, and a surface portion 12c.

[0071] The first contact plug portion 12a is provided, for example, between the silicon layer 10 and the surface layer portion 12c. The first contact plug portion 12a is in contact with, for example, the silicon layer 10. The first contact plug portion 12a is in contact with, for example, the contact region 39. For example, the bottom surface of the first contact plug portion 12a is in contact with the contact region 39.

[0072] The first contact plug portion 12a is in contact with, for example, the source region 38. For example, the side surface of the first contact plug portion 12a is in contact with the source region 38.

[0073] A portion of the first contact plug portion 12a fills, for example, a recess provided in the silicon layer 10. A portion of the first contact plug portion 12a is provided, for example, in a recess provided in the silicon layer 10.

[0074] The second contact plug portion 12b is provided, for example, between the contact portion and the surface layer portion 12c. The second contact plug portion 12b is in contact with the contact portion , for example.

[0075] A portion of the second contact plug portion 12b fills, for example, a recess provided in the contact portion 26. A portion of the second contact plug portion 12b is provided, for example, in the recess provided in the contact portion 26.

[0076] The surface layer portion 12c is provided on the plurality of first contact plug portions 12a and the plurality of second contact plug portions 12b, and electrically connects the plurality of first contact plug portions 12a and the plurality of second contact plug portions 12b.

[0077] The surface layer portion 12c is a region to which, for example, a bonding wire is connected when the MOSFET 100 is mounted.

[0078] The source electrode 12 is a conductor. The source electrode 12 is made of, for example, a metal. The first contact plug portion 12a, the second contact plug portion 12b, and the surface layer portion 12c may be made of the same material or different materials.

[0079] The first contact plug portion 12a and the second contact plug portion 12b have a laminated structure of, for example, titanium, titanium nitride, and tungsten, and the surface layer portion 12c has a laminated structure of, for example, titanium nitride and aluminum.

[0080] The drain electrode 14 is provided on the second face F2 side of the silicon layer 10. The drain electrode 14 is provided on the second face F2 of the silicon layer 10. The drain electrode 14 is electrically connected to the drain region 35. The drain electrode 14 contacts the drain region 35. The drain electrode 14 is electrically connected to the drift region 36.

[0081] The drain electrode 14 is a conductor. The drain electrode 14 is made of, for example, a metal. The drain electrode 14 has a laminated structure made of, for example, a material selected from the group consisting of titanium, aluminum, nickel, copper, silver, and gold.

[0082] The operation and effects of the semiconductor device of the first embodiment will be described below.

[0083] Fig. 3 is a schematic cross-sectional view of a semiconductor device of a comparative embodiment. Fig. 4 is a schematic plan view of a semiconductor device of a comparative embodiment. Fig. 4 is a plan view of the first plane (F1 in Fig. 3) of Fig. 3. Fig. 3 is a BB' cross section of Fig. 4.

[0084] Fig. 3 is a diagram corresponding to Fig. 1 of the first embodiment, and Fig. 4 is a diagram corresponding to Fig. 2 of the first embodiment.

[0085] The comparative semiconductor device is a vertical transistor in which a gate electrode and a field plate electrode are buried in a trench. The comparative semiconductor device is a vertical power MOSFET. The comparative semiconductor device is MOSFET 900.

[0086] The MOSFET 900 of the comparative example differs from the MOSFET 100 of the first embodiment in that it does not include the connection portion 24 and the contact portion 26.

[0087] 3, in the MOSFET 900, the source electrode 12 is in contact with the first field plate electrode 20. The second contact plug portion 12b of the source electrode 12 is in contact with the first field plate electrode 20.

[0088] MOSFET 900 has a first field plate electrode 20 electrically connected to source electrode 12 provided in first field plate trench 31. By changing the electric field distribution in drift region 36 using first field plate electrode 20, it becomes possible to increase the impurity concentration in drift region 36 while maintaining the breakdown voltage of MOSFET 900, for example. Therefore, MOSFET 900 makes it possible to reduce on-resistance while maintaining the breakdown voltage.

[0089] 5 is an explanatory diagram of the operation and effect of the semiconductor device of Embodiment 1. FIG. 5 is an equivalent circuit diagram of a MOSFET 900 of a comparative embodiment.

[0090] As shown in Figure 5, when the field plate electrode is electrically connected to the source electrode of a vertical transistor, a snubber circuit is formed between the source electrode and drain electrode, in which the electrical resistance between the source electrode and field plate electrode (R in Figure 5) and the capacitance between the field plate electrode and the semiconductor layer (Cds in Figure 5) are connected in series. By providing a snubber circuit, ringing during MOSFET off-state operation can be suppressed.

[0091] If the snubber circuit's electrical resistance R becomes low, ringing during off-state operation cannot be suppressed, and ringing may occur in the MOSFET. If ringing occurs in the MOSFET, it can cause problems, such as an increase in the current flowing through an electronic circuit containing the MOSFET, increasing the power consumption of the electronic circuit.

[0092] In the comparative MOSFET 900, the source electrode 12 and the first field plate electrode 20 are electrically connected directly above the first field plate electrode 20. This shortens the path between the source electrode 12 and the first field plate electrode 20, reducing the electrical resistance R between the source electrode 12 and the first field plate electrode 20. This may cause ringing when the MOSFET 900 is turned off.

[0093] The MOSFET 100 of the first embodiment includes a connection part 24 between the source electrode 12 and the first field plate electrode 20, the connection part 24 having a higher resistance than the first field plate electrode 20. Therefore, the electrical resistance R between the source electrode 12 and the first field plate electrode 20 is higher than that of the MOSFET 900 of the comparative embodiment. This suppresses the occurrence of ringing during the off operation of the MOSFET 100.

[0094] From the viewpoint of suppressing ringing, the electrical resistance of the connection portion 24 is preferably 100 times or more, and more preferably 1000 times or more, the electrical resistance of the first field plate electrode 20 .

[0095] From the viewpoint of suppressing ringing, the impurity concentration of the polycrystalline silicon of the connection portion 24 is preferably 1 / 100 or less, and more preferably 1 / 1000 or less, of the impurity concentration of the polycrystalline silicon of the first field plate electrode 20.

[0096] From the viewpoint of reducing the contact resistance of the second contact plug portion 12b, the impurity concentration of the polycrystalline silicon of the contact portion 26 is preferably 100 times or more, more preferably 1000 times or more, and even more preferably 10000 times or more, of the impurity concentration of the polycrystalline silicon of the connection portion 24.

[0097] From the viewpoint of reducing the contact resistance of the second contact plug portion 12b, the impurity concentration of the polycrystalline silicon of the contact portion 26 is preferably higher than the impurity concentration of the polycrystalline silicon of the first field plate electrode 20.

[0098] (Variation) The semiconductor device according to the modification of the first embodiment differs from the semiconductor device according to the first embodiment in that it does not include a contact portion.

[0099] Fig. 6 is a schematic cross-sectional view of a semiconductor device according to a modification of the first embodiment, which corresponds to Fig. 1 of the first embodiment.

[0100] The semiconductor device according to the modification of the first embodiment is a MOSFET 101.

[0101] The MOSFET 101 according to the modification of the first embodiment differs from the MOSFET 100 according to the first embodiment in that it does not include the contact portion 26.

[0102] In the MOSFET 101 according to the modification of the first embodiment, the occurrence of ringing during an off operation is suppressed, similar to the MOSFET 100 according to the first embodiment.

[0103] As described above, according to the first embodiment and its modifications, a MOSFET capable of suppressing ringing can be realized.

[0104] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the width of the connection portion in a first direction parallel to the first surface is smaller than the width of the first field plate electrode in the first direction. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0105] The semiconductor device of the second embodiment is a vertical transistor in which a gate electrode and a field plate electrode are buried in a trench. The semiconductor device of the second embodiment is a vertical power MOSFET. The semiconductor device of the second embodiment is a MOSFET 200.

[0106] Fig. 7 is a schematic cross-sectional view of a semiconductor device according to the second embodiment, which corresponds to Fig. 1 of the first embodiment.

[0107] The MOSFET 200 includes a silicon layer 10 (semiconductor layer), a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, a first field plate electrode 20, a first field plate insulating layer 22, a connection portion 24, and an interlayer insulating layer 28 (first insulating layer).

[0108] The source electrode 12 includes a first contact plug portion 12a, a second contact plug portion 12b, and a surface portion 12c.

[0109] The silicon layer 10 includes a gate trench 30, a first field plate trench 31 (first trench), and a + n-type drain region 35 - a p-type drift region 36 (first semiconductor region), a p-type body region 37 (second semiconductor region), and + a source region 38 (third semiconductor region) of p + The mold contact area 39 is included.

[0110] The width (w1 in FIG. 7) of connecting portion 24 in the first direction parallel to first face F1 is smaller than the width (w2 in FIG. 7) of first field plate electrode 20 in the first direction. The width w1 of connecting portion 24 in the first direction parallel to first face F1 is, for example, not less than one-hundredth and not more than one-half the width w2 of first field plate electrode 20 in the first direction.

[0111] The first field plate electrode 20 includes polycrystalline silicon. The first field plate electrode 20 is, for example, polycrystalline silicon containing impurities. The first field plate electrode 20 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The first field plate electrode 20 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0112] The contact 24 is provided in the first field plate trench 31 .

[0113] The connection portion 24 includes polycrystalline silicon. The connection portion 24 is, for example, polycrystalline silicon containing impurities. The connection portion 24 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The connection portion 24 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0114] The electrical resistance of the connection portion 24 is higher than the electrical resistance of the first field plate electrode 20. The electrical resistance of the connection portion 24 is, for example, 100 times or more and 10,000 times or less than the electrical resistance of the first field plate electrode 20.

[0115] The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, substantially equal to the impurity concentration of the polycrystalline silicon of the first field plate electrode 20. The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, lower than the impurity concentration of the polycrystalline silicon of the first field plate electrode 20. The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, 1 / 100 or less of the impurity concentration of the polycrystalline silicon of the first field plate electrode 20.

[0116] In the MOSFET 200 of the second embodiment, the width w1 of the connection portion 24 is made smaller than the width w2 of the first field plate electrode 20, thereby increasing the electrical resistance R between the source electrode 12 and the first field plate electrode 20. This suppresses the occurrence of ringing during the off operation of the MOSFET 200.

[0117] From the viewpoint of suppressing ringing, the width w1 of the connection portion 24 is preferably equal to or less than half the width w2 of the first field plate electrode 20, more preferably equal to or less than one-third, and even more preferably equal to or less than one-fourth.

[0118] (Variation) The semiconductor device of the modified example of the second embodiment differs from the semiconductor device of the second embodiment in that the width of the upper part of the first trench in the first direction is smaller than the width of the lower part of the first trench in the first direction.

[0119] Fig. 8 is a schematic cross-sectional view of a semiconductor device according to a modification of the second embodiment, which corresponds to Fig. 7 of the second embodiment.

[0120] The semiconductor device according to the modification of the second embodiment is a MOSFET 201.

[0121] In MOSFET 201 according to the modification of the second embodiment, the width in the first direction of the upper part of first field plate trench 31 (w3 in FIG. 8) is smaller than the width in the first direction of the lower part of first field plate trench 31 (w4 in FIG. 8). The width w3 in the first direction of the upper part of first field plate trench 31 is, for example, 10% to 80% of the width w4 in the first direction of the lower part of first field plate trench 31.

[0122] The MOSFET 201 can be manufactured, for example, by processing the first field plate trench 31 in the silicon layer 10 so that the width of the upper portion is smaller than the width of the lower portion.

[0123] In the MOSFET 201 according to the modification of the second embodiment, the occurrence of ringing during off operation is suppressed, similar to the MOSFET 200 according to the second embodiment. Furthermore, in the MOSFET 201, the distance between the gate trench 30 and the first field plate trench 31 on the first face F1 is greater than in the MOSFET 200. This makes it easier to form, for example, the first contact plug portion 12a.

[0124] As described above, according to the second embodiment and its modifications, a MOSFET capable of suppressing ringing can be realized.

[0125] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the material of the connection portion is different from the material of the first field plate electrode. In the following, some description of the content that overlaps with the first embodiment may be omitted.

[0126] The semiconductor device of the third embodiment is a vertical transistor in which a gate electrode and a field plate electrode are buried in a trench. The semiconductor device of the third embodiment is a vertical power MOSFET. The semiconductor device of the third embodiment is a MOSFET 300.

[0127] Fig. 9 is a schematic cross-sectional view of a semiconductor device according to the third embodiment, which corresponds to Fig. 1 of the first embodiment.

[0128] The MOSFET 300 includes a silicon layer 10 (semiconductor layer), a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, a first field plate electrode 20, a first field plate insulating layer 22, a connection portion 24, and an interlayer insulating layer 28 (first insulating layer).

[0129] The source electrode 12 includes a first contact plug portion 12a, a second contact plug portion 12b, and a surface portion 12c.

[0130] The silicon layer 10 includes a gate trench 30, a first field plate trench 31 (first trench), and a + n-type drain region 35 - a p-type drift region 36 (first semiconductor region), a p-type body region 37 (second semiconductor region), and + a source region 38 (third semiconductor region) of p + The mold contact area 39 is included.

[0131] The first field plate electrode 20 includes polycrystalline silicon. The first field plate electrode 20 is, for example, polycrystalline silicon containing impurities. The first field plate electrode 20 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The first field plate electrode 20 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0132] The contact 24 is provided in the first field plate trench 31 .

[0133] The material of the connection portion 24 is a material different from the material of the first field plate electrode 20. The material of the connection portion 24 is, for example, a material different from polycrystalline silicon. The material of the connection portion 24 is, for example, silicon nitride or silicon oxynitride. The material of the connection portion 24 is, for example, semi-insulating silicon nitride (SinSiN).

[0134] The electrical resistance of the connection portion 24 is higher than the electrical resistance of the first field plate electrode 20. The electrical resistance of the connection portion 24 is, for example, 100 times or more and 10,000 times or less than the electrical resistance of the first field plate electrode 20.

[0135] The electrical resistivity of the material of the connection portion 24 is greater than the electrical resistivity of the first field plate electrode 20 .

[0136] In the MOSFET 300 of the third embodiment, the connection portion 24 is made of a material having a higher electrical resistivity than the material of the first field plate electrode, thereby increasing the electrical resistance R between the source electrode 12 and the first field plate electrode 20. This suppresses the occurrence of ringing during the off-state of the MOSFET 300.

[0137] (Variation) The semiconductor device of the modified example of the third embodiment differs from the semiconductor device of the third embodiment in that the width of the connection portion in a first direction parallel to the first surface is smaller than the width of the first field plate electrode in the first direction.

[0138] Fig. 10 is a schematic cross-sectional view of a semiconductor device according to a modification of the third embodiment, which corresponds to Fig. 9 of the third embodiment.

[0139] The semiconductor device according to the modification of the third embodiment is a MOSFET 301.

[0140] In the MOSFET 301 of the modified example of the third embodiment, the width of the connection portion 24 in the first direction parallel to the first face F1 (w5 in FIG. 10) is smaller than the width of the first field plate electrode 20 in the first direction (w6 in FIG. 10).

[0141] In the MOSFET 301 according to the modification of the third embodiment, the width w5 of the connection portion 24 is made smaller than the width w6 of the first field plate electrode 20, thereby further increasing the electrical resistance R between the source electrode 12 and the first field plate electrode 20. This further suppresses the occurrence of ringing during the off operation of the MOSFET 301.

[0142] As described above, according to the third embodiment and its modifications, a MOSFET capable of suppressing ringing can be realized.

[0143] (Fourth embodiment) The semiconductor device of the fourth embodiment further includes a first insulating layer provided between the first electrode and the semiconductor layer, between the first electrode and the first field plate electrode, and between the first electrode and the gate electrode. The semiconductor device of the fourth embodiment differs from the semiconductor devices of the first to third embodiments in that the connection portion is surrounded by the first insulating layer. In other words, the semiconductor device of the fourth embodiment differs from the semiconductor devices of the first to third embodiments in that the connection portion is provided outside the first trench. Hereinafter, some of the description overlapping with the first to third embodiments may be omitted.

[0144] The semiconductor device of the fourth embodiment is a vertical transistor in which a gate electrode and a field plate electrode are buried in a trench. The semiconductor device of the fourth embodiment is a vertical power MOSFET. The semiconductor device of the fourth embodiment is a MOSFET 400.

[0145] Fig. 11 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. Fig. 12 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. Fig. 12 is a cross-section taken along CC' in Fig. 11. Fig. 11 is a cross-section taken along DD' in Fig. 12.

[0146] FIG. 11 is a diagram corresponding to FIG. 1 of the first embodiment.

[0147] The MOSFET 400 includes a silicon layer 10 (semiconductor layer), a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, a first field plate electrode 20, a first field plate insulating layer 22, a connection portion 24, and an interlayer insulating layer 28 (first insulating layer).

[0148] The source electrode 12 includes a first contact plug portion 12a and a surface portion 12c.

[0149] The silicon layer 10 includes a gate trench 30, a first field plate trench 31 (first trench), and a + n-type drain region 35 - a p-type drift region 36 (first semiconductor region), a p-type body region 37 (second semiconductor region), and+ a source region 38 (third semiconductor region) of p + The mold contact area 39 is included.

[0150] The first field plate electrode 20 includes polycrystalline silicon. The first field plate electrode 20 is, for example, polycrystalline silicon containing impurities. The first field plate electrode 20 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The first field plate electrode 20 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0151] 12, the connection portion 24 is surrounded by the interlayer insulating layer 28 in a cross section parallel to the first plane F1. The connection portion 24 is provided outside the first field plate trench 31.

[0152] The connection portion 24 is provided between the source electrode 12 and the first field plate electrode 20. The connection portion 24 electrically connects the source electrode 12 and the first field plate electrode 20. The connection portion 24 contacts the source electrode 12 and the first field plate electrode 20.

[0153] The electrical resistance of the connection portion 24 is higher than the electrical resistance of the first field plate electrode 20. The electrical resistance of the connection portion 24 is, for example, 100 times or more and 10,000 times or less than the electrical resistance of the first field plate electrode 20.

[0154] The material of the connection portion 24 is, for example, a material different from the material of the first field plate electrode 20. The material of the connection portion 24 is, for example, a material different from polycrystalline silicon. The material of the connection portion 24 is, for example, silicon nitride or silicon oxynitride. The material of the connection portion 24 is, for example, semi-insulating silicon nitride (SinSiN).

[0155] The electrical resistivity of the material of the connection portion 24 is greater than the electrical resistivity of the first field plate electrode 20, for example.

[0156] The material of the connection portion 24 is, for example, the same material as the material of the first field plate electrode 20. The connection portion 24 includes, for example, polycrystalline silicon. The connection portion 24 is, for example, polycrystalline silicon containing impurities. The connection portion 24 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The connection portion 24 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0157] The impurity concentration of the polycrystalline silicon of the connection portion 24 is lower than the impurity concentration of the polycrystalline silicon of the first field plate electrode 20. The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, 1 / 100 or less of the impurity concentration of the polycrystalline silicon of the first field plate electrode 20.

[0158] The electrical resistance of the connection portion 24 is higher than the electrical resistance of the first field plate electrode 20. The electrical resistance of the connection portion 24 is, for example, 100 times or more and 10,000 times or less than the electrical resistance of the first field plate electrode 20.

[0159] In the MOSFET 400 of the fourth embodiment, the high-resistance connection portion 24 is provided, thereby increasing the electrical resistance R between the source electrode 12 and the first field plate electrode 20. This suppresses the occurrence of ringing during the OFF operation of the MOSFET 400.

[0160] As described above, according to the fourth embodiment, a MOSFET capable of suppressing ringing can be realized.

[0161] (Fifth embodiment) The semiconductor device of the fifth embodiment differs from the semiconductor device of the first embodiment in that the connection portion extends in a direction parallel to the first surface, a first end of the connection portion is connected to the first field plate electrode, and a second end of the connection portion is connected to the first electrode. Hereinafter, some description of content that overlaps with the first to fourth embodiments may be omitted.

[0162] The semiconductor device of the fifth embodiment is a vertical transistor in which a gate electrode and a field plate electrode are buried in a trench. The semiconductor device of the fifth embodiment is a vertical power MOSFET. The semiconductor device of the fifth embodiment is a MOSFET 500.

[0163] Fig. 13 is a schematic cross-sectional view of the semiconductor device of the fifth embodiment. Fig. 14 is a schematic top view of the semiconductor device of the fifth embodiment. Fig. 14 is a diagram showing a state in which the surface layer portion 12c of the source electrode 12 and the interlayer insulating layer 28 have been peeled off. Fig. 13 is an E-E' cross section of Fig. 14.

[0164] FIG. 13 is a diagram corresponding to FIG. 1 of the first embodiment.

[0165] The MOSFET 500 includes a silicon layer 10 (semiconductor layer), a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, a first field plate electrode 20, a first field plate insulating layer 22, a connection portion 24, and an interlayer insulating layer 28 (first insulating layer).

[0166] The source electrode 12 includes a first contact plug portion 12a, a second contact plug portion 12b, and a surface portion 12c. The connection portion 24 has a first end E1 and a second end E2. The connection portion 24 includes a first portion 24a, a second portion 24b, a third portion 24c, and a fourth portion 24d.

[0167] The silicon layer 10 includes a gate trench 30, a first field plate trench 31 (first trench), and a + n-type drain region 35 - a p-type drift region 36 (first semiconductor region), a p-type body region 37 (second semiconductor region), and + a source region 38 (third semiconductor region) of p + The mold contact area 39 is included.

[0168] The first field plate electrode 20 includes polycrystalline silicon. The first field plate electrode 20 is, for example, polycrystalline silicon containing impurities. The first field plate electrode 20 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The first field plate electrode 20 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0169] The impurity concentration of the first field plate electrode 20 is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3 When the first field plate electrode 20 is made of n-type polycrystalline silicon, the n-type impurity concentration of the first field plate electrode 20 is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3 When the first field plate electrode 20 is made of p-type polycrystalline silicon, the p-type impurity concentration of the first field plate electrode 20 is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3 The following is the result.

[0170] The connection portion 24 is provided in the interlayer insulating layer 28. In a cross section parallel to the first face F1, the connection portion 24 is surrounded by the interlayer insulating layer 28. The connection portion 24 is provided outside the first field plate trench 31.

[0171] The connection portion 24 is provided between the source electrode 12 and the first field plate electrode 20. The connection portion 24 electrically connects the source electrode 12 and the first field plate electrode 20.

[0172] The connecting portion 24 extends in a direction parallel to the first face F1. The first portion 24a and the second portion 24b, the second portion 24b and the third portion 24c, and the third portion 24c and the fourth portion 24d extend in directions that intersect with each other.

[0173] For example, the first portion 24a of the connecting portion 24 extends in a first direction. For example, the second portion 24b of the connecting portion 24 extends in a second direction. For example, the third portion 24c of the connecting portion 24 extends in the first direction. For example, the fourth portion 24d of the connecting portion 24 extends in the second direction.

[0174] In Figure 14, the connecting portion 24 is shown as an example in which the first portion 24a and the second portion 24b, the second portion 24b and the third portion 24c, and the third portion 24c and the fourth portion 24d are perpendicular to each other, but it may also be in a form in which the direction gradually changes between each portion.

[0175] The connection portion 24 is in contact with the source electrode 12 and the first field plate electrode 20. A first end E1 of the connection portion 24 is connected to the first field plate electrode 20. A second end E2 of the connection portion 24 opposite to the first end E1 is connected to the second contact plug portion 12b of the source electrode 12.

[0176] The connection portion 24 includes polycrystalline silicon. The connection portion 24 is, for example, polycrystalline silicon containing impurities. The connection portion 24 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The connection portion 24 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0177] The impurity concentration of the polycrystalline silicon of the connection portion 24 is lower than the impurity concentration of the polycrystalline silicon of the first field plate electrode 20. The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, 1 / 100 or less of the impurity concentration of the polycrystalline silicon of the first field plate electrode 20.

[0178] The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, 1×10 11 cm -3 More than 1×10 17 cm -3 When the connection portion 24 is made of n-type polycrystalline silicon, the n-type impurity concentration of the connection portion 24 is, for example, 1×10 11 cm -3 More than 1×10 17cm -3 When the connection portion 24 is made of p-type polycrystalline silicon, the p-type impurity concentration of the connection portion 24 is, for example, 1×10 11 cm -3 More than 1×10 17 cm -3 The following is the result.

[0179] The electrical resistance of the connection portion 24 is higher than the electrical resistance of the first field plate electrode 20. The electrical resistance of the connection portion 24 is, for example, 100 times or more and 10,000 times or less than the electrical resistance of the first field plate electrode 20.

[0180] The impurity concentration of the polycrystalline silicon at the second end E2 is, for example, higher than the impurity concentration of the polycrystalline silicon at the first end E1, and is, for example, 100 times or more and 1,000,000 times or less than the impurity concentration of the polycrystalline silicon at the first end E1.

[0181] By increasing the impurity concentration of the polycrystalline silicon at the second end E2, for example, the contact resistance of the second contact plug portion 12b can be reduced.

[0182] In the MOSFET 500 of the fifth embodiment, the high-resistance connection portion 24 is provided, thereby increasing the electrical resistance R between the source electrode 12 and the first field plate electrode 20. This suppresses the occurrence of ringing during the OFF operation of the MOSFET 500.

[0183] (First Modification) The semiconductor device of the first modification of the fifth embodiment differs from the semiconductor device of the fifth embodiment in that the connection portion further includes a fifth portion.

[0184] Fig. 15 is a schematic top view of a semiconductor device according to a first modified example of the fifth embodiment. Fig. 15 is a view showing a state in which the surface layer portion 12c of the source electrode 12 and the interlayer insulating layer 28 have been peeled off. Fig. 15 is a view corresponding to Fig. 14 of the fifth embodiment.

[0185] The connecting portion 24 has a first end E1 and a second end E2, and includes a first portion 24a, a second portion 24b, a third portion 24c, a fourth portion 24d, and a fifth portion 24e.

[0186] The connecting portion 24 extends in a direction parallel to the first face F1. For example, the first portion 24a of the connecting portion 24 extends in the first direction. For example, the second portion 24b of the connecting portion 24 extends in the second direction. For example, the third portion 24c of the connecting portion 24 extends in the first direction. For example, the fourth portion 24d of the connecting portion 24 extends in the second direction. For example, the fifth portion 24e of the connecting portion 24 extends in the first direction.

[0187] (Second Modification) The semiconductor device of the second modified example of the fifth embodiment differs from the semiconductor device of the fifth embodiment in that the connecting portion 24 does not include the second portion 24b, the third portion 24c, and the fourth portion 24d.

[0188] Fig. 16 is a schematic top view of a semiconductor device according to a second modified example of the fifth embodiment. Fig. 16 is a view showing a state in which the surface layer portion 12c of the source electrode 12 and the interlayer insulating layer 28 have been peeled off. Fig. 16 is a view corresponding to Fig. 14 of the fifth embodiment.

[0189] The connecting portion 24 has a first end E1 and a second end E2. The connecting portion 24 includes a first portion 24a.

[0190] The connecting portion 24 extends in a direction parallel to the first face F1. For example, the first portion 24a of the connecting portion 24 extends in a first direction.

[0191] (Third Modification) The semiconductor device of the third modification of the fifth embodiment differs from the semiconductor device of the fifth embodiment in that the material of the connection portion is different from the material of the first field plate electrode.

[0192] The first field plate electrode 20 includes polycrystalline silicon. The first field plate electrode 20 is, for example, polycrystalline silicon containing impurities. The first field plate electrode 20 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The first field plate electrode 20 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0193] The material of the connection portion 24 is a material different from the material of the first field plate electrode 20. The material of the connection portion 24 is, for example, a material different from polycrystalline silicon. The material of the connection portion 24 is, for example, silicon nitride or silicon oxynitride. The material of the connection portion 24 is, for example, semi-insulating silicon nitride (SinSiN).

[0194] The electrical resistance of the connection portion 24 is higher than the electrical resistance of the first field plate electrode 20. The electrical resistance of the connection portion 24 is, for example, 100 times or more and 10,000 times or less than the electrical resistance of the first field plate electrode 20.

[0195] The electrical resistivity of the material of the connection portion 24 is greater than the electrical resistivity of the first field plate electrode 20 .

[0196] As described above, according to the fifth embodiment and its modifications, a MOSFET capable of suppressing ringing can be realized.

[0197] (Sixth embodiment) The semiconductor device of the sixth embodiment differs from the semiconductor device of the first embodiment in that the semiconductor layer further includes a second trench provided on the first surface side, surrounded by a gate trench, with the gate trench provided between the first trench and the second trench, a second field plate electrode provided in the second trench and in contact with the first electrode, and a second field plate insulating layer provided between the second field plate electrode and the semiconductor layer. Hereinafter, some description of content that overlaps with the first to fifth embodiments may be omitted.

[0198] The semiconductor device of the sixth embodiment is a vertical transistor in which a gate electrode and a field plate electrode are buried in a trench. The semiconductor device of the sixth embodiment is a vertical power MOSFET. The semiconductor device of the sixth embodiment is a MOSFET 600.

[0199] Fig. 17 is a schematic cross-sectional view of the semiconductor device of the sixth embodiment. Fig. 18 is a schematic plan view of the semiconductor device of the sixth embodiment. Fig. 18 is a plan view of the first plane (F1 in Fig. 17) of Fig. 17. Fig. 17 is a cross-section taken along line FF' of Fig. 18.

[0200] Fig. 17 is a diagram corresponding to Fig. 1 of the first embodiment, and Fig. 18 is a diagram corresponding to Fig. 2 of the first embodiment.

[0201] The MOSFET 600 includes a silicon layer 10 (semiconductor layer), a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, a first field plate electrode 20, a second field plate electrode 21, a first field plate insulating layer 22, a second field plate insulating layer 23, a connection portion 24, a contact portion 26, and an interlayer insulating layer 28 (first insulating layer).

[0202] The source electrode 12 includes a first contact plug portion 12a, a second contact plug portion 12b, and a surface portion 12c.

[0203] The silicon layer 10 includes a gate trench 30, a first field plate trench 31 (first trench), a second field plate trench 32 (second trench), and a + n-type drain region 35 - a p-type drift region 36 (first semiconductor region), a p-type body region 37 (second semiconductor region), and + a source region 38 (third semiconductor region) of p + The mold contact area 39 is included.

[0204] The gate trench 30 surrounds the first field plate trench 31. The gate trench 30 surrounds the second field plate trench 32. The gate trench 30 has a mesh shape on the first face F1.

[0205] The gate electrode 16 is disposed within the gate trench 30. A gate insulating layer 18 is disposed between the gate electrode 16 and the silicon layer 10.

[0206] The first field plate trench 31 is provided in the silicon layer 10. The first field plate trench 31 is provided on the first face F1 side of the silicon layer 10. The first field plate trench 31 is a groove formed in the silicon layer 10.

[0207] 18, the first field plate trenches 31 are provided in a dot pattern on the first face F1. The first field plate trenches 31 are surrounded by the gate trenches 30. The first field plate trenches 31 are deeper than the gate trenches 30.

[0208] The first field plate electrode 20 is provided in the first field plate trench 31 .

[0209] The first field plate electrode 20 is electrically connected to the source electrode 12 .

[0210] The first field plate electrode 20 includes polycrystalline silicon. The first field plate electrode 20 is, for example, polycrystalline silicon containing impurities. The first field plate electrode 20 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The first field plate electrode 20 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0211] The first field plate insulating layer 22 is provided between the first field plate electrode 20 and the silicon layer 10. The first field plate insulating layer 22 is provided between the first field plate electrode 20 and the drift region 36. The first field plate insulating layer 22 is, for example, silicon oxide.

[0212] The connection portion 24 is provided between the source electrode 12 and the first field plate electrode 20. The connection portion 24 electrically connects the source electrode 12 and the first field plate electrode 20. The connection portion 24 is provided in the first field plate trench 31.

[0213] The electrical resistance of the connection portion 24 is higher than the electrical resistance of the first field plate electrode 20. The electrical resistance of the connection portion 24 is, for example, 100 times or more and 10,000 times or less than the electrical resistance of the first field plate electrode 20.

[0214] The connection portion 24 includes polycrystalline silicon. The connection portion 24 is, for example, polycrystalline silicon containing impurities. The connection portion 24 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The connection portion 24 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0215] The impurity concentration of the polycrystalline silicon of the connection portion 24 is lower than the impurity concentration of the polycrystalline silicon of the first field plate electrode 20. The impurity concentration of the polycrystalline silicon of the connection portion 24 is, for example, 1 / 100 or less of the impurity concentration of the polycrystalline silicon of the first field plate electrode 20.

[0216] The contact portion 26 is provided between the source electrode 12 and the connection portion 24. The contact portion 26 electrically connects the source electrode 12 and the connection portion 24.

[0217] The contact portion 26 is in contact with the source electrode 12. The contact portion 26 is in contact with the second contact plug portion 12b of the source electrode 12. The contact portion 26 is in contact with the connection portion 24. The contact portion 26 is provided in the first field plate trench 31.

[0218] The contact portion 26 includes polycrystalline silicon. The contact portion 26 is, for example, polycrystalline silicon containing impurities. The contact portion 26 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The contact portion 26 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0219] The impurity concentration of the polycrystalline silicon of the contact portion 26 is higher than the impurity concentration of the polycrystalline silicon of the first field plate electrode 20, for example.

[0220] By providing the contact portion 26, for example, the contact resistance of the second contact plug portion 12b can be reduced.

[0221] The second field plate trench 32 is provided in the silicon layer 10. The second field plate trench 32 is provided on the first face F1 side of the silicon layer 10. The second field plate trench 32 is a groove formed in the silicon layer 10.

[0222] 18, the second field plate trenches 32 are provided in a dot pattern on the first face F1. The second field plate trenches 32 are surrounded by the gate trenches 30. The second field plate trenches 32 are deeper than the gate trenches 30.

[0223] A gate trench 30 is provided between the first field plate trench 31 and the second field plate trench 32. The first field plate trench 31 and the second field plate trench 32 are arranged in a checkerboard pattern, for example, as shown in FIG.

[0224] The second field plate electrode 21 is provided in the second field plate trench 32 .

[0225] The second field plate electrode 21 is electrically connected to the source electrode 12. The second field plate electrode 21 is in contact with the source electrode 12. The second field plate electrode 21 is in contact with the second contact plug portion 12b of the source electrode 12.

[0226] The second field plate electrode 21 includes polycrystalline silicon. The second field plate electrode 21 is, for example, polycrystalline silicon containing impurities. The second field plate electrode 21 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The second field plate electrode 21 is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0227] The material of the second field plate electrode 21 is, for example, the same material as the material of the first field plate electrode 20.

[0228] The second field plate insulating layer 23 is provided between the second field plate electrode 21 and the silicon layer 10. The second field plate insulating layer 23 is provided between the second field plate electrode 21 and the drift region 36. The second field plate insulating layer 23 is, for example, silicon oxide.

[0229] No connection portion 24 is provided between the source electrode 12 and the second field plate electrode 21.

[0230] If the electrical resistance R of the snubber circuit of the MOSFET becomes too high, there is a risk of increasing switching loss in the MOSFET. A MOSFET 600 of the sixth embodiment includes a region including a first field plate trench 31 with high electrical resistance R between the source electrode 12 and the first field plate electrode 20, and a region including a second field plate trench 32 with low electrical resistance R between the source electrode 12 and the second field plate electrode 21. This configuration makes it possible to suppress ringing and reduce switching loss at the same time.

[0231] Although the above description takes as an example a case where the arrangement pattern of first field plate trenches 31 and second field plate trenches 32 is a checkerboard pattern, the arrangement pattern of first field plate trenches 31 and second field plate trenches 32 is not limited to a checkerboard pattern. For example, it is also possible to change the ratio of first field plate trenches 31 to second field plate trenches 32.

[0232] As described above, according to the sixth embodiment, a MOSFET capable of suppressing ringing can be realized.

[0233] (Seventh embodiment) A semiconductor device according to a seventh embodiment includes a semiconductor layer having a first surface and a second surface opposite to the first surface, the semiconductor layer including a first trench provided on the first surface side, a gate trench provided on the first surface side and surrounding the first trench, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface, and a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; and a third semiconductor region provided in the first trench and including first polycrystalline silicon. the first field plate electrode, a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer, a gate electrode provided in the gate trench and including second polycrystalline silicon, a gate insulating layer provided between the gate electrode and the semiconductor layer, a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region and the first field plate electrode, and a second electrode provided on the second surface side of the semiconductor layer and electrically connected to the first semiconductor region, wherein the impurity concentration of the first polycrystalline silicon is lower than the impurity concentration of the second polycrystalline silicon.

[0234] The semiconductor device of the seventh embodiment differs from the semiconductor device of the first embodiment in that it does not include a connection portion and a contact portion. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0235] The semiconductor device of the seventh embodiment is a vertical transistor in which a gate electrode and a field plate electrode are buried in a trench. The semiconductor device of the seventh embodiment is a vertical power MOSFET. The semiconductor device of the seventh embodiment is a MOSFET 700.

[0236] Fig. 19 is a schematic cross-sectional view of the semiconductor device of the seventh embodiment. Fig. 20 is a schematic plan view of the semiconductor device of the seventh embodiment. Fig. 20 is a plan view of the first plane (F1 in Fig. 19) of Fig. 19. Fig. 19 is a cross-section taken along line GG' of Fig. 20.

[0237] The MOSFET 700 includes a silicon layer 10 (semiconductor layer), a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate electrode 16, a gate insulating layer 18, a first field plate electrode 20, a first field plate insulating layer 22, and an interlayer insulating layer 28 (first insulating layer).

[0238] The source electrode 12 includes a first contact plug portion 12a, a second contact plug portion 12b, and a surface portion 12c.

[0239] The silicon layer 10 includes a gate trench 30, a first field plate trench 31 (first trench), and a + n-type drain region 35 - a p-type drift region 36 (first semiconductor region), a p-type body region 37 (second semiconductor region), and + a source region 38 (third semiconductor region) of p + The mold contact area 39 is included.

[0240] The gate trench 30 is provided in the silicon layer 10. The gate trench 30 is provided on the first face F1 side of the silicon layer 10. The gate trench 30 is a groove formed in the silicon layer 10.

[0241] The gate trench 30 surrounds the first field plate trench 31. The gate trench 30 has a mesh shape on the first face F1.

[0242] The gate electrode 16 is disposed within the gate trench 30. A gate insulating layer 18 is disposed between the gate electrode 16 and the silicon layer 10.

[0243] The gate electrode 16 includes, for example, second polycrystalline silicon. The second polycrystalline silicon is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The second polycrystalline silicon is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0244] The impurity concentration of the second polycrystalline silicon is, for example, 1×1019 cm -3 More than 1×10 22 cm -3 When the second polycrystalline silicon is n-type polycrystalline silicon, the n-type impurity concentration of the second polycrystalline silicon is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3 When the second polycrystalline silicon is p-type polycrystalline silicon, the p-type impurity concentration of the second polycrystalline silicon is, for example, 1×10 19 cm -3 More than 1×10 22 cm -3 The following is the result.

[0245] The gate electrode 16 may have a laminated structure of, for example, a polycrystalline silicon layer containing the second polycrystalline silicon and a metal layer.

[0246] The first field plate trench 31 is provided in the silicon layer 10. The first field plate trench 31 is provided on the first face F1 side of the silicon layer 10. The first field plate trench 31 is a groove formed in the silicon layer 10.

[0247] 20, the first field plate trenches 31 are provided in a dot pattern on the first face F1. The first field plate trenches 31 are surrounded by the gate trenches 30. The first field plate trenches 31 are deeper than the gate trenches 30.

[0248] The first field plate electrode 20 is provided in the first field plate trench 31 .

[0249] The first field plate electrode 20 is electrically connected to the source electrode 12 .

[0250] The first field plate electrode 20 includes first polycrystalline silicon. The first polycrystalline silicon is, for example, polycrystalline silicon containing impurities. The first polycrystalline silicon is, for example, polycrystalline silicon containing n-type impurities or p-type impurities. The first polycrystalline silicon is, for example, n-type polycrystalline silicon or p-type polycrystalline silicon.

[0251] The impurity concentration of the first polycrystalline silicon is, for example, 1×10 11 cm -3 More than 1×10 18 cm -3 When the first polycrystalline silicon is n-type polycrystalline silicon, the n-type impurity concentration of the first polycrystalline silicon is, for example, 1×10 11 cm -3 More than 1×10 18 cm -3 When the first polycrystalline silicon is p-type polycrystalline silicon, the p-type impurity concentration of the first polycrystalline silicon is, for example, 1×10 11 cm -3 More than 1×10 18 cm -3 The following is the result.

[0252] The impurity concentration of the first polycrystalline silicon is lower than the impurity concentration of the second polycrystalline silicon, for example, 1 / 100 or less of the impurity concentration of the second polycrystalline silicon.

[0253] The electrical resistivity of the first polycrystalline silicon is greater than the electrical resistivity of the second polycrystalline silicon, for example, 100 times or more greater than the electrical resistivity of the second polycrystalline silicon.

[0254] The source electrode 12 is provided on the first face F1 side of the silicon layer 10. The source electrode 12 is provided on the first face F1 of the silicon layer 10.

[0255] The source electrode 12 is electrically connected to the source region 38. The source electrode 12 is electrically connected to the first field plate electrode 20.

[0256] The source electrode 12 includes a first contact plug portion 12a, a second contact plug portion 12b, and a surface portion 12c.

[0257] The first contact plug portion 12a is provided, for example, between the silicon layer 10 and the surface layer portion 12c. The first contact plug portion 12a is in contact with, for example, the silicon layer 10. The first contact plug portion 12a is in contact with, for example, the contact region 39. For example, the bottom surface of the first contact plug portion 12a is in contact with the contact region 39.

[0258] The first contact plug portion 12a is in contact with, for example, the source region 38. For example, the side surface of the first contact plug portion 12a is in contact with the source region 38.

[0259] A portion of the first contact plug portion 12a fills, for example, a recess provided in the silicon layer 10. A portion of the first contact plug portion 12a is provided, for example, in a recess provided in the silicon layer 10.

[0260] The second contact plug portion 12b is provided, for example, between the first field plate electrode 20 and the surface layer portion 12c. The second contact plug portion 12b is in contact with the first field plate electrode 20, for example.

[0261] A portion of the second contact plug portion 12b fills, for example, a recess provided in the first field plate electrode 20. A portion of the second contact plug portion 12b is provided, for example, in the recess provided in the first field plate electrode 20.

[0262] The operation and effects of the semiconductor device of the seventh embodiment will be described below.

[0263] If the electrical resistance R of a MOSFET snubber circuit becomes low, ringing during off-state operation cannot be suppressed, and ringing may occur in the MOSFET. If ringing occurs in a MOSFET, it can cause problems, such as an increase in the current flowing through an electronic circuit containing the MOSFET, increasing the power consumption of the electronic circuit.

[0264] In the MOSFET 700 of the seventh embodiment, the impurity concentration of the first polycrystalline silicon contained in the first field plate electrode 20 is lower than the impurity concentration of the second polycrystalline silicon contained in the gate electrode 16. This increases the electrical resistance R between the source electrode 12 and the first field plate electrode 20. This suppresses the occurrence of ringing during the off operation of the MOSFET 700.

[0265] From the viewpoint of suppressing ringing, the impurity concentration of the first polycrystalline silicon is preferably 1 / 100 or less of the impurity concentration of the second polycrystalline silicon, more preferably 1 / 1000 or less, and even more preferably 1 / 10,000 or less.

[0266] From the viewpoint of suppressing ringing, the impurity concentration of the first polycrystalline silicon is set to 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is 1×10 or less. 16 cm -3 It is more preferable that:

[0267] As described above, according to the seventh embodiment, a MOSFET capable of suppressing ringing can be realized.

[0268] In the above, the first to seventh embodiments have been described using examples in which the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible to configure the first conductivity type as p-type and the second conductivity type as n-type.

[0269] Furthermore, in the first to seventh embodiments, the material of the first field plate electrode 20 is polycrystalline silicon, but the material of the first field plate electrode 20 is not necessarily limited to polycrystalline silicon.

[0270] Furthermore, in the first to seventh embodiments, the shape of the first surface F1 of the gate trench 30 is a quadrangular mesh shape, but the shape of the gate trench 30 may be a hexagonal mesh shape, an octagonal mesh shape, or any other polygonal mesh shape.

[0271] Furthermore, in the first to seventh embodiments, silicon has been used as an example of the semiconductor material, but other semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) can also be used.

[0272] Furthermore, in the sixth embodiment, an example was described in which the structure of the connection portion 24 is the structure of the connection portion 24 of the first embodiment, but in the sixth embodiment, the structure of the connection portion 24 is not limited to the structure of the connection portion 24 of the first embodiment, and it is also possible for it to have the structure of the connection portion 24 of, for example, the second to fifth embodiments.

[0273] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0274] 10 Silicon layer (semiconductor layer) 12 Source electrode (first electrode) 14 Drain electrode (second electrode) 16 gate electrode 18 Gate insulating layer 20 First field plate electrode 21 Second field plate electrode 22 first field plate insulating layer 23 Second field plate insulating layer 24 Connection 24a First Section 24b Second Part 26 Contact part 28 Interlayer insulating layer (first insulating layer) 30 Gate Trench 31 First field plate trench (first trench) 32 Second field plate trench (second trench) 36 drift region (first semiconductor region) 37 Body region (second semiconductor region) 38 source region (third semiconductor region) 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 400 MOSFET (semiconductor device) 500 MOSFET (semiconductor device) 600 MOSFET (semiconductor device) 700 MOSFET (semiconductor device) E1 First end E2 Second end F1 First Side F2 Second side

Claims

1. A semiconductor layer having a first surface and a second surface opposite to the first surface, a first trench provided on the first surface side; a gate trench provided on the first surface side and surrounding the first trench; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a semiconductor layer comprising: a first field plate electrode provided in the first trench; a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer; a gate electrode provided in the gate trench; a gate insulating layer provided between the gate electrode and the semiconductor layer; a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region and the first field plate electrode; a second electrode provided on the second surface side of the semiconductor layer and electrically connected to the first semiconductor region; a connection portion provided between the first electrode and the first field plate electrode, electrically connected to the first electrode and the first field plate electrode, and having an electrical resistance higher than an electrical resistance of the first field plate electrode; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, wherein the electrical resistance of said connection portion is 100 times or more the electrical resistance of said first field plate electrode.

3. 2. The semiconductor device according to claim 1, wherein the electrical resistivity of said connection portion is higher than the electrical resistivity of said first field plate electrode.

4. The semiconductor device according to claim 1 , wherein said connection portion is provided in said first trench.

5. 5. The semiconductor device according to claim 4, wherein the connection portion includes polycrystalline silicon, the first field plate electrode includes polycrystalline silicon, and an impurity concentration of the polycrystalline silicon included in the connection portion is lower than an impurity concentration of the polycrystalline silicon included in the first field plate electrode.

6. a contact portion provided in the first trench, between the connection portion and the first electrode, in contact with the connection portion and the first electrode, and including polycrystalline silicon; 6. The semiconductor device according to claim 5, wherein the impurity concentration of the polycrystalline silicon contained in said contact portion is higher than the impurity concentration of the polycrystalline silicon contained in said connecting portion.

7. 7. The semiconductor device according to claim 6, wherein the impurity concentration of the polycrystalline silicon contained in said contact portion is higher than the impurity concentration of the polycrystalline silicon contained in said first field plate electrode.

8. 5. The semiconductor device according to claim 4, wherein a width of said connection portion in a first direction parallel to said first surface is smaller than a width of said first field plate electrode in said first direction.

9. 9. The semiconductor device according to claim 8, wherein said connection portion includes polycrystalline silicon, and said first field plate electrode includes polycrystalline silicon.

10. 5. The semiconductor device according to claim 4, wherein the material of said connection portion is different from the material of said first field plate electrode.

11. 2. The semiconductor device according to claim 1, wherein the connection portion extends in a direction parallel to the first surface, a first end of the connection portion is connected to the first field plate electrode, and a second end of the connection portion is connected to the first electrode.

12. 12. The semiconductor device according to claim 11, wherein the connection portion includes a first portion extending in a first direction parallel to the first surface, and a second portion extending in a second direction parallel to the first surface and intersecting the first direction.

13. 12. The semiconductor device according to claim 11, wherein said connection portion is made of polycrystalline silicon, and an impurity concentration of said second end portion is higher than an impurity concentration of said first end portion.

14. the semiconductor layer further includes a second trench provided on the first surface side, surrounded by the gate trench, and having the gate trench provided between the first trench and the second trench; a second field plate electrode provided in the second trench and in contact with the first electrode; 2. The semiconductor device according to claim 1, further comprising: a second field plate insulating layer provided between said second field plate electrode and said semiconductor layer.

15. a first insulating layer provided between the first electrode and the semiconductor layer, between the first electrode and the first field plate electrode, and between the first electrode and the gate electrode; 2. The semiconductor device according to claim 1, wherein said connection portion is surrounded by said first insulating layer.

16. A semiconductor layer having a first surface and a second surface opposite to the first surface, a first trench provided on the first surface side; a gate trench provided on the first surface side and surrounding the first trench; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided between the first semiconductor region and the first surface; a third semiconductor region of the first conductivity type provided between the second semiconductor region and the first surface; a semiconductor layer comprising: a first field plate electrode disposed in the first trench and including first polycrystalline silicon; a first field plate insulating layer provided between the first field plate electrode and the semiconductor layer; a gate electrode provided in the gate trench and including a second polycrystalline silicon; a gate insulating layer provided between the gate electrode and the semiconductor layer; a first electrode provided on the first surface side of the semiconductor layer and electrically connected to the third semiconductor region and the first field plate electrode; a second electrode provided on the second surface side of the semiconductor layer and electrically connected to the first semiconductor region; The semiconductor device, wherein the first polycrystalline silicon has an impurity concentration lower than the impurity concentration of the second polycrystalline silicon.

17. 17. The semiconductor device according to claim 16, wherein the impurity concentration of said first polycrystalline silicon is 1 / 100 or less of the impurity concentration of said second polycrystalline silicon.

18. The impurity concentration of the first polycrystalline silicon is 1×10 １８ cm －３ The impurity concentration in the second polycrystalline silicon is 1×10 ２０ cm －３ 17. The semiconductor device according to claim 16.

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