High-side on-period control circuit and method for asymmetric half-bridge power converter

Abstract

This invention relates to a control circuit and method for controlling an asymmetric half-bridge power converter. [Solution] The active off period is controlled so that the emission of magnetization energy and resonant capacitor energy in the asymmetric half-bridge converter 100 ends simultaneously, and all of the stored energy is delivered to the output in each switching cycle. Several similar techniques for controlling the high-side switch-on period are shown. One is to track the volt-seconds applied during the storage cycle and allow the active emission off period to be limited to the same volt-seconds. A second option is to provide a high-side switch-on period proportional to the low-side switch-on period in that switching cycle. A third option is to provide a maximum high-side switch-on period that can be programmed to ensure that the high-side switch-on period is less than or equal to half of the resonant period.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 703,463, filed on 4 October 2024, which is incorporated by reference in its entirety.

[0002]

[0002] This disclosure generally relates to power converters, and more specifically to control circuits and methods for controlling asymmetric half-bridge power converters. [Background technology]

[0003]

[0003] Asymmetric capacitively coupled resonant flyback converters (AHBs) have significant advantages over more typical flyback converters in terms of high output voltage and output power. An AHB converter combines energy storage in the magnetization of a transformer with storage in a capacitor that is part of the resonant tank, which can be called a storage cycle. When the storage cycle is completed, the energy from the magnetization of the transformer and the energy stored in the resonant capacitor are released to the power converter output. The energy in the resonant capacitor, together with the leakage inductance of the transformer, forms a resonant release cycle.

[0004]

[0004] Ideally, at maximum output voltage and power, the release of magnetization energy and resonant capacitor energy would end simultaneously, and all of the stored energy would be delivered to the output. However, in real-world operation at maximum output voltage, magnetization ends prematurely and begins to circulate energy back to the primary side of the power converter. This is inefficient and, in some cases, can lead to output collapse at lighter loads.

[0005]

[0005] Typical control methods for AHB power converters are complex and include burst mode operation at lighter output loads, which further increases complexity and reduces performance. [Overview of the Initiative]

[0006]

[0006] Typical control methods for asymmetrical half-bridge (AHB) power converters, such as burst mode operation, are complex and result in known drawbacks in such designs. This disclosure provides examples of control circuits and methods for controlling the on-period of the high-side switch in an asymmetrical half-bridge power converter, which overcome the drawbacks of other control methods.

[0007]

[0007] The AHB converter includes a high-side switch coupled to the positive rail of the input voltage and a low-side switch coupled to the input return path of the AHB converter. Energy storage cycles in the AHB converter occur when the low-side switch is on, and energy release occurs when the low-side switch is off.

[0008]

[0008] The circuits and methods of the present disclosure control the active-off period (the period during which the high-side switch is on) to ensure that the discharge of magnetization energy and resonant capacitor energy in the AHB converter are completed simultaneously, and that all of the stored energy is delivered to the output in each switching cycle.

[0009]

[0009] For example, if the AHB converter is designed for a wide range of adjustable outputs, in lower output voltage situations, magnetization emission takes longer than the resonant emission period. In this case, the high-side switch-on period is made the same as the resonant period so that magnetization emission takes a sufficient period to deliver all of the stored energy to the output, but not to the resonant capacitor.

[0010]

[0010] The circuits and methods of the present disclosure may provide a number of parallel techniques for controlling the high-side switch-on period. One option described herein is to track the volt-seconds applied during the storage cycle so that the active emission off period is limited to the same volt-seconds. This is done by integrating a signal representing the primary side winding voltage to determine the high-side switch-on period.

[0011]

[0011] A second option for controlling the high-side switch-on period as described herein is to provide a high-side switch-on period that is proportional to the low-side switch-on period in its switching cycle. A third option for controlling the high-side switch-on period as described herein is to provide a maximum high-side switch-on period that can be programmed to ensure that the high-side switch-on period is less than or equal to half of the resonant period. Resonance is caused by the transformer leakage inductor and the resonant capacitor.

[0012]

[0012] Non-exclusive and non-exclusive embodiments of controlling the secondary switch to achieve zero-voltage switching are described below with reference to the figures, where similar reference numerals indicate the same parts throughout the various drawings unless otherwise specified. [Brief explanation of the drawing]

[0013] [Figure 1]

[0013] Figure 1 shows an exemplary asymmetric half-bridge (AHB) power converter comprising a primary control unit that implements an exemplary high-side on-period control circuit and method as taught in this disclosure. [Figure 2]

[0014] Figure 2 shows exemplary waveforms related to the operation of the AHB power converter 100 in Figure 1. [Figure 3]

[0015] Figure 3 shows a functional block diagram for an exemplary primary control unit that implements an exemplary high-side on-period control circuit as taught in this disclosure. [Figure 4]

[0016] Figure 4 shows a simplified diagram of an exemplary volt-second on-period block of an exemplary high-side control block as taught in this disclosure. [Figure 5]

[0017] Figure 5 shows a simplified diagram of an exemplary proportional on-period block of an exemplary high-side on-period control circuit as taught in this disclosure. [Figure 6]

[0018] Figure 6 shows a simplified diagram of an exemplary maximum high-side on-period block of an exemplary high-side on-period control circuit as taught in this disclosure. [Figure 7]

[0019] Figure 7 shows a more detailed schematic for an exemplary volt-second high-side-on-period block of an exemplary high-side-on-period control circuit as taught in this disclosure. [Figure 8]

[0020] Figure 8 shows a more detailed circuit diagram for an exemplary proportional high-side on-period block of an exemplary high-side on-period control circuit as taught in this disclosure. [Figure 9]

[0021] Figure 9 shows a more detailed schematic for an exemplary maximum high-side on-period block of an exemplary high-side on-period control circuit as taught in this disclosure. [Figure 10]

[0022] Figure 10 shows a flowchart illustrating an exemplary method for controlling the high-side switch-on period using volt-second calculations for use in an asymmetric half-bridge power converter as taught in this disclosure. [Figure 11]

[0023] Figure 11 shows a flowchart illustrating another exemplary method for controlling the on-period of the high-side switch in an AHB power converter as taught in this disclosure. [Figure 12A]

[0024] Figure 12A shows a voltage-second (volt-second) on-period circuit according to an embodiment of the present disclosure. [Figure 12B]

[0025] Figure 12B shows the waveform according to the embodiment shown in Figure 12A. [Figure 12C]

[0026] Figure 12C shows a buffer circuit according to an embodiment of the present disclosure. [Figure 12D]

[0027] Figure 12D shows a trigger circuit according to an embodiment of the present disclosure. [Figure 13A]

[0028] Figure 13A shows waveforms according to embodiments of the present disclosure. [Figure 13B]

[0029] Figure 13B shows a waveform according to another embodiment of the present disclosure. [Figure 14]

[0030] Figure 14 shows a trigger circuit according to another embodiment of the present disclosure. [Figure 15]

[0031] Figure 15 shows the waveform according to the embodiment shown in Figure 14. [Figure 16]

[0032] Figure 16 shows a trigger circuit according to another embodiment of Figure 14. [Figure 17]

[0033] Figure 17 shows the waveform according to the embodiment of Figure 16. [Modes for carrying out the invention]

[0014]

[0034] In the drawings, corresponding reference numerals indicate corresponding components. Those skilled in the art will understand that the elements in the drawings are drawn to be concise and clear, and not necessarily to a constant scale. For example, the dimensions of some elements in the drawings may be exaggerated compared to others to make the various embodiments of the teachings herein easier to understand. Furthermore, common but well-understood elements that are useful or necessary in commercially available embodiments are often not shown to avoid obscuring the drawings of these various embodiments that control secondary switches to achieve zero-voltage switching.

[0015]

[0035] Figure 1 shows an exemplary AHB power converter 100 as taught in this disclosure. The AHB power converter 100 has an input voltage source V IN Includes 101. Input voltage source V IN101 may come from a rectified AC input or a substantially DC input. Input capacitor C IN 102 is V IN It is connected between the positive terminal of 101 and the primary ground 107.

[0016]

[0036] The AHB power converter 100 includes a power transformer T1 having a primary winding 104, a secondary winding 105, and an auxiliary winding 106. Resonant capacitor C R 103 is the input capacitor C. IN It is coupled between 102 and the primary winding 104. The opposite end of the primary winding 104 is coupled to the half-bridge node HB120. During operation, the primary current I P 110 flows through the primary winding 104, as will be explained in more detail below.

[0017]

[0037] The AHB power converter 100 includes a primary control unit 150. In one example, the primary control unit 150 may be implemented as a circuit packaged in a single integrated circuit package. In other examples, the primary control unit 150 may be implemented as a circuit packaged in multiple packages. The primary control unit 150 includes a high-side switch 151 and a low-side switch 153. In some examples, either or both of the switches 151 and 153 may reside in the same integrated circuit package as the control circuit, or may be packaged separately from the control circuit.

[0018]

[0038] The high-side switch 151 and the low-side switch 153 are high-voltage transistor switches, which in one example may be transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), high-electron-mobility transistors (HEMTs), gallium nitride (GaN)-based transistors, or silicon carbide (SiC)-based transistors. In another example, the high-side switch and / or low-side switch may be a cascode switch comprising a normally-on first switch and a normally-off second switch coupled together in a cascode configuration. The first switch may generally be a GaN or SiC-based transistor, while the second switch may be a MOSFET, BJT, or IGBT.

[0019]

[0039] The primary control device 150 has an input voltage source V IN It includes a drain terminal D162 connected to 101 and a source terminal S163 connected to the primary ground 107. The drain of the high-side switch 151 is connected to the drain terminal D162, and the source of the low-side switch 153 is connected to the source terminal. The source of the high-side switch 151 and the drain of the low-side switch 153 are connected together to a half-bridge node HB120 which is connected as an input to the primary control unit 150.

[0020]

[0040] The primary control unit 150 includes a high-side driver 152 that generates appropriate output signals for driving the high-side switch 151 on and off. The primary control unit 150 further includes a low-side driver 154 that generates appropriate output signals for driving the low-side switch 153 on and off.

[0021]

[0041] As will be described in more detail below, the primary control device 150 further includes a primary control block 155 that generates control signals for instructing the high-side driver 152 and the low-side driver 154 to switch the high-side switch 151 and the low-side switch 153 on / off, respectively. The primary control device 150 includes a communication path 157 for communicating the control signal from the primary control block 155 to the high-side driver 152.

[0022]

[0042] The AHB power converter 100 includes a capacitor C LBias 172 for providing a bias power supply to the primary control block 155 and the low-side driver 154 of the primary control device 150. The AHB power converter 100 includes a capacitor C HBias 173 for providing a bias power supply to the high-side driver 152 of the primary control device 150. A diode 174 is coupled between the auxiliary winding 106 and the capacitor C HBIAS 173 to provide a current source for maintaining the voltage across the capacitor C HBIAS 173.

[0023]

[0043] The primary control block 155 includes an input AUX130 for receiving a signal representing the voltage across the auxiliary winding 106 through a resistor 175. The primary control block 155 further includes an input FL160 for receiving a signal from the secondary side of the AHB power converter 100 and for controlling the low-side switch 153, as will be described in more detail below.

[0024]

[0044] The primary control block 155 further includes an input I SNS 156 for receiving a signal representing the current through the low-side switch 153 and for controlling the low-side switch 153, as will be described in more detail below. The primary control block 155 further includes an input HMX161 for receiving the voltage across a resistor R HMX 171 for setting the maximum on-time for the high-side switch 151, as will be described in more detail below.

[0025]

[0045] The AHB power converter 100 has an output capacitor C coupled across the secondary winding 105. O It also includes 181. During operation, secondary current I S 180 flows through the secondary winding 105, and the output capacitor C O Output voltage V at 181 O Generates 182. Output current I O 183 is the output capacitor C. O It is supplied to load 185 which is coupled to 181 and secondary ground 190.

[0026]

[0046] The AHB power converter 100 includes a synchronous rectifier 186 comprising a transistor 188 and a diode 187. The diode 187 may be an intrinsic diode of transistor 188 or a separate component. In other examples, the AHB power converter may include only a diode instead of the synchronous rectifier 186.

[0027]

[0047] The AHB power converter 100 has an output power U O To detect 184, and U O Output detection signal U representing 184 OS It includes a detection circuit 191 configured to generate 192. O 184 is the output voltage V O 182. Output current I O 183, or a combination of both, may be indicated. The AHB power converter 100 further comprises a secondary control device 196. The secondary control device 196 receives an output detection signal U OS To receive 192, and the synchronous rectifier control signal U SR 134 and request signal U REQ It includes a secondary control block 193 configured to generate 194.

[0028]

[0048] The primary control unit 150 and the secondary control unit 196 can together be called the control system for the AHB power converter 100.

[0029]

[0049] request signal U REQ 194 is a signal representing the energy required by load 185. In one example, request signal U REQ 194 may represent a signal communicated to the primary control unit 150 to request that additional power be transmitted from the input to the output of the AHB power converter 100. In one example, the request signal U REQ 194 may be transmitted from the secondary control block 193 through a transmission mechanism that provides galvanic isolation between the input and output of the AHB power converter 100. In one example, request signal U REQ 194 can be transmitted through a FluxLink® component available from Power Integrations, Inc.

[0030]

[0050] The secondary control device 196 is based on the primary ground 107 and the request signal U REQ The system includes a receiving unit 195 configured to receive 194 and, in response, generate a signal that is coupled to the FL input 160 of the primary control unit 150. Output detection signal U OS 192, request signal U REQ Signals 194 and FL input 160 can all be called "feedback" signals because they all provide information about the output for use on the primary side of the AHB power converter.

[0031]

[0051] In one example, the secondary control unit 196 may be implemented in a single integrated circuit package. In another example, the components of the secondary control unit 196 may be implemented in multiple packages.

[0032]

[0052] Figure 2 shows the waveforms for signals within the AHB power converter 100 during the entire switching cycle of the converter and during a portion of subsequent cycles. As shown in Figure 2, the waveforms share an x-axis representing elapsed time.

[0033]

[0053] Waveform 210 shows the primary side current I of the AHB power converter 100 over time. P Waveform 220 represents the voltage at the half-bridge node HB120 of the AHB power converter 100 over time. Waveform 230 represents the detected voltage at the auxiliary winding 106 at the AUX input 130 of the primary control unit 150 over time. Waveform 240 represents the excitation current at the transformer T1 of the AHB power converter 100 over time.

[0034]

[0054] Waveforms 225 and 257 represent control signals generated by the primary control block 155, which controls the switching of the low-side switch 153 and the high-side switch 151 of the AHB power converter 100 over time.

[0035]

[0055] Tracing the waveform in Figure 2 from left to right, at time 211, the low-side switch control signal 225 transitions from low to high, indicating that the low-side switch 153 is switched on. In this example, the on-switching control signal 225 is shown as transitioning from low to high, but as those skilled in the art will understand, the logic of the control signal may be inverted. At time 211, the on-switching of the low-side switch 153 causes VHB220 and VAUX230 to go low, but the primary-side current I in the primary winding 104 P Currents 210 and 240 begin to rise. These currents continue to increase for the duration that the low-side switch 153 is on.

[0036]

[0056] At time point 212, the low-side switch control signal 225 transitions from high to low, indicating that the low-side switch 153 is switched off. In response to the switching off of the low-side switch 153, at time point 212, VAUX 230 and VHB 220 begin to rise. Furthermore, at time point 212, the excitation current 240 and the primary side current I P The waveform at 210 begins to decrease.

[0037]

[0057] At time point 213, the high-side switch control signal 257 transitions from low to high, indicating that the high-side switch 151 is switched on. In this example, the on-switch control signal 257 is shown as transitioning from low to high, but as those skilled in the art will understand, the logic of the control signals may be inverted.

[0038]

[0058] A dead time is maintained between the time 212 when the low-side switch 153 switches to the off position and the time 213 when the high-side switch 151 switches to the on position. This dead time is maintained to ensure that there is no overlap in the conduction of the low-side switch 153 and the high-side switch 151, preventing the possibility of cross-conduction. In one example, the dead time between the off position of the low-side switch 153 and the on position of the high-side switch 151 may be a fixed period. In other examples, the dead time may be adaptive and depend on the operating conditions within the AHB power converter 100.

[0039]

[0059] At time point 213, switching the high-side switch 151 on results in the voltages of VHB220 and VAUX230 being clamped to their maximum values. In one example, the maximum value of VHB220 may be in the range of 100 volts to 420 volts. In one example, the maximum value of VAUX230 may be in the range of 5 volts to 70 volts.

[0040]

[0060] At time point 214, the high-side switch control signal 257 transitions from high to low, indicating that the high-side switch 151 is switched off. In the example shown in Figure 2, at time point 214, the waveforms for the excitation current 240 and the primary-side current 210 are close to zero or zero, indicating that energy delivery for that switching cycle is complete.

[0041]

[0061] As will be explained in more detail below, the on-period of the high-side switch 151 (the period between time points 213 and 214 in the example of Figure 2) is controlled by the primary control unit 150 in such a way that the high-side switch 151 is kept on for a sufficiently long time so that the emission of magnetization is sufficient to deliver substantially all of the stored energy to the output of the AHB power converter.

[0042]

[0062] Between time points 214 and 215, the voltage waveforms VHB220 and VAUX230 decrease and then resonate in the form of a sine wave at a frequency and magnitude determined by the Coss of the low-side switch 153 and the high-side switch 151 and the excitation inductance of the primary winding 104 of transformer T1. Similarly, the excitation current waveform 240 and the primary current waveform 210 also change in the form of a sine wave near zero. Due to relaxation ringing, a resonant current exists through the excitation inductance of the primary winding 104 of transformer T1.

[0043]

[0063] At time point 215, the low-side switch control 225 transitions again from low to high, and the next switching cycle, which is repeated using the same method as described above, begins.

[0044]

[0064] Figure 3 shows an exemplary primary control unit 350 corresponding to the primary control unit 150 in the example shown in Figure 1. As shown in Figure 3, the exemplary primary control unit 350 is implemented in a single integrated circuit package with several terminals configured to be coupled to the rest of the components of the AHB power converter. In other examples, the components of the primary control unit 350 may be implemented in multiple packages.

[0045]

[0065] The primary control unit 350 incorporates a high-side switch 351 and its associated high-side driver 352, as well as a low-side switch 353 and its associated low-side driver 354. In some examples, the high-side switch 351 and / or the low-side switch 153 may be packaged in the same integrated circuit package as the control circuit, and in other examples, they may be packaged separately. The primary control unit 350 has a drain terminal D(HS)362 for coupling the drain of the high-side switch 351 to the input voltage. The primary control unit further has a source terminal S(LS)363 for coupling the source of the low-side switch 353 to ground reference. The primary control unit 350 has a terminal HB320 for coupling the source of the high-side switch 351 and the drain of the low-side switch 353 to the half-bridge node of the AHB power converter.

[0046]

[0066] The primary control unit 350 has a terminal FL 360 configured to receive a signal from the secondary side of the AHB power converter in order to control the switching of the low-side switch 353. In one example, the signal received at terminal FL may be a request signal representing a request for further power to be transmitted from the input to the output of the AHB power converter 100.

[0047]

[0067] The primary control unit 350 has a terminal AUX330 configured to receive a signal representing the voltage across the auxiliary winding of the AHB power converter. The primary control unit 350 further has a terminal HMX361 configured to receive a signal for programming the maximum on-period of the high-side switch 351.

[0048]

[0068] Although not shown, as those skilled in the art will understand, the primary control unit 350 further has an input terminal for receiving an operating bias source for the low-side component and an input terminal for receiving an operating bias source for the high-side component. Other terminals for implementing other features and functions may be realized in various examples of the primary control unit 350 consistent with the teachings of this disclosure.

[0049]

[0069] The primary control device 350 includes a primary control block 355 corresponding to the primary control block 155 in the example shown in Figure 1. The primary control block 355 comprises a DCM detection block 321, a low-side control block 322, and a high-side control block 365.

[0050]

[0070] The DCM detection block 321 receives a signal (V) representing the voltage at the half-bridge node HB320 of the AHB power converter. HB The DCM detection block 321 is configured to receive ). The DCM detection block 321 is configured to detect discontinuous conduction operating modes in the AHB power converter. The DCM detection block 321 is further configured to introduce a dead time period between the switching of the high-side switch and the low-side switch to ensure that both switches are never turned on at the same time in order to prevent the possibility of cross-conduction in the AHB power converter.

[0051]

[0071] The low-side control block 322 is configured to receive a signal from the secondary side of the AHB power converter through terminal FL360. In one example, the signal at terminal FL may consist of a pulse train arriving at a variable frequency, with each received pulse indicating that a switching cycle must be initiated. In other examples, the signal may take other forms to represent the status of the power converter's output load.

[0052]

[0072] The low-side control block 322 receives the signal at terminal FL360 and the output of the DCM detection block 321, and generates a low-side switch control signal 325a to control the operation of the low-side switch 353. The low-side switch control signal 325a is input to the low-side driver 354, which in turn generates an appropriate drive signal at the gate of the low-side switch 353 to control the on and off switching of the low-side switch 353.

[0053]

[0073] In some examples, the low-side control block 322 represents the current passing through the low-side switch 353. SNS It is configured to receive signal 356. In some examples, the low-side control block 322 is I SNS In response to signal 356, when the current through the low-side switch 353 reaches a current threshold, the low-side switch 353 is switched off. As will be understood by those skilled in the art, other techniques for controlling the on-period of the low-side switch 353 can be implemented in accordance with the teachings of this disclosure.

[0054]

[0074] The low-side control block 322 further outputs a copy 325b of the low-side switch control signal as input to the high-side control block 365. As will be understood by those skilled in the art, the control signal 325b may be routed to multiple destinations and may be the same signal as 325a. In the disclosed example, the low-side switch control signal 325b is a logic level voltage that is in a first state when the low-side switch 353 is on (conducting current) and in a second state when the low-side switch 353 is off (not conducting any substantial current). In other examples, the low-side switch control signal 325b may represent the operation of the low-side switch 353 in other analog, logical, or digital forms.

[0055]

[0075] The exemplary high-side control block 365 implements three functional blocks for controlling the on-period of the high-side switch 351. In other examples, not all three functional blocks need to be implemented; they may be implemented individually or in various combinations consistent with the teachings of this disclosure.

[0056]

[0076] The volt-second on-period block 335 is configured to receive the low-side switch control signal 325b and a signal at terminal AUX 330 representing the voltage across the auxiliary winding of the AHB power converter. As will be described in more detail below, the volt-second on-period block 335 uses the signal from terminal AUX 330 to generate an output signal for controlling the high-side switch-on period, thereby achieving balanced volt-second operation in the AHB power converter.

[0057]

[0077] The proportional on-period block 340 is configured to receive the low-side switch control signal 325b and to generate an output signal for controlling the high-side switch on-period in proportion to the on-period of the low-side switch 353 in each switching cycle, as will be described in more detail below.

[0058]

[0078] The maximum on-period block 345 is configured to receive the low-side switch control signal 325b and a signal at terminal HMX361, which is an input signal that enables the maximum high-side switch-on period to be programmed, as will be described in more detail below.

[0059]

[0079] In the exemplary high-side control block 365, the outputs of the volt-second on-period block 335 and the proportional on-period block 340 are coupled to an OR gate 327. The output of the OR gate 327 is coupled to an AND gate 328 along with the output of the maximum on-period block 345. In the example in Figure 3, the outputs of the volt-second on-period block 335, the proportional on-period block 340, and the maximum on-period block 345 transition to a logical high state to initiate the switching on of the high-side switch 351. As will be described in more detail below, the output of each block transitions to a logical low state to indicate that the high-side switch 351 must be switched off.

[0060]

[0080] Although not shown in Figure 3, a circuit may be incorporated into the primary control block 355 to achieve a dead time between the off-switching of the low-side switch 353 and the on-switching of the high-side switch 351, as described in relation to Figure 2.

[0061]

[0081] In the exemplary high-side control block 365, both the outputs of the volt-second on-period block 335 and the proportional on-period block 340 must transition to a low state so that the output of the OR gate 327 transitions to low, instructing the high-side switch 351 to switch off. Thus, the block that indicates a longer on-period for the high-side switch 351, whichever block it is, controls the duration of the high-side switch on-period in a given cycle.

[0062]

[0082] Furthermore, if either the output of the maximum on-period block 345 or the OR gate 327 transitions to low, the output of the AND gate 328 transitions to low, instructing the high-side switch 351 to switch off. In other words, if the output of the maximum on-period block 345 indicates that the maximum on-period has expired, the high-side switch 351 is instructed to switch off, regardless of the state of the outputs of the volt-second on-period block 335 and the proportional on-period block 340.

[0063]

[0083] However, while the exemplary high-side control block 365 implements a specific logic unit for combining the outputs of its individual subblocks, other exemplary combinations consistent with the teachings of this disclosure are also possible, as will be understood by those skilled in the art. Combining the maximum on-period, proportional on-period, and volt-second on-period may, in some examples, provide more robust operation across a wide range of possible operating conditions for the AHB power converter.

[0064]

[0084] The output of the AND gate 328 is input to link 329 to the high-side block. This block provides the necessary level shift of the high-side control signal so that it is communicated through the communication path 357. The high-side control signal controls the on and off switching of the high-side switch 351. Since the high-side switch 351 is referenced to a different voltage range than the low-side switch 353 (i.e., coupled between the high-voltage input and the half-bridge node of the AHB power converter), the control signal from the primary control unit to the high-side switch may be level-shifted accordingly.

[0065]

[0085] Link 329 to the high-side block further communicates with the DCM detection block 321 to ensure an appropriate dead time between the switching of the low-side switch 353 and the switching of the high-side switch 351. After a balanced state of volts*seconds is reached in each switching cycle, DCM detection begins. After DCM detection is complete, the low side is allowed to switch on.

[0066]

[0086] The primary control unit 350 includes an HS receiver and driver logic block 358 configured to receive a high-side control signal through a communication path 357. The HS receiver and driver logic block 358 receives the high-side control signal and, in response, generates a signal to the high-side driver 352 to control the operation of the high-side switch 351. Although not shown, the HS receiver and driver logic block 358 may incorporate other inputs to realize further features and functions. For example, the HS receiver and driver logic block 358 may be configured to receive a signal for detecting temperature and / or high-side bias voltage and, in response, realize an abnormality management mode. As will be understood by those skilled in the art, other exemplary features and functions can be realized by the HS receiver and driver logic block 358 in accordance with the teachings of this disclosure.

[0067]

[0087] Figure 4 shows a simplified circuit diagram for an exemplary volt-second on-period block 435 corresponding to the volt-second on-period block 335 in the exemplary primary control device 350 of Figure 3. The volt-second on-period block 435 controls the charge current I C The system comprises a first current source 401, a first switch 403, and a capacitor 405 for providing the following. The first current source 401, the first switch 403, and the capacitor 405 together constitute a first integrator 431.

[0068]

[0088] The first current source 401 receives a signal V representing the voltage in the primary winding, such as the auxiliary winding 106 shown in Figure 1. LSON It is configured to receive 430a. In one example, V LSON This can be derived from the signal at AUX input 130 shown in Figure 1. V LSON 430a represents the voltage in the primary winding when the low-side switch is on. Charge current I C V LSON It is proportional to 430a.

[0069]

[0089] The volt-second ON period block 435 is the discharge current I DIS The system further comprises a second current source 402 and a second switch 404 for providing the same. The second current source 402, the second switch 404, and the capacitor 405 together constitute a second integrator 432.

[0070]

[0090] The second current source 402 is a signal V representing the voltage in the primary winding, such as the auxiliary winding 106 shown in Figure 1. HSON It is configured to receive 430b. In one example, V HSON This can be derived from the signal at AUX input 130 shown in Figure 1. V HSON 430b represents the voltage in the primary winding when the high-side switch is on. Discharge current I DIS V HSON It is proportional to 430b.

[0071]

[0091] During the volt-second on-period block 435, the voltage across capacitor 405 is referenced to the voltage V REF1 The system further comprises a comparator 406 configured to compare with 411. While the example in Figure 4 shows comparator 406 as a voltage comparator, other examples of analog and / or digital comparators may be used in accordance with the teachings of this disclosure, as will be understood by those skilled in the art. Capacitor 405 is coupled to the non-inverting input of comparator 406, with a reference voltage V REF1 411 is coupled to the inverting input of comparator 406. Reference voltage V REF1 411 is a voltage slightly off from ground, and therefore, when capacitor 405 is reset, the output of comparator 406 becomes logic 0. REF1 The deviation at 411 helps to provide stability to the operation of comparator 405.

[0072]

[0092] The volt-second on-period block 435 further comprises a third switch 409 configured to reset the voltage across capacitor 405 in each switching cycle. The volt-second on-period block 435 further comprises an inverter 407 and a reset circuit 408 coupled between the output of comparator 406 and the third switch 409. The reset circuit 408 is configured to realize a reset pulse between the change in the output state of comparator 406 and the switching of the third switch 409 in order to reset capacitor 405.

[0073]

[0093] The output of comparator 406 is further coupled to one input of AND gate 412. Volt-second on-period block 435 further includes an input for receiving low-side (LS) switch control signal 425b, which represents the on and off switching timing of the low-side switch of the AHB power converter, such as the low-side switch 353 of the exemplary primary control unit 350 in Figure 3. The LS switch control signal 425b is coupled to control the first switch 403 so that the first switch 403 is on when the low-side switch is on, and off when the low-side switch is off. The LS switch control signal 425b is further coupled to inverter 413. The output of inverter 413 is coupled to the second input of AND gate 412. The output of AND gate 412 is the HS switch-on period signal, which is coupled to control the second switch 404 and is further coupled as the output of volt-second on-period block 435.

[0074]

[0094] Waveform 420 shows the voltage across capacitor 405 during an exemplary switching cycle, as will be described in detail below.

[0075]

[0095] In an exemplary switching cycle of an AHB power converter, the volt-second on-period block 435 may operate as follows: At the start of the switching cycle, the LS switch control signal 425b changes state (for example, from low to high, as shown in the example) to indicate that the low-side switch has been switched on. When the LS switch control signal 425b is high, the output of the AND gate 412 is low.

[0076]

[0096] The first switch 403 is configured to switch on in response to the LS switch control signal 425b, causing the capacitor 405 to begin charging. The rate at which the capacitor 405 is charged is V LSONIt depends on the value of 430a. As shown in waveform 420, the voltage across capacitor 405 rises during the ON period of the low-side switch. The voltage across capacitor 405 is equal to the reference voltage V REF1 When the value is higher than 411, the output of comparator 406 becomes high.

[0077]

[0097] At the end of the low-side switch-on period, the LS switch control signal 425b changes state (for example, from high to low as shown in the example), and in response, the first switch 403 is configured to switch off, which stops the charging of capacitor 405. After the LS switch control signal 425b transitions to indicate the end of the low-side switch-on period, the output of the AND gate 412 transitions to high to indicate the start of the high-side switch-on period. The output of the AND gate 412 becoming high switches the second switch 404 on. As already explained in the description of Figure 2, a dead time may occur between the end of the low-side switch-on period and the start of the high-side switch-on period.

[0078]

[0098] When the second switch 404 is turned on, the second current source 402 discharges the capacitor 405. The rate at which the capacitor 405 discharges is V HSON It depends on the value of 430a. As shown in waveform 420, the voltage across capacitor 405 drops during the on period of the high-side switch. The voltage across capacitor 405 is V REF1 When the voltage drops below the threshold set by 411, the output of comparator 406 changes state (for example, from high to low as shown in the example), and therefore the output of AND gate 412 goes further low. The output of AND gate 412 is output from volt-second on-period block 435 to control the off-switching of the high-side switch.

[0079]

[0099] When the output of the AND gate 412 changes state, the second switch 404 is switched off. Furthermore, when the output of the comparator 406 changes state (for example, from high to low in the shown example), after a reset implemented by the reset circuit 408, the third switch 409 is switched on, resetting the voltage across the capacitor 405 and preparing the volt-second on-period block 435 for the next switching cycle.

[0080]

[0100] Figure 4 shows a specific example of the logic section for controlling the first integrator 431 and the second integrator 432, and for input and output signals, but other configurations consistent with the teachings of this disclosure are also possible, as will be understood by those skilled in the art. Furthermore, Figure 4 shows a specific exemplary circuit structure for integrating the value of an input signal over time, but other analog and / or digital structures consistent with the teachings of this disclosure are also possible, as will be understood by those skilled in the art.

[0081]

[0101] Figure 5 shows a simplified circuit diagram for an exemplary proportional on-period block 540, which in one example may correspond to block 340 in the exemplary primary control unit 350 of Figure 3. The exemplary proportional on-period block 540 is substantially identical to the volt-second on-period block 435 of Figure 4, and operates in substantially the same manner, although there are at least the differences described below.

[0082]

[0102] In the proportional on-period block 540, the input to the first current source 501 is the first reference voltage V REF2 The current is 530A, and the input to the second current source 502 is the second reference voltage K*V REF2 530b. Therefore, instead of responding to the detected auxiliary winding voltage, the proportional on-period block 540 is configured to control the on-period of the high-side switch 151 in proportion to the on-period of the low-side switch 153 based on the scaling factor K.

[0083]

[0103] In proportional on-period block 540, the first integrator 531 controls V during the on-period of the low-side switch.REF2 The second integrator 532 is configured to integrate the value of 530a. The second integrator 532 is configured to integrate k*V during the ON period of the high-side switch 151. REF2 Integrate the value of 530b. When these integrated values ​​are substantially equal to each other, it indicates that the output of comparator 506 has changed state and the high-side switch must be switched off.

[0084]

[0104] In detail, the operation of the proportional on-period block 540 is similar to that of the volt-second on-period block 435, as already described with reference to Figure 4. In one example, the value of K may be equal to 1, and thus the on-period of the high-side switch is controlled to be substantially the same as the on-period of the low-side switch. In other examples, other values ​​of K are also possible.

[0085]

[0105] Ideally, the value of K is equal to 1. Due to the possibility of mismatch in the charging and discharging circuits, in some cases, the value of K may be 0.95, 1.05, or some other value close to 1 to compensate for noise or mismatch in the circuit implementation. In some cases, the value of K may be a trimmable or programmable parameter.

[0086]

[0106] Figure 6 shows a simplified circuit diagram for an exemplary maximum on-period block 645, which in one example may correspond to block 345 in the exemplary primary control device 350 of Figure 3. The maximum on-period block 645 controls the reference current I REF The system includes a reference current source 601, a capacitor 605, and a comparator 606 to provide a reference voltage V. The reference current source 601, capacitor 605, and comparator 606 together constitute a timer. The maximum on-period block 645 receives the reference voltage V input to comparator 606. REF4 Further includes 611. Reference voltage V REF4 611 is coupled to the non-inverting input of comparator 606, and capacitor 605 is coupled to the inverting input of comparator 606.

[0087]

[0107] The maximum on-period block 645 is an external resistor R for programming the duration of the maximum high-side switch-on period. HMX It further comprises terminal HMX661 configured to be coupled to 671. Terminal HMX661 may correspond to terminal HMX161, and resistor R HMX 671 is the resistor R in the example shown in Figure 1. HMX It can correspond to 171.

[0088]

[0108] The maximum on-period block 645 further includes a switch 609 for resetting the voltage across capacitor 605 during each switching cycle. The maximum on-period block 645 further includes an input for receiving an LS switch control signal 625b representing the on and off timing of low-side switches of the AHB power converter, such as the low-side switch 353 of the exemplary primary control unit 350 in Figure 3. The LS switch control signal 625b is further an example of the LS switch control signal 325b described in relation to Figure 3. The LS switch control signal 625b is coupled to control switch 609 so that it is on when low-side switch 153 is on, and so that it is off when low-side switch 153 is off.

[0089]

[0109] Inverter 613 is coupled to receive the LS switch control signal, and the output of inverter 613 is coupled to one input of AND gate 612. The output of comparator 606 is coupled to the second input of AND gate 612, and the output of AND gate 612 is coupled to provide a high-side switch maximum on-period signal as the output of maximum on-period block 645.

[0090]

[0110] In an exemplary switching cycle of the AHB power converter, the maximum on-period block 645 may operate as follows: At the start of the switching cycle, the LS switch control signal 625b changes state (for example, from low to high, as shown in the example) to indicate that the low-side switch 151 has been switched on. In response to the LS switch control signal 625b, switch 609 is switched on, resetting the voltage across capacitor 605 to low and resetting the output of comparator 606 to high. In the example shown, the voltage across capacitor 605 is reset to primary ground. When the LS switch control signal 625b is high, the output of inverter 613 is low and the output of AND gate 612 is also low.

[0091]

[0111] At the end of the low-side switch-on period, the LS switch control signal 625b changes state (from high to low, for example, as shown in the example) to indicate that the low-side switch 153 has been switched off. In response to the LS switch control signal 625b, switch 609 is switched off, allowing the current source 601 to charge the capacitor 605. When the LS switch control signal 625b is in the low state, the output of the inverter 613 is high. The output of the AND gate 612 transitions to the high state, indicating the start of the maximum high-side switch-on period.

[0092]

[0112] As shown in waveform 620, the voltage across capacitor 605 increases. REF4 When 611 is crossed, the output of comparator 606 goes low, and therefore the output of AND gate 612 goes even lower, indicating the expiration of the maximum on-period for the high-side switch.

[0093]

[0113] In the example disclosed in Figure 6, I REF and V REF4 611 has a fixed value, and therefore capacitor 605 is the reference voltage V REF4 The time required to charge up to 611 is determined by the external resistor R connected to terminal HMX661. HMXIt depends on the value of 671. With this method, the maximum on period for the high-side switch is determined by resistor R. HMX It can be programmed by selecting one of 671 values.

[0094]

[0114] Figure 6 shows a specific example of the circuit structure and logic section for controlling the timer and for input and output signals, but other analog and / or digital structures and configurations consistent with the teachings of this disclosure are also possible, as will be understood by those skilled in the art.

[0095]

[0115] Figure 7 shows a circuit diagram for a volt-second on-period block 735 that may correspond in one example to the volt-second on-period block 335 of the primary control device 350 in Figure 3, and / or the volt-second on-period block 435 shown in Figure 4.

[0096]

[0116] The volt-second on-period block 735 comprises a first reference voltage 700, a first transistor 701a, a second transistor 701b, and a first resistor 741. The first transistor 701a, the second transistor 701b, and the first resistor 741 together constitute a first current source for charging the first capacitor 705. The volt-second on-period block 735 further comprises a third transistor 702a, a fourth transistor 702b, a second resistor 742, and a ground reference 707. The third transistor 702a, the fourth transistor 702b, and the second resistor 742 together constitute a second current source for discharging the first capacitor 705. The volt-second on-period block 735 further comprises a fifth transistor 703 for controlling the charging of the first capacitor 705, and a sixth transistor 704 for controlling the discharging of the first capacitor 705.

[0097]

[0117] The first transistor 701a, the second transistor 701b, the first resistor 741, the fifth transistor 703, and the first capacitor 705 together constitute the first integrator 731. The third transistor 702a, the fourth transistor 702b, the second resistor 742, the sixth transistor 704, and the first capacitor 705 together constitute the second integrator 732. The fifth transistor 703 and the second resistor 742 are coupled to terminal AUX 730, which is configured to receive a signal representing the voltage in the primary winding of the AHB power converter, such as the auxiliary winding 106 shown as an example in Figure 1.

[0098]

[0118] The volt-second on-period block 735 further comprises a comparator 706 configured to compare the voltage across the first capacitor 705 with a second reference voltage 711. While the example in Figure 7 shows comparator 706 as a voltage comparator, other examples of analog and / or digital comparators consistent with the teachings of this disclosure may be used, as will be understood by those skilled in the art.

[0099]

[0119] The volt-second on-period block 735 further comprises a seventh transistor 709 configured to reset the voltage across the first capacitor 705 in each switching cycle. The volt-second on-period block 735 further comprises a first inverter 714 and a second capacitor 708b coupled between the output 706 of the comparator and the seventh transistor 709. The volt-second on-period block 725 further comprises a third resistor 708a coupled to the seventh transistor 709. The resistor 708a and capacitor 708b together constitute a reset circuit configured to realize a reset pulse between the change in the output state of the comparator 706 and the switching of the seventh transistor 709 in order to reset the first capacitor 705.

[0100]

[0120] The volt-second on-period block 735 further comprises an AND gate 712 configured to provide an output for controlling the on-period of high-side switches of an AHB power converter, such as the high-side switch 351 in Figure 3 and the high-side switch 151 in Figure 1, as taught in this disclosure. The first input of the AND gate 712 is coupled to the output of the comparator 706.

[0101]

[0121] The volt-second on-period block 735 further includes an input for receiving an LS switch control signal 725b representing the on and off timing of the low-side switches of the AHB power converter, such as the low-side switch 353 of the exemplary primary control unit 350 in Figure 3 and the low-side switch 153 of the primary control unit 150 in Figure 1. The LS switch control signal 725b is coupled to control the fifth transistor 703 so that it is on when the low-side switch is on and off when the low-side switch is off. The LS switch control signal 725b is further coupled to a second inverter 713, the output of which is coupled to the second input of an AND gate 712. The output of the AND gate 712 is coupled as the output of the volt-second on-period block 735 and further coupled to the input of a sixth transistor 704 to control the operation of a second integrator. The output of the AND gate 712 is the HS switch-on period signal.

[0102]

[0122] Block 720 shows an example of the relative timing between the LS switch control signal 725b and the output of the AND gate 712.

[0103]

[0123] In an exemplary switching cycle of the AHB power converter, the volt-second on-period block 735 may operate as follows: At the start of the switching cycle, the LS switch control signal 725b changes state (from low to high, for example, as shown in the example) to indicate that the low-side switch has been switched on. When the LS switch control signal 725b is high, the output of the AND gate 712 is low. The fifth transistor 703 is configured to switch on in response to the LS switch control signal 725b, and is configured to cause the first capacitor 705 to begin charging. The rate at which the first capacitor 705 is charged depends on the input value at terminal AUX 730. During the on-period of the low-side switch, the voltage across the first capacitor 705 rises from a low value to a higher value. The voltage across the first capacitor 705 is higher than the second reference voltage 711, and the output of the comparator 706 is high.

[0104]

[0124] At the end of the low-side switch-on period, the LS switch control signal 725b changes state (for example, from high to low as shown in the example), and the fifth transistor 703 is configured to switch off in response, which stops the charging of the first capacitor 705. After the LS switch control signal 725b transitions, indicating the end of the low-side switch-on period, the output of the AND gate 712 transitions to high, indicating the start of the high-side switch-on period. The output of the AND gate 712 becoming high switches the sixth transistor 704 on. As already explained in the description of Figure 2, a dead time may occur between the end of the low-side switch-on period and the start of the high-side switch-on period.

[0105]

[0125] When the sixth transistor 704 is switched on, the voltage across the first capacitor 705 begins to discharge. The rate at which the first capacitor 705 discharges depends on the value of the signal at terminal AUX 730. During the on period of the high-side switch, the voltage across the first capacitor 705 decreases. When the voltage across the first capacitor 705 drops below the threshold set by the second reference voltage 711, the output of the comparator 706 changes state (for example, from high to low as shown in the example), and therefore the output of the AND gate 712 also goes low. The output of the AND gate 712 is output from the volt-second on-period block 735 to control the off switching of the high-side switch.

[0106]

[0126] When the output of the AND gate 712 changes state, the sixth transistor 704 is switched off. Furthermore, when the output of the comparator 706 changes state (for example, from high to low in the shown example), after a reset circuit implemented by the third resistor 708a and the second capacitor 708b, the seventh transistor 709 is switched on, resetting the voltage across the first capacitor 705 and preparing the volt-second on-period block 735 for the next switching cycle.

[0107]

[0127] Figure 7 shows a specific example of a logic unit for controlling the first integrator 731 and the second integrator 732, and for input and output signals, but other configurations consistent with the teachings of this disclosure are also possible, as will be understood by those skilled in the art. Furthermore, Figure 7 shows a specific exemplary circuit structure for integrating the value of an input signal over time, but other analog and / or digital structures consistent with the teachings of this disclosure are also possible, as will be understood by those skilled in the art.

[0108]

[0128] Figure 8 shows a schematic diagram for an exemplary proportional on-period block 840, which in one example may correspond to block 340 in the exemplary primary control unit 350 of Figure 3 and / or the proportional on-period block 540 shown in Figure 5. The exemplary proportional on-period block 840 is substantially identical to the volt-second on-period block 735 of Figure 7 and operates in substantially the same manner, with at least one difference as described below.

[0109]

[0129] In the proportional on-period block 840, the fifth transistor 803 is coupled to ground reference 807 rather than to an external terminal. Furthermore, the second resistor 842 is coupled to voltage reference 800 rather than to an external terminal. Thus, rather than responding to a detected auxiliary winding voltage, the proportional on-period block is configured to control the high-side switch on-period in proportion to the low-side switch on-period, based on a scaling factor K. The scaling factor K is determined based on the ratio of the values ​​of the first resistor 841 and the second resistor 842.

[0110]

[0130] In the proportional on-period block 840, the first integrator 831 integrates the value of the voltage reference 800 divided by the value of the first resistor 841 during the on-period of the low-side switch. The second integrator 832 integrates the value of the voltage reference 800 divided by the value of the second resistor 842 during the on-period of the high-side switch. When these integrated values ​​are equal, the output of comparator 806 changes state, indicating that the high-side switch must be switched off.

[0111]

[0131] In detail, the operation of the proportional on-period block 840 is similar to the operation of the volt-second on-period block 735, which has already been described with reference to Figure 7, and the reference numerals are numbered accordingly.

[0112]

[0132] In one example, the value of K may be equal to 1, thus controlling the on-duration of the high-side switch to be substantially the same as the on-duration of the low-side switch. In other examples, other values ​​of K are also possible. Ideally, the value of K is equal to 1. Due to the possibility of mismatch in the charging and discharging circuits, in some examples, the value of K may be 0.95, 1.05, or some other value close to 1 to compensate for noise or mismatch in the circuit implementation. In some examples, the value of K may be a trimmable or programmable parameter.

[0113]

[0133] Figure 9 shows a schematic diagram for an exemplary maximum on-period block 945, which in one example may correspond to block 345 and / or maximum on-period block 645 in the exemplary primary control unit 350 of Figure 3.

[0114]

[0134] The maximum on-period block 945 comprises a first reference voltage source 900, a first transistor 901a, a second transistor 901b, a capacitor 905, and a comparator 906. The first reference voltage source 900, the first transistor 901a, the second transistor 901b, the capacitor 905, and the comparator 906 together constitute a timer. The maximum on-period block 945 further comprises a second reference voltage 911 which is input to the comparator 906. The second reference voltage 911 is coupled to the non-inverting input of the comparator 906, and the capacitor 905 is coupled to the inverting input of the comparator 906.

[0115]

[0135] The maximum on-period block 945 is an external resistor R for programming the duration of the maximum high-side switch-on period. HMX It further comprises terminal HMX961 configured to be coupled to 971. Terminal HMX961 may correspond to terminal HMX161, and resistor R HMX 971 is the resistor R in the example shown in Figure 1. HMX This corresponds to 171. The maximum on-period block 945 further includes a switch 909 for resetting the voltage in capacitor 905 during each switching cycle.

[0116]

[0136] The maximum on-period block 945 further includes an input for receiving an LS switch control signal 925b representing the on-and-off timing of the low-side switches of the AHB power converter, such as the low-side switch 353 of the exemplary primary control unit 350 in Figure 3 and the low-side switch 153 of the primary control unit 150 in Figure 1. The LS switch control signal 925b is coupled to control switch 909 so that it is on when the low-side switch is on and off when the low-side switch is off. The LS switch control signal 925b is coupled to an inverter 913, and the output of the inverter 913 is coupled to one input of an AND gate 912. The output of a comparator 906 is coupled to a second input of an AND gate 912, and the output of an AND gate 912 is coupled to provide a high-side switch maximum on-period signal as an output to the maximum on-period block 945.

[0117]

[0137] In an exemplary switching cycle of the AHB power converter, the maximum on-period block 945 may operate as follows: At the start of the switching cycle, the LS switch control signal 925b changes state (for example, from low to high, as shown in the example) to indicate that the low-side switch has been switched on. The LS switch control signal 925b switches switch 909 on, resetting the voltage across capacitor 905 to a low state. The low state is less than the voltage reference 911, and the output of comparator 906 becomes high. The output of inverter 913 becomes low, and therefore the output of AND gate 912 also becomes low.

[0118]

[0138] At the end of the low-side switch-on period, the LS switch control signal 925b changes state (from high to low, as shown in the example) to indicate that the low-side switch has been switched off. The LS switch control signal 925b going low allows switch 909 to switch off, enabling capacitor 905 to begin charging. The voltage across capacitor 905 is less than the second reference voltage 911, and the output of comparator 606 is high. The output of inverter 913 goes high, and therefore the output of AND gate 912 also transitions to a high state, indicating the start of the maximum high-side switch-on period.

[0119]

[0139] The voltage across capacitor 905 rises from a low level to a higher level. When the voltage across capacitor 905 reaches the second reference voltage 911, the output of comparator 906 goes low, and therefore the output of AND gate 912 also goes low, indicating the end of the maximum on-period for the high-side switch.

[0120]

[0140] In the example disclosed in Figure 9, the first reference voltage 900 and the second reference voltage 911 have fixed values, and therefore the rate at which the capacitor 905 is charged, and the time it takes for the capacitor 905 to be charged to the second reference voltage 911, are determined by an external resistor R coupled to terminal HMX961. HMX It depends on the value of 971. With this method, the maximum on period for the high-side switch is determined by resistor R. HMX It can be programmed by selecting a value of 971.

[0121]

[0141] Figure 9 shows a specific example of the circuit structure and logic section for controlling the operation of the maximum on-period block 945 and for input and output signals, but other analog and / or digital structures and configurations consistent with the teachings of this disclosure are also possible, as will be understood by those skilled in the art.

[0122]

[0142] Figure 10 shows a series of steps in an exemplary method 1000 for controlling the on-period of the high-side switch of an AHB power converter using volt-second calculations.

[0123]

[0143] In step 1010, the low-side switch of the AHB power converter, which is the low-side switch 153 shown in FIG. 1 for example, is switched on, and the voltage (VAUX) applied to the primary-side auxiliary winding such as the winding 106 shown in FIG. 1 for example is measured. In step 1020, the measured VAUX is integrated during the low-side switch-on period, and the resulting first integrated value (V LSON *T LSON ) is stored. In step 1030, the low-side switch is switched off, allowing the dead-time period to elapse.

[0124]

[0144] In step 1040, the high-side switch of the AHB power converter, which is the high-side switch 151 shown in FIG. 1 for example, is switched on, and the voltage (VAUX) of the auxiliary winding is measured again. In step 1050, the measured VAUX is integrated during the high-side switch-on period, and the second integrated value (V HSON *T HSON ) is calculated.

[0125]

[0145] In step 1060, (V HSON *T HSON ) is compared with (V LSON [[ID= / / ]] LSON ) and the result of the comparison is evaluated. If (V LSON *T LSON ) is less than or equal to (V HSON *T HSON ), the method returns to step 1050 and the integration of VAUX continues. If (V{ LSON *T LSON ) is greater than (V<0 / / 00098>*T HSON ), or rather, when (V HSON *T HSON ) exceeds (V LSON *T LSON ), method 1000 proceeds to step 1080. In step 1080, the high-side switch is switched off.

[0126]

[0146] This method controls the on-period of the high-side switch based on the volt-second balance between the operation of the AHB power converter during the on-periods of the low-side switch and the high-side switch.

[0127]

[0147] Figure 11 shows a flowchart for method 1100 for controlling the on-period of the high-side switch of an AHB power converter using three different optional techniques in parallel: volt-second on-period, proportional on-period, and maximum on-period.

[0128]

[0148] In step 1110, the low-side switch of the AHB power converter, such as the low-side switch 153 shown in Figure 1, is switched on. After step 1110, method 1100 branches into two branches. In step 1111, the voltage (VAUX) across the primary auxiliary winding, such as the winding 106 shown in Figure 1, is measured. Substantially simultaneously with step 1111, in step 1112, the first reference voltage (V REF5 ) is generated.

[0129]

[0149] In step 1113, the measured VAUX is integrated during the low-side switch-on period, and the resulting first integrated value (V LSON *T LSON ) is stored. Substantively simultaneously with step 1113, in step 1114, V REF5 This is integrated during the low-side switch-on period, and the resulting third integrated value (V) REF5 *T LSON ) is stored in memory.

[0130]

[0150] In step 1120, the low-side switch is switched off, allowing the dead time period to elapse. Subsequently, the high-side switch of the AHB power converter, such as the high-side switch 151 shown in Figure 1, is switched on.

[0131]

[0151] In step 1121, the auxiliary winding voltage (VAUX) is measured again. Substantively simultaneously with step 1121, in step 1122, a second reference voltage (kV REF5 ) is generated. Furthermore, substantially simultaneously with steps 1121 and 1122, in step 1130, the timer is started.

[0132]

[0152] In step 1123, the measured VAUX is integrated during the high-side switch-on period, and the second integrated value (V HSON *T HSON ) is calculated. In substantially the same time as step 1123, in step 1124, KV REF5 This is integrated during the low-side switch-on period, and the resulting fourth integrated value (KV) REF5 *T HSON ) is calculated. In step 1125, (V HSON *T HSON ) is (V LSON *T LSON ) is compared with, and in step 1126, (KV REF5 *T HSON ) is (V REF5 *T LSON It is compared to ).

[0133]

[0153] In step 1135, the elapsed time of the timer is compared to a predetermined maximum period. If the maximum period has not been exceeded, the timer continues to operate and the method repeats step 1135. If the elapsed time of the timer exceeds the predetermined maximum period at any point, the method 1100 immediately proceeds to step 1150, where the high-side switch is switched off.

[0134]

[0154] In step 1140, if the maximum period has not been reached, the results of the comparison in steps 1125 and 1126 are evaluated. (V HSON *T HSON ) is (V LSON *T LSON ) is larger than, and (KV REF5 *T HSON ) is (V REF5 *TLSON If it is greater than (V), method 1100 proceeds to step 1150, and the high-side switch is switched off. HSON *T HSON ) is (V LSON *T LSON ) or less, or (KV REF5 *T HSON ) is (V REF5 *T LSON If the following conditions are met, method 1100 returns to step 1123 or 1124, respectively. This technique ensures that the longer of the periods determined by the volt-second on period or the proportional on period (if both are shorter than the maximum period) controls the switching off of the high-side switch in any given switching cycle.

[0135]

[0155] Combining the maximum on-period, proportional on-period, and volt-second on-period can, in some examples, provide more robust operation across a wide range of possible operating conditions for AHB power converters. Furthermore, as those skilled in the art will understand, alternative methods exist for implementing the various circuit blocks and circuits described herein.

[0136]

[0156] For example, Figure 12A shows a voltage-second (volt-second) on-period circuit 1235 according to another embodiment of the present disclosure. The volt-second on-period circuit 1235 may be an alternative implementation of the volt-second on-period block 335, but unlike the aforementioned circuit implementations, the volt-second on-period circuit 1235 can implement a stable or fixed input bias voltage VA having a regulated value of zero volts or greater. For example, the bias voltage VA may be 25 volts (2.5V).

[0137]

[0157] The volt-second on-period circuit 1235 includes a buffer circuit 1201 and a trigger circuit 1202. In addition to providing a bias voltage VA, the buffer circuit 1201 can receive an external resistor current IA and provide a buffered current IAR. Referring to Figure 1, the resistor current IA may be related to the resistance RA and resistor voltage VRES of resistor 175 according to Ohm's law. Thus, the resistor current IA can be expressed in terms of the auxiliary winding voltage VAUX and bias voltage VA by Equation 1.

number

[0138]

[0158] The buffer circuit 1201 includes an offset correction circuit 1203 and a current buffer 1204. The offset correction circuit 1203 may provide an offset current IX to adjust the input current IAX with respect to the resistor current IA. For example, if the offset current IX is equal to the bias voltage VA divided by the resistance RA, the input current IAX may be given by equation 2.

number

[0139]

[0159] The current buffer 1204 receives the input current IAX and can provide the buffered current IAR to the trigger circuit 1202. The buffered current IAR may be proportional to the input current IAX. For example, the buffered current IAR may be a duplicate of the input current IAX with the opposite sign, as shown in Equation 3.

number

[0140]

[0160] As taught herein, a volt-second on-period circuit 1235 may receive a resistor current IA and, in response, provide a state voltage VCX indicating when to switch the high-side switch 151 off. For example, a trigger circuit 1202 may receive a buffered current IAR and transition the state voltage VCX to indicate when to switch the high-side switch 151 off.

[0141]

[0161] Figure 12B shows the waveform 1225 of the resistor current IA and the waveform 1226 of the state voltage VCX according to an embodiment of the present disclosure. Referring to Figure 2 and according to Equation 1, waveform 1225 may be analogous to that of the auxiliary winding voltage VAUX, showing a transition over the switching period TSW from time 211 to time 215. During the switching period TSW, the low-side switch 153 is ON from time 211 to time 212, and the high-side switch 151 is ON from time 213 to time 214. During the period TIR from time 214 to time 215, both the low-side switch 153 and the high-side switch 151 may be OFF.

[0142]

[0162] Similar to that of the auxiliary winding voltage VAUX, waveform 1225 may show switching transitions at time points 211, 212, 214, and 215. For example, when the low-side switch 153 is on from time point 211 to time point 212, the resistor current IA may be approximately -22.5 microamperes (-22.5 uA), and when the high-side switch 151 is on from time point 213 to time point 214, the resistor current IA may be approximately +17.5 microamperes (17.5 uA).

[0143]

[0163] As taught herein, the volt-second on-period circuit 1235 may indicate, through the state voltage VCX, when to switch the high-side switch 151 off. Thus, the waveform 1226 may indicate the transition immediately preceding time 214, such that the high-side switch 151 is switched off at time 214.

[0144]

[0164] As those skilled in the art will understand, the waveform 1225 of the resistor current IA, like that of the auxiliary winding voltage VAUX, can be dependent on operating conditions and configuration. For example, when the auxiliary winding 106 is wound in the reverse direction such that the winding "dots" are connected to ground, the auxiliary winding voltage VAUX may be of reverse polarity with respect to those in Figures 1 and 2. As a result, the waveforms of the auxiliary winding voltage VAUX and the corresponding resistor current IA may be of reverse polarity.

[0145]

[0165] Figure 12C shows a buffer circuit 1201 according to an embodiment of the present disclosure. As described above, the buffer circuit 1201 may include an offset correction circuit 1203 and a current buffer 1204. As shown in the figure, the offset correction circuit 1203 may include a p-channel field-effect transistor (PFET) MP1. The gate of the PFET MP1 may receive a bias potential VGP, and the drain of the PFET MP1 may be coupled to node NA to add an offset correction current IX to the resistor current IA.

[0146]

[0166] As further shown, the current buffer 1204 can be implemented using p-channel field-effect transistors (PFETs) MP2-MP9 and n-channel field-effect transistors (NFETs) MN1-MN9. The bias potential VGP may be supplied to the gate of PFET MP2, and the bias potential VGN may be supplied to the gates of NFETs MN6-MN8. During operation, thanks to the feedback and circuit configuration, the current buffer 1204 can provide a bias voltage VA at node NA that is substantially equal to the bias reference VCM at the gate of NFET MN4. For example, if the bias reference VCM is equal to 2.5 volts (2.5V), the bias voltage VA can be adjusted to 2.5V plus or minus any offset.

[0147]

[0167] Furthermore, thanks to the circuit configuration, the current buffer 1204 can provide a buffered current IAR from the drains of the NFET MN9 and PFET MP7, both coupled to node ND. As shown by the waveforms of the input current IAX 1250 and the buffered current IAR 1251, respectively, the buffered current IAR may have the opposite sign to that of the input current IAX, but other configurations are also possible. For example, an implementation of the current buffer 1201 may include additional components for the buffered current IAR to replicate the input current IAX without reversing the polarity and direction of the current.

[0148]

[0168] Figure 12D shows a trigger circuit 1202 according to an embodiment of the present disclosure. The trigger circuit 1202 includes a switching voltage source 1205, a capacitor C1, and a comparator circuit block 1210. Capacitor C1 is connected at node NC1 to the input of the comparator circuit block 1210 and to the switching voltage source 1205. Before the start of a switching cycle (e.g., switching period TSW), the capacitor voltage VC1 at node NC1 may be pre-charged by the switching voltage source 1205 to a reference voltage VR, and during the switching cycle (e.g., switching period TSW), while the switch S1 is open, the capacitor voltage VC1 may change as a function of the buffered current IAR.

[0149]

[0169] Therefore, before the start of a switching cycle (e.g., switching period TSW), switch S1 may be closed by the switch signal PS1. During the switching cycle, switch S1 may be opened by the switch signal PS1.

[0150]

[0170] As illustrated, the comparator circuit block 1210 may include a comparator 1211 and a logic circuit 1212. During a switching cycle (e.g., switching period TSW), the comparator 1211 may compare the capacitor voltage VC1 with a comparator reference voltage VRN. During the switching cycle, the comparator reference voltage VRN may be selected, programmed, and / or derived such that the comparator 1211 changes state in response to the capacitor voltage VC1 crossing the reference voltage VR. For example, the comparator reference voltage VRN may be set to a value equal to, or substantially equal to, the reference voltage VR plus or minus an arbitrary offset.

[0151]

[0171] The comparator circuit block 1210 may further include a logic circuit 1212. The logic circuit 1212 may receive the comparator output voltage VC and provide a state voltage VCX. For example, to ensure that the state voltage VCX is provided as a pulse following a transition in the comparator output voltage VC, the logic circuit 1212 may include latches, switches, logic gates, and / or one-shot circuits.

[0152]

[0172] Figure 13A shows waveforms 1301a to 1304a corresponding to the capacitor voltage VC1, low gate voltage VGL, high gate voltage VGH, and state voltage VCX according to embodiments of the present disclosure. Waveforms 1301a to 1304a are plotted to begin at time 1330. Referring to Figure 1, the low gate voltage VGL can drive the low switch 153, and the high gate voltage VGH can drive the high switch 151. For example, from time 1330 to time 1332, the low gate voltage VGL drives the low switch 153 to operate in the ON state, and from time 1333 to time 1335, the high gate voltage VGH drives the high switch 151 to operate in the ON state.

[0153]

[0173] Furthermore, the switching period TSW can be conveniently defined from time 1330 when the low-side switch 153 switches on to time 1337 when the low-side switch 153 switches on again. Thus, as shown by waveform 1302a, the switching cycle may begin at time 1330 with a transition from low to high of the low-side gate voltage VGL. Furthermore, as shown by waveform 1301a, the capacitor voltage VC1 may be held constant at the reference voltage VR from time 1330 to time 1331.

[0154]

[0174] According to the teachings herein, waveforms 1301a to 1304a can further correspond to auxiliary winding configurations (i.e., dot winding configurations) as shown in Figure 1. Thus, as shown by waveform 1301a, after a short delay (e.g., a delay of 100 nanoseconds), the capacitor voltage VC1 may rise from its initial value (e.g., reference voltage VR). Then, at time 1332, the low-side switch 153 is switched off, and the capacitor voltage VC1 may reach its peak Vpk1.

[0155]

[0175] Referring to waveform 1303a, at time 1333 after a break-before-make delay (e.g., a delay of 250 nanoseconds), the high-side switch 151 may be switched on. As shown by waveform 1301a, the capacitor voltage VC1 may decrease from time 1333 to time 1335 while the high-side switch 151 is on.

[0156]

[0176] Referring to waveform 1304a and according to the teachings herein, the state voltage VCX transitions to high at time 1335, indicating when the high-side switch 151 is switched off. Thus, at time 1335, and immediately after the transition of the state voltage VCX, the high-side switch 151 is switched off (i.e., the high-side voltage VGH transitions to low). While waveform 1304a shows the state voltage VCX as a short pulse between time 1335 and time 1336, other waveforms may also be possible, provided that the transition edge at time 1335 triggers the high-side switch 151 to switch off.

[0157]

[0177] As shown by waveform 1301a, an undershoot of the capacitor voltage VC1 may exist, beginning at time 1334. The undershoot may be at least partially due to the sub-ideal behavior of the circuit, including the comparator circuit block 1210. Ideally, the state voltage VCX would transition to high simultaneously with the intersection of the capacitor voltage VC1 and the reference voltage VR at time 1334. However, due to circuit delay and / or offset, the comparator circuit block 1210 may not respond until time 1335, generating a total undershoot voltage VUS.

[0158]

[0178] During the TIR period, from time 1335 to time 1337, both the high-side switch 151 and the low-side switch 153 are off. Furthermore, switch S1 may conduct so that the switching voltage source 1205 provides a reference voltage VR to node NC1. Thus, as shown in waveform 1301a, the capacitor voltage VC1 returns (i.e., rises) toward its starting value (i.e. toward the reference voltage VR). For stable operation and circuit performance, the capacitor voltage VC1 must be equal to, or substantially equal to, the reference voltage VR before the start of the subsequent switching cycle.

[0159]

[0179] Unfortunately, there may be system operating modes that include transient and / or heavy load conditions with relatively short TIR periods (e.g., less than 100 nanoseconds). Furthermore, due to process and / or device limitations, the switching voltage source 1205 may not have sufficient bandwidth (i.e., may not be fast enough) to allow the capacitor voltage VC1 to return to the reference voltage VR.

[0160]

[0180] Therefore, as shown in waveforms 1301a and 1302a, the low-side switch 153 may switch on at time 1338 before the capacitor voltage VC1 can reach its initial value corresponding to the reference voltage VR. This can result in an undesirable shift error. Under these conditions, the capacitor voltage VC1 may rise until it reaches its subsequent peak Vpk2 at time 1339, and the subsequent peak Vpk2 at time 1339 may be less than the peak Vpk1 at time 1332, partly due to the shift error. Finally, after several switching cycles, the shift error may accumulate, and the capacitor voltage VC1 and its subsequent peaks may decrease until the capacitor voltage VC1 is no longer within the operating range.

[0161]

[0181] A similar condition may exist for alternative auxiliary winding configurations (i.e., dot winding configurations with the opposite winding direction to that of Figure 1).

[0162]

[0182] For example, Figure 13B shows waveforms 1301b to 1304b corresponding to the capacitor voltage VC1, low-side gate voltage VGL, high-side gate voltage VGH, and state voltage VCX in an embodiment where the auxiliary winding 106 has reverse winding polarity. When the auxiliary winding 106 has reverse winding polarity (i.e., the dot side is connected to ground 107), the corresponding auxiliary winding voltage VAUX and buffered current IAR may also have reversed signs. Therefore, the comparator circuit block 1210 and / or the switching voltage source 1205 can be reconfigured to take reverse winding polarity into account.

[0163]

[0183] Therefore, waveforms 1301b to 1304b may be the same as waveforms 1301a to 1304a, except for waveform 1301b which corresponds to the capacitor voltage VC1, and the transitions and waveform behavior at time points 1341 to 1349 may be the same as those at time points 1331 to 1339, except for waveform 1301b. Furthermore, similar to that in Figure 13A, the switching period TSW can be defined for waveforms 1301b to 1304b from time point 1340 to time point 1347.

[0164]

[0184] In relation to waveform 1301b, at time 1341, the capacitor voltage VC1 may decrease from its initial value (e.g., reference voltage VR) and reach the trough Vval1 at time 1342 when the low-side switch 153 switches off. Next, from time 1343 to time 1345, while the high-side switch 151 is on, the capacitor voltage VC1 may increase.

[0165]

[0185] As shown by waveform 1301b, an overshoot of the capacitor voltage VC1 may exist, beginning at time 1344. Similar to undershoot, the overshoot may be at least partially attributable to the suboptimal behavior of the circuit, including the comparator circuit block 1210. Therefore, the comparator circuit block 1210 may not respond until time 1345, which generates the total overshoot voltage VOV.

[0166]

[0186] As shown in waveforms 1301b and 1302b, the low-side switch 153 may switch on at time 1348 before the capacitor voltage VC1 can reach its initial value corresponding to the reference voltage VR. Under these conditions, the capacitor voltage VC1 may drop until it reaches the subsequent trough Vval2 at time 1349. In comparison, the subsequent trough Vval2 at time 1349 may be higher than the trough Vval1 at time 1342, partly due to the shift error. Finally, after several switching cycles, the shift error may accumulate, and the capacitor voltage VC1 and its subsequent troughs may rise until the capacitor voltage VC1 is no longer within the operating range.

[0167]

[0187] Therefore, there is a need to develop an embodiment of the trigger circuit 1202 that reduces shift errors and allows the capacitor voltage VC1 to remain within the operating range.

[0168]

[0188] In this regard, Figure 14 shows a trigger circuit 1402 as taught herein. Similar to the trigger circuit 1202, the trigger circuit 1402 includes a switching voltage source 1205, a comparator circuit block 1210, and a capacitor C1. Furthermore, the trigger circuit 1402 further includes a capacitor C2 and switches S2-S6. As shown, the switches S1-S6 are controlled by switch signals PS1-PS6, respectively, and the voltage source 1205 includes an additional switch S2.

[0169]

[0189] As shown in the diagram, capacitor C1 is connected to switch S1 at node NC1. Furthermore, switch S3 is connected between node NR and node NC1, and switch S5 is connected between node NP and node NC1. Thus, switch S1 can be closed so that the switching voltage source 1205 provides a reference voltage VR to capacitor C1. Next, when switches S3 and S5 are closed, a buffered current IAR can be supplied to capacitor C1, and a capacitor voltage VC1 can be supplied to comparator circuit block 1210.

[0170]

[0190] Furthermore, capacitor C2 is connected to switch S2 at node NC2. Additionally, switch S4 is connected between node NR and node NC2, and switch S6 is connected between node NP and node NC2. Thus, switch S2 can be closed so that the switching voltage source 1205 provides a reference voltage VR to capacitor C1. When switches S4 and S6 are closed, a buffered current IAR can be supplied to capacitor C2, and a capacitor voltage VC2 can be supplied to the comparator circuit block 1210.

[0171]

[0191] As described herein, the use of capacitors C1 and C2, and switches S1 to S6 can be beneficially enabled to swap capacitor C1 with capacitor C2 over two switching cycles in a manner that ensures sufficient time for the switching voltage source 1205 to provide voltage VR.

[0172]

[0192] Figure 15 shows waveforms 1501 to 1505 corresponding to the capacitor voltage VC1, capacitor voltage VC2, low gate voltage VGL, high gate voltage VGH, and state voltage VCX according to the embodiment of Figure 14. The switching period TSW can be defined from time 1520 to time 1525. The low switch 153 may be on between time 1520 and time 1522, and the high switch 151 may be on between time 1523 and time 1524. The comparator circuit block 1210 can swing the state voltage VCX high at time 1524, and a new switching cycle may begin at time 1525.

[0173]

[0193] At time 1521, switches S3 and S5 may be closed, allowing the capacitor voltage VC1 to rise in response to the buffered current IAR. As shown, the capacitor voltage VC1 may rise from its initial value at time 1521 (i.e., the initial value of its reference voltage VR) and reach its peak Vpkc1 at time 1522.

[0174]

[0194] According to the teachings herein, the switching voltage source 1205 may provide a reference voltage VR to the capacitor C2 before time 1525. In this manner, at time 1526, the capacitor voltage VC2 may be equal to, or substantially equal to, the reference voltage VR. Then, at time 1527, the capacitor voltage VC2 may reach its peak Vpkc2 without shift error.

[0175]

[0195] Figure 16 shows a trigger circuit 1602 according to another embodiment. The trigger circuit 1602 is similar to the trigger circuit 1402 except that the switching voltage source 1205 and the comparator circuit block 1210 are replaced by the switching voltage source 1605 and the comparator circuit block 1610, respectively.

[0176]

[0196] Similar to the switching voltage source 1205, the switching voltage source 1605 includes switches S1 and S2. Furthermore, the switching voltage source 1605 includes a multiplexer 1615 and an operational transconductance amplifier (OTA) 1616. In response to a multiplexer control signal PSM, the multiplexer 1615 may select either voltage V1 or voltage V2 and provide it to the non-inverting input of the OTA 1616. The OTA 1616 may then provide a reference voltage VR that is equal to, or substantially equal to, the selected one of voltages V1 or V2.

[0177]

[0197] For example, voltage V1 could be 1.5 volts (1.5V) and voltage V2 could be 3 volts (3.0V). Next, if the capacitor voltage VC1 is similar to that of waveform 1501, it may be beneficial to select voltage V1 such that the capacitor voltage VC1 rises from its initial value (i.e., from the reference voltage VR) with a sufficient common-mode range. Alternatively, if the auxiliary winding 106 has the opposite winding polarity, and the capacitor voltage VC1 falls from its initial value (i.e., from the reference voltage VR), it may be beneficial to select voltage V2.

[0178]

[0198] The switching voltage source 1205 is shown as allowing selection of two volts, V1 and V2, but other configurations allowing more or fewer than two volts may also be possible.

[0179]

[0199] Furthermore, similar to comparator circuit block 1210, comparator circuit block 1610 may include comparator 1211 and logic circuit 1212. In addition, comparator circuit block 1610 may include capacitor CRN, switch S7, and switch S8. Switches S7 and S8 may be controlled by switch signals PS7 and PS8, respectively, so that a comparator reference voltage VRN is supplied to capacitor CRN during a switching cycle (e.g., switching period TSW). Thus, thanks to autozeroing, comparator 1211, together with logic circuit 1212, may cause (oscillate) state voltage transitions in response to the crossover of the capacitor voltage (i.e., capacitor voltage VC1 and / or capacitor voltage VC2) with respect to the reference voltage VR.

[0180]

[0200] Figure 17 shows waveforms 1701 to 1705 corresponding to capacitor voltage VC1, capacitor voltage VC2, low gate voltage VGL, high gate voltage VGH, and state voltage VCX, respectively, and waveforms 1706 to 1713 corresponding to switch signals PS1 to PS8, respectively.

[0181]

[0201] The first switching period TSW1 may be defined from time 1720 to time 1729, and the second switching period TSW2 may be defined from time 1729 to time 1738. The low-side gate voltage VGL transitions to high at time 1720, completes the first switching cycle at time 1729, and completes the second switching cycle at time 1738. During the period TIR1 from time 1727 to time 1729, and the period TIR2 from time 1735 to time 1338, both the high-side switch 151 and the low-side switch 153 are off.

[0182]

[0202] The high-side gate voltage VGH transitions to high at time 1723, to low at time 1727, to high at time 1732, and to low at time 1735. According to the teachings herein, in response to the transition of the state voltage VCX at time 1727, the high-side gate voltage VGH transitions to low (i.e., the high-side switch 151 switches off), and in response to the transition of the state voltage VCX at time 1735, the high-side gate voltage VGH transitions to low again.

[0183]

[0203] Waveforms 1706 to 1713 of the switch signals PS1 to PS8 each represent the conducted state (i.e., on or off state) of switches S1 to S8 as a function of time. In the embodiment of Figure 17, when each of the switch signals (e.g., one of the corresponding switch signals PS1 to PS8) is high, the switch (e.g., one of the switches S1 to S8) may be on (i.e., conducting), and when each of the switch signals (e.g., one of the corresponding switch signals PS1 to PS8) is low, the switch (e.g., one of the switches S1 to S8) may be off (i.e., blocking).

[0184]

[0204] Therefore, switch S1 switches on at time 1730 and off at time 1738. Switch S2 switches on at time 1721 and off at time 1729. Switch S3 switches on at time 1721 and off at time 1727. Switch S4 switches on at time 1730 and off at time 1735. Switch S5 switches on at time 1726 and off at time 1727. Switch S6 switches on at time 1734 and off at time 1735. Switch S7 switches off at time 1725, on at time 1729, off at time 1733, and on at time 1737. Switch S8 switches off at time 1724, on at time 1728, off at time 1732, and on at time 1736.

[0185]

[0205] Referring to the trigger circuit 1602, waveforms 1706-1707 may show the conduction states of switches S1-S2, respectively, related to how the switching voltage source 1605 provides reference voltage VR to capacitors C1 and C2, and waveforms 1708-1711 may show the conduction states of switches S3-S6, related to how the buffered current IAR is provided to capacitors C1 and C2, and how capacitors C1 and C2 provide capacitor voltages VC1 and VC2, respectively, to the comparator circuit block 1610.

[0186]

[0206] Therefore, waveforms 1706 to 1711 may show how switches S1 to S6 alternate (i.e., swap) the functions of capacitors C1 and C2 over a first switching period TSW1 and a second switching period TSW2, respectively, in order to generate waveforms 1701 to 1702. Thus, as shown by waveform 1701 of capacitor voltage VC1 and waveform 1702 of capacitor voltage VC2, the reference voltage VR can be supplied to capacitor C2 while capacitor C1 receives the reference voltage VR.

[0187]

[0207] As shown by waveforms 1701-1702, the fact that capacitor C2 receives a reference voltage VR while capacitor C1 provides voltage VC1 during the first switching period TSW1, and then capacitor C2 provides voltage VC2 during the second switching period TSW2 while capacitor C1 receives the reference voltage VR, benefitsly allows sufficient time for the switching voltage source 1605 to provide voltage VR. For example, capacitor C2 may receive the reference voltage VR over almost the entire switching period TSW1 while capacitor C1 provides the capacitor voltage VC1 to the comparator circuit block 1610. Then, capacitor C1 may receive the reference voltage VR over almost the entire switching period TSW2 while capacitor C2 provides the capacitor voltage VC2 to the comparator circuit block 1610.

[0188]

[0208] Furthermore, referring to the trigger circuit 1602, waveforms 1712-1713 may represent the conducted states of switches S7-S8, respectively, associated with the auto-zeroing function of the comparator circuit block 1610. Although the comparator circuit block 1610 is shown as including the auto-zeroing function, other configurations of the comparator circuit 1610 and the trigger circuit 1602 are also possible.

[0189]

[0209] For example, the comparator circuit block 1610 may use a comparator section 1211 that does not require auto-zeroing. Furthermore, as those skilled in the art will understand, there may be a configuration of the trigger circuit 1602 that allows more than two capacitors C1, C2 to be replaced during more than two switching periods TSW1, TSW2.

[0190]

[0210] The above description includes many specific details to provide a full understanding of this disclosure. However, it will be apparent to those skilled in the art that these specific details are not necessarily used to carry out the teachings herein. In other instances, well-known materials or methods are not described in detail so as not to obscure this disclosure.

[0191]

[0211] In this specification, any reference to “one embodiment,” “an embodiment,” “an example,” or “an example” means that any particular feature, structure, or characteristic described in relation to an embodiment or example is included in at least one embodiment of this disclosure. Therefore, the use of expressions such as “one embodiment,” “an embodiment,” “an example,” or “an example” in various places in this specification does not necessarily relate to the same embodiment or example. Furthermore, any particular feature, structure, or characteristic may be combined in any suitable combination and / or partial combination in one or more embodiments or examples. Any particular feature, structure, or characteristic may be included in an integrated circuit, electronic circuit, logic circuit, or other suitable component that provides the function described. In addition, it should be understood that the drawings provided with this specification are intended for those skilled in the art and that the drawings are not necessarily drawn to a fixed scale.

[0192]

[0212] The above description of the examples shown in this disclosure, including matters described in the abstract, is not intended to be exhaustive and is not intended to be limited to the forms disclosed. Specific embodiments and examples for controlling the on-period of the high-side switch in an AHB converter are described herein for illustrative purposes only, but various equivalent modifications are possible without departing from the broader spirit and scope of this disclosure. In fact, it is understood that specific and exemplary voltages, currents, frequencies, output range values, times, etc., are presented for illustrative purposes, and that other values ​​may be used in other embodiments and examples in accordance with the teachings herein.

[0193]

[0213] The preceding description may refer to elements or features together as “connected,” “electrically connected,” and / or “joined.” As used herein, unless otherwise expressly stated, “connected” means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically connected. Similarly, unless otherwise expressly stated, “joined” means that one element / feature is directly or indirectly joined to another element / feature, and not necessarily mechanically connected. Therefore, while the various schematic diagrams shown in the figures illustrate exemplary configurations of elements and components, there may be further intervening elements, devices, features, or components in actual embodiments (provided that the functionality of the shown circuits is not adversely affected).

[0194]

[0214] Furthermore, conditional expressions used herein, such as "may," "can," "may," "may," "for example," "as an example," etc., are generally intended to convey that a particular embodiment includes a particular feature, element, and / or state, while other embodiments do not, unless explicitly stated otherwise or understood differently in the context in which they are used. Thus, such conditional expressions are generally not intended to suggest that the feature, element, and / or state is required in any way in one or more embodiments, nor are they intended to suggest that one or more embodiments necessarily include logic for determining whether these features, elements, and / or states are included in or implemented in any particular embodiment.

[0195]

[0215] While specific embodiments have been described, these embodiments are presented only as examples and are not intended to limit the scope of this disclosure. In fact, the novel apparatus, methods, and systems described herein may be embodied in various other forms, and furthermore, various omissions, substitutions, and modifications in the forms of methods and systems described herein may be made without departing from the spirit of this disclosure. For example, while the disclosed embodiments are shown in a given configuration, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in various different ways. Any suitable combination of elements and operations of the various embodiments described above may be combined to provide further embodiments. Accordingly, the scope of the invention is defined solely by reference to the appended claims.

[0196]

[0216] The claims presented in this application are in a form that is one dependent for filing with the USPTO, but it is understood that any claim may be dependent on any one of the prior claims of the same kind, unless it is clearly not technically feasible.

Claims

1. A high-side switch-on period control circuit for use in an asymmetric half-bridge (AHB) power converter, wherein the AHB power converter comprises a high-side switch, a low-side switch, and a primary-side winding, and the high-side switch-on period control circuit is A terminal coupled to receive a signal representing the winding voltage in the primary winding, A first integrator configured to integrate the signal during the ON period of the low-side switch and to output a first integrated value, A second integrator configured to integrate the signal during the ON period of the high-side switch and to output a second integrated value, A first comparator configured to compare the first integrated value with the second integrated value and to output a control signal in response to the comparison, wherein the control signal is coupled to control the end of the on period of the high-side switch, A high-side switch-on period control circuit is provided.

2. The first integrator, A first current source that provides a first current proportional to the winding voltage during the ON period of the low-side switch, A first switch coupled to the first current source, A first capacitor coupled to the first current source so as to be charged by the first current source, Equipped with, The first current source is coupled to charge the first capacitor through the first switch, The first integrated value is the voltage across the first capacitor at the end of the ON period of the low-side switch. The high-side switch-on period control circuit according to claim 1.

3. The second integrator described above, A second current source that provides a second current proportional to the winding voltage during the ON period of the high-side switch, A second switch coupled to the second current source, The first capacitor is configured to be discharged by the second current source, Equipped with, The second current source is coupled to discharge the first capacitor through the second switch. The high-side switch-on period control circuit according to claim 2.

4. When the voltage in the first capacitor is discharged to below the first reference voltage, the first comparator is configured to output the control signal for controlling the end of the ON period of the high-side switch. The high-side switch-on period control circuit according to claim 3.

5. The system further comprises a third switch configured to reset the voltage across the first capacitor once during each switching cycle in response to the output of the first comparator. The high-side switch-on period control circuit according to claim 4.

6. The system further comprises a reset circuit coupled between the output of the first comparator and the third switch. The high-side switch-on period control circuit according to claim 5.

7. The first comparator is a voltage comparator. The high-side switch-on period control circuit according to claim 1.

8. The first reference voltage and A third integrator configured to integrate the first reference voltage during the ON period of the low-side switch and to output a third integrated value, A second reference voltage, wherein the second reference voltage is a constant K times the first reference voltage, A fourth integrator configured to integrate the second reference voltage during the ON period of the high-side switch and to output a fourth integrated value, A second comparator configured to compare the third integrated value with the fourth integrated value and to output a second control signal in response to the comparison, wherein the second control signal is coupled to control the end of the on period of the high-side switch; The high-side switch-on period control circuit according to claim 1, further comprising:

9. K is equal to 1. The high-side switch-on period control circuit according to claim 8.

10. The third integrator, A third current source that provides a first current proportional to the first reference voltage, A third switch coupled to the third current source, A second capacitor coupled to be charged by the third current source, Equipped with, The third current source is coupled to charge the second capacitor through the third switch, The third integrated value is the voltage across the second capacitor at the end of the ON period of the low-side switch. The high-side switch-on period control circuit according to claim 8.

11. The fourth integrator, A fourth current source that provides a current proportional to the second reference voltage, A fourth switch coupled to the fourth current source, The second capacitor is coupled to the fourth current source so as to be discharged by the fourth current source, Equipped with, The fourth current source is coupled to discharge the second capacitor through the fourth switch. The high-side switch-on period control circuit according to claim 10.

12. When the voltage in the second capacitor is discharged to below the third reference voltage, the second comparator is configured to output the second control signal for controlling the end of the ON period of the high-side switch. The high-side switch-on period control circuit according to claim 11.

13. The system further comprises a fifth switch configured to reset the voltage across the second capacitor once during each switching cycle in response to the output of the second comparator. The high-side switch-on period control circuit according to claim 12.

14. The system further comprises a reset circuit coupled between the output of the second comparator and the fifth switch. The high-side switch-on period control circuit according to claim 13.

15. It also has a timer, The timer comprises an input coupled to receive a signal indicating when the high-side switch is switched on, and an output configured to provide a second control signal when a predetermined maximum time has been reached after the high-side switch has been switched on. The high-side switch-on period control circuit according to claim 1.

16. The predetermined maximum time is programmable. The high-side switch-on period control circuit according to claim 15.

17. A primary control device for use in an asymmetric half-bridge (AHB) power converter, wherein the AHB power converter comprises a high-side switch, a low-side switch, and a primary-side winding, and the primary control device is A first terminal coupled to receive a first signal representing the voltage applied to the primary winding, A second terminal coupled to receive a feedback signal representing the output of the AHB power converter, A third terminal coupled to receive a second signal representing the voltage at the half-bridge node of the AHB power converter, A low-side control circuit is configured to respond to the feedback signal and the second signal, and to generate a low-side switch control signal in response thereto. A high-side control circuit configured to respond to the first signal and the second signal, and to generate a high-side switch control signal in response thereto, Equipped with, The high-side control circuit, A maximum on-duration circuit configured to generate a first high-side control signal for controlling the maximum on-duration period of the high-side switch, A proportional on-period circuit configured to generate a second high-side control signal for controlling the on-period of the high-side switch in proportion to the on-period of the low-side switch in the switching cycle of the AHB power converter, A volt-second on-period circuit configured to receive the first signal and generate a third high-side control signal in response thereto, Equipped with, Primary control device.

18. The system further comprises a fourth terminal configured to receive a programming signal for programming the duration of the maximum on-period, The primary control device according to claim 17.

19. The system further includes a fourth terminal for receiving a current detection signal representing the current passing through the low-side switch. The primary control device according to claim 17.

20. The low-side control circuit changes the frequency of the on-switching of the low-side switch in response to the feedback signal. The low-side control circuit switches the low-side switch to the OFF position in response to the current detection signal. The primary control device according to claim 19.

21. The system further includes a discontinuous conduction mode detection circuit configured to realize a dead time period between the switching of the high-side switch and the low-side switch in response to the second signal. The primary control device according to claim 17.

22. The system further comprises a high-side communication circuit configured to generate a level-shifted control signal from the output of the high-side control circuit, which is coupled to the high-side switch. The primary control device according to claim 17.

23. The system further comprises a logic circuit configured to receive the first high-side control signal and the second high-side control signal, and to output a fourth high-side control signal that indicates the longer on-period of the high-side switch. The primary control device according to claim 17.

24. The logic circuit is further configured to receive the third high-side control signal and the fourth high-side control signal, and to output the one indicating the shorter on-period of the high-side switch as the high-side switch control signal. The primary control device according to claim 23.

25. The volt-second ON-period circuit, A first integrator configured to integrate the first signal during the ON period of the low-side switch and to output a first integrated value, A second integrator configured to integrate the first signal during the ON period of the high-side switch and to output a second integrated value, A first comparator configured to compare the first integrated value with the second integrated value and to output the third high-side control signal in response thereto, Equipped with, The primary control device according to claim 17.

26. The proportional ON period circuit, The first reference voltage and A third integrator configured to integrate the first reference voltage during the ON period of the low-side switch and to output a third integrated value, A second reference voltage, wherein the second reference voltage is a constant K times the first reference voltage, A fourth integrator configured to integrate the second reference voltage during the ON period of the high-side switch and to output a fourth integrated value, A second comparator configured to compare the third integrated value with the fourth integrated value and to output the second high-side control signal in response thereto, Equipped with, The primary control device according to claim 25.

27. A method for controlling the on-period of the high-side switch of an asymmetric half-bridge power converter comprising a high-side switch, a low-side switch, and a primary-side winding, wherein the method is: Switching the aforementioned low-side switch to the ON position, Measuring a first signal representing the voltage in the primary winding during the ON period of the low-side switch, The first signal during the ON period of the low-side switch is integrated to generate a first integrated value, Switching the aforementioned low-side switch to the off position, To allow the dead time period to expire, Switching the aforementioned high-side switch to the ON position, Measuring a second signal representing the voltage in the primary winding during the ON period of the high-side switch, The second signal during the ON period of the high-side switch is integrated to generate a second integrated value, Comparing the second integrated value with the first integrated value, When the second integrated value exceeds the first integrated value, the high-side switch is switched off. Methods that include...

28. Integrating the first signal includes charging a capacitor using a current proportional to the first signal. The method according to claim 27.

29. Integrating the second signal includes discharging a capacitor using a current proportional to the second signal. The method according to claim 27.

30. The further step includes resetting the capacitor after switching the high-side switch to the off position and before switching the low-side switch to the on position. The method according to claim 29.

31. A method for controlling the on-period of the high-side switch of an asymmetric half-bridge power converter comprising a high-side switch, a low-side switch, and a primary-side winding, wherein the method is: To generate a first high-side control signal that represents the maximum on-period of the high-side switch, This involves generating a second high-side control signal, To generate a first integrated value by integrating a first signal representing the voltage in the primary winding during the ON period of the low-side switch, The second signal representing the voltage in the primary winding during the ON period of the high-side switch is integrated to generate a second integrated value, Comparing the second integrated value with the first integrated value, This generates the second high-side control signal, This involves generating a third high-side control signal, The first reference voltage during the ON period of the low-side switch is integrated to generate a third integrated value, A fourth integrated value is generated by integrating the second reference voltage, which is proportional to the first reference voltage during the ON period of the high-side switch, Comparing the third integrated value with the fourth integrated value, This generates the third high-side control signal, To control the ON period of the high-side switch, select from the first high-side control signal, the second high-side control signal, and the third high-side control signal. Methods that include...

32. Selecting from the first high-side control signal, the second high-side control signal, and the third high-side control signal is When the aforementioned maximum ON period has expired, the high-side switch is switched to the OFF position in response to the first high-side control signal. Selecting which of the second high-side control signal and the third high-side control signal represents the longer on-period of the high-side switch, If the aforementioned maximum on period has not yet expired, the high-side switch is turned off in response to the selected signal. The method according to claim 31, further comprising:

33. A voltage-second (volt-second) on-period circuit for use in an asymmetric half-bridge (AHB) power converter comprising a low-side switch and a high-side switch configured to alternately conduct primary-side current during at least one switching cycle, wherein the volt-second on-period circuit is A buffer circuit configured to provide a buffered current proportional to the auxiliary winding voltage of the AHB power converter, A trigger circuit configured to receive the buffered current and, in response, to provide a state voltage indicating when to switch the high-side switch off during at least one switching cycle, A volt-second on-period circuit equipped with this.

34. The buffer circuit is further configured to provide an input bias voltage and to receive an external resistance current proportional to the difference between the auxiliary winding voltage and the input bias voltage. The volt-second on-period circuit according to claim 33.

35. The input bias voltage is substantially equal to 2.5 volts (2.5V). The volt-second on-period circuit according to claim 34.

36. The buffer circuit further comprises a current buffer configured to provide the input bias voltage, to receive the input current, and to provide the buffered current in proportion to the input current. The volt-second on-period circuit according to claim 34.

37. The input current includes the external resistance current, The volt-second on-period circuit according to claim 36.

38. The buffer circuit further comprises an offset correction circuit configured to provide an offset current proportional to the input bias voltage. The volt-second on-period circuit according to claim 37.

39. The input current includes the offset current. The volt-second on-period circuit according to claim 38.

40. The trigger circuit, A switching voltage source, At least one capacitor, A comparator circuit block configured to provide the aforementioned state voltage, Equipped with, The volt-second on-period circuit according to claim 36.

41. Prior to the at least one switching cycle, the switching voltage source is configured to charge the at least one capacitor to a reference voltage. During the at least one switching cycle, the at least one capacitor is configured to receive the buffered current and to provide a capacitor voltage to the comparator circuit block. The volt-second on-period circuit according to claim 40.

42. The aforementioned reference voltage is between 1 volt (1V) and 5 volts (5V). The volt-second ON-period circuit according to claim 41.

43. The comparator circuit block comprises a comparator configured to bring about a transition in the state voltage in response to the crossover between the capacitor voltage and the reference voltage. The volt-second ON-period circuit according to claim 41.

44. The high-side switch is configured to switch off in response to the transition of the state voltage. The volt-second on-period circuit according to claim 43.

45. Before the crossover between the capacitor voltage and the reference voltage, the capacitor voltage is less than the reference voltage. The volt-second on-period circuit according to claim 43.

46. Before the crossover between the capacitor voltage and the reference voltage, if the capacitor voltage is higher than the reference voltage, The volt-second on-period circuit according to claim 43.

47. The at least one capacitor comprises a first capacitor and a second capacitor, The at least one switching cycle includes a first switching cycle and a second switching cycle following the first switching cycle. The volt-second ON-period circuit according to claim 41.

48. During the first switching cycle, the first capacitor is configured to receive the buffered current and to provide the capacitor voltage to the comparator circuit block, and the switching voltage source is configured to provide the reference voltage to the second capacitor. During the second switching cycle, the second capacitor is configured to receive the buffered current and to provide the capacitor voltage to the comparator circuit block, and the switching voltage source is configured to provide the reference voltage to the first capacitor. The volt-second on-period circuit according to claim 47.

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