Indication device
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- SEMICON ENERGY LAB CO LTD
- Filing Date
- 2026-04-02
- Publication Date
- 2026-06-25
AI Technical Summary
【0051】 酸化物半導体層を用い、電気特性や信頼性に優れた薄膜トランジスタを備えた半導体装置 を実現できる。
Smart Images

Figure 2026104880000001_ABST
Abstract
Claims
1. It has a first transistor, a second transistor, and a capacitor. The first transistor described above includes a first gate electrode layer, a first oxide semiconductor layer, a first source electrode layer, a first drain electrode layer, and a second gate electrode layer. The second transistor comprises a third gate electrode layer, a second oxide semiconductor layer, a second source electrode layer, and a second drain electrode layer. The first transistor has a dual-gate structure in which the first gate electrode layer and the second gate electrode layer overlap via the first oxide semiconductor layer. The second transistor has a single-gate structure having a region where the third gate electrode layer and the second oxide semiconductor layer overlap. The channel formation region of the first transistor is provided in the first oxide semiconductor layer, The channel formation region of the second transistor is provided in the second oxide semiconductor layer, The first oxide semiconductor layer comprises indium, gallium, and zinc. The second oxide semiconductor layer comprises indium, gallium, and zinc. The aforementioned capacitor comprises a first conductive layer, a first insulating layer, a second insulating layer, and a second conductive layer. The first conductive layer has a region that overlaps with the second conductive layer via the first insulating layer and the second insulating layer. The first conductive layer is provided on the same layer as the first gate electrode layer and is made of the same material. The second conductive layer has a region that functions as a pixel electrode electrically connected to either the second source electrode layer or the second drain electrode layer. The first insulating layer has a region in contact with the lower surface of the first oxide semiconductor layer, a region in contact with the upper surface of the first gate electrode layer, a region in contact with the lower surface of the second oxide semiconductor layer, and a region in contact with the upper surface of the third gate electrode layer. The second insulating layer has a region in contact with the upper surface of the first oxide semiconductor layer, a region in contact with the lower surface of the pixel electrode, and a region in contact with the upper surface of the second oxide semiconductor layer. Either the first source electrode layer or the first drain electrode layer is electrically connected to the third conductive layer. The third conductive layer is provided on the same layer as the first gate electrode layer and is made of the same material. In a cross-sectional view of the first transistor in the channel length direction, the first oxide semiconductor layer has a region at its edge that is in contact with the other of the first source electrode layer or the first drain electrode layer. In a cross-sectional view of the first transistor in the channel length direction, the edge of the first oxide semiconductor layer having a region in contact with the other of the first source electrode layer or the first drain electrode layer does not have a region overlapping with the first gate electrode layer and does not have a region overlapping with the second gate electrode layer. A display device wherein the first conductive layer has a region that extends in the channel length direction of the second transistor.
2. In claim 1, An organic resin layer is provided, The organic resin layer is a display device having a region located between the second insulating layer and the second conductive layer.
Citation Information
Patent Citations
Semiconductor device and method for manufacturing the same
JP2007096055A
Semiconductor device and its manufacturing method
JP2007123861A