Frequency synthesizer

Abstract

Regarding frequency synthesizers, the goal is to reduce manufacturing costs while minimizing the time required to obtain the output at the set frequency. [Solution] The frequency synthesizer of the present invention comprises an ADC that digitizes a frequency signal corresponding to the output of a VCO, a first processing unit and a second processing unit that process the frequency signal and output a first digital signal and a second digital signal, respectively, that eliminate the phase difference between the frequency signal and a reference frequency signal, a DAC shared by the first processing unit and the second processing unit, provided downstream of an adder that adds the outputs from the first processing unit and the second processing unit, a parameter monitoring unit that changes according to the change in the frequency signal corresponding to the control voltage, and a switching unit that switches from a first state in which one of the first digital signal and the second digital signal is supplied to the adder to a second state in which the second digital signal and the first digital signal, set to a fixed value, are supplied to the adder, respectively, based on the parameters.

Description

Technical Field

[0001] The present invention relates to a frequency synthesizer.

Background Art

[0002] As a frequency synthesizer, there is known one that forms a PLL (Phased Lock Loop) by feeding back the output of a voltage controlled oscillator. In forming such a PLL, there is one in which the output of the control voltage to the voltage controlled oscillator is controlled by digital processing. In such a frequency synthesizer, the oscillation output of the voltage controlled oscillator is converted into a digital signal by an analog / digital converter and then taken into a digital processing circuit for phase comparison with a reference frequency signal. The control voltage is generated by outputting this comparison result as an analog signal via a digital / analog converter. An example of such a frequency synthesizer is shown in Patent Document 1.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Disclosure of the Invention

Problems to be Solved by the Invention

[0004] The present invention has been made in view of the above circumstances, and an object thereof is to provide a technology capable of suppressing the manufacturing cost while suppressing the time required to obtain an output of a set frequency for a frequency synthesizer.

Means for Solving the Problems

[0005] The frequency synthesizer of the present invention includes a voltage controlled oscillator that outputs a frequency signal corresponding to a control voltage, an analog / digital converter that digitizes the frequency signal corresponding to the output of the voltage controlled oscillator, A first processing unit and a second processing unit each process the digitized frequency signal and output a first digital signal and a second digital signal for frequency adjustment, respectively, in order to eliminate the phase difference between the digitized frequency signal and the reference frequency signal. An adder that outputs an added signal obtained by adding the output from the first processing unit and the output from the second processing unit to a subsequent stage, A digital-to-analog converter is provided downstream of the adder, to be shared by the first and second processing units, and which converts the input signal to analog and outputs it in order to generate the control voltage. A monitoring unit that monitors parameters that change in accordance with changes in the frequency signal corresponding to the control voltage, A switching unit that switches from a first state in which only the first digital signal among the first and second digital signals is supplied to the adder, to a second state in which the second digital signal and the first digital signal, set to a fixed value, are each supplied to the adder, based on the parameters, It is equipped with. [Effects of the Invention]

[0006] According to the frequency synthesizer of the present invention, it is possible to reduce manufacturing costs while minimizing the time required to obtain an output of the set frequency. [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of a frequency synthesizer according to one embodiment of the present invention. [Figure 2] This is a block diagram showing a more detailed portion of the frequency synthesizer mentioned above. [Figure 3] This is a block diagram showing the switching behavior of the frequency synthesizer. [Figure 4] This is a block diagram of a frequency synthesizer related to a comparative example. [Modes for carrying out the invention]

[0008] A schematic configuration of a frequency synthesizer 1, which is one embodiment of the present invention, will be described with reference to the block diagram in Figure 1. The frequency synthesizer 1 includes a voltage-controlled oscillator (VCO) 21 that forms a PLL to output an oscillation signal synchronized with the input signal, and whose output frequency fout increases in accordance with the increase in the supplied control voltage Vc. The output of the VCO 21 is the output of the frequency synthesizer 1.

[0009] A control voltage Vc is generated based on the phase difference between a reference frequency corresponding to the user-set frequency of the frequency synthesizer 1 and a frequency identified by a digitized signal obtained by dividing the frequency of the feedback signal obtained by feeding back the output signal of the VCO21. This control voltage Vc is supplied to the input side of the VCO21, thereby feedback-controlling the output frequency fout of the VCO21. When the frequency of the divided signal matches the reference frequency, the output frequency fout is locked to the set frequency. Before this output frequency fout is locked, the circuit used to generate the control voltage Vc is switched within the processing unit 10 that performs digital processing on the frequency synthesizer 1.

[0010] To briefly describe the processing unit 10, it includes a first processing unit 11 for coarse adjustment that relatively quickly increases the output frequency fout of the VCO 21 to pull it towards the set frequency, and a second processing unit 12 for fine adjustment to match the output frequency fout to the set frequency. When a user performs a predetermined operation from an operation unit (not shown) and instructs the frequency synthesizer 1 to start operating, the first processing unit 11 first forms the feedback control loop described above, and then the second processing unit 12 forms the control loop. The processing unit 10 also includes a selection unit 13 for switching between these loops.

[0011] In addition to the VCO21, the frequency divider22 that divides the output frequency of the feedback signal of the VCO21 by a division ratio of 1 / N (where N is an integer greater than or equal to 1), and the processing unit10, the frequency synthesizer 1 includes an analog-to-digital converter (ADC)23, a digital-to-analog converter (DAC)24, a low-pass filter (LPF)25, a phase comparison unit14, a reference signal oscillator15, and a pull-in detection unit16 for detecting the pull-in state of the above frequency. The reference signal oscillator15 is configured, for example, by a Direct Digital Synthesizer (DDS) and outputs a digital signal (reference frequency signal) corresponding to the reference frequency.

[0012] The analog signal divided by the frequency divider 22 is output to the ADC 23. The ADC 23 samples the analog signal using a clock signal supplied from a clock signal source (not shown), and outputs the sampled value as a digital signal to the phase comparison unit 14. The phase comparison unit 14 outputs a signal (a rotation vector V, described later) corresponding to the phase difference between the frequency identified by this digital signal and the reference frequency of the reference frequency signal output from the reference signal oscillator 15.

[0013] A processing unit 10 is provided after the phase comparison unit 14, and the first processing unit 11 and the second processing unit 12 each act to eliminate the phase difference in the frequencies of the above signals input to the phase comparison unit 14. A selection unit 13, a DAC 24, and an LPF 25 are provided in order after the first processing unit 11 and the second processing unit 12. Therefore, the DAC 24 and the LPF 25 are configured to be shared by the first processing unit 11 and the second processing unit 12.

[0014] The digital signal output from the processing unit 10 by the DAC 24 is converted into an analog signal and output to the LPF 25. Then, the output voltage from the LPF 25 is input to the VCO 21 as the control voltage Vc. Since noise is likely to be included in a relatively high frequency band among the frequency signals supplied from the DAC 24, the LPF 25 is provided to cut that frequency band. The cut-off frequency of the LPF 25 is, for example, 100 kHz or more, specifically, for example, 250 kHz.

[0015] The output signal from the first processing unit 11 is also input to the frequency pull-in detection unit 16. Based on the detection result by the pull-in detection unit 16, the switching of the control loop is performed via the selection unit 13. Since FIG. 1 is a schematic diagram, it shows that the signal of the first processing unit 11 is not input to the subsequent stage when the loop is formed by the second processing unit 12, but actually it is input as will be described later.

[0016] The processing unit 10, the phase comparison unit 14, and the pull-in detection unit 16 are configured by, for example, an FPGA (Field Programmable Gate Array) as a digital processing unit that performs digital processing. In addition to the above-described ADC 23, this digital processing unit and the DAC 24 also operate by a clock signal supplied from a clock source.

[0017] Hereinafter, the phase comparison unit 14 and the processing unit 10 will be further described with reference to the block diagram of FIG. 2. The phase comparison unit 14 extracts a rotation vector V having a predetermined length A and a rotation angle θ from each signal input from the reference signal oscillator 15 and the ADC 23 and outputs it to the processing unit 10. This rotation vector V is schematically shown in FIG. 2. In the orthogonal coordinate plane shown in FIG. 2, the I-axis, which is the horizontal axis, represents the real part of the rotation vector V, and the Q-axis, which is the vertical axis, represents the imaginary part of the rotation vector V.

[0018] If the difference between the reference frequency and the frequency specified by the signal output from ADC23 is defined as the error frequency df, the rotation angle θ of the rotation vector V is a parameter that varies according to the error frequency df, and the rotation angle θ is 0 when the error frequency df is 0. The outputs from the first processing unit 11 and the second processing unit 12 are controlled so that the rotation angle θ becomes 0. The extraction of this rotation vector V is performed, for example, as disclosed in Japanese Patent Application Laid-Open No. 2007-74291. That is, for the sine wave signal specified by the output signal from ADC23, quadrature detection is performed using the sine wave signal specified by the reference frequency signal, and further, by passing through a low-pass filter, the real part value and the imaginary part value of the rotation vector V are obtained.

[0019] Next, the first processing unit 11 will be described. The first processing unit 11 includes a frequency difference detection unit 31, a delay circuit 32, an adder 33, a first switch 34, and a first integration circuit 35. The frequency difference detection unit 31 includes a delay circuit. Regarding this delay circuit, the data held in the register is output to the subsequent stage. For each cycle of the frequency of the clock signal, the data held above is updated to the data input to the delay circuit, so that the data input to this delay circuit is output to the subsequent stage with a delay of one clock cycle. Note that, for other delay circuits in the following description, similar to the delay circuit of the frequency difference detection unit 31, the input data is output with a delay of one clock cycle.

[0020] In the frequency difference detection unit 31, a predetermined operation is performed using the rotation vector V newly input to the frequency difference detection unit 31 and the rotation vector V obtained with a delay of one clock cycle with respect to the rotation vector V by the above-described delay circuit, thereby obtaining the error frequency df.

[0021] The error frequency df is input to the delay circuit 32 and adder 33, respectively, which are located after the frequency difference detection unit 31. The signal output from the delay circuit 32 is input to the adder 33. In the adder 33, the frequency output from the delay circuit 32 (denoted as the error frequency df') is inverted in sign and then added to the error frequency df input from the frequency difference detection unit 31. This calculated value, the error frequency change amount df1 (=df-df'), is output to the next stage. As obtained in this way, the error frequency change amount df1 is the difference between the error frequency df obtained at the nth sampling and the error frequency df obtained at the (n-1)th sampling.

[0022] The first switch 34 selectively outputs either the error frequency change amount df1 or a constant (i.e., a preset signal) supplied from a parameter supply unit (not shown) to the first integrating circuit 35. This predetermined constant is 0. The switching of the first switch 34 is synchronized with the switching of the second switch 71 in the selection unit 13, which will be described later. When the first processing unit 11 is used as a feedback control loop, the output from the adder 33 is supplied to the first integrating circuit 35, and when the second processing unit 12 is used as the same loop, the first switch 34 is switched to supply the constant 0 to the first integrating circuit 35.

[0023] The first integrating circuit 35 comprises a first adder 45, a saturation processing circuit 46, and a delay circuit 47, with these components arranged in this order toward the later stages. The output of the delay circuit 47 is input to the selection unit 13 as a first digital signal and is also fed back to the first adder 45. In the first adder 45, the frequency value of the signal thus fed back is added to the frequency value of the signal supplied via the first switch 34, and this added value is input to the saturation processing circuit 46.

[0024] The saturation processing circuit 46 outputs a signal to the delay circuit 47 for the input value when it is less than a predetermined lower limit, for the input value when it is greater than a predetermined upper limit, and for the input value when it is greater than or equal to the lower limit and less than or equal to the upper limit. Therefore, the saturation processing circuit 46 is a selective output unit that selects and outputs either the output signal from the first adder 45 or a preset signal. By including such a saturation processing circuit 46, the first integrator 35 not only smooths the output to the subsequent stage, but also contributes to rapid frequency pull-in by keeping the input value to the delay circuit 47 within a predetermined range.

[0025] Incidentally, the error frequency change amount df1, which is the output of the adder 33 of the first processing unit 11 described above, is also supplied to the pull detection unit 16. The pull detection unit 16 is configured as a monitoring unit that monitors this error frequency change amount df1 and compares it with a threshold. If, as a result of this comparison, it is determined that the error frequency change amount df1 exceeds the threshold, the pull detection unit 16 outputs a signal to switch the first switch 34 and the second switch 71.

[0026] Next, the second processing unit 12 will be described. This second processing unit 12, which forms the loop filter of the PLL circuit, includes an imaginary part extraction unit 51, multipliers 52-54 for adjusting the loop gain of the filter, a second adder 55, and a second integrating circuit 56. The imaginary part extraction unit 51 outputs the value of the imaginary part of the rotation vector V to the multipliers 52 and 53. The reason for outputting the value of the imaginary part to the subsequent stage is that when the control loop is formed by the second processing unit 12, the phase difference between the output frequency from the ADC 23 and the reference frequency is suppressed by the frequency pull-in by the first processing unit 11, and in such a suppressed phase difference state, the imaginary part represents that phase difference.

[0027] A second integrator 56 and a second adder 55 are provided after multipliers 52 and 53, respectively. A multiplier 54 is provided after the second integrator 56, and the output of multiplier 54 is input to the second adder 55. For multipliers 52 and 53, in addition to the output from the imaginary part extraction unit 51, a constant (i.e., a pre-set signal) is input, and the product of these input values ​​is output to the next stage. For multiplier 54, in addition to the output value from the second integrator 56, a constant is input, and the product of these input values ​​is output to the next stage.

[0028] The second integrating circuit 56 includes an adder 61 and a delay circuit 62 located downstream of the adder 61. The output of the delay circuit 62 is fed back to the adder 61. In the adder 61, the value thus fed back is added to the output value from the multiplier 52, and the resulting sum is output to the second delay circuit 62. In the second adder 55, the output values ​​from the multipliers 53 and 54 are added together, and the signal of this sum is output to the selection unit 13 as a second digital signal. Although not shown in the figure, a circuit is provided to reset the value held in the second delay circuit 62. This reset is performed at the timing when the first switch 34 and the second switch 71 are operated so that the first processing unit 11 forms a loop.

[0029] Next, the selection unit 13 will be described. The selection unit 13 consists of a second switch 71 and an adder 72 located downstream of the second switch 71. The second switch 71, together with the first switch 34 described above, forms a switching unit for switching the control loop, and selectively outputs one of the following to the adder 72: the output from the second adder 55 of the second processing unit 12, and a constant (i.e., a preset signal) supplied from a parameter supply unit (not shown). This constant is, for example, 0.

[0030] In the adder 72, the signal value supplied via the second switch 71 and the signal value from the first integrating circuit 35 of the first processing unit 11 are added together, and the signal of the added value (addition signal) is output to the DAC 24. The DAC 24 then outputs a voltage signal corresponding to the addition signal.

[0031] The operation of the frequency synthesizer 1 described above will now be explained. After the user inputs a set frequency, when a predetermined operation start instruction is given via an operation unit (not shown), a constant 0 is output to the adder 72 via the second switch 71 of the selection unit 13, and the output from the adder 33 is input to the first integrator circuit 35 via the first switch 34 of the first processing unit 11, resulting in a first state. Figure 2 above shows this first state. At the same time that the operation of the first switch 34 and the second switch 71 is controlled in this way, the value held in the delay circuit 62 in the second integrator circuit 56 of the second processing unit 12 is reset.

[0032] As previously described, the first processing unit 11 forms a feedback control loop for the output frequency fout of the VCO21, and an output corresponding to the rotation vector V generated by the phase comparison unit 14 is supplied to the adder 72. As described above, the other input to the adder 72 by the second switch 71 is 0, so the output of the adder 72 is the same as the output of the first processing unit 11 and is supplied to the DAC24. A control voltage Vc corresponding to the output to the DAC24 is applied to the VCO21.

[0033] With the formation of this control loop by the first processing unit 11, the oscillation output of the VCO 21 is obtained, while the pull detection unit 16 determines whether the error frequency change amount df1, which is the output from the adder 33, exceeds a threshold. If it is determined that it does not exceed the threshold, the states of the first switch 34 and the second switch 71 are maintained. That is, the formation of the control loop by the first processing unit 11 is maintained. Then, as the control voltage Vc supplied to the VCO 21 increases due to the action of the first processing unit 11, the output frequency fout increases and the pull of the output frequency fout to the set frequency progresses.

[0034] As the pull-in progresses, the error frequency df gradually decreases, and when the pull-in detection unit 16 determines that the error frequency change amount df1 exceeds a threshold, the first switch 34 and the second switch 71 are switched. Specifically, as shown in Figure 3, the second switch 71 replaces the constant 0 and supplies the output from the second adder 55 of the second processing unit 12 to the adder 72 of the selection unit 13, and the first switch 34 replaces the output from the adder 33 and outputs the constant 0 to the first integrating circuit 35, resulting in a second state.

[0035] In this second state, a constant 0 is input to the first adder 45, which constitutes the first integrating circuit 35 of the first processing unit 11, so the output from the first adder 45 becomes constant. Therefore, the output from the first integrating circuit 35, i.e., from the first processing unit 11 to the adder 72, is maintained at the output at the time of switching to the second state. Then, an output corresponding to the rotation vector V is supplied from the second processing unit 12 to the adder 72 and added to the output from the first processing unit 11. The added output is supplied to the DAC 24, and a control voltage Vc corresponding to the output to the DAC 24 is applied to the VCO 21. Thus, a feedback control loop is formed by the second processing unit 12 instead of the first processing unit 11. Through the action of the second processing unit 12, the output frequency fout approaches the set frequency and eventually matches and locks.

[0036] To demonstrate the advantages of frequency synthesizer 1 described above, the configuration of comparative frequency synthesizer 8 will be explained, focusing on the differences from frequency synthesizer 1, with reference to Figure 4. In frequency synthesizer 8, the selection unit 13 and the pull-in detection unit 16 are not provided, and a DAC 24 is provided after the first processing unit 11 and the second processing unit 12, respectively, and an LPF 25 is provided after each DAC 24.

[0037] Hereafter, the DAC24 and LPF25 after the first processing unit 11 will be referred to as DAC24A and LPF25A, and the DAC24 and LPF25 after the second processing unit 12 will be referred to as DAC24B and LPF25B. The outputs from LPF25A and LPF25B are input to the coupler 81, and the coupler 81 applies a voltage equivalent to the sum of these outputs as a control voltage Vc to the VCO21. In addition, the first processing unit 11 of the frequency synthesizer 8 does not have a first switch 34, and the output of the adder 33 in the first processing unit 11 is directly input to the first integrating circuit 35.

[0038] In this frequency synthesizer 8, since the DAC24 and LPF25 are provided in conjunction with each of the first processing unit 11 and the second processing unit 12, the manufacturing cost may be relatively high. Conversely, in frequency synthesizer 1, where the DAC24 and LPF25 are common to both the first processing unit 11 and the second processing unit 12, the manufacturing cost can be reduced. Furthermore, frequency synthesizer 1 is preferable from the standpoint of reducing power consumption during operation because it has fewer DAC24 and LPF25 units.

[0039] Incidentally, in the case of frequency synthesizer 8, just like frequency synthesizer 1, the second processing unit 12 plays a role in fine-tuning the output frequency fout. For this reason, the DAC24B attached to the second processing unit 12 needs to have relatively good phase noise characteristics, but the DAC24A attached to the first processing unit 11, which performs coarse adjustment, does not need to have phase noise characteristics as good as the DAC24B. Therefore, in order to reduce the manufacturing cost of frequency synthesizer 8, it is conceivable to use a DAC24A with inferior phase noise characteristics compared to the DAC24B.

[0040] However, in that case, in order to suppress the noise contained in the output of VCO21 after the output frequency fout of VCO21 is locked, the cutoff frequency of LPF25A needs to be set to a relatively low value, for example, around several hundred Hz. If the cutoff frequency of LPF25A is set in such a low value, the rise in the control voltage Vc supplied to VCO21 after the user gives the command to start operation will be suppressed, so the speed at which the output frequency fout is drawn to the set frequency will be slower, and the time required from the command to start operation until the output frequency fout is locked will be longer. As described above, with respect to the frequency synthesizer 8, it can be difficult to keep the time required to lock the output frequency fout while keeping the manufacturing cost at the desired cost.

[0041] On the other hand, for frequency synthesizer 1, only one DAC24 is required, and this DAC24 should have good phase noise characteristics. Because the phase noise characteristics of the DAC24 are good, even if the cutoff frequency of the subsequent LPF25 is relatively low, noise is less likely to be introduced into the output frequency fout after it has locked to the set frequency. Therefore, the cutoff frequency can be set to a relatively high value, as exemplified, allowing for a relatively large speed at which the output frequency fout is drawn to the set frequency. Thus, for frequency synthesizer 1, it is possible to reduce manufacturing costs while minimizing the time required to lock the output frequency fout.

[0042] By the way, when switching the first switch 34 and the second switch 71, it is not limited to monitoring the error frequency change amount df1 described above, but may also be done by monitoring other parameters that change in accordance with the change in the output frequency fout from the VCO21. Specifically, for example, the output value from the ADC23 may be monitored and the first switch 34 and the second switch 71 may be switched based on a comparison with a threshold, or the error frequency df may be monitored.

[0043] Furthermore, the second processing unit 12 described above is configured such that the output from the imaginary part extraction unit 51 is supplied to a system including an integrating circuit 56 (integrating system) and a system including only a multiplier 53 without an integrating circuit 56 (direct system), and the outputs of the integrating system and the direct system are added by the second adder 55 and output. However, it is sufficient if a signal to eliminate the phase difference between the reference frequency and the frequency of the output signal from the ADC 23 is output to the subsequent stage. Therefore, the configuration is not limited to this, and for example, a configuration that includes only one of the direct system and the integrating system may also be used.

[0044] Furthermore, the rotation vector V, the error frequency df and error frequency change amount df1 calculated from the rotation vector V, and the imaginary part of the rotation vector V input to the second processing unit 12 all correspond to signals corresponding to the phase difference between the reference frequency and the frequency of the output signal from the ADC23. Since the reference frequency corresponds to the set frequency, these rotation vectors V, etc., are also signals corresponding to the phase difference between the set frequency and the frequency of the output signal from the ADC23.

[0045] The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. The above embodiments may be omitted, replaced, modified and combined in various ways without departing from the scope and spirit of the appended claims.

[0046] [Evaluation Test] The phase noise characteristics of frequency synthesizers 1 (described in Figure 1) and 8 (described in Figure 4) were evaluated. For the evaluation, the frequency division ratio of the frequency divider 22 was set to 1 for frequency synthesizers 1 and 8, and the set frequency was 950 MHz. The cutoff frequencies of LPF25 for frequency synthesizer 1 and LPF25B for frequency synthesizer 8 were 250 kHz, as exemplified in the embodiment, and the cutoff frequency of LPF25A for frequency synthesizer 8 was several hundred Hz. As a result of measurements performed with these settings, the phase noise characteristics for frequency synthesizers 1 and 8 were approximately -130 dBc / Hz.

[0047] Furthermore, for frequency synthesizers 1 and 8, the time from power-on until the set frequency is output (the time required to lock the output frequency fout) was also measured. For frequency synthesizer 8, this was 200 milliseconds, while for frequency synthesizer 1, it was 200 microseconds. Therefore, this evaluation test demonstrated that, for frequency synthesizer 1, the time required to lock the output frequency fout can be shortened without degrading the phase noise characteristics compared to frequency synthesizer 8. [Explanation of symbols]

[0048] 1. Frequency Synthesizer 11. Section 1 12 Second Processing Unit 21. Voltage-controlled oscillator (VCO) 23. Analog-to-Digital Converter (ADC) 24. Digital-to-Analog Converter (DAC) 34. Switch 1 71 Second switch

Claims

1. A voltage-controlled oscillator that outputs a frequency signal corresponding to the control voltage, An analog-to-digital converter that digitizes the frequency signal corresponding to the output of the voltage-controlled oscillator, A first processing unit and a second processing unit each process the digitized frequency signal and output a first digital signal and a second digital signal for frequency adjustment, respectively, in order to eliminate the phase difference between the digitized frequency signal and the reference frequency signal. An adder that outputs an added signal obtained by adding the output from the first processing unit and the output from the second processing unit to a subsequent stage, A digital-to-analog converter is provided downstream of the adder, to be shared by the first and second processing units, and which converts the input signal to analog and outputs it in order to generate the control voltage. A monitoring unit that monitors parameters that change in accordance with changes in the frequency signal corresponding to the control voltage, A switching unit that switches from a first state in which only the first digital signal among the first and second digital signals is supplied to the adder, to a second state in which the second digital signal and the first digital signal, set to a fixed value, are each supplied to the adder, based on the parameters, A frequency synthesizer equipped with [features / equipment].

2. The first processing unit includes a first integrating circuit and The first integrator is switched so that in the first state a signal corresponding to the phase difference is input to the first integrator, and in the second state a preset signal is input to the first integrator, and the first switch forming the switching unit is included, The frequency synthesizer according to claim 1, wherein a second switch is provided between the adder and the second processing unit, which switches between inputting a preset signal in the first state and a signal from the second processing unit in the first state, and the switch forming the switching unit.

3. The first integrating circuit is, Delay circuit and, A first adder is provided prior to the aforementioned delay circuit, and the output signal of the delay circuit is fed back and input to it. Between the first adder and the delay circuit, there is a selection output unit that outputs to the delay circuit one of the output signals from the first adder and a preset signal, in accordance with the output signal from the first adder. The frequency synthesizer according to claim 2, comprising:

4. A low-pass filter is interposed between the digital-to-analog converter and the voltage-controlled oscillator. The frequency synthesizer according to claim 3, wherein the cutoff frequency of the low-pass filter is 100 kHz or higher.

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