Package with optical integrated devices

Abstract

A package comprising: a package substrate; a first integrated device coupled to the package substrate via a plurality of first solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects at least partially located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion via a plurality of second solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Description

Technical Field

[0001] (Cross - Reference to Related Applications)

[0001] This application claims the priority and benefit of non - provisional patent application No. 18 / 340,733, filed with the United States Patent and Trademark Office on June 23, 2023, and the entire content thereof is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes.

[0002]

[0002] Various features relate to packages including integrated devices.

Background Art

[0003]

[0003] A package may include a substrate and an integrated device. These components are coupled together to provide a package that can perform various functions. The performance of the package and its components can depend on many factors. There is a current need to provide packages that offer improved performance. Further, there is a current need to include packages with a more compact form factor so that the package can be implemented within a smaller device.

Summary of the Invention

[0004]

[0004] Various features relate to packages including integrated devices.

[0005]

[0005] One example is a package comprising: a first package substrate; a second package substrate bonded to the first package substrate via a plurality of first solder interconnects; a first integrated device bonded to the second package substrate via a plurality of second solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion bonded to the plurality of post interconnects; a second integrated device bonded to the metallization portion via a plurality of third solder interconnects; an optical integrated device bonded to the first package substrate; and an optical fiber bonded to the optical integrated device.

[0006]

[0006] Another example is a package comprising a first package substrate, an intermediate portion coupled to the first package substrate via a first plurality of solder interconnects, the intermediate portion including a first integrated device and a first sealing layer, a second integrated device coupled to the intermediate portion via a second plurality of solder interconnects, a second sealing layer that at least partially seals the first integrated device, a plurality of post interconnects located within the sealing layer, a metallization portion coupled to the plurality of post interconnects, a third integrated device coupled to the metallization portion via a third plurality of solder interconnects, an optical integrated device coupled to the first package substrate, and an optical fiber coupled to the optical integrated device. [Brief explanation of the drawing]

[0007]

[0007] By reading the "Modes for Carrying Out the Invention" described below in conjunction with the drawings, various features, essences, and advantages can be revealed. In the drawings, the same reference numerals throughout indicate corresponding parts. [Figure 1]

[0008] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 2]

[0009] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 3]

[0010] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 4]

[0011] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 5]

[0012] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 6]

[0013] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 7]

[0014] An exemplary cross-sectional view of an optically integrated device is shown. [Figure 8]

[0015] An exemplary cross-sectional view of an optically integrated device is shown. [Figure 9]

[0016] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 10]

[0017] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 11]

[0018] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 12]

[0019] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 13]

[0020] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 14]

[0021] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 15]

[0022] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 16]

[0023] A cross-sectional view of an exemplary package containing an optical integrated device is shown. [Figure 17A]

[0024] This shows an exemplary sequence for fabricating a package containing an optically integrated device. [Figure 17B] An exemplary sequence for fabricating a package including an optical integrated device is shown. [Figure 17C] An exemplary sequence for fabricating a package including an optical integrated device is shown. [Figure 17D] An exemplary sequence for fabricating a package including an optical integrated device is shown. [Figure 17E] An exemplary sequence for fabricating a package including an optical integrated device is shown. [Figure 18]

[0025] An exemplary flowchart of a method for fabricating a package including an optical integrated device is shown. [Figure 19]

[0026] Various electronic devices that can integrate a die, an integrated device, an integrated passive device (IPD), passive components, a package, and / or the device packages described herein are shown.

Embodiments of the Invention

[0008]

[0027] In the following description, specific details are set forth in order to provide a thorough understanding of the various aspects of the present disclosure. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details. For example, circuits may be shown in block diagrams in order to avoid obscuring the aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure the aspects of the present disclosure.

[0009]

[0028] This disclosure describes a package comprising: a first package substrate; a second package substrate coupled to the first package substrate via a plurality of first solder interconnects; a first integrated device coupled to the second package substrate via a plurality of second solder interconnects; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnects located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion via a plurality of third solder interconnects; an optical integrated device coupled to the first package substrate; and an optical fiber coupled to the optical integrated device. The optical integrated device coupled to the package substrate reduces the distance of at least one electrical path from the package to various integrated devices. Furthermore, the proximity of the optical integrated device to the integrated devices reduces IR drop, which helps improve the performance of the integrated devices and / or the package.

[0010] Exemplary package with optical integrated device

[0029] Figure 1 shows a cross-sectional view of a package 100 including an optical integrated device. The package 100 includes an optical integrated device 101, a package substrate 102a, a package substrate 102b, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, and a sealing layer 106. Note that the package substrate 102b may be mounted as an interposer including through silicon vias (TSVs). The interposer may include a silicon substrate having vias that extend perpendicularly through the silicon substrate.

[0011]

[0030] The package substrate 102a includes at least one dielectric layer 120a and a plurality of interconnection parts 122a (e.g., substrate interconnection parts). The optical integrated device 101 is coupled to the package substrate 102a. For example, the optical integrated device 101 may be embedded within the package substrate 102a. In some mounting configurations, the optical integrated device 101 may be located within a cavity in the package substrate 102a. The package substrate 102a may be a first package substrate. The optical integrated device 101 may be coupled to the package substrate 102a via an adhesive (not shown). The optical fiber 110 is coupled to the optical integrated device 101. The optical fiber 110 may be considered part of the package 100. The optical fiber 110 may be coupled to another optical integrated device (not shown). Other optical integrated devices may be coupled to another package or board. An example of the optical integrated device 101 is shown and illustrated in Figure 7 below. Optical integrated devices may include (i) the ability to convert optical signals / optical energy into electrical signals / optical energy, and / or (ii) the ability to convert electrical signals / electrical energy into optical signals / optical energy. For example, a signal may be received as an optical signal and converted into an electrical signal. Similarly, a signal may be received as an electrical signal and converted into an optical signal. Optical integrated devices may transmit signals as optical signals and / or electrical signals.

[0012]

[0031] The package substrate 102b includes at least one dielectric layer 120b and a plurality of interconnection parts 122b (e.g., substrate interconnection parts). The package substrate 102b may be a second package substrate. The package substrate 102b is bonded to the package substrate 102a via a plurality of solder interconnection parts 123. The plurality of solder interconnection parts 123 may be bonded to the plurality of interconnection parts 122a and the plurality of interconnection parts 122b. The package substrate 102b may also be bonded to the optical integrated device 101 via the plurality of solder interconnection parts 123. There is an underfill 127 between the package substrate 102a and the package substrate 102b. The underfill 127 may laterally surround the plurality of solder interconnection parts 123.

[0013]

[0032] The sealing layer 106 can at least partially seal the integrated device 103, integrated device 105, and the plurality of post interconnects 160. Integrated device 103 is bonded to the package substrate 102b via solder interconnects from the plurality of solder interconnects 163. The surface of integrated device 103 faces the package substrate 102b. Integrated device 105 is bonded to the package substrate 102b via other solder interconnects from the plurality of solder interconnects 163. The surface of integrated device 105 faces the package substrate 102b. The plurality of post interconnects 160 are bonded to the package substrate 102b via other solder interconnects from the plurality of solder interconnects 163. There is an underfill 125 between the package substrate 102b and the sealing layer 106. The underfill 125 may laterally surround the plurality of solder interconnects 163. The underfill 125 is coupled to and can come into contact with the package substrate 102b, the plurality of solder interconnects 123, the sealing layer 106, the integrated device 103, and the integrated device 105.

[0014]

[0033] The metallization portion 104 is coupled to the sealing layer 106 and a plurality of post interconnects 160. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 may be a redistribution portion. The plurality of metallization interconnects 142 may include redistribution interconnects. The plurality of post interconnects 160 may be coupled to metallization interconnects from the plurality of metallization interconnects 142 of the metallization portion 104. The back surface of the integrated device 103 may face the metallization portion 104. The back surface of the integrated device 105 may face the metallization portion 104. The bottom surface of the metallization portion 104 may be coupled to the sealing layer 106.

[0015]

[0034] The passive device 111 can be coupled to the upper surface of the metallization portion 104 via a plurality of solder interconnects 112. For example, the passive device 111 can be coupled to metallization interconnects from a plurality of metallization interconnects 142 via a plurality of solder interconnects 112.

[0016]

[0035] The integrated device 109 can be coupled to the upper surface of the metallization portion 104 via a plurality of solder interconnects 190. For example, the integrated device 109 can be coupled to metallization interconnects from a plurality of metallization interconnects 142 via a plurality of solder interconnects 190. The integrated device 130 can be coupled to the upper surface of the metallization portion 104 via a plurality of solder interconnects 131. For example, the integrated device 130 can be coupled to metallization interconnects from a plurality of metallization interconnects 142 via a plurality of solder interconnects 131.

[0017]

[0036] Integrated device 132 is coupled to integrated device 130 via a plurality of solder interconnects 133. Integrated device 134 is coupled to integrated device 132 via a plurality of solder interconnects 135. Integrated devices 130, 132, and 134 may be stack-type integrated devices.

[0018]

[0037] The connector socket 107 is coupled to the upper surface of the metallization portion 104 via a plurality of solder interconnects 170. The connector socket 107 is configured to be electrically coupled to the connector socket 113. The connector socket 107 is configured to provide an electrical path for power. The connector socket 107 is configured to provide an electrical path for grounding. The connector socket 107 may be coupled to the connector socket 113 via one or more wires.

[0019]

[0038] Package 100 is coupled to board 108 via a plurality of solder interconnects 183. Board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. Connector socket 113 is coupled to board 108 via a plurality of solder interconnects 114.

[0020]

[0039] The optical fiber 110 is coupled to the optical integration device 101. The optical fiber 110 may extend through the package substrate 102a. The optical fiber 110 may extend through cavities within the package substrate 102a. In some configurations, the optical fiber 110 may extend into the board 108. In some configurations, the optical fiber 110 may extend between the package substrate 102a and the board 108. One or more optical signals may propagate through the optical fiber 110 to and / or from the optical integration device 101.

[0021]

[0040] The integrated device 103 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path 151 that includes solder interconnects from a plurality of solder interconnects 163, a package substrate 102b, and solder interconnects from a plurality of solder interconnects 123. The integrated device 105 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path 153 that includes solder interconnects from a plurality of solder interconnects 163, a package substrate 102b, and solder interconnects from a plurality of solder interconnects 123. The integrated device 103 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path that includes solder interconnects from a plurality of solder interconnects 163, a package substrate 102b, and other solder interconnects from a plurality of solder interconnects 163. In some implementation configurations, the integrated device 103 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path that includes solder interconnects from a plurality of solder interconnects 163, a package substrate 102b, solder interconnects from a plurality of solder interconnects 123, the optical integrated device 101, solder interconnects from a plurality of solder interconnects 123, the package substrate 102b, and another solder interconnect from a plurality of solder interconnects 163. The integrated device 130 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path 155 that includes solder interconnects from a plurality of solder interconnects 131, a metallization interconnect from a metallization portion 104, post interconnects from a plurality of post interconnects 160, solder interconnects from a plurality of solder interconnects 163, the package substrate 102b, and solder interconnects from a plurality of solder interconnects 123. The electrical path 155 may include an electrical path between integrated device 130 and integrated device 134.The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects described above.

[0022]

[0041] The integrated device 130 may be configured to be electrically coupled to the integrated device 103 via an electrical path 157 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, post interconnects from a plurality of post interconnects 160, solder interconnects from a plurality of solder interconnects 163, interconnects from a package substrate 102b, and other solder interconnects from a plurality of solder interconnects 163. The electrical path 157 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects described above.

[0023]

[0042] The integrated device 130 may be configured to be electrically coupled to the integrated device 105 via an electrical path 159 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, post interconnects from a plurality of post interconnects 160, solder interconnects from a plurality of solder interconnects 163, interconnects from a package substrate 102b, and other solder interconnects from a plurality of solder interconnects 163. The electrical path 159 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects described above.

[0024]

[0043] In some implementations, the optical signal may be received by the optical integrator 101 via the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using one or more of the electrical paths described above.

[0025]

[0044] In some implementations, electrical signals may be received by the optical integrated device 101 via one or more of the electrical paths described above. The electrical signals may be converted into optical signals by the optical integrated device 101, and the optical signals may be transmitted via the optical fiber 110.

[0026]

[0045] The integrated device 103 may be a system on a chip (SoC). The integrated device 109 may include a power management integrated circuit (PMIC). The passive device 111 may include a capacitor. The integrated devices 130, 132, and / or 134 may include memory. The electrical path between the integrated device 109 and the integrated device 130 may include solder interconnects from a plurality of solder interconnects 190, metallization interconnects from a plurality of metallization interconnects 142, and solder interconnects from a plurality of solder interconnects 131. The electrical path between the integrated device 109 and the integrated device 134 may include the electrical path between the integrated device 130 and the integrated device 134, as described above.

[0027]

[0046] In some implementations, the optical integrated device 101 may be configured to operate as a bridge. The integrated device 103 may be configured to be electrically coupled to the integrated device 105 via the optical integrated device 101. For example, the electrical path between the integrated device 103 and the integrated device 105 may include the optical integrated device 101. The electrical path between the integrated device 103 and the integrated device 105 may include the electrical path 151 (as described above), the interconnect from the optical integrated device 101, and the electrical path 153 (as described above).

[0028]

[0047] Figure 2 shows a cross-sectional view of a package 200 including an optical integrated device. The package 200 includes an optical integrated device 101, a package substrate 102a, a package substrate 102b, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, a sealing layer 206, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205. Note that the package substrate 102b may be mounted as an interposer including through-silicon vias (TSVs). The interposer may include a silicon substrate having vias extending perpendicularly through the silicon substrate. The interposer may also include surface pads and / or surface traces on a first surface and / or a second surface of the interposer.

[0029]

[0048] At least one back-side power rail interconnect 203 can be considered part of the integrated device 103. For example, at least one back-side power rail interconnect 203 may be located within the die substrate of the integrated device 103. The back-side power rail interconnect 203 may include trace interconnects and / or through-substrate vias. The back-side power rail interconnect 203 can be considered part of the back surface of the integrated device 103. At least one back-side power rail interconnect 205 can be considered part of the integrated device 105. For example, at least one back-side power rail interconnect 205 may be located within the die substrate of the integrated device 105. The back-side power rail interconnect 205 may include trace interconnects and / or through-substrate vias. The back-side power rail interconnect 205 can be considered part of the back surface of the integrated device 105.

[0030]

[0049] Package 200 is similar to package 100. However, some of the components of package 200 are located and / or combined in a different way than some of the components in package 100.

[0031]

[0050] The integrated device 103 is coupled to the bottom surface of the metallization portion 104 via a plurality of solder interconnects 223. The surface of the integrated device 103 may face the metallization portion 104. The integrated device 105 is coupled to the bottom surface of the metallization portion 104 via a plurality of solder interconnects 225. The surface of the integrated device 105 may face the metallization portion 104. The integrated device 109 is coupled to the bottom surface of the metallization portion 104 via a plurality of solder interconnects 190. The passive device 111 is coupled to the bottom surface of the metallization portion 104 via a plurality of solder interconnects 112. The sealing layer 106 can at least partially seal the integrated device 103, integrated device 105, integrated device 109, passive device 111, the back surface power rail interconnect 203, the back surface power rail interconnect 205, and the plurality of post interconnects 160. The sealing layer 106 may include a mold, resin, and / or epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the sealing layer 106.

[0032]

[0051] The package substrate 102b is bonded to the package substrate 102a via a plurality of solder interconnections 123. The integrated device 103 is bonded to the package substrate 102b via a plurality of solder interconnections 163. The integrated device 105 is bonded to the package substrate 102b via a plurality of solder interconnections 163.

[0033]

[0052] The package 200 is coupled to the board 108 via multiple solder interconnects 183. The connector socket 113 is coupled to the board 108 via multiple solder interconnects 114.

[0034]

[0053] The integrated device 130 may be configured to be electrically coupled to the integrated device 103 via an electrical path 257 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 223. The integrated device 130 may be configured to be electrically coupled to the integrated device 105 via an electrical path 259 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 225. The electrical path 257 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, there may be pillar interconnects between (i) integrated device 130 and integrated device 132 and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the pillar interconnects described above. The electrical path 259 may include the electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some mounting configurations, pillar interconnects may be present between (i) integrated device 130 and integrated device 132 and / or between integrated device 132 and integrated device 134.In such cases, the electrical path between the integrated device 130 and the integrated device 134 may also include the pillar interconnect described above.

[0035]

[0054] The integrated device 130 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path 255 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, post interconnects from a plurality of post interconnects 160, solder interconnects from a plurality of solder interconnects 163, the package substrate 102b, and solder interconnects from a plurality of solder interconnects 123. The electrical path 255 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between the integrated device 130 and the integrated device 134 may include die interconnects from the integrated device 130, through-substrate vias from the integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from the integrated device 132, through-substrate vias from the integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from the integrated device 134. In some implementations, pillar interconnects may exist between (i) integrated device 130 and integrated device 132, and / or between integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnects.

[0036]

[0055] In some implementation configurations, the integrated device 103 may be configured to be electrically coupled to the integrated device 105 via a plurality of solder interconnects 223, metallization interconnects from a plurality of metallization interconnects 142, and a plurality of solder interconnects 225.

[0037]

[0056] In some implementations, the integrated device 103 may be configured to be electrically coupled to the integrated device 105 via solder interconnects from multiple solder interconnects 163, the package substrate 102b, and other solder interconnects from the multiple solder interconnects 163. In some implementations, the optical integrated device 101, the integrated device 103, and / or the integrated device 105 may be one or more chiplets. In some implementations, the integrated device 103 may be fabricated using a first technology node, and the integrated device 105 may be fabricated using a second technology node that is less advanced than the first technology node. The optical integrated device 101 may be fabricated using a third technology node different from the first and / or second technology nodes.

[0038]

[0057] In some implementations, the optical signal may be received by the optical integrator 101 via the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using one or more of the electrical paths described above.

[0039]

[0058] In some implementations, electrical signals may be received by the optical integrated device 101 via one or more of the electrical paths described above. The electrical signals may be converted into optical signals by the optical integrated device 101, and the optical signals may be transmitted via the optical fiber 110.

[0040]

[0059] The optical integrated device 101 is coupled to the package substrate 102a. For example, the optical integrated device 101 may be embedded within the package substrate 102a. In some mounting configurations, the optical integrated device 101 may be located within a cavity in the package substrate 102a. The optical integrated device 101 may be coupled to the package substrate 102a via at least one bump interconnect and / or at least one solder interconnect. The optical fiber 110 is coupled to the optical integrated device 101. The optical fiber 110 may be considered part of the package 200.

[0041]

[0060] Power may be supplied to the integrated device 103 via its back surface. For example, an electrical path for power to the integrated device 103 may include interconnects from a plurality of interconnects 122b, at least one solder interconnect from a plurality of solder interconnects 123, and at least one back surface power rail interconnect 203. Similarly, power may be supplied to the integrated device 105 via its back surface. For example, an electrical path for power to the integrated device 105 may include interconnects from a plurality of interconnects 122a, at least one solder interconnect from a plurality of solder interconnects 123, and at least one back surface power rail interconnect 205.

[0042]

[0061] Figure 3 shows a cross-sectional view of a package 300 including an optical integrated device. The package 300 includes an optical integrated device 101, a package substrate 102a, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0043]

[0062] Package 300 is similar to package 200. However, some of the components of package 300 are located and / or combined in a different way than some of the components in package 200.

[0044]

[0063] For example, the optical integrated device 101 is coupled to the upper surface of the metallization portion 104 via a plurality of solder interconnects 310. An example of the optical integrated device 101 is shown and explained in Figure 8 below. The optical integrated device 101 is coupled to the optical integrated device 301 via an optical fiber 110. The optical integrated device 301 is coupled to the board 108. The optical integrated device 301 may be coupled to the board 108 via a plurality of solder interconnects.

[0045]

[0064] The integrated device 130 may be configured to be electrically coupled to the integrated device 103 via an electrical path 257 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 223. The integrated device 130 may be configured to be electrically coupled to the integrated device 105 via an electrical path that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 225.

[0046]

[0065] The integrated device 130 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path 355 that includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 310. The electrical path 355 may include an electrical path between the integrated device 130 and the integrated device 134. The electrical path between the integrated device 130 and the integrated device 134 may include die interconnects from the integrated device 130, through-substrate vias from the integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from the integrated device 132, through-substrate vias from the integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from the integrated device 134. In some implementations, pillar interconnects may exist between (i) integrated device 130 and integrated device 132, and / or between integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnects.

[0047]

[0066] The integrated device 103 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path 353 that includes solder interconnects from a plurality of solder interconnects 223, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 310.

[0048]

[0067] The integrated device 105 may be configured to be electrically coupled to the optical integrated device 101 via an electrical path 357 that includes solder interconnects from a plurality of solder interconnects 225, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 310.

[0049]

[0068] In some implementations, the optical signal may be received by the optical integrator 101 via the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using one or more of the electrical paths described above.

[0050]

[0069] In some implementations, electrical signals may be received by the optical integrated device 101 via one or more of the electrical paths described above. The electrical signals may be converted into optical signals by the optical integrated device 101, and the optical signals may be transmitted via the optical fiber 110.

[0051]

[0070] Figure 4 shows a cross-sectional view of a package 400 including an optical integrated device. The package 400 includes an optical integrated device 101, a package substrate 102a, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0052]

[0071] Package 400 is similar to package 300. However, some of the components of package 400 are located and / or coupled in a different manner than some of the components in package 300. For example, package substrate 102a includes interconnectors 122aa and 122ab. Interconnectors 122aa and 122ab are configured as a heat spreader within package substrate 102a. Board 108 includes board interconnectors 182a and 182b. A heat sink 403 is coupled to board 108. A thermal interface material may be used to couple the heat sink 403 to board 108. A heat sink 405 is coupled to board 108. A thermal interface material may be used to couple the heat sink 405 to board 108. The heat generated by the integrated device 103 and / or the back-side power rail interconnect 203 can be dissipated via the solder interconnects from the multiple solder interconnects 123, interconnect 122aa, the solder interconnects from the multiple solder interconnects 183, the board interconnect 182a, and the heat sink 403. The heat generated by the integrated device 105 and / or the back-side power rail interconnect 205 can be dissipated via the solder interconnects from the multiple solder interconnects 123, interconnect 122ab, the solder interconnects from the multiple solder interconnects 183, the board interconnect 182b, and the heat sink 405.

[0053]

[0072] In another example, multiple via interconnects 460 may be located within the sealing layer 206. The multiple via interconnects 460 may be located laterally on the package substrate 102b. The multiple via interconnects 460 may be coupled to multiple solder interconnects 123 and multiple solder interconnects 163.

[0054]

[0073] In some implementations, the integrated device 103 may be a first chiplet, and the integrated device 105 may be a second chiplet. The integrated device 103 may be configured to perform a first set of functions and / or operations. The integrated device 105 may be configured to perform a second set of functions and / or operations. The second set of functions and / or operations includes at least one function and / or operation that is different from the first set of functions and / or operations. In some implementations, the integrated device 103 may be fabricated using a first technology node, and the integrated device 105 may be fabricated using a second technology node that is less advanced than the first technology node.

[0055]

[0074] Figure 5 shows a cross-sectional view of a package 500 including an optical integrated device. The package 500 includes an optical integrated device 101, a package substrate 102a, a package substrate 102b, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0056]

[0075] Package 500 is similar to package 300 and / or package 400. However, some of the components of package 500 are located and / or combined in a different way than some of the components in package 300 and / or package 400.

[0057]

[0076] As shown in Figure 5, the optical integrated device 101 is coupled to the upper surface of the metallization portion 104 (for example, the second integrated device) via a plurality of solder interconnects 310. The integrated device 109 is coupled to the upper surface of the metallization portion 104 via a plurality of solder interconnects 190. The passive device 111 is coupled to the upper surface of the metallization portion 104 via a plurality of solder interconnects 112.

[0058]

[0077] In some implementations, the optical signal may be received by the optical integrator 101 via the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using at least one or more of the electrical paths described above in Figure 3.

[0059]

[0078] In some implementations, electrical signals can be received by the optical integrated device 101 via at least one or more of the electrical paths described above in Figure 3. The electrical signals can be converted into optical signals by the optical integrated device 101, and the optical signals can be transmitted via the optical fiber 110.

[0060]

[0079] Figure 5 shows that the package substrate 102b is bonded to the package substrate 102a via a plurality of solder interconnects 123. The integrated device 103 is bonded to the package substrate 102b via a plurality of solder interconnects 163. The integrated device 105 is bonded to the package substrate 102b via a plurality of solder interconnects 163. The underfill 125 can at least partially seal the plurality of solder interconnects 163. The underfill 125 and / or underfill 127 can each be sealing layers.

[0061]

[0080] Figure 6 shows a cross-sectional view of a package 600 including an optical integrated device. The package 600 includes an optical integrated device 101, a package substrate 102a, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0062]

[0081] Package 600 is similar to package 300 and / or package 400. However, some of the components of package 600 are positioned and / or combined differently from some of the components in package 300 and / or package 400.

[0063]

[0082] The package substrate 102a includes interconnection sections 122aa and 122ab. The interconnection sections 122aa and 122ab are configured as a heat spreader within the package substrate 102a. The board 108 includes board interconnection sections 182a and 182b. A heat sink 403 is bonded to the board 108. A thermal interface material may be used to bond the heat sink 403 to the board 108. A heat sink 405 is bonded to the board 108. A thermal interface material may be used to bond the heat sink 405 to the board 108. The heat generated by the integrated device 103 and / or the back-side power rail interconnection section 203 can be dissipated through the solder interconnection sections from the plurality of solder interconnection sections 123, interconnection section 122aa, the solder interconnection sections from the plurality of solder interconnection sections 183, board interconnection section 182a, and heat sink 403. The heat generated by the integrated device 105 and / or the back-side power rail interconnect 205 can be dissipated through the solder interconnects from the multiple solder interconnects 123, the interconnect 122ab, the solder interconnects from the multiple solder interconnects 183, the board interconnect 182b, and the heat sink 405.

[0064]

[0083] In some implementations, the optical signal may be received by the optical integrator 101 via the optical fiber 110. The optical signal may be converted into an electrical signal by the optical integrator 101, and the electrical signal may be sent to the integrator 103, integrator 105, and / or integrator 130 using at least one or more of the electrical paths described above in Figure 3.

[0065]

[0084] In some implementations, electrical signals can be received by the optical integrated device 101 via at least one or more of the electrical paths described above in Figure 3. The electrical signals can be converted into optical signals by the optical integrated device 101, and the optical signals can be transmitted via the optical fiber 110.

[0066]

[0085] Figure 6 shows that the package substrate 102b is bonded to the package substrate 102a via a plurality of solder interconnects 123. The integrated device 103 is bonded to the package substrate 102b via a plurality of solder interconnects 163. The integrated device 105 is bonded to the package substrate 102b via a plurality of solder interconnects 163. The sealing layer 206 can at least partially seal the plurality of solder interconnects 163 and / or the plurality of solder interconnects 123 of the package substrate 102b.

[0067]

[0086] It should be noted that any package may include additional and / or other components. For example, an integrated device may be replaced by a stack of integrated devices. For instance, integrated device 103 and / or integrated device 105 may each be replaced by a stack of integrated devices (similar to, for example, integrated devices 130, 132, and 134). A stack of integrated devices may include integrated devices with opposing faces, integrated devices with opposing faces and back faces, and / or integrated devices with opposing back faces. In another example, a substrate and / or interposer may be located between the package substrate 102a and integrated devices 103 and / or integrated devices 105.

[0068]

[0087] It should be noted that any of the multiple solder interconnects described herein may be implemented as multiple bump interconnects. Bump interconnects may include pillar interconnects and solder interconnects. In some implementations, multiple bump interconnects may include multiple microbump interconnects. Microbump interconnects may be similar to bump interconnects. However, microbump interconnects may have smaller dimensions than bump interconnects to accommodate finer interconnect pitches. For example, in some implementations, multiple solder interconnects 123 and / or multiple solder interconnects 163 may be implemented as multiple microbump interconnects, while multiple solder interconnects 183 may be implemented as multiple bump interconnects. In some implementations, one or more bump interconnects may have a pitch in the range of about 80 to 120 micrometers (e.g., minimum pitch). In some implementations, one or more microbump interconnects may have a pitch (e.g., minimum pitch) in the range of approximately 25 to 50 micrometers.

[0069] Exemplary optical integrated device

[0088] Figure 7 shows an exemplary optical integrated device 700. The optical integrated device 700 may be the optical integrated device 101 described in Figures 1 to 6 and Figures 9 to 16. The optical integrated device 700 includes a substrate 702 (e.g., a silicon substrate), an optical device 704, waveguides 706, 708, 709, an oxide layer 710, a plurality of interconnectors 730, and a fiber ferrule 720. The optical fiber 110 is coupled to waveguides 706 and fiber ferrule 720. Optical signals from the optical fiber 110 can propagate through waveguides 706, 709, and 708. The optical signals can be processed by optical device 704 and converted into electrical signals. The electrical signals can be transmitted through the plurality of interconnectors 730. The oxide layer 710 may surround waveguides 709 and 708. Waveguide 709 may contain silicon(S) or silicon nitride. Waveguide 709 may extend through the thickness of the substrate 702, such as through-silicon vias (TSVs). Waveguide 708 may contain silicon(S), germanium(Ge), or silicon nitride.

[0070]

[0089] Figure 8 shows an exemplary optical integrated device 800. The optical integrated device 800 may be the optical integrated device 101 described in Figures 1 to 6. The optical integrated device 800 includes a substrate 702 (e.g., a silicon substrate), an optical device 704, a waveguide 706, a plurality of interconnectors 830, a plurality of interconnectors 840, and a fiber ferrule 720. The optical fiber 110 is coupled to the waveguide 706 and the fiber ferrule 720. Optical signals from the optical fiber 110 can propagate through the waveguide 706. The optical signals can be processed by the optical device 704, and the optical signals can be converted into electrical signals. The electrical signals can be transmitted through the plurality of interconnectors 830 and / or the plurality of interconnectors 840.

[0071]

[0090] Although not shown, the fiber ferrule 720 may be coupled to a carrier (e.g., a silicon carrier), which is used to help couple the fiber ferrule 720 to the waveguide 706. In some implementations, two or more optical fibers may be present.

[0072]

[0091] Different implementations may use different waveguide designs. In some implementations, the waveguide may include silicon ridge waveguides, silicon rib waveguides, silicon slot waveguides, and / or silicon nitride ridge waveguides. However, other implementations may use other waveguide designs. For example, some implementations may use germanium in combination with silicon.

[0073] Exemplary package with optical integrated device

[0092] Figure 9 shows a cross-sectional view of a package 900 including an optical integrated device. The package 900 includes an optical integrated device 101, a package substrate 102, an intermediate portion 902, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0074]

[0093] Package 900 is similar to package 200. However, some of the components of package 900 are located and / or combined in a different way than some of the components in package 200.

[0075]

[0094] The intermediate portion 902 is coupled to the package substrate 102 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the optical integrated device 101 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the integrated device 103 and / or integrated device 105 via a plurality of solder interconnects 163. The intermediate portion 902 includes a sealing layer 906, integrated device 903, integrated device 905, and a plurality of via interconnects 960. In some mounting configurations, the plurality of solder interconnects 123 and / or the plurality of solder interconnects 163 may be considered as part of the intermediate portion 902.

[0076]

[0095] Integrated device 903 is coupled to integrated device 103 via solder interconnects from a plurality of solder interconnects 163. Integrated device 905 is coupled to integrated device 105 via solder interconnects from a plurality of solder interconnects 163. Integrated device 903 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Integrated device 905 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Optical integrated device 101 may be configured as a bridge (for electrical paths) between integrated device 903 and integrated device 905. Integrated devices 903 and 103 may be stacked integrated devices. Integrated devices 905 and 105 may be stacked integrated devices.

[0077]

[0096] Figure 9 shows an electrical path 1055 between the integrated device 130 and the optical integrated device 101. The electrical path 1055 may include at least one solder interconnect from a plurality of solder interconnects 131, at least one metallization interconnect from a plurality of metallization interconnects 142, at least one post interconnect from a plurality of post interconnects 160, at least one solder interconnect from a plurality of solder interconnects 163, at least one post interconnect from a plurality of via interconnects 960, and / or at least one solder interconnect from a plurality of solder interconnects 123.

[0078]

[0097] Figure 10 shows a cross-sectional view of a package 1000 including an optical integrated device. The package 1000 includes an optical integrated device 101, a package substrate 102, an intermediate portion 902, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0079]

[0098] Package 1000 is similar to package 100. However, some of the components of package 1000 are located and / or combined in a different way than some of the components in package 100.

[0080]

[0099] The intermediate portion 902 is coupled to the package substrate 102 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the optical integrated device 101 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the integrated device 103 and / or integrated device 105 via a plurality of solder interconnects 163. The intermediate portion 902 includes a sealing layer 906, integrated device 903, integrated device 905, and a plurality of via interconnects 960. In some mounting configurations, the plurality of solder interconnects 123 and / or the plurality of solder interconnects 163 may be considered as part of the intermediate portion 902.

[0081]

[0100] Integrated device 903 is coupled to integrated device 103 via solder interconnects from a plurality of solder interconnects 163. Integrated device 905 is coupled to integrated device 105 via solder interconnects from a plurality of solder interconnects 163. Integrated device 903 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Integrated device 905 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Optical integrated device 101 may be configured as a bridge (for electrical paths) between integrated device 903 and integrated device 905. Integrated devices 903 and 103 may be stacked integrated devices. Integrated devices 905 and 105 may be stacked integrated devices.

[0082]

[0101] Figure 11 shows a cross-sectional view of a package 1100 including an optical integrated device. The package 1100 includes an optical integrated device 101, a package substrate 102, an intermediate portion 902, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0083]

[0102] Package 1100 is similar to package 400. However, some of the components of package 1100 are located and / or combined in a different way than some of the components in package 400.

[0084]

[0103] The intermediate portion 902 is coupled to the package substrate 102 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the optical integrated device 101 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the integrated device 103 and / or integrated device 105 via a plurality of solder interconnects 163. The intermediate portion 902 includes a sealing layer 906, integrated device 903, integrated device 905, and a plurality of via interconnects 960. In some mounting configurations, the plurality of solder interconnects 123 and / or the plurality of solder interconnects 163 may be considered as part of the intermediate portion 902.

[0085]

[0104] Integrated device 903 is coupled to integrated device 103 via solder interconnects from a plurality of solder interconnects 163. Integrated device 905 is coupled to integrated device 105 via solder interconnects from a plurality of solder interconnects 163. Integrated device 903 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Integrated device 905 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Optical integrated device 101 may be configured as a bridge (for electrical paths) between integrated device 903 and integrated device 905. Integrated devices 903 and 103 may be stacked integrated devices. Integrated devices 905 and 105 may be stacked integrated devices.

[0086]

[0105] Figure 12 shows a cross-sectional view of a package 1200 including an optical integrated device. The package 1200 includes an optical integrated device 101, a package substrate 102, an intermediate portion 902, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0087]

[0106] Package 1200 is similar to package 500. However, some of the components of package 1200 are located and / or combined in a different way than some of the components in package 500.

[0088]

[0107] The intermediate portion 902 is coupled to the package substrate 102 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the optical integrated device 101 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the integrated device 103 and / or integrated device 105 via a plurality of solder interconnects 163. The intermediate portion 902 includes a sealing layer 906, integrated device 903, integrated device 905, and a plurality of via interconnects 960. In some mounting configurations, the plurality of solder interconnects 123 and / or the plurality of solder interconnects 163 may be considered as part of the intermediate portion 902.

[0089]

[0108] Integrated device 903 is coupled to integrated device 103 via solder interconnects from a plurality of solder interconnects 163. Integrated device 905 is coupled to integrated device 105 via solder interconnects from a plurality of solder interconnects 163. Integrated device 903 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Integrated device 905 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Optical integrated device 101 may be configured as a bridge (for electrical paths) between integrated device 903 and integrated device 905. Integrated devices 903 and 103 may be stacked integrated devices. Integrated devices 905 and 105 may be stacked integrated devices.

[0090]

[0109] Figure 13 shows a cross-sectional view of a package 1300 including an optical integrated device. The package 900 includes an optical integrated device 101, a package substrate 102, an intermediate portion 902, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0091]

[0110] Package 1300 is similar to package 200 and / or package 900. However, some of the components of package 1300 are located and / or combined in a different way than some of the components in package 200 and / or package 900.

[0092]

[0111] The intermediate portion 902 is coupled to the package substrate 102 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the optical integrated device 101 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the integrated device 103 and / or integrated device 105 via a plurality of solder interconnects 163. The intermediate portion 902 includes a sealing layer 906, integrated device 1303, integrated device 1305, and a plurality of via interconnects 960. In some mounting configurations, the plurality of solder interconnects 123 and / or the plurality of solder interconnects 163 may be considered as part of the intermediate portion 902.

[0093]

[0112] Integrated device 1303 is coupled to integrated device 103 via direct metal-to-metal bonding (e.g., hybrid bonding, copper-to-copper bonding). There are no solder interconnects between integrated device 1303 and integrated device 103. Therefore, there may be no solder interconnects in the electrical path between integrated device 1303 and integrated device 103. Integrated device 1305 is coupled to integrated device 105 via direct metal-to-metal bonding (e.g., hybrid bonding, copper-to-copper bonding). There are no solder interconnects between integrated device 1305 and integrated device 105. Therefore, there may be no solder interconnects in the electrical path between integrated device 1305 and integrated device 105.

[0094]

[0113] Integrated device 1303 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Integrated device 1305 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Optical integrated device 101 may be configured as a bridge (for electrical paths) between integrated device 1303 and integrated device 1305. Integrated devices 1303 and 103 may be stacked integrated devices. Integrated devices 1305 and 105 may be stacked integrated devices.

[0095]

[0114] Figure 14 shows a cross-sectional view of a package 1400 including an optical integrated device. The package 900 includes an optical integrated device 101, a package substrate 102, an intermediate portion 902, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0096]

[0115] Package 1400 is similar to package 100 and / or package 1000. However, some of the components of package 1400 are located and / or combined in a different way than some of the components in package 100 and / or package 1000.

[0097]

[0116] The intermediate portion 902 is coupled to the package substrate 102 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the optical integrated device 101 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the integrated device 103 and / or integrated device 105 via a plurality of solder interconnects 163. The intermediate portion 902 includes a sealing layer 906, integrated device 1303, integrated device 1305, and a plurality of via interconnects 960. In some mounting configurations, the plurality of solder interconnects 123 and / or the plurality of solder interconnects 163 may be considered as part of the intermediate portion 902.

[0098]

[0117] Integrated device 1303 is coupled to integrated device 103 via direct metal-to-metal bonding (e.g., hybrid bonding, copper-to-copper bonding). There are no solder interconnects between integrated device 1303 and integrated device 103. Therefore, there may be no solder interconnects in the electrical path between integrated device 1303 and integrated device 103. Integrated device 1305 is coupled to integrated device 105 via direct metal-to-metal bonding (e.g., hybrid bonding, copper-to-copper bonding). There are no solder interconnects between integrated device 1305 and integrated device 105. Therefore, there may be no solder interconnects in the electrical path between integrated device 1305 and integrated device 105.

[0099]

[0118] Integrated device 1303 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Integrated device 1305 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Optical integrated device 101 may be configured as a bridge (for electrical paths) between integrated device 1303 and integrated device 1305. Integrated devices 1303 and 103 may be stacked integrated devices. Integrated devices 1305 and 105 may be stacked integrated devices.

[0100]

[0119] Figure 15 shows a cross-sectional view of a package 1500 including an optical integrated device. The package 900 includes an optical integrated device 101, a package substrate 102, an intermediate portion 902, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0101]

[0120] Package 1500 is similar to package 400 and / or package 1100. However, some of the components of package 1500 are located and / or combined in a different way than some of the components in package 400 and / or package 1100.

[0102]

[0121] The intermediate portion 902 is coupled to the package substrate 102 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the optical integrated device 101 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the integrated device 103 and / or integrated device 105 via a plurality of solder interconnects 163. The intermediate portion 902 includes a sealing layer 906, integrated device 1303, integrated device 1305, and a plurality of via interconnects 960. In some mounting configurations, the plurality of solder interconnects 123 and / or the plurality of solder interconnects 163 may be considered as part of the intermediate portion 902.

[0103]

[0122] Integrated device 1303 is coupled to integrated device 103 via direct metal-to-metal bonding (e.g., hybrid bonding, copper-to-copper bonding). There are no solder interconnects between integrated device 1303 and integrated device 103. Therefore, there may be no solder interconnects in the electrical path between integrated device 1303 and integrated device 103. Integrated device 1305 is coupled to integrated device 105 via direct metal-to-metal bonding (e.g., hybrid bonding, copper-to-copper bonding). There are no solder interconnects between integrated device 1305 and integrated device 105. Therefore, there may be no solder interconnects in the electrical path between integrated device 1305 and integrated device 105.

[0104]

[0123] Integrated device 1303 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Integrated device 1305 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Optical integrated device 101 may be configured as a bridge (for electrical paths) between integrated device 1303 and integrated device 1305. Integrated devices 1303 and 103 may be stacked integrated devices. Integrated devices 1305 and 105 may be stacked integrated devices.

[0105]

[0124] Figure 16 shows a cross-sectional view of a package 1600 including an optical integrated device. The package 900 includes an optical integrated device 101, a package substrate 102, an intermediate portion 902, an integrated device 103, a metallization portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of post interconnects 160, a sealing layer 106, at least one back-side power rail interconnect 203, and at least one back-side power rail interconnect 205.

[0106]

[0125] Package 1600 is similar to package 500 and / or package 1200. However, some of the components of package 1600 are located and / or combined in a different way than some of the components in package 500 and / or package 1200.

[0107]

[0126] The intermediate portion 902 is coupled to the package substrate 102 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the optical integrated device 101 via a plurality of solder interconnects 123. The intermediate portion 902 is coupled to the integrated device 103 and / or integrated device 105 via a plurality of solder interconnects 163. The intermediate portion 902 includes a sealing layer 906, integrated device 1303, integrated device 1305, and a plurality of via interconnects 960. In some mounting configurations, the plurality of solder interconnects 123 and / or the plurality of solder interconnects 163 may be considered as part of the intermediate portion 902.

[0108]

[0127] Integrated device 1303 is coupled to integrated device 103 via direct metal-to-metal bonding (e.g., hybrid bonding, copper-to-copper bonding). There are no solder interconnects between integrated device 1303 and integrated device 103. Therefore, there may be no solder interconnects in the electrical path between integrated device 1303 and integrated device 103. Integrated device 1305 is coupled to integrated device 105 via direct metal-to-metal bonding (e.g., hybrid bonding, copper-to-copper bonding). There are no solder interconnects between integrated device 1305 and integrated device 105. Therefore, there may be no solder interconnects in the electrical path between integrated device 1305 and integrated device 105.

[0109]

[0128] Integrated device 1303 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Integrated device 1305 is coupled to optical integrated device 101 via solder interconnects from a plurality of solder interconnects 123. Optical integrated device 101 may be configured as a bridge (for electrical paths) between integrated device 1303 and integrated device 1305. Integrated devices 1303 and 103 may be stacked integrated devices. Integrated devices 1305 and 105 may be stacked integrated devices.

[0110]

[0129] It should be noted that different implementations may have different electrical paths between different components. Therefore, the electrical paths between components are not limited to those shown or described in this disclosure. Other electrical paths may be possible between components. For example, the electrical path between a first component and a second component may be along any path including a set of connecting components that may be conductive.

[0111]

[0130] An integrated device (e.g., 103) may include a die (e.g., a bare semiconductor die). An integrated device may include a power management integrated circuit (PMIC). An integrated device may include an application processor. An integrated device may include a modem. An integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memory, power management processors, and / or combinations thereof. An integrated device (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). An integrated device may include a transistor. An integrated device may be an example of an electrical component and / or electrical device. In some implementations, an integrated device can be a chiplet. In some implementations, an optical integrated device (e.g., 101) can be a chiplet. Chiplets can be fabricated using processes that yield better results compared to other processes used to fabricate other types of integrated devices, thus reducing the overall cost of fabricating chiplets. Different chiplets can have different sizes and / or shapes. Different chiplets can be configured to provide different functions. Different chiplets can have different interconnect density (e.g., interconnects with different widths and / or spacing). In some implementations, several chiplets can be used to perform the functions of one or more chips (e.g., another integrated device). Therefore, for example, a single integrated device can be divided into several chiplets.As described above, using several chiplets that perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some implementations, one or more of the chiplets and / or one or more of the integrated devices (e.g., 103) described herein may be fabricated using the same technology node or two or more different technology nodes. For example, an integrated device may be fabricated using a first technology node, and a chiplet may be fabricated using a second technology node that is less advanced than the first technology node. In such an example, the integrated device may include components having a first minimum size (e.g., interconnects, transistors), and the chiplet may include components having a second minimum size (e.g., interconnects, transistors), where the second minimum size is larger than the first minimum size. In some implementations, one integrated device and another integrated device in the package may be fabricated using the same technology node or different technology nodes. In some implementations, one chiplet and another chiplet in the package may be fabricated using the same technology node or different technology nodes.

[0112]

[0131] A technology node can refer to a specific fabrication process and / or technology used to fabricate an integrated device and / or chiplet. A technology node can specify the minimum possible size that can be fabricated (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. A technology node that produces components with finer details (e.g., traces, transistors) may be more expensive and have a higher yield loss than a technology node that produces components with less fine details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and have a higher yield loss than less advanced technology nodes. If all the functionality of a package is implemented within a single integrated device, the same technology node is used to fabricate the entire integrated device, even if some of the functionality of the integrated device does not need to be fabricated using that particular technology node. Thus, an integrated device is fixed to one technology node. To optimize the cost of the package, some of the functions can be implemented in different integrated devices and / or chiplets, and different integrated devices and / or chiplets can be fabricated using different technology nodes to reduce the overall cost. For example, functions that require the use of a state-of-the-art technology node can be implemented in an integrated device, while functions that can be implemented using a less advanced technology node can be implemented in a different integrated device and / or one or more chiplets. One example is an integrated device fabricated using a first technology node (e.g., a state-of-the-art technology node) configured to provide a computing application, and at least one chiplet fabricated using a second technology node configured to provide other functions, wherein the second technology node is not as expensive as the first technology node, and the second technology node fabricates components with a minimum size greater than the minimum size of components fabricated using the first technology node.Examples of computing applications may include high-performance computing and / or high-performance processing, which can be achieved by fabricating and packing as many transistors as possible within an integrated device, because integrated devices configured for computing applications can be fabricated using the most advanced technology nodes available, while other chiplets can be fabricated using less advanced technology nodes, as they do not require the fabrication of as many transistors within the chiplet. Therefore, combining the use of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0113]

[0132] Another advantage of splitting functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign all integrated devices and / or chiplets. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet the same. Thus, the first chiplet can be reused with an improved and / or different configuration of the first integrated device. This saves costs by eliminating the need to redesign the first chiplet when a package with an improved integrated device is manufactured.

[0114] Exemplary sequence for fabricating a package with an optically integrated device

[0133] In some implementations, creating a package involves several processes. Figures 17A to 17E show exemplary sequences for providing or creating a package. In some implementations, the sequences in Figures 17A to 17E may be used to provide or create package 300 in Figure 3. However, the processes in Figures 17A to 17E may be used to create any of the packages described in this disclosure (e.g., 100, 200, 400, 500, 600, 1200, 1300, 1400, 1500, 1600).

[0115]

[0134] It should be noted that the sequences in Figures 17A to 17E may be combinations of one or more steps to simplify and / or clarify the sequence for providing or producing a package. In some implementations, the order of the process may be changed or modified. In some implementations, one or more of the processes may be replaced or substituted without departing from the spirit of this disclosure.

[0116]

[0135] Stage 1 shows the state after the metallization portion 104 has been provided on the carrier 1700, as shown in Figure 17A. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 can be formed on the carrier 1700. A deposition process, a masking process, an exposure process, an etching process, a plating process, and / or a stripping process may be used to form the metallization portion 104. A deposition, lamination, exposure, development, and / or etching process may be used to form and pattern at least one dielectric layer. A plating process and / or a patterning process may be used to form the metallization interconnects.

[0117]

[0136] Stage 2 shows the state after multiple post interconnects 160 have been formed on the metallization portion 104 and coupled to the metallization portion 104. The multiple post interconnects 160 are coupled to the multiple metallization interconnects 142. A plating process may be used to form the multiple post interconnects 160.

[0118]

[0137] Stage 3 shows the state after multiple integrated devices and / or at least one passive device are coupled to the surface of the metallization portion 104. For example, integrated device 103 is coupled to the surface of the metallization portion 104 via multiple solder interconnects 223. For example, the surface of integrated device 103 is coupled to the surface of the metallization portion 104. Integrated device 103 may include a back-side power rail interconnect 203. Integrated device 105 is coupled to the surface of the metallization portion 104 via multiple solder interconnects 225. For example, the surface of integrated device 105 is coupled to the surface of the metallization portion 104. Integrated device 105 may include a back-side power rail interconnect 205. Integrated device 109 is coupled to the surface of the metallization portion 104 via multiple solder interconnects 190. Passive device 111 is coupled to the surface of the metallization portion 104 via multiple solder interconnects 112. One or more solder reflow processes may be used to combine multiple integrated devices and / or passive devices into the metallization portion 104.

[0119]

[0138] Stage 4 shows the state after the sealing layer 106 has been formed on and bonded to the metallization portion 104, as shown in Figure 17B. The sealing layer 106 may include mold, resin, and / or epoxy. Compression molding, transfer molding, or liquid molding processes may be used to form the sealing layer 106. The sealing may seal (e.g., partially seal) the integrated device 103 / backside power rail interconnect 203, the integrated device 105 / backside power rail interconnect 205, the integrated device 109, the passive device 111, and the multiple post interconnects 160.

[0120]

[0139] Stage 5 shows the state after the carrier 1700 has been separated from the metallization portion 104.

[0121]

[0140] Step 6 shows the state after the package substrate 102b has been coupled to the back-side power rail interconnects (e.g., 203, 205) and the post interconnects 160 of the integrated devices (e.g., 103, 105) via a plurality of solder interconnects 163. A solder reflow process may be used to couple the power rail interconnects and the post interconnects 160 via the plurality of solder interconnects 163. The package substrate 102b may be coupled to the back surface of the integrated device 103 and the back surface of the integrated device 105. The package substrate 102b includes at least one dielectric layer 120b and a plurality of interconnects 122b.

[0122]

[0141] Step 7 shows the state after an underfill 125 has been provided between the package substrate 102b and the sealing layer 106. The underfill 125 may be formed so that it laterally surrounds a plurality of solder interconnects 123. The underfill 125 may be coupled to and in contact with the package substrate 102b, the plurality of solder interconnects 123, the sealing layer 106, the integrated device 103, and / or the integrated device 105.

[0123]

[0142] Step 8 shows the state after one or more integrated devices have been bonded to the surface of the metallization portion 104, as shown in Figure 17C. For example, a stack of integrated devices may be bonded to the metallization portion 104. In one example, a stack of integrated devices comprising integrated device 130, integrated device 132, and integrated device 134 may be bonded to the metallization portion 104 via a solder reflow process.

[0124]

[0143] Stage 9 shows the state after the package substrate 102a is bonded to the package substrate 102b via a plurality of solder interconnects 123. A solder reflow process may be used to bond the package substrate 102a to the package substrate 102b. In some mounting configurations, the package substrate 102a may include an optical integrated device 101, and / or the optical integrated device 101 may be bonded to the package substrate 102. As illustrated and described in Figures 1 and 2, in some mounting configurations, the optical integrated device 101 may be part of the package substrate 102. The optical integrated device 101 may be located within a cavity in the package substrate 102a. The optical integrated device 101 may be bonded to the package substrate 102a via an adhesive.

[0125]

[0144] Step 10 shows the state after the package substrate 102a has been bonded to the board 108 via a plurality of solder interconnects 183, as shown in Figure 17D. A solder reflow process may be used to bond the package substrate 102 to the board 108.

[0126]

[0145] Step 11 shows the state after the optical integrated device 101 is coupled to the metallization portion 104 via a plurality of solder interconnects 310, as shown in Figure 17E. The optical integrated device 301 is coupled to the board 108. The optical integrated device 301 may be similar to the optical integrated device 101. The optical integrated device 301 may be coupled to the board 108 via a plurality of solder interconnects. The optical fiber 110 may be coupled to the optical integrated device 101 and the optical integrated device 301.

[0127]

[0146] Stage 11 also shows the state after the connector socket 107 is coupled to the metallization portion 104 via a plurality of solder interconnects 170 and the connector socket 113 is coupled to the board 108 via a plurality of solder interconnects 114. A solder reflow process may be used to couple the connector socket 107 to the metallization portion 104 and the connector socket 113 to the board 108. The connector socket 107 may be coupled to the connector socket 113 via one or more wires.

[0128] Exemplary flowchart of a method for fabricating a package containing an optically integrated device.

[0147] In some implementations, creating a package involves several processes. Figure 18 shows an illustrative flowchart of a method 1800 for providing or creating a package. In some implementations, the method 1800 in Figure 18 may be used to provide or create at least the packages shown in Figures 1-6 and 9-16.

[0129]

[0148] It should be noted that Method 1800 in Figure 18 may combine one or more processes to simplify and / or clarify the method for providing or producing a package. In some implementations, the order of the processes may be changed or modified.

[0130]

[0149] The method involves providing a metallization portion and a plurality of post interconnects (in 1805). The metallization portion may be provided on a carrier. In some implementations, providing a metallization portion and a plurality of post interconnects includes fabricating the metallization portion and a plurality of post interconnects. Steps 1 and 2 of Figure 17A illustrate and describe an example of providing a metallization portion 104 and a plurality of post interconnects 160. The metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. The metallization portion 104 may be formed on a carrier 1700. Deposition, lamination, exposure, development, and / or etching processes may be used to form and pattern the at least one dielectric layer. Plating processes and / or patterning processes may be used to form the metallization interconnects.

[0131]

[0150] Step 2 in Figure 17A illustrates and describes an example of multiple post interconnects 160 formed on and coupled to the metallization portion 104. The multiple post interconnects 160 are coupled to the multiple metallization interconnects 142. A plating process may be used to form the multiple post interconnects 160.

[0132]

[0151] This method (in 1810) connects one or more integrated devices and / or at least one passive device to the metallization portion. Step 3 in Figure 17A illustrates and describes an example of multiple integrated devices and / or at least one passive device connected to the surface of the metallization portion 104. For example, integrated device 103 is connected to the surface of the metallization portion 104 via multiple solder interconnects 223. Integrated device 105 is connected to the surface of the metallization portion 104 via multiple solder interconnects 225. Integrated device 109 is connected to the surface of the metallization portion 104 via multiple solder interconnects 190. Passive device 111 is connected to the surface of the metallization portion 104 via multiple solder interconnects 112. One or more solder reflow processes may be used to connect multiple integrated devices and / or passive devices to the metallization portion 104.

[0133]

[0152] This method forms a sealing layer (in 1815). The sealing layer can at least partially seal multiple post interconnects, integrated devices, and / or passive devices. Step 4 in Figure 17B illustrates and describes an example of a sealing layer 106 formed on and bonded to the metallization portion 104. The sealing layer 106 may include mold, resin, and / or epoxy. A compression molding process, a transfer molding process, or a liquid molding process may be used to form the sealing layer 106. The sealing can at least partially seal the integrated device 103 / backside power rail interconnect 203, the integrated device 105 / backside power rail interconnect 205, the integrated device 109, the passive device 111, and multiple post interconnects 160.

[0134]

[0153] This method can also remove carriers bound to the metallization portion (in 1815). Step 5 in Figure 17B illustrates and describes an example of carriers 1700 detached from the metallization portion 104.

[0135]

[0154] This method allows a package substrate to be coupled to a plurality of post interconnects via a plurality of solder interconnects (in 1820). Step 6 of Figure 17B illustrates and describes an example of a package substrate 102b coupled to power rail interconnects (e.g., 203, 205) of an integrated device (e.g., 103, 105) and a plurality of post interconnects 160 via a plurality of solder interconnects 163. A solder reflow process may be used to couple the power rail interconnects and the plurality of post interconnects 160 via the plurality of solder interconnects 163. The package substrate 102b includes at least one dielectric layer 120b and a plurality of interconnects 122b.

[0136]

[0155] This method allows a package substrate to be coupled to a plurality of post interconnects via a plurality of solder interconnects (in 1820). Step 6 of Figure 17B illustrates and describes an example of a package substrate 102b coupled to power rail interconnects (e.g., 203, 205) of an integrated device (e.g., 103, 105) and a plurality of post interconnects 160 via a plurality of solder interconnects 163. A solder reflow process may be used to couple the power rail interconnects and the plurality of post interconnects 160 via the plurality of solder interconnects 163. The package substrate 102b includes at least one dielectric layer 120b and a plurality of interconnects 122b.

[0137]

[0156] In some implementation configurations, once the package substrate 102b is coupled to a plurality of post interconnects via a plurality of solder interconnects, an underfill 125 may be provided between the package substrate 102 and the sealing layer 106. The underfill 125 may be formed such that it laterally surrounds a plurality of solder interconnects 123. The underfill 125 may be coupled to and in contact with the package substrate 102, the plurality of solder interconnects 123, the sealing layer 106, the integrated device 103, and / or the integrated device 105.

[0138]

[0157] The method may also (in 1820) combine integrated devices and / or passive devices into a package. For example, the method may combine integrated devices and / or passive devices into the surface of the metallization portion. Step 8 in Figure 17C illustrates and describes an example of one or more integrated devices combined into the surface of the metallization portion 104. For example, a stack of integrated devices may be combined into the metallization portion 104. In one example, a stack of integrated devices comprising integrated device 130, integrated device 132, and integrated device 134 may be combined into the metallization portion 104 via a solder reflow process.

[0139]

[0158] This method allows one package substrate to be bonded to another package substrate via multiple solder interconnects (in 1825). Step 9 in Figure 17C illustrates and describes an example of a package substrate 102a bonded to package substrate 102b via multiple solder interconnects 123. A solder reflow process may be used to bond the package substrate 102a via the multiple solder interconnects 123. The package substrate 102a includes at least one dielectric layer 120a and multiple interconnects 122a.

[0140]

[0159] In some implementations, the package substrate 102a may include the optical integrated device 101, and / or the optical integrated device 101 may be bonded to the package substrate 102a. As illustrated and described in Figures 1 and 2, in some implementations, the optical integrated device 101 may be part of the package substrate 102. The optical integrated device 101 may be located within a cavity in the package substrate 102. The optical integrated device 101 may be bonded to the package substrate 102 via an adhesive.

[0141]

[0160] This method allows the package substrate to be bonded to the board via multiple solder interconnects (in 1830). Step 10 in Figure 17D illustrates and describes an example of a package substrate 102 bonded to the board 108 via multiple solder interconnects 183. A solder reflow process may be used to bond the package substrate 102 to the board 108.

[0142]

[0161] This method allows (in 1835) connector sockets to be coupled to a package and a board. This method also allows (in 1835) optical integrated devices to be coupled to a package and another optical integrated device to a board. Step 11 of Figure 17E illustrates and describes an example of an optical integrated device 101 coupled to a metallization portion 104 via a plurality of solder interconnects 310. The optical integrated device 301 is coupled to a board 108. The optical integrated device 301 may be similar to the optical integrated device 101. The optical integrated device 301 may be coupled to the board 108 via a plurality of solder interconnects. An optical fiber 110 may be coupled to the optical integrated device 101 and the optical integrated device 301.

[0143]

[0162] Step 11 in Figure 17E also illustrates and describes an example of a connector socket 107 coupled to a metallization portion 104 via a plurality of solder interconnects 170, and a connector socket 113 coupled to a board 108 via a plurality of solder interconnects 114. A solder reflow process may be used to couple the connector socket 107 to the metallization portion 104 and the connector socket 113 to the board 108. The connector socket 107 may be coupled to the connector socket 113 via one or more wires.

[0144] Exemplary electronic device

[0163] Figure 19 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, package-on-package (PoP), system in package (SiP), or system on chip (SoC). For example, a mobile phone device 1902, a laptop computer device 1904, a fixed-location terminal device 1906, a wearable device 1908, or a motor vehicle 1910 may include a device 1900 as described herein. Device 1900 may be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Devices 1902, 1904, 1906, and 1908, and vehicle 1910 shown in Figure 19 are merely examples. Device 1900 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, meter reading devices, and other fixed-location data units, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automated vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0145]

[0164] One or more of the components, processes, features, and / or functions shown in Figures 1 to 16, Figures 17A to 17E, and / or Figures 18 to 19 may be reconfigured and / or combined into a single component, process, feature, or function, or may be embodied as several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. Note that Figures 1 to 16, Figures 17A to 17E, and / or Figures 18 to 19, and their corresponding descriptions in this disclosure, are not limited to dies and / or ICs. In some implementations, Figures 1 to 16, Figures 17A to 17E, and / or Figures 18 to 19, and their corresponding descriptions may be used to manufacture, develop, provide, and / or produce devices and / or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipation device, and / or an interposer.

[0146]

[0165] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to exact scale. In some cases, not all elements and / or components may be shown for clarity. In some cases, the position, location, size, and / or shape of various components and / or elements in the figures may be illustrative. In some implementations, various components and / or elements in the figures may be optional.

[0147]

[0166] The term “exemplary” is used herein to mean “to serve as an example, case, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even though they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can travel between them. Two electrically coupled objects may or may not transmit an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or fourth or higher) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may be the first, second, third, or fourth component. The term “encapsulating” means that an object can partially or completely encapsulate another object. A first component “located” within a second component may mean that the first component is partially located within the second component or completely located within the second component. A first component “embedded” within a second component may mean that the first component is “partially embedded” within the second component or “completely embedded” within the second component. The terms “top” and “bottom” are arbitrary.A component located at the top may be located above a component located at the bottom. A component at the top may be considered a component at the bottom, and vice versa. As described in this disclosure, a first component located "over" a second component may mean that the first component is located above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of the second component, in which case the second surface is on the opposite side of the first surface. It should be further noted that, in the context of one component being located above another, the term "on" as used in this application may be used to mean a component that is on and / or inside another component (e.g., on the surface of a component or embedded within a component). Therefore, for example, a first component on a second component may mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A value of about X to XX may mean a value between X and XX, including X and XX. The value (singular or plural) between X and XX may be discrete or continuous. As used in this disclosure, the terms “about ‘value X’” or “approximately value X” mean within 10 percent of “value X.” For example, a value of “about 1” or “approximately 1” means a value in the range of 0.9 to 1.1. “Multiple” components may include all possible components, or only some of all possible components. For example, if a device contains 10 components, the term "multiple components" could refer to all 10 components or only some of the 10 components.

[0148]

[0167] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, redistribution metal layers, and / or underbump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., seed layer + metal layer). In some implementations, an interconnect may be a conductive material configured to provide an electrical path for current (e.g., data signal, ground, or power). An interconnect may be part of a circuit. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form the interconnect. In some implementations, these processes are chemical vapor deposition (CVD) and / or physical vapor deposition (PVD). For example, sputtering processes, spray coating, and / or electroplating or electroless plating processes may be used to form interconnections.

[0149]

[0168] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many of these operations can also be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0150]

[0169] Further embodiments are described below to facilitate understanding of the present invention.

[0151]

[0170] Embodiment 1: A package comprising: a first package substrate; a second package substrate coupled to the first package substrate via a first plurality of solder interconnections; a first integrated device coupled to the second package substrate via a second plurality of solder interconnections; a sealing layer that at least partially seals the first integrated device; a plurality of post interconnections at least partially located within the sealing layer; a metallization portion coupled to the plurality of post interconnections; a second integrated device coupled to the metallization portion via a third plurality of solder interconnections; an optical integrated device coupled to the first package substrate; and an optical fiber coupled to the optical integrated device.

[0152]

[0171] Embodiment 2: The package according to Embodiment 1, wherein the surface of the first integrated device faces the second package substrate.

[0153]

[0172] Embodiment 3: The package according to Embodiment 1 or 2, further comprising a third integrated device coupled to a second package substrate via a fourth plurality of solder interconnects.

[0154]

[0173] Embodiment 4: The package according to Embodiment 1 or 2, further comprising a third integrated device coupled to the first integrated device via a fourth plurality of solder interconnections.

[0155]

[0174] Embodiment 5: The package according to Embodiment 1 or 2, further comprising a third integrated device coupled to the first integrated device.

[0156]

[0175] Embodiment 6: The package according to embodiments 1 to 5, wherein the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path including solder interconnects from a second plurality of solder interconnects, metallization interconnects from a metallization portion, post interconnects from a plurality of post interconnects, and solder interconnects from a first plurality of solder interconnects, an optical integrated device, and another solder interconnect from the first plurality of solder interconnects.

[0157]

[0176] Embodiment 7: The package according to embodiments 1 to 6, further comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

[0158]

[0177] Embodiment 8: The package according to Embodiments 1 to 7, wherein the optical integrated device includes a waveguide and circuits for processing optical and / or electrical signals.

[0159]

[0178] Embodiment 9: The package according to Embodiments 1 to 8, wherein the optical fiber extends through the first package substrate.

[0160]

[0179] Embodiment 10: The package according to Embodiments 1 to 9, wherein the second integrated device includes memory.

[0161]

[0180] Embodiment 11: A package comprising: a first package substrate; an intermediate portion coupled to the first package substrate via a plurality of first solder interconnects, the intermediate portion including a first integrated device and a first sealing layer; a second integrated device coupled to the intermediate portion via a plurality of second solder interconnects; a second sealing layer that at least partially seals the first integrated device; a plurality of post interconnects at least partially located within the sealing layer; a metallization portion coupled to the plurality of post interconnects; a third integrated device coupled to the metallization portion via a plurality of third solder interconnects; an optical integrated device coupled to the first package substrate; and an optical fiber coupled to the optical integrated device.

[0162]

[0181] Embodiment 12: The package according to Embodiment 11, wherein the surface of the second integrated device faces the intermediate portion.

[0163]

[0182] Embodiment 13: The package according to Embodiment 11 or 12, further comprising a fourth integrated device coupled to an intermediate portion via a fourth plurality of solder interconnects.

[0164]

[0183] Embodiment 14: The package according to Embodiment 11 or 12, further comprising a fourth integrated device coupled to the first integrated device via a fourth plurality of solder interconnects.

[0165]

[0184] Embodiment 15: The package according to Embodiment 11 or 12, further comprising a fourth integrated device coupled to the first integrated device.

[0166]

[0185] Embodiment 16: The package according to embodiments 11 to 15, wherein the second integrated device is configured to be electrically coupled to the second integrated device via an electrical path including solder interconnects from a third plurality of solder interconnects, metallization interconnects from a metallization portion, post interconnects from a plurality of post interconnects and solder interconnects from a first plurality of solder interconnects, an optical integrated device, and another solder interconnect from the first plurality of solder interconnects.

[0167]

[0186] Embodiment 17: The package according to embodiments 11 to 16, further comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

[0168]

[0187] Embodiment 18: The package according to Embodiments 11 to 17, wherein the optical integrated device includes a waveguide and circuits for processing optical and / or electrical signals.

[0169]

[0188] Embodiment 19: The package according to embodiments 11 to 18, wherein the optical fiber extends through the first package substrate.

[0170]

[0189] Embodiment 20: The package according to Embodiments 11 to 19, wherein the third integrated device includes memory.

[0171]

[0190] Embodiment 21: The package according to Embodiments 11 to 20, wherein the package is implemented in a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automated vehicles.

[0172]

[0191] Embodiment 22: The package according to Embodiments 1 to 10, wherein the package is implemented in a device selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, stationary terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in automated vehicles.

[0173]

[0192] Embodiment 23: A device comprising the package described in Embodiments 11 to 20, wherein the device is selected from the group consisting of music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in an automated vehicle.

[0174]

[0193] Embodiment 24: A device comprising the package described in Embodiments 1 to 10, wherein the device is selected from the group consisting of a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, fixed-location terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, and device in an automated vehicle.

[0175]

[0194] Various features of the Disclosure described herein can be implemented in various systems without departing from the Disclosure. It should be noted that the above-described embodiments of the Disclosure are merely examples and should not be construed as limiting the Disclosure. The descriptions of the embodiments of the Disclosure are intended to be illustrative and not to limit the scope of embodiments. Therefore, the teachings can be readily applied to other types of devices, and many alternative, modified, and variant forms will be apparent to those skilled in the art.

Claims

1. The first package substrate and A second package substrate bonded to the first package substrate via a plurality of first solder interconnections, A first integrated device coupled to the second package substrate via a second plurality of solder interconnections, A sealing layer that at least partially seals the first integrated device, A plurality of post interconnection portions located at least partially within the sealing layer, A metallization portion coupled to the plurality of post interconnection parts, A second integrated device coupled to the metallization portion via a third plurality of solder interconnections, The optical integrated device coupled to the first package substrate, An optical fiber coupled to the aforementioned optical integration device, A package that includes the following features.

2. The package according to claim 1, wherein the surface of the first integrated device faces the second package substrate.

3. The package according to claim 1, further comprising a third integrated device coupled to the second package substrate via a fourth plurality of solder interconnections.

4. The package according to claim 1, further comprising a third integrated device coupled to the first integrated device via a fourth plurality of solder interconnections.

5. The package according to claim 1, further comprising a third integrated device coupled to the first integrated device.

6. The package according to claim 1, wherein the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, post interconnects from the plurality of post interconnects, solder interconnects from the first plurality of solder interconnects, the optical integrated device, and another solder interconnect from the first plurality of solder interconnects.

7. The package according to claim 1, further comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

8. The package according to claim 1, wherein the optical integrated device includes a waveguide and a circuit for processing optical and / or electrical signals.

9. The package according to claim 1, wherein the optical fiber extends through the first package substrate.

10. The package according to claim 1, wherein the second integrated device includes a memory.

11. The first package substrate and An intermediate portion bonded to the first package substrate via a plurality of first solder interconnections, the intermediate portion including a first integrated device and a first sealing layer, A second integrated device coupled to the intermediate portion via a second plurality of solder interconnections, A second sealing layer that at least partially seals the first integrated device, A plurality of post interconnection portions located at least partially within the sealing layer, A metallization portion coupled to the plurality of post interconnection parts, A third integrated device coupled to the metallization portion via a third plurality of solder interconnections, The optical integrated device coupled to the first package substrate, An optical fiber coupled to the aforementioned optical integration device, A package that includes the following features.

12. The package according to claim 11, wherein the surface of the second integrated device faces the intermediate portion.

13. The package according to claim 11, further comprising a fourth integrated device coupled to the intermediate portion via a fourth plurality of solder interconnections.

14. The package according to claim 11, further comprising a fourth integrated device coupled to the first integrated device via a fourth plurality of solder interconnections.

15. The package according to claim 11, further comprising a fourth integrated device coupled to the first integrated device.

16. The package according to claim 11, wherein the third integrated device is configured to be electrically coupled to the second integrated device via an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, post interconnects from the plurality of post interconnects and solder interconnects from the first plurality of solder interconnects, the optical integrated device, and another solder interconnect from the first plurality of solder interconnects.

17. The package according to claim 11, further comprising a connector socket coupled to the metallization portion, wherein the connector socket is configured to provide an electrical path for power.

18. The package according to claim 11, wherein the optical integrated device includes a waveguide and a circuit for processing optical and / or electrical signals.

19. The package according to claim 11, wherein the optical fiber extends through the first package substrate.

20. The package according to claim 11, wherein the third integrated device includes a memory.

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