Noise reduction processing device, audio system, and method for controlling the noise reduction processing device

Abstract

According to the present invention, spurious noise is reduced in a noise reduction processing device provided with a loop filter and a quantizer.　A difference calculation unit obtains a difference between an input signal and a predetermined feedback signal, and outputs it as an error signal. A delay signal adder adds the error signal and a predetermined delay signal and outputs it as an integrated signal. An internal dither adder adds the integrated signal and a predetermined internal dither signal and outputs it as a filter output signal. A delay unit in the filter delays the filter output signal and outputs it as a delay signal. A quantizer quantizes the filter output signal and feeds it back as a feedback signal.

Description

[Technical field]

[0001] The present technology relates to a noise reduction processing device, and more particularly to a noise reduction processing device using a delta-sigma modulator, an audio system, and a method for controlling the noise reduction processing device. [Background technology]

[0002] Conventionally, a delta-sigma modulator has been used in an analog-to-digital converter to process signals such as audio signals. For example, a delta-sigma modulator has been proposed that includes a loop filter and a quantizer that adds a dither signal to the output of the loop filter and quantizes the result (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-314427 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional technology, spurious noise can be reduced by adding a dither signal. However, when the number of bits of the dither signal is reduced in order to reduce power consumption, the spurious noise may not be sufficiently reduced. For example, when the number of bits of the dither signal is set to 1, spurious noise may occur.

[0005] The present technology has been developed in view of these circumstances, and has an object to reduce spurious noise in a noise reduction processing device provided with a loop filter and a quantizer. [Means for solving the problem]

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a noise reduction processing device including a difference calculation unit that calculates a difference between an input signal and a predetermined feedback signal and outputs the difference as an error signal, a delay signal adder that adds the error signal and a predetermined delay signal and outputs the result as an integrated signal, an internal dither adder that adds the integrated signal and a predetermined internal dither signal and outputs the result as a filter output signal, an internal filter delay unit that delays the filter output signal and outputs the result as the delayed signal, and a quantizer that quantizes the filter output signal and feeds it back as the feedback signal, and a control method thereof, which brings about an effect of reducing spurious noise.

[0007] In addition, in the first aspect, the present invention may further include a dither signal generator that generates the internal dither signal and supplies the internal dither signal to the internal dither adder when a differential signal is input as the input signal, thereby providing an effect of reducing spurious noise of the differential signal.

[0008] In addition, in the first aspect, the digital signal may further include an adder that adds a predetermined input-type dither signal to the digital signal and supplies the result as the input signal, and when a single-ended signal is input as the input signal, the dither signal generator may generate the input-type dither signal and supply it to the adder, thereby providing an effect of reducing spurious noise in the single-ended signal.

[0009] In addition, in the first aspect, the present invention may further include an NTF dither adder that adds a predetermined NTF (Noise Transfer Function) dither signal to the filter output signal and outputs the result to the quantizer, and the dither signal generator may generate either the NTF dither signal or the internal dither signal when a differential signal is input as the input signal. This provides the effect of reducing spurious noise by the NTF dither signal.

[0010] In addition, in the first aspect, the differential signal may include a positive signal and a negative signal, and the adder may include a selector that alternately selects the positive signal and the negative signal and outputs the selected signal as the input signal, thereby providing an effect of reducing the circuit size.

[0011] Also, in this first aspect, the differential signal includes a positive side signal and a negative side signal, the adder includes a positive side adder that adds the input type dither signal to the positive side signal and supplies the result to a positive side circuit, and a negative side adder that adds the input type dither signal to the negative side signal and supplies the result to a negative side circuit, and the difference calculation unit, the delayed signal adder, the internal dither adder, and the filter internal delay unit may be disposed in the positive side circuit and the negative side circuit, respectively. This provides the effect of processing the positive side signal and the negative side signal in parallel.

[0012] A second aspect of the present technology is an audio system including an analog-digital converter that generates an input signal by analog-digital conversion, a difference calculation unit that calculates a difference between the input signal and a predetermined feedback signal and outputs the difference as an error signal, a delay signal adder that adds the error signal and a predetermined delay signal and outputs the result as an integrated signal, an internal dither adder that adds the integrated signal and a predetermined internal dither signal and outputs the result as a filter output signal, an internal filter delay unit that delays the filter output signal and outputs the result as the delayed signal, and a quantizer that quantizes the filter output signal and feeds it back as the feedback signal. This provides the effect of reducing spurious noise in the output signal from the audio system.

[0013] In addition, in the second aspect, the digital signal processing apparatus may further include a pulse shaper that shapes the waveform of the filter output signal, thereby providing an effect of shaping the waveform.

[0014] In addition, in the second aspect, the digital signal processing apparatus may further include a Cascaded Integrator-Comb (CIC) filter to which the filter output signal is input, thereby providing an effect of eliminating the need for a pulse shaper. [Brief description of the drawings]

[0015] [Figure 1] 1 is a block diagram showing an example configuration of an audio system according to a first embodiment of the present technology. [Diagram 2] 1 is a block diagram showing an example of the configuration of a noise reduction processing device according to a first embodiment of the present technology. [Diagram 3] 2 is a block diagram showing an example configuration of an addition unit according to the first embodiment of the present technology. FIG. [Figure 4] 1 is a block diagram showing an example of the configuration of a delta-sigma modulator according to a first embodiment of the present technology. [Diagram 5] FIG. 2 is a diagram summarizing types of quantizers according to the first embodiment of the present technology. [Figure 6] 4 is a diagram showing the relationship between quantization classes of quantization class type A, class numerical ranges, and class medians in the first embodiment of the present technology. FIG. [Figure 7] 11 is a diagram showing the relationship between the quantization ranks of quantization rank type B, the rank numerical range, and the rank median value in the first embodiment of the present technology. FIG. [Figure 8] 11 is a diagram showing the relationship between a quantization rank of quantization rank type C, a rank numerical range, and a rank median value according to the first embodiment of the present technology. FIG. [Figure 9] 11 is a diagram showing the relationship between the quantization rank of quantization rank type D, the rank numerical range, and the rank median value according to the first embodiment of the present technology. FIG. [Figure 10] 11 is a diagram showing the relationship between the quantization rank of quantization rank type E, the rank numerical range, and the rank median value according to the first embodiment of the present technology. FIG. [Figure 11] FIG. 2 is a diagram illustrating an example of implementation of an LFSR (Linear Feedback Shift Register) according to the first embodiment of the present technology. [Figure 12] 4 is a diagram showing an example of a dither signal before scaling in the first embodiment of the present technology; FIG. [Figure 13] 4 is a diagram showing an example of a relationship between the number of quantization bits and the amount of scaling when using a dither signal of this method according to the first embodiment of the present technology. FIG. [Figure 14] 4 is a diagram showing an example of frequency characteristics of an input signal when the dither signal according to the present method in the first embodiment of the present technology is 2 bits and 3 bits. FIG. [Figure 15] 4 is a diagram showing an example of frequency characteristics of an input signal when the dither signal according to the first embodiment of the present technology is 4 bits and 5 bits. FIG. [Figure 16] 4 is a diagram showing an example of frequency characteristics of an output signal when the dither signal according to the first embodiment of the present technology is 2 bits and 3 bits. FIG. [Figure 17] 4 is a diagram showing an example of frequency characteristics of an output signal when the dither signal according to the first embodiment of the present technology is 4 bits and 5 bits. FIG. [Figure 18] 4 is a diagram illustrating an example of a relationship between the number of quantization bits and the amount of scaling when an NTF (Noise Transfer Function) dither signal is used in the first embodiment of the present technology. FIG. [Figure 19] 4 is a diagram illustrating an example of frequency characteristics of an output signal when the NTF dither signal is 1 bit and 2 bits in the first embodiment of the present technology. FIG. [Figure 20] 4A to 4C are diagrams illustrating an example of frequency characteristics of an output signal when the NTF dither signal is 3 bits and 4 bits in the first embodiment of the present technology. [Figure 21] 1 is a diagram illustrating an example of frequency characteristics of an output signal when an NTF dither signal is 5 bits according to the first embodiment of the present technology. [Figure 22] 4 is a diagram illustrating an example of a relationship between the number of quantization bits and the amount of scaling when an input-type dither signal is used in the first embodiment of the present technology. FIG. [Diagram 23]1 is a diagram illustrating an example of frequency characteristics of an output signal when the random number sampling frequency is the same as, or 1 / 2 of, the delta-sigma modulation sampling frequency according to the first embodiment of the present technology. [Figure 24] 4A to 4C are diagrams illustrating an example of frequency characteristics of an output signal when the random number sampling frequency is ¼ and ⅛ of the delta-sigma modulation sampling frequency in the first embodiment of the present technology. [Diagram 25] 4A to 4C are diagrams illustrating an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 16 and 1 / 32 of the delta-sigma modulation sampling frequency in the first embodiment of the present technology. [Figure 26] 11 is a diagram illustrating an example of frequency characteristics of an output signal when the random number sampling frequency is the same as, or 1 / 2 of, the delta-sigma modulation sampling frequency when the scale is changed in the first embodiment of the present technology. FIG. [Figure 27] 11 is a diagram illustrating an example of frequency characteristics of an output signal when the random number sampling frequency is ¼ and ⅛ of the delta-sigma modulation sampling frequency when the scale is changed in the first embodiment of the present technology. [Figure 28] 11 is a diagram illustrating an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 16 and 1 / 32 of the delta-sigma modulation sampling frequency when the scale is changed in the first embodiment of the present technology. FIG. [Figure 29] 1 is a block diagram showing an example configuration of a loop filter according to a first embodiment of the present technology. [Diagram 30] 4 is a circuit diagram showing a configuration example of a rear-stage tap in the first embodiment of the present technology. FIG. [Diagram 31] 1 is a diagram summarizing the configuration of a delta-sigma modulator according to a first embodiment of the present technology. [Diagram 32] 4 is a diagram showing a frequency amplitude characteristic of a transfer function in the first embodiment of the present technology; [Diagram 33] 4 is a diagram illustrating a frequency-phase characteristic of a transfer function according to the first embodiment of the present technology. FIG. [Diagram 34]FIG. 2 is a diagram showing an example of a THD (Total Harmonic Distortion)+N (Noise) characteristic when using a dither signal of this method according to the first embodiment of the present technology. [Diagram 35] FIG. 2 is a diagram showing an example of a THD+N characteristic when an NTF dither signal is used in the first embodiment of the present technology. [Diagram 36] 1 is a diagram illustrating an example of a THD+N characteristic when an input-type dither signal is used in the first embodiment of the present technology. [Figure 37] 1 is a diagram illustrating an example of a THD+N characteristic when the number of quantized output bits is 3 bits according to the first embodiment of the present technology. [Figure 38] 4 is a diagram illustrating an example of a THD+N characteristic when the number of quantized output bits is 4 bits according to the first embodiment of the present technology. FIG. [Figure 39] 1 is a diagram illustrating an example of a THD+N characteristic when the number of quantized output bits is 5 bits according to the first embodiment of the present technology. [Diagram 40] 2 is a diagram for explaining a configuration subsequent to a pulse shaper in the first embodiment of the present technology. FIG. [Diagram 41] 1 is a diagram showing an example of a pulse waveform when a non-return-to-zero (NRZ) waveform is used in the first embodiment of the present technology; [Diagram 42] 3 is a diagram showing an example of a pulse waveform when an RZ (Return-to-Zero) waveform is used in the first embodiment of the present technology; FIG. [Diagram 43] 13 is a block diagram showing an example configuration of an addition unit according to a second embodiment of the present technology. FIG. [Diagram 44] 11 is a block diagram showing a configuration example of a delta-sigma modulator according to a second embodiment of the present technology. FIG. [Diagram 45] FIG. 11 is a block diagram showing an example configuration of a loop filter according to a second embodiment of the present technology. [Figure 46] FIG. 11 is a circuit diagram showing a configuration example of a rear-stage tap according to a second embodiment of the present technology. [Figure 47]FIG. 13 is a block diagram showing an example configuration of an audio system according to a third embodiment of the present technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, modes for carrying out the present technology (hereinafter, referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (example in which a dither signal is input to the final stage of a loop filter) 2. Second embodiment (example in which a dither signal is input to the final stage of a loop filter shared by the positive and negative sides) 3. Third embodiment (an example in which a dither signal is input to the final stage of the loop filter, eliminating the need for a pulse shaper)

[0017] <1. First embodiment> [Example of sound system configuration] 1 is a block diagram showing an example of a configuration of an audio system 100 according to a first embodiment of the present technology. The audio system 100 is a system for reproducing an audio signal, and is installed in a noise-canceling headphone, an audio player, or the like. The audio system 100 includes an ADC (Analog to Digital Converter) 110, a digital processing unit 120, and a noise reduction processing device 200. The audio system 100 further includes a predetermined number of flip-flops 141, a DAC (Digital to Analog Converter) 150, an amplifier 160, and a speaker 170.

[0018] The ADC 110 converts an analog signal into a digital signal. For example, an electric signal converted from audio is input as the analog signal. The ADC 110 supplies the digital signal to the digital processing unit 120. A reference sampling frequency in the analog-to-digital conversion is set to, for example, 44.1 kilohertz (kHz) or 48 kilohertz (kHz). For example, a PCM (Pulse Code Modulation) signal is generated as the digital signal.

[0019] The digital processing unit 120 performs predetermined signal processing on the digital signal from the ADC 110. The digital processing unit 120 supplies the processed digital signal to the noise reduction processing device 200.

[0020] The crystal oscillator 130 supplies a predetermined clock signal to the noise reduction processing device 200 and the flip-flop 141. The noise reduction processing device 200 and the flip-flop 141 operate in synchronization with this clock signal.

[0021] The noise reduction processing device 200 performs processing to reduce noise in a digital signal. The noise reduction processing device 200 causes a predetermined number of flip-flops 141 to hold the processed digital signal.

[0022] The DAC 150 converts the digital signals from the predetermined number of flip-flops 141 into analog signals. The DAC 150 supplies the analog signals to an amplifier 160.

[0023] The amplifier 160 amplifies the analog signal. The amplifier 160 supplies the amplified analog signal to the speaker 170. The speaker 170 converts the analog electrical signal into sound.

[0024] [Example of the configuration of a noise reduction processing device] 2 is a block diagram showing an example of a configuration of a noise reduction processing device 200 according to the first embodiment of the present technology. The noise reduction processing device 200 includes an input converter 210, an adder 220, a delta-sigma modulator 230, a pulse shaper 250, a dither signal generator 260, a clock timing generator 270, and a register 280.

[0025] The dither signal generator 260 generates a uniform random noise signal and inputs it to the adder 220 and the delta sigma modulator 230. The noise average power is specified by scaling from the reference uniform random number to be generated. The method of inserting the noise signal into the delta sigma modulator 230, the number of bits of the random number, the scale value of the amplitude, and the timing are determined according to the setting of the number of bits of the quantized output. The random number inputs to the adder 220 and the delta sigma modulator 230 are mutually exclusive. The noise signal to the delta sigma modulator 230 is divided into a signal input to the front stage of the internal quantizer (not shown) and a signal input to the final stage tap (not shown) of the internal loop filter.

[0026] The noise signal input to the adder 220 is hereinafter referred to as the "input type dither signal IN_DITH". The noise signal input to the previous stage of the quantizer (not shown) is hereinafter referred to as the "NTF dither signal NTFD". The noise signal input to the final stage tap (not shown) of the loop filter is hereinafter referred to as the "original dither signal DITH".

[0027] In the noise reduction processing device 200, the output level is defined in correlation with the configuration of the quantizer of the delta-sigma modulator 230 and the maximum value of the input signal source, 0 dBFS (Decibels Full Scale). Other than that, it does not depend on other configurations, such as the topology of the delta-sigma modulator 230, which will be described later.

[0028] The input converter 210 converts the bit depth of a digital signal (such as a PCM signal) and the like. The input converter 210 supplies the converted digital signal to the addition unit 220.

[0029] The adder 220 adds the input-type dither signal IN_DITH from the dither signal generator 260 to the digital signal from the input converter 210 , and outputs the result to the delta-sigma modulator 230 .

[0030] The delta-sigma modulator 230 performs delta-sigma modulation on the signal from the addition unit 220. This delta-sigma modulator 230 supplies the modulated signal to the pulse shaper 250. In addition, the delta-sigma modulator 230 operates at a sampling frequency that ensures a sufficient signal-to-noise (SN) ratio for an output signal passed by an application in a noise transfer function (NTF).

[0031] The dither signal generator 260 does not depend on the topology of the delta-sigma modulator 230, but can suppress spurious generation to the maximum extent possible, so an example of the topology of the delta-sigma modulator 230 that is optimal for PDM (Pulse Density Modulation) output applications is illustrated. The STF (Signal Transfer Function) of the delta-sigma modulator 230 is realized in two types. The first type has a minimum delay characteristic near a linear phase and a flat frequency characteristic over the entire range. The second type is an LPF type that can approximate a linear phase to the passband.

[0032] The first method is actively used because it can suppress spurious noise. The second method is used when you want to attenuate aliasing signals that do not change with the average input power and occur at frequencies that are integer multiples of the sampling frequency of the input signal more than the attenuation achieved by sample-and-hold. Such aliasing signals occur, for example, when the sampling frequency of the input signal is lower than the sampling frequency of the delta-sigma modulator 230, such as 4FS (Full Scale).

[0033] The delta-sigma modulator 230, given as an example, requires that the sampling frequency of the input data be at most the same as the sampling frequency of the delta-sigma modulator 230, and at most 1 / 32 of the sampling frequency. When the sampling frequency is 128 fs, for example, the sampling frequency is 4 FS. The signal bandwidth of the application is assumed to be approximately DC (Direct Current)-40 kilohertz (kHz).

[0034] The input converter 210 converts the number of channels of the input data, which is a digital signal from the digital processing unit 120, as necessary, and supplies the converted data to the adder unit 220. As the input data, data obtained by AD conversion of a microphone input using a sample-and-hold circuit, or data input via S / PDIF (Sony Philips Digital InterFace) or I2S (Inter-IC Sound) is input. The input data may be input as is, or may be input after some processing has been performed, or may be input as sampled data with a fixed attenuation of less than 6 decibels (dB) in consideration of the distortion characteristics of the output. The input converter 210 has a function of selecting whether to shift the input data by 1 bit to -6 decibels (dB) or not, and a function of inverting one channel of input data to output two channels of in-phase and out-of-phase data. The input converter 210 also has a function of outputting two channels of in-phase signals to operate with one input and one output instead of differential, thereby reducing the power consumption of the delta-sigma modulator 230 by half, and a function of outputting two channels of in-phase from two channel inputs.

[0035] When the data from the input converter 210 is 1 bit, the adder 220 adds the input-type dither signal IN_DITH to the data, and supplies the result to the delta-sigma modulator 230 .

[0036] The pulse shaper 250 shapes the waveform of the signal from the delta-sigma modulator 230 into a pulse waveform and outputs it to the flip-flop 141 .

[0037] The clock timing generator 270 generates a timing signal in synchronization with the clock signal from the crystal oscillator 130, and supplies the timing signal to the input converter 210, the adder unit 220, the delta-sigma modulator 230, the pulse shaper 250, and the dither signal generator 260. The register 280 holds various setting values ​​used by the input converter 210, the adder unit 220, the delta-sigma modulator 230, the pulse shaper 250, and the dither signal generator 260.

[0038] [Example of configuration of addition unit 220] 3 is a block diagram showing an example of a configuration of the adder 220 according to the first embodiment of the present technology. The adder 220 includes an inverting amplifier 221 and adders 222 and 223. The delta-sigma modulator 230 includes a positive-side circuit 231 and a negative-side circuit 232.

[0039] The inverting amplifier 221 inverts the input signal In_p from the input converter 210 and supplies the inverted signal to the adder 223 as an input signal In_n.

[0040] The adder 222 adds the input-type dither signal IN_DITH to the input signal In_p, and supplies the result to the positive-side circuit 231. The adder 222 is an example of a positive-side adder as defined in the claims.

[0041] The adder 223 adds the input-type dither signal IN_DITH to the input signal In_n, and supplies the result to the negative side circuit 232. The adder 223 is an example of a negative side adder as defined in the claims.

[0042] In the configuration illustrated in the figure, a differential signal or a single-ended signal is input to the delta-sigma modulator 230 .

[0043] For example, if the downstream amplifier 160 is an S / E digital amplifier that cannot adopt a differential configuration or an analog amplifier that cannot suppress the gain difference of a differential amplifier, a single-ended signal is input. In other cases, a differential signal is input.

[0044] Furthermore, when the quantizer in the delta-sigma modulator 230 has a 1-bit output, a single-ended signal is not input within the scope of the present invention, but a differential signal is input and an input-type dither signal is added thereto.

[0045] When the quantizer output is 2 bits or more, the dither signal of this method can be selected. The number of bits, level, and frequency of the appropriate dither signal are uniquely determined for each case.

[0046] When data is supplied to the differential amplifier as a single-ended signal, the adder 220 can output one of the signals to the delta-sigma modulator 230 and generate data by inverting the sign of the other signal. In the case of audio signals, DC is cut, so there is no problem even with 1's complement. In the case of 1's complement, it is easy to generate even after slate binary conversion.

[0047] [Example of a delta-sigma modulator] 4 is a block diagram showing an example of a configuration of the delta-sigma modulator 230 according to the first embodiment of the present technology. The positive-side circuit 231 in the delta-sigma modulator 230 includes a loop filter 300, an adder 233, a quantizer 234, a delay unit 235, and a delay unit 236. The configuration of the negative-side circuit 232 is similar to that of the positive-side circuit 231.

[0048] The loop filter 300 receives the input signal In_p from the adder 220 and the feedback signal FD OUT1 and F.D. OUT2 When the dither signal DITH of this method is input, the loop filter 300 adds the dither signal DITH of this method to the integrated signal.

[0049] When the NTF dither signal NTFD is input, the adder 233 adds the NTF dither signal NTFD to the filter output signal Fout from the loop filter 300. The adder 233 supplies the added data to the quantizer 234.

[0050] The quantizer 234 quantizes the data from the adder 233 and supplies the quantized data to delay units 235 and 236. The output signal of the quantizer 234 is a feedback signal FD OUT2 is input to the loop filter 300.

[0051] The delay unit 235 delays the output signal of the quantizer 234 by one clock and outputs the delayed signal as a positive output signal Out_p to the pulse shaper 250. The delay unit 236 delays the output signal of the quantizer 234 by one clock and outputs a feedback signal FD OUT1 The signal is supplied to the loop filter 300 as a signal.

[0052] [Quantizer configuration example] FIG. 5 is a diagram summarizing the types of the quantizer 234 in the first embodiment of the present technology. There are roughly two types of class settings at the time of quantization of the quantizer 234. The first type is a type having the origin as the center value of the class, and the second type is a type in which the classes are arranged symmetrically with respect to the origin. The first type is called the "origin class median type" and the second type is called the "origin symmetric class type." When the number of output bits of the quantizer 234 is 1 and 2, the representative value fed back in the delta sigma modulator 230 is given individually. In particular, when the number is 2, the thresholds are also given individually. When the number is 3 or more, the classes and class thresholds are implemented in a formulated method.

[0053] In addition, the following is a case where the number of defined classes is 2 for the origin class median type. N -1 (N is an integer) is set as quantization class type A. The number of defined classes is 2 for the origin symmetric class type. N Let's call the one with the origin symmetric class type and the number of defined classes 2 be quantization class type C. Let's call the one with the origin symmetric class type and the number of defined classes 3 be quantization class type D. Let's call the one with the origin symmetric class type and the number of defined classes 4 be quantization class type E.

[0054] FIG. 6 is a diagram showing the relationship between the quantization ranks of quantization rank type A, the rank numerical range, and the rank median value in the first embodiment of the present technology.

[0055] FIG. 7 is a diagram showing the relationship between the quantization ranks of quantization rank type B, the rank numerical ranges, and the rank medians in the first embodiment of the present technology.

[0056] FIG. 8 is a diagram showing the relationship between the quantization ranks of the quantization rank type C, the rank numerical range, and the rank median value in the first embodiment of the present technology.

[0057] FIG. 9 is a diagram showing the relationship between the quantization ranks of the quantization rank type D, the rank numerical range, and the rank median value in the first embodiment of the present technology.

[0058] FIG. 10 is a diagram showing the relationship between the quantization ranks of the quantization rank type E, the rank numerical range, and the rank median value in the first embodiment of the present technology.

[0059] When the number of quantization output bits is 1, quantization rank type C is used. When the number of quantization output bits is 2, quantization rank type D or quantization rank type E is used. For the purpose of simplifying the implementation, quantization rank type D is selected.

[0060] Furthermore, quantization class type B is used when the number of quantization output bits is 3. Quantization class type A is also possible, but its THD+N characteristics at large inputs are inferior to those of quantization class type B.

[0061] When the quantization output bit rate is 4 or more, quantization class type A is used for PWM output. Quantization class type B is used for PDM output. Type A is also possible, but its THD+N characteristics at large inputs are inferior to type B. When the quantization bit rate is 3 or more, quantization class type B has better THD+N characteristics at large inputs than quantization class type A.

[0062] [Example of dither signal generator configuration] The device generating uniform random numbers in the dither signal generator 260 switches the number of random number bits simultaneously obtained and the timing of change in the dither signal generated from the random numbers depending on the selected dither insertion location.

[0063] When generating a dither signal according to this method, the random number acquired by the dither signal generator 260 at the same time is 1 bit. When it is 1 bit, the condition for suppressing spuriousness is satisfied and the average noise power is the lowest. The update timing of the uniform random number is the same as the sampling frequency of the delta-sigma modulator 230.

[0064] When generating an NTF dither signal, the random numbers acquired by the dither signal generator 260 at the same time are 2 bits. The condition that satisfies the condition for suppressing spuriousness and the condition for the lowest average noise power is 2 bits, but since the noise power increases by about 0.26 decibels (dB) even if the number of bits is increased from 2 bits to 4 bits, the 4-bit random numbers for the input type dither signal can also be used. In addition, the update timing of the uniform random numbers is the same as the sampling frequency of the delta-sigma modulator 230.

[0065] When generating an input-type dither signal, the number of random number bits that the dither signal generator 260 simultaneously acquires is 4 bits. There is no problem with sharing long-period random numbers of 4 bits or more with other systems. With 1 or 2 bits, spuriousness is prominent, and even with 3 bits, spuriousness cannot be completely removed from the quantization noise, so the random numbers are limited to 4 bits or more. The update timing of the uniform random numbers is 2 / 16 or less than the sampling frequency of the delta-sigma modulator 230. (-N') Here, N' is an integer equal to or greater than 4. The upper limit of N' is determined by the bandwidth that does not fold back within the frequency band that the application handles, such as the audible band. When the sampling frequency of the input signal meets the conditions, the timing is adjusted to that frequency.

[0066] Regarding the random number generator in the dither signal generator 260, when multiple input signals are time-division multiplexed to operate the delta-sigma modulator 230 at twice the sampling frequency or more of the sampling frequency of the delta-sigma modulator 230, the dither signal input to the arithmetic unit is set in common.

[0067] The random numbers may be uniform random numbers, and may be independent for each channel of the input signal or may be common to all channels. For pseudo-random numbers with periodicity, the period is set to a long period as long as it does not cause problems in the application.

[0068] As an example, a 24-bit LFSR will give the sequence (24, 23, 22, 17). The Fibonacci and Galois types of LFSRs are also determined solely for the convenience of the implementer.

[0069] Figure 11 shows an example of a Verilog code defined in the Fibonacci format. It controls the timing of initial value assignment and value update to the register, and predefines the determinant A to A 2 Or A 4 By calculating the above in advance, multiple random bits required can be obtained, either 2 bits or 4 bits at the same time.

[0070] The determinant A is the state of the register v at the nth cycle (n is an integer). n and the state of the register in the n+1th cycle v n+1 These states are uniquely determined by the implementation of the LFSR and can be expressed, for example, by the following equation:

number

[0071] Since one bit of random number can be newly obtained in one cycle, in order to simultaneously obtain m bits (m is an integer), the register state v is calculated based on the following formula. n The register state after m cycles from v n+m The determinant required for the generating formula is A m It is.

number

number

[0072] The initial value is v_0 and is expressed, for example, by the following equation.

number

[0073] The following equation also has determinants A and A 2 and A 4 This is an example.

number

number

number

[0074] The interval at which random numbers are generated is determined by the dither signal generation method. When using this dither signal or an NTF dither signal, the interval is set to the same interval as the sampling period of the delta-sigma modulation.

[0075] When an input-type dither signal is used, a frequency that satisfies the following two conditions is set. (1) 1 / 16 or less of the sampling frequency of the delta-sigma modulator 230, for example, 2 -N To be. (2) It must be equal to or greater than the application frequency bandwidth. If the application is a baseband signal, such as audio, it must be equal to or greater than twice the application frequency bandwidth. In the case of audio, since the audible band is in the range of DC-20 kilohertz (kHz), it must be at least 40 kilohertz (kHz), and is usually set to the sampling frequency of the input signal (4fs in this example) or the reference sampling frequency fs.

[0076] 12 is a diagram showing an example of a dither signal before scaling in the first embodiment of the present technology. In the figure, a shows a 1-bit dither signal, b shows a 2-bit dither signal, and c shows a 4-bit dither signal.

[0077] When a 1-bit dither signal is used, the correspondence with the RTL is expressed by the following formula. v(0)=v1[1]

[0078] When a 2-bit dither signal is used, the correspondence with the RTL is expressed by the following formula. n(0)=v2[1] n(1)=v2[2]

[0079] When a 4-bit dither signal is used, the correspondence with the RTL is expressed by the following formula. r(0)=v4[1] r(1)=v4[2] r(2)=v4[3] r(3)=v4[4]

[0080] Next, in the random number-signed signal conversion process of the dither signal generator 260, the generated random number bit string is treated as one sample data, with the integer part being a signed decimal with one bit. Then, as shown in FIG. 12, the dither signal generator 260 adds a one-bit fixed value to the LSB side to make the signal with an average value of 0.

[0081] When the bit length of the dither signal is M bits (M is an integer), the average noise power P is expressed by the following equation.

number

number

[0082] From Equation 8 and Equation 9, as the number of bits of the dither signal increases, the uniform random number approaches 1 / 3 of the average power value when the value is continuous. In dBFS units, this is expressed as 10 × log10 P+10×log 10 At 2, it asymptotically approaches -1.76dBFS.

[0083] The smallest average power value is -3.01 dBFS when the dither signal is 1 bit. The average power value increases with each additional bit of the dither signal. For example, the average power value is -2.04 dBFS when the dither signal is 2 bits, -1.83 dBFS when the dither signal is 3 bits, -1.78 dBFS when the dither signal is 4 bits, and -1.78 dBFS when the dither signal is 5 bits.

[0084] Next, consider a case where the dither signal generator 260 scales a 1-bit dither signal of this method having two values, 0.5 and -0.5, generated by using the above-mentioned LFSR or the like.

[0085] FIG. 13 is a diagram showing an example of the relationship between the number of quantization bits and the amount of scaling when using the dither signal of this method in the first embodiment of the present technology.

[0086] 14 is a diagram showing an example of the frequency characteristics of an input signal when the dither signal of this method is 2 bits and 3 bits in the first embodiment of the present technology. In the figure, a is a diagram showing an example of the frequency characteristics of an input signal before modulation when the dither signal of this method is 2 bits. In the figure, b is a diagram showing an example of the frequency characteristics of an input signal before modulation when the dither signal of this method is 3 bits.

[0087] 15 is a diagram showing an example of the frequency characteristics of an input signal when the dither signal of this method is 4 bits and 5 bits in the first embodiment of the present technology. In the figure, a is a diagram showing an example of the frequency characteristics of an input signal when the dither signal of this method is 4 bits. In the figure, b is a diagram showing an example of the frequency characteristics of an input signal when the dither signal of this method is 5 bits.

[0088] 16 is a diagram showing an example of the frequency characteristics of the output signal when the dither signal of the present method in the first embodiment of the present technology is 2 bits and 3 bits. In the figure, a is a diagram showing an example of the frequency characteristics of the output signal after modulation when the dither signal of the present method is 2 bits. In the figure, b is a diagram showing an example of the frequency characteristics of the output signal after modulation when the dither signal of the present method is 3 bits.

[0089] 17 is a diagram showing an example of the frequency characteristics of the output signal when the dither signal of this method is 4 bits and 5 bits in the first embodiment of the present technology. In the figure, a is a diagram showing an example of the frequency characteristics of the output signal when the dither signal of this method is 4 bits. In the figure, b is a diagram showing an example of the frequency characteristics of the output signal when the dither signal of this method is 5 bits.

[0090] 14 to 17, the vertical axis indicates the level of the input / output signal, and the horizontal axis indicates the frequency.

[0091] When using this dither signal, in addition to the 1-bit quantized output of quantization class type B, the following three conditions are excluded from system operation because they are of no use if the noise power of the dither signal is large.

[0092] The first condition is when N=1 (i.e., the noise signal scaling is 1) and the quantization class type is C. In this case, the quantization noise generated by the delta-sigma modulator 230 causes a significant degradation of THD+N when the noise power is low enough to suppress spurious signals.

[0093] The second condition is when N=2 (noise signal scaling is 1 / 4) and the quantization class type is A. The quantization class type A has very low tolerance to strong input.

[0094] The third condition is when N=2 and quantization class type B. Quantization class type B is inferior to quantization class type E in terms of resistance to strong input, and is almost the same as when the number of quantization bits for the input dither type is 1.

[0095] Next, consider the case where an NTF dither signal is used. For example, an NTF dither signal is used when a differential signal cannot be accepted by the system downstream of the pulse shaper 250, and when the noise level is not satisfied with the dither signal of this method. For example, this applies when the amplifier 160 is S / E and a PWM signal is used. Alternatively, an NTF dither signal is used when a differential signal is accepted but there is a large analog variation, the noise level is not satisfied with the dither signal of this method, and the number of output bits of the quantizer is 2 bits or more.

[0096] Assume that the dither signal generator 260 scales a 2-bit random number to generate the NTF dither signal.

[0097] FIG. 18 is a diagram illustrating an example of the relationship between the number of quantization bits and the amount of scaling when an NTF dither signal is used in the first embodiment of the present technology.

[0098] 19 is a diagram showing an example of the frequency characteristics of an output signal when the NTF dither signal is 1 bit and 2 bits in the first embodiment of the present technology. In the figure, a is a diagram showing an example of the frequency characteristics of an output signal when the NTF dither signal is 1 bit. In the figure, b is a diagram showing an example of the frequency characteristics of an output signal when the NTF dither signal is 2 bits.

[0099] 20 is a diagram showing an example of frequency characteristics of an output signal when the NTF dither signal is 3 bits and 4 bits in the first embodiment of the present technology. In the figure, a is a diagram showing an example of frequency characteristics of an output signal when the NTF dither signal is 3 bits. In the figure, b is a diagram showing an example of frequency characteristics of an output signal when the NTF dither signal is 4 bits.

[0100] FIG. 21 is a diagram illustrating an example of frequency characteristics of an output signal when the NTF dither signal is 5 bits in the first embodiment of the present technology.

[0101] 19 to 21, the vertical axis indicates the level of the output signal, and the horizontal axis indicates the frequency.

[0102] When using an NTF dither signal, in addition to the case where the quantization output is 1 bit in quantization class type B, the following three conditions are excluded from system operation because they are of no use if the noise power of the dither signal is large.

[0103] The first condition is when N=1 and the quantization class type is C. In this case, the quantization noise generated by the delta-sigma modulator 230 causes a significant degradation of THD+N when the noise power is sufficient to suppress spurious signals.

[0104] The second condition is when N=2 and the quantization class type is A. In this case, the tolerance to strong input is very low.

[0105] The third condition is when N=2 and the quantization class type B is used. In this case, the resistance to strong input is inferior to that of the quantization class type E, and is almost the same as when the number of quantization bits of the input dither type is 1.

[0106] Next, consider the case where an input-type dither signal is used. The input-type dither signal is used when the quantizer output is 1 bit and the quantization class type is C.

[0107] Assume that the dither signal generator 260 generates an input-type dither signal by scaling a random number of 4 or more bits.

[0108] FIG. 22 is a diagram illustrating an example of a relationship between the number of quantization bits and the amount of scaling when an input-type dither signal is used in the first embodiment of the present technology.

[0109] 23 is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is the same as the delta-sigma modulation sampling frequency and is 1 / 2 of the delta-sigma modulation sampling frequency in the first embodiment of the present technology. In the figure, a is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is the same as the delta-sigma modulation sampling frequency. In the figure, b is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 2 of the delta-sigma modulation sampling frequency.

[0110] 24 is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is ¼ and ⅛ of the delta-sigma modulation sampling frequency in the first embodiment of the present technology. In the figure, a is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is ¼ of the delta-sigma modulation sampling frequency. In the figure, b is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is ⅛ of the delta-sigma modulation sampling frequency.

[0111] 25 is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 16 and 1 / 32 of the delta-sigma modulation sampling frequency in the first embodiment of the present technology. In the figure, a is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 16 of the delta-sigma modulation sampling frequency. In the figure, b is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 32 of the delta-sigma modulation sampling frequency.

[0112] 26 is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is the same as the delta-sigma modulation sampling frequency and 1 / 2 the delta-sigma modulation sampling frequency when the scale is changed in the first embodiment of the present technology. In the figure, a is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is the same as the delta-sigma modulation sampling frequency. In the figure, b is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 2 the delta-sigma modulation sampling frequency.

[0113] 27 is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is ¼ and ⅛ of the delta-sigma modulation sampling frequency when the scale is changed in the first embodiment of the present technology. In the figure, a is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is ¼ of the delta-sigma modulation sampling frequency. In the figure, b is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is ⅛ of the delta-sigma modulation sampling frequency.

[0114] 28 is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 16 and 1 / 32 of the delta-sigma modulation sampling frequency when the scale is changed in the first embodiment of the present technology. In the figure, a is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 16 of the delta-sigma modulation sampling frequency. In the figure, b is a diagram showing an example of frequency characteristics of an output signal when the random number sampling frequency is 1 / 32 of the delta-sigma modulation sampling frequency.

[0115] 23 to 28, the vertical axis indicates the level of the output signal, and the horizontal axis indicates the frequency.

[0116] When an input type dither signal is used, the optimal scaling amount is 1 / 16, but since the variation of the analog section in the subsequent stage determines the final noise power, the scaling amount is variable, such as 1 / 32, 1 / 64, 1 / 128, etc. The DC component α supplies half the scaling value. Spurious diffusion near 1 / 2Fs is gradual due to overlapping caused by aliasing. From Figures 23 to 25, the DC amount is -27dBFS (1 / 32) when the noise signal scaling is 1 / 16. From Figures 26 to 28, -39dBFS (1 / 128) is appropriate when the noise signal scaling is 1 / 64.

[0117] Furthermore, when the scaling cannot be set large due to variations in the downstream analog components, or when the downstream amplifier cannot accept differential output, the DC component α is determined and input under certain conditions when a small signal is input. The random number component β is set to 0. Here, the certain conditions are when the frequency estimated from the following formula does not fall within the application band.

number

number

number

number

number

number

[0118] In Equations 10 to 15, x represents the average power of the input signal to the delta-sigma modulator 230 .

[0119] 29 is a block diagram showing an example configuration of a loop filter 300 according to the first embodiment of the present technology. The loop filter 300 includes multiple tap stages, buffer amplifiers 361, 363, and 365, and adders 362 and 364. The number of tap stages is, for example, five, and taps 310, 320, 330, 340, and 350 are provided, for example.

[0120] When the buffer amplifier 361 is operated with low delay, it supplies the input signal In_p as is to the taps 320, 330, 340, and 350. On the other hand, when the loop filter 300 is made to function as a low-pass filter (LPF), the buffer amplifier 361 does not output the input signal In_p.

[0121] The feedback signal FD from the quantizer 234 out2 is input to tap 310 , adder 362 , tap 330 and adder 364 .

[0122] The buffer amplifier 363 amplifies the signal from the tap 330 by 1 / 256 and supplies the signal to the adder 362. The adder 362 multiplies the signal from the buffer amplifier 363 and the feedback signal FD out2 The result is added and supplied to tap 320.

[0123] The buffer amplifier 365 amplifies the signal from the tap 350 by 1 / 256 and supplies the multiplied signal to the adder 364. The adder 364 multiplies the signal from the buffer amplifier 365 and the feedback signal FD out2 and the sum is supplied to tap 340.

[0124] Moreover, tap 310 includes adders 311, 312, a limiter 313, and a delay unit 314. Tap 320 includes a buffer amplifier 321, adders 322, 323, a limiter 324, and a delay unit 325. Tap 330 includes a buffer amplifier 331, adders 332, 333, a limiter 334, and a delay unit 335.

[0125] The adder 311 adds the input signal In_p from the addition unit 220 and the signal from the adder 312, and supplies the result to the delay unit 314 via the limiter 313. The adder 312 adds the signal from the delay unit 314 and the feedback signal FD out2 The delay unit 314 delays the signal from the adder 311 by one clock and supplies the delayed signal to the adder 312 and the buffer amplifier 321. The limiter 313 limits the signal level to within a range of ±16 bits.

[0126] The buffer amplifier 321 amplifies the signal from the delay unit 314 by 1 / 16 and supplies the signal to the adder 322. The adder 322 adds the signal from the buffer amplifier 361, the signal from the buffer amplifier 321, and the signal from the adder 323, and supplies the result to the delay unit 325 via the limiter 324. The adder 323 adds the signal from the delay unit 325 and the signal from the adder 362, and supplies the result to the adder 322. The limiter 324 limits the level of the signal to within a range of ±8 bits. The delay unit 325 delays the signal from the adder 322 by one clock and supplies the signal to the adder 323 and the buffer amplifier 331.

[0127] The buffer amplifier 331 amplifies the signal from the delay unit 325 by 1 / 8 and supplies the signal to the adder 332. The adder 332 adds the signal from the buffer amplifier 361, the signal from the buffer amplifier 331, and the signal from the adder 333, and supplies the result to the delay unit 335 via the limiter 334. The adder 333 multiplies the signal from the delay unit 335 and the feedback signal FD out2 The delay unit 335 adds the signal from the adder 332 and supplies the result to the adder 333, the buffer amplifier 363, and the tap 340. The limiter 334 limits the signal level to within a range of ±4 bits. The delay unit 335 delays the signal from the adder 332 by one clock and supplies the delayed signal to the adder 333, the buffer amplifier 363, and the tap 340.

[0128] 30 is a circuit diagram showing an example configuration of the latter-stage taps 340 and 350 in the first embodiment of the present technology. The tap 340 includes a buffer amplifier 341, an adder 342, an adder 343, a limiter 344, and a delay unit 345. The tap 350 includes a buffer amplifier 351, an adder 352, a limiter 353, an adder 354, an adder 355, and a delay unit 356.

[0129] The buffer amplifier 341 amplifies the signal from the tap 330 by 4 and supplies the signal to the adder 342. The adder 342 adds the signal from the buffer amplifier 361, the signal from the buffer amplifier 341, and the signal from the adder 343, and supplies the result to the delay unit 345 via the limiter 344. The adder 343 adds the signal from the delay unit 345 and the signal from the adder 364, and supplies the result to the adder 342. The limiter 344 limits the level of the signal to within a range of ±4 bits. The delay unit 345 delays the signal from the adder 342 by one clock and supplies the signal to the adder 343 and the buffer amplifier 351.

[0130] The buffer amplifier 351 amplifies the signal from the delay unit 345 by 2 and supplies the result to an adder 352. The adder 352 adds the signal from the buffer amplifier 361, the signal from the buffer amplifier 351, and the signal from the adder 354, and supplies the result to an adder 355. The limiter 353 limits the level of the signal to within a range of ±8 bits. The adder 354 multiplies the signal from the delay unit 356 and the feedback signal FD from the delay unit 236 by 2. out1 The result is supplied to an adder 352 via a limiter 353.

[0131] The adder 355 adds the dither signal DITH of this system and the signal from the adder 352, and supplies the result as a filter output signal Fout to the delay unit 356 and the adder 233. The delay unit 356 delays the signal from the adder 355 by one clock and supplies the result to the adder 354 and the buffer amplifier 365.

[0132] The transfer function of the loop filter 300 illustrated in FIGS.

number

number

number

number

[0133] STF of Equation 16 LL (z) shows the STF (Signal Transfer Function) during low-latency operation. The STF of Equation 17 LPF (z) indicates the STF when the LPF is operating. NTF(z) in Equation 18 indicates the NTF (Noise Transfer Function) of the quantization noise. DTF(z) in Equation 19 indicates the DTF (Dither Transfer Function) of this method. Each frequency characteristic is expressed as e in z when the sampling frequency of delta-sigma modulation is Fs. (j2πf / Fs) can be obtained by substituting

[0134] 31 is a diagram illustrating a configuration of the delta-sigma modulator 230 according to the first embodiment of the present technology. The first-stage tap 310 receives the feedback signal FD out2 and the input signal In_p (in other words, a quantization error), and outputs a signal corresponding to the difference to a tap in the subsequent stage. Note that the tap 310 is an example of a difference calculation section described in the claims.

[0135] In the final-stage tap 350 in the loop filter 300, an adder 352 adds the signal from the previous-stage tap 340 and a signal corresponding to the delayed signal from the delay unit 356, and outputs the result to an adder 355. The output signal of the adder 352 is a signal accumulated by the tap 350, etc. The adder 352 is an example of a delayed signal adder as described in the claims.

[0136] The adder 355 adds the signal from the adder 352 and the dither signal DITH of the present invention, and outputs the result as a filter output signal Fout to the adder 233 and the delay unit 356. Note that the dither signal of the present invention is an example of an internal dither signal recited in the claims, and the adder 355 is an example of an internal dither adder recited in the claims.

[0137] The delay unit 356 delays the filter output signal Fout and supplies the delayed signal to the adder 354. The delay unit 356 is an example of an in-filter delay unit as defined in the claims.

[0138] Moreover, the adder 233 adds the NTF dither signal NTFD to the filter output signal Fout, and supplies the result to the quantizer 234. The adder 233 is an example of an NTF dither adder as defined in the claims.

[0139] The quantizer 234 quantizes the signal from the adder 233 to generate a feedback signal FD out2 The output is fed back to the tap 310 or the like.

[0140] With the configurations illustrated in Figures 29 to 31, spurious noise can be suppressed as illustrated in Figures 13 to 17 regardless of the type of signal that is input, such as an AD converted signal or a signal created by processing a digital source and that contains a DC component.

[0141] For any input signal, only quantization noise similar to the power frequency characteristics of the NTF transfer function determined by the topology of delta-sigma modulation is added, as represented by the examples of the transfer functions in Equations 16 to 19. Therefore, the following effects are obtained.

[0142] It is possible to prevent the occurrence of unexpected sounds that are not in the original sound due to spurious quantization noise. This is particularly noticeable when a small signal within the audible band is input. In addition, since the influence of spurious quantization noise on the analog circuit is prevented in advance, a stable noise level is provided to the analog circuit as theoretically obtained from the NTF transfer function. In addition, the noise level leaking from the differential input multi-bit delta sigma modulator 230 to the audio application band is reduced in response to the variation of the analog circuit.

[0143] Furthermore, appropriate noise can be generated from simple uniform random numbers with the minimum required power. Also, the minimum number of bits required for the dither signal is clear for each dither format, and the output characteristics are stable and spurious-free, making it easier to set design targets for downstream systems regarding leaked noise power. Also, reducing the number of bits to the required number makes it possible to suppress noise signal power. By using 1-bit random numbers for dithering in this method, the noise signal power is reduced by more than -1.0 decibels (dB) compared to when using 2-bit random numbers, which are required for NTF dither signals.

[0144] Furthermore, ineffective and unnecessary circuits can be eliminated. Since the quantized output has a nearly flat frequency amplitude characteristic, a linear frequency phase characteristic, and a minimum delay, the present invention can be effectively used in the following applications.

[0145] For example, there are applications where low latency improves characteristics, such as noise cancellation, and applications where the output of a multi-bit ADC device is converted to 1 bit and the ADC data is transmitted between devices. In the latter case, the transmission power can be reduced.

[0146] Also, since spurious noise generated in the quantizer 234 is logically removed, the filter placed after the pulse shaper 250 can be designed theoretically according to the input tolerance of the amplifier. Also, the acoustic system 100 can logically remove spurious noise generated in the quantizer 234. Therefore, even in an RZ waveform PDM signal that adheres to a linear time-invariant system, spurious removal only requires consideration of spurious that are integer multiples of the sampling frequency of the delta-sigma modulation, making it easier to design a system that maintains low delay.

[0147] Furthermore, in the DTF dithering method and the NTF dithering method, noise leaking into the audible band is suppressed in advance, as represented by the examples of the transfer functions of Equations 16 to 19. Therefore, the influence of noise on the audible band due to variations in gain in the subsequent stages can be ignored.

[0148] The 1-bit quantizer 234 requires an input-type dither signal to obtain an ideal output from any input signal. This makes it clear that the goal of suppressing the variation in gain in the subsequent stages is to avoid noise input into the audible band.

[0149] The NTF dither signal has the advantage that it can be used for all output amplifiers, including S / E digital amplifiers. In contrast, the dither signal of this method is premised on differential input, such as an analog amplifier or a digital amplifier connected in a BTL (Balanced Transformer Less) connection. The source of spurious is a quantizer that operates nonlinearly, and the frequency at which spurious occurs is uniquely determined, as shown in Equations 10 to 15. However, the frequency changes depending on the intermodulation product between the input average power value and the input signal. The loop filter 300 operates linearly, so it does not convert the frequency. Therefore, it is desirable to remove the periodicity of quantization by adding noise with a flat frequency characteristic, and the NTF dither signal, which inputs a countermeasure signal just before the quantizer that is the source of spurious, does not become flat because its frequency characteristic is NTF. If the dither signal is generated using a 1-bit random number, it is not possible to completely suppress the occurrence of spurious. In this case, a 2-bit random number is essential. The dither signal of this method, which is inserted into the final stage of the loop filter 300, can be generated using a 1-bit random number. As a result, the power required for random number generation is reduced by 50%, and the power of unnecessary noise signals input into the system can be reduced by more than 20%.

[0150] Fig. 32 is a graph showing the frequency amplitude characteristics of each transfer function of Equation 16 to Equation 19. Fig. 32 shows the frequency phase characteristics of the STF. The low-delay STF has a linear phase and an almost flat amplitude characteristic over the entire range.

[0151] The input / output delay amount calculated from the phase characteristic is 0.163 microseconds (μs) for the low-delay STF when Fs=48 kilohertz (kHz) for audio applications and the sampling frequency of the delta-sigma modulator 230 is Fs=128 fs. Also, the STF of the LPF is 2.82 microseconds (μs) in the range of DC-20 kilohertz (kHz). Since the sampling interval of the delta-sigma modulator 230 is 0.163 microseconds (μs), the low-delay STF has reached its limit value.

[0152] If necessary, the latency can be further reduced by shifting the clock phase of only the flip-flop of the output port. However, it is necessary to execute the operations of all channels within the shortened interval.

[0153] Figure 33 shows the THD+N characteristics for each quantizer output type and dithering method. It can be seen that the origin symmetric class type has better characteristics than the origin class median type. NTF dither is the characteristic during S / E, and is the lower limit of the characteristics that can be guaranteed in a system with a quantizer output bit count of 2 or more.

[0154] 34 to 36 are diagrams comparing the characteristics of the dither signal of this system and the NTF dither signal of differential operation in the degradation region of this topology where the average power of the input signal is −6 dBFS or more.

[0155] 34A is a diagram showing an example of the THD+N characteristics when the dither signal of this method and the origin symmetric class type are used, and FIG. 34B is a diagram showing an example of the THD+N characteristics when the dither signal of this method and the origin symmetric median type are used.

[0156] 35A is a diagram showing an example of the THD+N characteristics when an NTF dither signal and an origin symmetric class type are used, and FIG. 35B is a diagram showing an example of the THD+N characteristics when an NTF dither signal and an origin symmetric median type are used.

[0157] 36A is a diagram showing an example of the THD+N characteristics when an input type dither signal and an origin symmetric class type are used, and FIG. 36B is a diagram showing an example of the THD+N characteristics when an input type dither signal and an origin symmetric median type are used.

[0158] The advantage of a 1 decibel (dB) difference in dither signal power does not appear in the threshold of the degradation of the input average power of the THD+N characteristics. It is selected due to the effect that appears when noise with frequency characteristics determined by the transfer function of DTF(f)?N0 and NTF(f)?N0×1.25 and the white noise power density N0 is output to the outside due to the variation in the analog domain.

[0159] 37 is a diagram showing an example of THD+N characteristics when the number of quantization output bits in the first embodiment of the present technology is 3. In the figure, a shows the characteristics when the origin symmetric class type is used, and b shows the characteristics when the origin symmetric median type is used.

[0160] 38 is a diagram showing an example of THD+N characteristics when the number of quantization output bits in the first embodiment of the present technology is 4. In the figure, a shows the characteristics when the origin symmetric class type is used, and b shows the characteristics when the origin symmetric median type is used.

[0161] 39 is a diagram showing an example of THD+N characteristics when the number of quantization output bits in the first embodiment of the present technology is 5. In the figure, a shows the characteristics when the origin symmetric class type is used, and b shows the characteristics when the origin symmetric median type is used.

[0162] 37 to 39 also determine the 6 decibel (dB) attenuator function of the input converter 210, or the amount of adjustment of a fixed attenuator of the signal power in the stage preceding the input converter 210. The amount of adjustment varies with the topology of the delta-sigma modulation.

[0163] Next, a description will be given of the pulse shaper 250 outputting a PWM signal. In this case, the clock timing generator 270 outputs a PWM signal twice as fast as the sampling frequency of the delta-sigma modulation, such as 16 times or 32 times. N When the amplifier 160 is an S / E amplifier, the pulse shaper 250 uses only one output from the delta-sigma modulator 230 per channel of the input signal and outputs it to the amplifier 160. On the other hand, when the amplifier 160 is a BTL amplifier, the pulse shaper 250 uses two outputs from the delta-sigma modulator 230 per channel of the input signal and outputs them to two amplifiers.

[0164] The method of conversion to a PWM signal is one-sided modulation, two-sided modulation, etc., and the pulse shaper 250 converts the straight binary value of the delta-sigma modulator 230 into a pulse waveform in accordance with a known modulation method and outputs it.

[0165] Next, the pulse shaper 250 will be described when outputting a PDM signal. The pulse shaper 250 has a function of treating the output of the delta-sigma modulator 230 as an impulse train, generating a waveform for one impulse, and providing a delay tap for a subsequent FIR (Finite Impulse Response) filter. The delay tap in the FIR filter delays and outputs a pulse waveform according to the sampling frequency of the FIR filter required to define the target filter characteristics. The frequency of the clock supplied to the pulse shaper 250 can be adapted to the configuration of the delay tap as long as it has the accuracy to generate a pulse waveform.

[0166] The most conventional method is to drive the DAC 150 and amplifier 160 with a pulse width that is the inverse of the delta-sigma modulation sampling frequency, making it possible to operate the device by supplying a clock with the same frequency as the delta-sigma modulation sampling frequency. Spurious signals that occur at integer multiples of the delta-sigma modulation sampling frequency are attenuated at the zero point of the sample-and-hold frequency characteristics. For this reason, the analog FIR filter achieves the characteristic of attenuating quantization noise to a level acceptable to the DAC 150 and amplifier 160 in accordance with the number of quantizer output bits.

[0167] 40 is a diagram for explaining the configuration after pulse shaper 250 which outputs a PDM signal. Retiming circuit 140 in the figure corresponds to a circuit consisting of a predetermined number of flip-flops 141. An FIR filter is provided in DAC 150. Inside pulse shaper 250, a delay device synchronized with a clock corresponding to the tap of the FIR filter is configured. When the number of output bits of a quantizer (not shown) is large and attenuation by the FIR filter is not necessary, one output is generated per input, and the other outputs are fixed to 0.

[0168] A system having a pulse width that is the inverse of the sampling frequency of delta-sigma modulation is an NRZ waveform output by a flip-flop, and therefore is not, in principle, a linear time-invariant system.

[0169] Figure 41 shows that the pulse waveform of "1", "1" generated by the NRZ waveform in the top row becomes the waveform in the middle row, which is an LTI (Linear Time-Invariant) system, and the actual output of the flip-flop becomes the waveform in the bottom row, showing that linearity is lost.

[0170] FIG. 42 shows that linearity is maintained with an RZ waveform.

[0171] A clock signal with a frequency eight times the sampling frequency of the delta modulation is supplied to the pulse shaper 250, and the output of an RZ waveform with a pulse width of 7 / 8 is 20 × log 10At (7 / 8), there is a loss of -1.1 decibels (dB) in the output. However, an output that is close to the original value can be generated by using an LTI system. If the FIR filter is driven at the same sampling frequency as the delta-sigma modulator 230, as with the NRZ waveform, spurious signals at integer multiples of the sampling frequency of the delta-sigma modulation will be generated significantly, except for multiples of 8. This is because the frequency characteristics of the NRZ waveform are equivalent to those of the FIR filter coefficients and the sampling frequency of the FIR filter.

[0172] As an example, a filter in which the sampling frequency of the FIR filter is eight times the sampling frequency of the delta-sigma modulation and all coefficients of the eight taps are the same is presented by the following equation.

number

[0173] This is based on the assumption that the number of quantization bits is large and the quantization noise is at a low level. The number of quantized output bits is 4 or more. When the quantized output is 3 bits, this can be achieved by determining the power supplies of the DAC 150 and the amplifier 160 so that they operate with a signal whose quantization noise has been attenuated by an analog RC filter, or by setting the sampling frequency of the delta-sigma modulator 230 to a high value.

[0174] This application example is merely an example and does not limit the operation of the pulse shaper 250, but it is possible to minimize the delay caused by the FIR filter.

[0175] In this way, according to the first embodiment of the present technology, the dither signal DITH of this method is added to the integrated signal in the loop filter 300, so that spurious noise can be suppressed more than when the NTF dither signal is added outside the loop filter 300.

[0176] <2. Second embodiment> In the above-described first embodiment, the loop filter 300 and the like are arranged on each of the positive and negative sides of the differential signal in the delta-sigma modulator 230, but the circuit size may increase as the number of filter stages increases. The noise reduction processing device 200 of the second embodiment differs from the first embodiment in that a circuit is shared between the positive and negative sides.

[0177] 43 is a block diagram showing an example of a configuration of the addition unit 220 according to the second embodiment of the present technology. The addition unit 220 according to the second embodiment includes flip-flops 224 to 226 and adders 222 and 223.

[0178] The flip-flop 224 is synchronous with the clock signal and holds the input signal In from the input converter 210. The flip-flop 224 supplies the held signal to the adder 222.

[0179] The flip-flop 225 holds the input signal In in synchronization with the clock signal. The flip-flop 225 supplies the held signal to the adder 223.

[0180] The flip-flop 226 synchronizes with the clock signal and holds a signal indicating the integer value intSRFs from the dither signal generator 260 as the input dither signal IN_DITH. The flip-flop 226 supplies the held signal to the adders 222 and 223.

[0181] The adder 222 adds the signal from the flip-flop 224 and the signal from the flip-flop 226, and supplies the result as a positive input signal In_p to the selector 227. The adder 223 adds the signal from the flip-flop 225 and the signal from the flip-flop 226, and supplies the result as a negative input signal In_n to the selector 227.

[0182] An integer value intDSFs of “0” or “1” is input to the selector 227. The integer value intDSFs is set, for example, by the clock timing generator 270. When the integer value intDSFs is “0”, the selector 227 selects the input signal In_p and outputs it to the delta-sigma modulator 230, and when the integer value intDSFs is “1”, the selector 227 selects the input signal In_n and outputs it to the delta-sigma modulator 230.

[0183] 44 is a block diagram showing a configuration example of a delta-sigma modulator 230 according to a second embodiment of the present technology. The delta-sigma modulator 230 according to the second embodiment includes a loop filter 300, an adder 233, a quantizer 234, and flip-flops 241 to 246. The delta-sigma modulator 230 according to the second embodiment differs from the first embodiment in that the loop filter 300 and the like shown in the figure are shared by two channels, the positive side and the negative side.

[0184] The flip-flop 241 holds a signal indicating the integer value intDSFs as the dither signal DITH of the present invention in synchronization with the clock signal.

[0185] The flip-flop 242 holds a signal indicating the integer value intDSFs as an NTF dither signal NTFD in synchronization with the clock signal. The flip-flop 242 supplies the held NTF dither signal NTFD to the adder 233.

[0186] The flip-flop 243 synchronizes with the clock signal when the integer value intDSFs is “1”, and holds the signal from the quantizer 234 as the positive output signal Out_p. The flip-flop 243 supplies the held output signal Out_p to the pulse shaper 250.

[0187] The flip-flop 244 synchronizes with the clock signal when the integer value intDSFs is “1”, and holds the signal from the flip-flop 245 as the negative output signal Out_n. The flip-flop 244 supplies the held output signal Out_n to the pulse shaper 250.

[0188] The flip-flop 245 holds the signal from the quantizer 234 in synchronization with the clock signal, and outputs it to the flip-flops 244 and 246 .

[0189] The flip-flop 246 holds the signal from the flip-flop 245 in synchronization with the clock signal and outputs a feedback signal FD out2 to the loop filter 300.

[0190] 45 is a block diagram showing a configuration example of a loop filter 300 according to a second embodiment of the present technology. A tap 310 according to the second embodiment differs from the first embodiment in that it includes flip-flops 315 and 316 instead of the delay unit 314. A tap 320 according to the second embodiment differs from the first embodiment in that it includes flip-flops 326 and 327 instead of the delay unit 325. A tap 330 according to the second embodiment differs from the first embodiment in that it includes flip-flops 336 and 337 instead of the delay unit 335.

[0191] 46 is a circuit diagram showing a configuration example of a latter-stage tap in the second embodiment of the present technology. Tap 340 of the second embodiment differs from the first embodiment in that it includes flip-flops 346 and 347 instead of delay unit 345. Tap 350 of the second embodiment differs from the first embodiment in that it includes flip-flops 357 and 358 instead of delay unit 356.

[0192] With the configurations shown in Figures 43 and 44, various arithmetic units can be shared between the two channels, the positive and negative sides. The same signal can also be input to both channels. In this case, there is an advantage that data changes are halved even when operating with a double-speed clock.

[0193] For example, in an application where only one input signal is to be output in phase, the input converter 210 at the front stage generates identical input data for both channels and provides it to the delta-sigma modulator 230. The value held in the flip-flop of one output is fixed to "0." Also, the data of the output port is set to straight binary format. When performing an operation in two's complement, only the MSB (Most Significant Bit) is logically inverted.

[0194] 43 and 44 can be used for the following four applications. The input signal is controlled by the input converter 210, and the output signal is controlled by the delta-sigma modulator 230. Each has limitations on the dithering method.

[0195] The first use is when one signal x is converted by the following formula, input to the delta-sigma modulator 230, and outputted as differential signals {Out_p, Out_n}. {In_p, In_n}={+X(+IN_DITH), -X(+IN_DITH)}

[0196] The second use is when one signal x is converted by the following formula, input to the delta-sigma modulator 230, and one of the signals is output as {OUT_P, 0}, which is fixed to 0. {In_p, In_n}={+X(+IN_DITH),+X(+IN_DITH)}

[0197] The second use is effective when using NTF dither signals and when the random number component of the input dither signal is set to 0. This setting is also the setting when outputting an S / E PWM signal.

[0198] The third use case is to convert a differential signal to ADC1 and ADC2 and select one of them as needed to output one signal, or to output two signals simultaneously, using the following formula: {In_p, In_n} = {ADC1, ADC1} →{Out_p, Out_n} = {ADC1, 0} {In_p, In_n} = {ADC2, ADC2} →{Out_p, Out_n}={0, ADC2} {In_p, In_n} = {ADC1, ADC2} →{Out_p, Out_n}={ADC1, ADC2}

[0199] The third use is useful when the random component of an input dither signal is set to zero.

[0200] If the system subsequent to the pulse shaper 250 supports differential input but requires a common for noise components between differential signals due to variations, the following fourth setting is made.

[0201] The fourth use is when one signal x is converted according to the following formula, input to the delta-sigma modulator 230, and one of the signals is logically inverted and output as {Out_p, −Out_n}. {In_p, In_n}={+X(+IN_DITH),+X(+IN_DITH)}

[0202] The fourth use is useful when using NTF dither signals and when the random component of the input dither signal is set to 0.

[0203] When the input PCM data is P bits (P is an integer), the delta sigma modulator 230 sets the P+1 bit input signal to 0 dBFS. The MSB is configured as the integer part of a P+1 bit signed integer part, a 1-bit fixed point number.

[0204] The input converter 210 receives a P-bit PCM signal and outputs a P+1-bit output PCM signal to the delta-sigma modulator 230. When the input signal is shifted from the MSB side and output with the LSB at 0, an attenuation of 0 dB is achieved, and when the input signal is arithmetically right-shifted by 1 bit and output, an attenuation of 6 decibels (dB) is achieved.

[0205] The configurations illustrated in Figures 43 and 44 are two-channel multiplexed, but the number of channels to be multiplexed is determined by the ratio of the operating clock to the sampling frequency required for delta-sigma modulation, and the signal is converted by the input converter 210 so that the amount of toggle is minimized.

[0206] The input converter 210 adds an input signal for the input dither signal equally to the output signal when it is input.

[0207] In this way, according to the second embodiment of the present technology, the selector 227 in the adder 220 alternately selects the positive input signal and the negative input signal, so that the positive and negative sides can share the circuit. This allows the circuit scale to be reduced compared to a case where the circuit is not shared.

[0208] <3. Third embodiment> In the first embodiment described above, the delta sigma modulator 230 outputs a filter output signal to the flip-flop 141 via the pulse shaper 250. However, the delta sigma modulator 230 can also output a signal to a CIC (Cascaded Integrator-Comb) filter. The audio system of the third embodiment differs from the first embodiment in that the delta sigma modulator 230 outputs a signal to a CIC filter.

[0209] 47 is a block diagram showing an example of a configuration of an audio system 100 according to the third embodiment of the present technology. The audio system 100 according to the third embodiment includes multi-bit ADCs 181 and 182, a noise reduction processing device 200, and a subsequent device 190.

[0210] Furthermore, the noise reduction processing device 200 does not include the pulse shaper 250. The subsequent device 190 includes a CIC filter 191 and a crystal oscillator 192.

[0211] The multi-bit ADCs 181 and 182 provide input signals to the input converter 210. The crystal oscillator 192 provides a clock signal to the clock timing generator 270. The delta-sigma modulator 230 provides a filter output signal to the CIC filter 191.

[0212] In the CIC filter 191, the random number component β is set to 0 since the quantization noise is folded back by the decimation.

[0213] If the delta-sigma modulator 230 provides the filter output signal to the CIC filter 191, then the pulse shaper 250 is unnecessary and eliminated, as illustrated in the figure.

[0214] As described above, according to the third embodiment of the present technology, the delta-sigma modulator 230 supplies a filter output signal to the CIC filter 191, so that the pulse shaper 250 can be eliminated.

[0215] The above-mentioned embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specified in the claims correspond to each other. Similarly, the matters specified in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist of the technology.

[0216] It should be noted that the effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0217] The present technology can also be configured as follows. (1) a difference calculation unit that calculates a difference between an input signal and a predetermined feedback signal and outputs the difference as an error signal; a delay signal adder that adds the error signal and a predetermined delay signal and outputs the result as an integrated signal; an internal dither adder that adds the integrated signal and a predetermined internal dither signal and outputs the result as a filter output signal; a filter internal delay unit that delays the filter output signal and outputs the delayed signal; a quantizer that quantizes the filter output signal and feeds it back as the feedback signal. (2) A dither signal generator is further provided for generating the internal dither signal and supplying the internal dither signal to the internal dither adder when a differential signal is input as the input signal. The noise reduction processing device according to (1). (3) further comprising an adder for adding a predetermined input type dither signal to the digital signal and supplying the result as the input signal; The dither signal generator generates the input type dither signal when a single-ended signal is input as the input signal and supplies the input type dither signal to the adder. The noise reduction processing device according to (2). (4) further comprising an NTF dither adder for adding a predetermined NTF (Noise Transfer Function) dither signal to the filter output signal and outputting the result to the quantizer; The dither signal generator generates either the NTF dither signal or the internal dither signal when a differential signal is input as the input signal. The noise reduction processing device according to (3) above. (5) the differential signal includes a positive signal and a negative signal; The adding unit includes a selector that alternately selects the positive side signal and the negative side signal and outputs the selected signal as the input signal. The noise reduction processing device according to (3) or (4). (6) the differential signal includes a positive signal and a negative signal; The adding unit is a positive-side adder that adds the input type dither signal to the positive-side signal and supplies the result to a positive-side circuit; a negative-side adder that adds the input-type dither signal to the negative-side signal and supplies the result to a negative-side circuit; Equipped with The difference calculation unit, the delay signal adder, the internal dither adder, and the filter internal delay unit are disposed in the positive side circuit and the negative side circuit, respectively. The noise reduction processing device according to (3) or (4). (7) an analog-to-digital converter that generates an input signal by analog-to-digital conversion; a difference calculation unit that calculates a difference between the input signal and a predetermined feedback signal and outputs the difference as an error signal; a delay signal adder that adds the error signal and a predetermined delay signal and outputs the result as an integrated signal; an internal dither adder that adds the integrated signal and a predetermined internal dither signal and outputs the result as a filter output signal; a filter internal delay unit that delays the filter output signal and outputs the delayed signal; a quantizer that quantizes the filter output signal and feeds it back as the feedback signal; An audio system equipped with: (8) Further comprising a pulse shaper for shaping the waveform of the filter output signal. 8. The acoustic system according to claim 7. (9) The filter output signal is further provided with a CIC (Cascaded Integrator-Comb) filter. The acoustic system according to (7) or (8) above. (10) a difference calculation procedure for calculating a difference between an input signal and a predetermined feedback signal and outputting the difference as an error signal; a delay signal adding step of adding the error signal and a predetermined delay signal and outputting the result as an integrated signal; an internal dither adding step of adding the integrated signal and a predetermined internal dither signal and outputting the result as a filter output signal; a filter delay step of delaying the filter output signal and outputting the delayed signal; a quantization step of quantizing the filter output signal and feeding it back as the feedback signal; A method for controlling a noise reduction processing device comprising the steps of: [Explanation of symbols]

[0218] 100 Sound System 110 ADC 120 Digital Processing Unit 130, 192 Crystal oscillator 140 Retiming Circuit 141, 224-226, 241-246, 315, 316, 326, 327, 336, 337, 346, 347, 357, 358 Flip-flops 150DAC 160 Amps 170 Speaker 181, 182 Multi-bit ADC 190 Back-end device 191 CIC Filter 200 Noise reduction processing device 210 Input Converter 220 Addition section 221 Inverting Amplifier 222, 223, 233, 311, 312, 322, 323, 332, 333, 342, 343, 352, 354, 355, 362, 364 adders 227 Selector 230 Delta Sigma Modulator 231 Positive side circuit 232 Negative side circuit 234 Quantizer 235, 236, 314, 325, 335, 345, 356 Delay section 250 Pulse Shaper 260 Dither Signal Generator 270 Clock Timing Generator 280 Registers 300 Loop Filter 310, 320, 330, 340, 350 Tap 313, 324, 334, 344, 353 Limiter 321, 331, 341, 351, 361, 363, 365 Buffer Amplifiers

Claims

1. a difference calculation unit that calculates a difference between an input signal and a predetermined feedback signal and outputs the difference as an error signal; a delay signal adder that adds the error signal and a predetermined delay signal and outputs the result as an integrated signal; an internal dither adder that adds the integrated signal and a predetermined internal dither signal and outputs the result as a filter output signal; a filter internal delay unit that delays the filter output signal and outputs the delayed signal; a quantizer that quantizes the filter output signal and feeds it back as the feedback signal; A noise reduction processing device comprising:

2. The input signal may further include a dither signal generator for generating the internal dither signal and supplying the internal dither signal to the internal dither adder when a differential signal is input as the input signal. The noise reduction processing device according to claim 1.

3. An adder unit that adds a predetermined input type dither signal to the digital signal and supplies the result as the input signal, The dither signal generator generates the input type dither signal when a single-ended signal is input as the input signal and supplies the input type dither signal to the adder. The noise reduction processing device according to claim 2.

4. an NTF dither adder that adds a predetermined NTF (Noise Transfer Function) dither signal to the filter output signal and outputs the result to the quantizer; a dither signal generator for generating the NTF dither signal when a differential signal is input as the input signal; Further comprising The noise reduction processing device according to claim 1.

5. the differential signal includes a positive signal and a negative signal, The adding unit is a positive-side adder that adds the input-type dither signal to the digital signal and outputs the result as the positive-side signal; a negative-side adder that adds the input-type dither signal to the digital signal and outputs the result as the negative-side signal; a selector that alternately selects the positive side signal and the negative side signal and outputs the selected signal as the input signal; Equipped The noise reduction processing device according to claim 3.

6. the differential signal includes a positive signal and a negative signal, The adding unit is a positive-side adder that adds the input type dither signal to the positive-side signal and supplies the result to a positive-side circuit; a negative-side adder that adds the input-type dither signal to the negative-side signal and supplies the result to a negative-side circuit; Equipped with The difference calculation unit, the delay signal adder, the internal dither adder, and the filter internal delay unit are disposed in the positive side circuit and the negative side circuit, respectively. The noise reduction processing device according to claim 3.

7. an analog-to-digital converter for generating an input signal by analog-to-digital conversion; a difference calculation unit that calculates a difference between the input signal and a predetermined feedback signal and outputs the difference as an error signal; a delay signal adder that adds the error signal and a predetermined delay signal and outputs the result as an integrated signal; an internal dither adder that adds the integrated signal and a predetermined internal dither signal and outputs the result as a filter output signal; a filter internal delay unit that delays the filter output signal and outputs the delayed signal; a quantizer that quantizes the filter output signal and feeds it back as the feedback signal; An audio system equipped with:

8. The filter further includes a pulse shaper for shaping the waveform of the filter output signal.

8. The audio system of claim 7.

9. The filter output signal is input to a CIC (Cascaded Integrator-Comb) filter.

8. The audio system of claim 7.

10. a difference calculation procedure for calculating a difference between an input signal and a predetermined feedback signal and outputting the difference as an error signal; a delay signal adding step of adding the error signal and a predetermined delay signal and outputting the result as an integrated signal; an internal dither adding step of adding the integrated signal and a predetermined internal dither signal and outputting the result as a filter output signal; a filter delay step of delaying the filter output signal and outputting the delayed signal; a quantization step of quantizing the filter output signal and feeding it back as the feedback signal; A method for controlling a noise reduction processing device comprising the steps of:

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