Decoding System and Physical Layout for Analog Neural Memory in Deep Learning Artificial Neural Networks

By combining CMOS technology and nonvolatile memory arrays, the coding system and physical layout are improved, and the shortcomings of artificial neural network hardware technology in the existing technology are solved, efficient vector matrix multiplication and space utilization efficiency are achieved, which is suitable for the high-performance implementation of deep learning artificial neural networks.

JP7668307B2Active Publication Date: 2025-04-24SILICON STORAGE TECHNOLOGY INC
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Patent Information

Application Number
JP2023111962
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2019-07-03
Filing Date
2023-07-07
Publication Date
2025-04-24
Estimated Expiration
2039-11-17

AI Technical Summary

Technical Problem

The prior art lacks appropriate hardware technology when developing high-performance artificial neural networks, especially in the encoding system and physical layout of nonvolatile memory cells, making it difficult to achieve efficient vector matrix multiplication operations, and at the same time there is a problem of low space utilization efficiency.

Method used

Using a coding system and physical layout combining CMOS technology and nonvolatile memory arrays, through improved line decoder and control gate decoder design, the encoding and operation mode of nonvolatile memory units is optimized, space utilization efficiency is improved, and efficient vector matrix multiplication is supported.

Benefits of technology

It realizes efficient vector matrix multiplication operation, reduces energy consumption and improves space utilization efficiency, and is suitable for high-performance implementation of deep learning artificial neural networks.

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Abstract

To provide an improved decoding system and physical layout for an analog neural memory system which uses a non-volatile memory cell.SOLUTION: An analog neural memory system includes a plurality of vector matrix multiplication arrays, a plurality of low voltage row decoders, and a plurality of global high voltage row decoders. Each of the low voltage row decoders provides a row decoder function for one of the plurality of vector matrix multiplication arrays, and each of the global high voltage row decoders is shared by two of the plurality of vector matrix multiplication arrays and provides a high voltage signal to two of the plurality of low voltage row decoders.SELECTED DRAWING: None
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