Control System

Abstract

The present invention suppresses current collapse in a normally-ON dual-gate bidirectional switch. A dual-gate bidirectional switch (1) has a first gate (G1), a first source (S1), a second gate (G2), and a second source (S2). A control system (10) is provided with a first gate drive circuit (11), a second gate drive circuit (12), and a controller (13). The controller (13) controls the first gate drive circuit (11) and the second gate drive circuit (12). In the event that the potential of the first source (S1) is lower than the potential of the second source (S2) when the dual-gate bidirectional switch (1) is turned ON, the controller (13) applies a first positive voltage between the first gate (G1) and first source (S1) from the first gate drive circuit (11) for only a first period, and applies a voltage smaller than the first positive voltage after the first period has elapsed.

Description

Control system and method for controlling dual gate bidirectional switch

[0001] The present disclosure relates to a control system, a switch system, and a control method for a dual-gate bidirectional switch, and more particularly to a control system for a dual-gate bidirectional switch or a unidirectional switch, a switch system including the control system, and a control method for a dual-gate bidirectional switch.

[0002] Conventionally, semiconductor devices using nitride semiconductors have been known to have a problem called current collapse, in which conduction resistance increases when the device is switched on. Also, a bidirectional switch element that can suppress current collapse is known (Patent Document 1).

[0003] International Publication No. 2020 / 004021

[0004] The bidirectional switch element disclosed in Patent Document 1 is a normally-off type transistor, and Patent Document 1 does not describe suppressing current collapse in a normally-on type dual-gate bidirectional switch.

[0005] An object of the present disclosure is to provide a control system for suppressing current collapse in a switch made of a normally-on nitride semiconductor, and a control method for a dual-gate bidirectional switch.

[0006] A control system according to one aspect of the present disclosure is a control system for a normally-on dual-gate bidirectional switch. The dual-gate bidirectional switch has a first gate, a first source corresponding to the first gate, a second gate, and a second source corresponding to the second gate. The control system includes a first gate drive circuit, a second gate drive circuit, and a controller. The first gate drive circuit is connected between the first gate and the first source. The second gate drive circuit is connected between the second gate and the second source. The controller controls the first gate drive circuit and the second gate drive circuit. When turning on the dual-gate bidirectional switch, if the potential of the first source is lower than the potential of the second source, the controller causes the first gate drive circuit to apply a first positive voltage between the first gate and the first source for a first period, and then applies a voltage smaller than the first positive voltage after the first period has elapsed.

[0007] In a control method for a dual-gate bidirectional switch according to another aspect of the present disclosure, the dual-gate bidirectional switch is a normally-on dual-gate bidirectional switch having a first gate, a first source corresponding to the first gate, a second gate, and a second source corresponding to the second gate. In the control method for the dual-gate bidirectional switch, when turning on the dual-gate bidirectional switch, if the potential of the first source is lower than the potential of the second source, a first positive voltage is applied between the first gate and the first source for a first period, and a voltage smaller than the first positive voltage is applied after the first period has elapsed.

[0008] Another aspect of the control system according to the present disclosure is a control system for a normally-on single-gate field effect transistor having a gate, a source, and a drain. The field effect transistor includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a source electrode, a gate electrode, a drain electrode, and a p-type layer. The first nitride semiconductor layer is formed on the substrate. The second nitride semiconductor layer is formed on the first nitride semiconductor layer. The second nitride semiconductor layer has a larger bandgap than the first nitride semiconductor layer. The source electrode, the gate electrode, and the drain electrode are formed on the second nitride semiconductor layer. The p-type layer is interposed between the gate electrode and the second nitride semiconductor layer. The gate includes a gate electrode and the p-type layer. The source includes a source electrode, and the drain includes a drain electrode. The control system includes a gate drive circuit and a controller. The gate drive circuit is connected between the gate and the source. The controller controls the gate drive circuit. Furthermore, when the field effect transistor is turned on, if the potential of the source is lower than the potential of the drain, the controller causes the gate drive circuit to apply a first positive voltage between the gate and the source for only a first period, and then applies a voltage smaller than the first positive voltage after the first period has elapsed.

[0009] The control system and control method for a dual-gate bidirectional switch disclosed herein can suppress current collapse in a normally-on dual-gate bidirectional switch. Also, the control system disclosed herein can suppress current collapse in a normally-on unidirectional switch made of a nitride semiconductor.

[0010] FIG. 1 is a circuit diagram of a switch system including a control system according to an embodiment. FIG. 2A is a circuit diagram of a first gate drive circuit in the control system. FIG. 2B is a circuit diagram of a second gate drive circuit in the control system. FIG. 3 is a cross-sectional view of a dual-gate bidirectional switch controlled by the control system. FIG. 4 is a gate voltage-gate current characteristic diagram of the dual-gate bidirectional switch controlled by the control system. FIG. 5 is a timing chart for explaining the operation of the control system. FIG. 6 is a timing chart for explaining an example of switching timing of the first switch, the second switch, and the third switch in the control system. FIG. 7 is an explanatory diagram of the operation of the dual-gate bidirectional switch controlled by the control system. FIG. 8A is an explanatory diagram of the operation of a control system according to a first modified example of the embodiment. FIG. 8B is an explanatory diagram of the operation of a control system according to a second modified example of the embodiment. FIG. 9 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a third modified example of the embodiment. FIG. 10 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a fourth modified example of the embodiment. FIG. 11 is an explanatory diagram of the operation of the control system of the same. FIG. 12 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a fifth modified example of the embodiment. FIG. 13 is an explanatory diagram of the operation of the control system of the same. FIG. 14 is a circuit diagram of a CMOS inverter in a control system according to a sixth modified example of the embodiment. FIG. 15 is an explanatory diagram of the operation of the control system of the same. FIG. 16 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a seventh modified example of the embodiment. FIG. 17A is a circuit diagram of a first gate drive circuit in a control system according to an eighth modified example of the embodiment. FIG. 17B is a circuit diagram of a second gate drive circuit in the control system of the same. FIG. 18 is a waveform diagram of a first gate voltage and a second gate voltage of a switch system including the control system of the same. FIG. 19 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a comparative example. FIG. 20 is a waveform diagram of a first gate voltage and a second gate voltage of a switch system including the control system of the same.FIG. 21 is a characteristic diagram of on-resistance of a control system according to an eighth modification of the embodiment and a control system according to a comparative example. FIG. 22 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a ninth modification of the embodiment. FIG. 23 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a tenth modification of the embodiment. FIG. 24A is an explanatory diagram of the operation of the control system according to the same. FIG. 24B is an explanatory diagram of the operation of the control system according to the same. FIG. 25 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to an eleventh modification of the embodiment. FIG. 26A is an explanatory diagram of the operation of the control system according to the same. FIG. 26B is an explanatory diagram of the operation of the control system according to the same. FIG. 27 is a circuit diagram showing another configuration example of a clamp circuit. FIG. 28 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a twelfth modification of the embodiment. FIG. 29 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a thirteenth modification of the embodiment. Fig. 30 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a fourteenth modification of an embodiment. Fig. 31 is a circuit diagram of a first gate drive circuit and a second gate drive circuit in a control system according to a fifteenth modification of an embodiment. Fig. 32 is a circuit diagram of a switch system including a control system according to a sixteenth modification of an embodiment. Fig. 33 is a characteristic diagram of an on-resistance of a control system according to a sixteenth modification of an embodiment and a timing chart for explaining the operation of the control system. Fig. 34 is a cross-sectional view of a field-effect transistor used in a control system according to a sixteenth modification of an embodiment.

[0011] (Embodiment) A control system 10 according to an embodiment and a switch system 20 including the same will be described below with reference to Fig. 1. Fig. 1 is a circuit diagram of the switch system 20 including the control system 10 according to an embodiment.

[0012] (1) Overview The control system 10 is a control system for a normally-on dual-gate bidirectional switch 1. The dual-gate bidirectional switch 1 has a first gate G1, a first source S1 corresponding to the first gate G1, a second gate G2, and a second source S2 corresponding to the second gate G2. A load circuit including, for example, a series circuit of a load and a power supply is connected between the first source S1 and the second source S2 of the dual-gate bidirectional switch 1. The power supply is, for example, an AC power supply.

[0013] The control system 10 includes a first gate drive circuit 11, a second gate drive circuit 12, and a controller 13. The first gate drive circuit 11 is connected between a first gate G1 and a first source S1. The second gate drive circuit 12 is connected between a second gate G2 and a second source S2. The controller 13 controls the first gate drive circuit 11 and the second gate drive circuit 12.

[0014] The switch system 20 includes a control system 10 and a normally-on type dual-gate bidirectional switch 1 .

[0015] (2) Components of the Switch System (2.1) Dual-Gate Bidirectional Switch The dual-gate bidirectional switch 1 is a one-chip semiconductor switch element. As shown in the cross-sectional view of FIG. 3 , the dual-gate bidirectional switch 1 includes a substrate 102, a first nitride semiconductor layer 104, a second nitride semiconductor layer 105, a first source electrode 171, a first gate electrode 181, a second gate electrode 182, a second source electrode 172, a first p-type layer 161, and a second p-type layer 162.

[0016] The first gate G1 in the dual-gate bidirectional switch 1 includes a first gate electrode 181 and a first p-type layer 161. The second gate G2 in the dual-gate bidirectional switch 1 includes a second gate electrode 182 and a second p-type layer 162. The dual-gate bidirectional switch 1 is a dual-gate GaN-based GIT (Gate Injection Transistor). The first nitride semiconductor layer 104 is, for example, a GaN layer. The second nitride semiconductor layer 105 is, for example, an AlGaN layer. The first p-type layer 161 is, for example, a p-type AlGaN layer. The second p-type layer 162 is, for example, a p-type AlGaN layer.

[0017] The first nitride semiconductor layer 104 is formed on the substrate 102. The second nitride semiconductor layer 105 is formed on the first nitride semiconductor layer 104. The band gap of the second nitride semiconductor layer 105 is larger than the band gap of the first nitride semiconductor layer 104. The first source electrode 171 is formed on the second nitride semiconductor layer 105. The first gate electrode 181 is formed on the second nitride semiconductor layer 105 and is spaced apart from the first source electrode 171. The second gate electrode 182 is formed on the second nitride semiconductor layer 105 and is spaced apart from the first gate electrode 181 on the side opposite to the first source electrode 171 as viewed from the first gate electrode 181. The second source electrode 172 is formed on the second nitride semiconductor layer 105 and is spaced apart from the second gate electrode 182 on the side opposite to the first gate electrode 181 as viewed from the second gate electrode 182. The first p-type layer 161 is interposed between the first gate electrode 181 and the second nitride semiconductor layer 105. The second p-type layer 162 is interposed between the second gate electrode 182 and the second nitride semiconductor layer 105. In the dual-gate bidirectional switch 1, a stacked body 110 including the first nitride semiconductor layer 104, the second nitride semiconductor layer 105, the first p-type layer 161, and the second p-type layer 162 is formed on the substrate 102.

[0018] The substrate 102 is, for example, a silicon substrate. The substrate 102 has a first main surface 121 and a second main surface 122 opposite to the first main surface 121. In the dual-gate bidirectional switch 1, the stack 110 is formed on the first main surface 121 of the substrate 102.

[0019] The first nitride semiconductor layer 104 is formed on the substrate 102 via the buffer layer 103. Here, the above-described stacked body 110 includes the buffer layer 103. In the stacked body 110, the buffer layer 103, the first nitride semiconductor layer 104, and the second nitride semiconductor layer 105 are arranged in this order from the substrate 102 side. The stacked body 110 also includes a first p-type layer 161 and a second p-type layer 162 formed on the second nitride semiconductor layer 105. The buffer layer 103 is, for example, an undoped GaN layer. The GaN layer constituting the first nitride semiconductor layer 104 is, for example, an undoped GaN layer. The AlGaN layer constituting the second nitride semiconductor layer 105 is, for example, an undoped AlGaN layer. The buffer layer 103, the first nitride semiconductor layer 104, and the second nitride semiconductor layer 105 may each contain impurities such as Mg, H, Si, C, and O that are inevitably mixed in during growth by MOVPE (Metal Organic Vapor Phase Epitaxy) or the like.

[0020] The first p-type layer 161 and the second p-type layer 162 cover only a portion of the surface 115 of the second nitride semiconductor layer 105. Therefore, the surface 115 of the second nitride semiconductor layer 105 includes a region that is covered by the first p-type layer 161 and the second p-type layer 162, and a region that is not covered by the first p-type layer 161 and the second p-type layer 162. The first p-type layer 161 and the second p-type layer 162 are separated from each other.

[0021] In the dual-gate bidirectional switch 1, the second nitride semiconductor layer 105 and the first nitride semiconductor layer 104 form a heterojunction HJ1. In the first nitride semiconductor layer 104, two-dimensional electron gas is generated near the heterojunction HJ1. The region containing the two-dimensional electron gas (hereinafter also referred to as a "two-dimensional electron gas layer") can function as an n-channel layer (electron conduction layer). In the dual-gate bidirectional switch 1, the first p-type layer 161, the second nitride semiconductor layer 105, and the n-channel layer form a first pin diode structure. In the dual-gate bidirectional switch 1, the second p-type layer 162, the second nitride semiconductor layer 105, and the n-channel layer form a second pin diode structure.

[0022] The first source electrode 171 and the second source electrode 172 are formed in regions of the surface 115 of the second nitride semiconductor layer 105 that are not covered by the first p-type layer 161 and the second p-type layer 162. The first source electrode 171 and the second source electrode 172 are spaced apart from each other. The first source electrode 171 and the second source electrode 172 are electrically connected to the heterojunction HJ1. Here, "electrically connected" means that they are in ohmic contact. Each of the first source electrode 171 and the second source electrode 172 contains, for example, Ti and Al.

[0023] The first gate electrode 181 is formed on the second nitride semiconductor layer 105 with the first p-type layer 161 interposed therebetween. The second gate electrode 182 is formed on the second nitride semiconductor layer 105 with the second p-type layer 162 interposed therebetween. The distance between the first gate electrode 181 and the second gate electrode 182 is longer than the distance between the first p-type layer 161 and the second p-type layer 162. The first gate electrode 181 and the second gate electrode 182 are spaced apart from the corresponding first source electrode 171 and second source electrode 172, respectively, in a direction along the surface 115 of the second nitride semiconductor layer 105. The first gate electrode 181 and the second gate electrode 182 are in ohmic contact with the first p-type layer 161 and the second p-type layer 162, for example. Each of the first gate electrode 181 and the second gate electrode 182 contains, for example, Pd and Au.

[0024] In the dual-gate bidirectional switch 1, the first source electrode 171, the first gate electrode 181, the second gate electrode 182, and the second source electrode 172 are arranged in this order in one direction along the surface 115 of the second nitride semiconductor layer 105. The first source electrode 171, the first gate electrode 181, the second gate electrode 182, and the second source electrode 172 are spaced apart from each other in the one direction.

[0025] Hereinafter, for convenience of explanation, a state in which a voltage less than a first threshold voltage Vth (e.g., −10 V) with respect to the first source S1 is applied between the first gate G1 and the first source S1 is also referred to as an off state of the first gate G1. Also, a state in which a voltage equal to or greater than the first threshold voltage (including 0 V) ​​with respect to the first source S1 is applied between the first gate G1 and the first source S1 is also referred to as an on state of the first gate G1. Also, a state in which a voltage less than a second threshold voltage Vth2 (e.g., −10 V) with respect to the second source S2 is also referred to as an off state of the second gate G2. Also, a state in which a voltage equal to or greater than the second threshold voltage (including 0 V) ​​with respect to the second source S2 is applied between the second gate G2 and the second source S2 is also referred to as an on state of the second gate G2.

[0026] The dual-gate bidirectional switch 1 is a normally-on bidirectional switch, so that the first gate G1 is in the ON state even when the voltage between the first gate G1 and the first source S1 is 0 V, and the second gate G2 is in the ON state even when the voltage between the second gate G2 and the second source S2 is 0 V.

[0027] The dual-gate bidirectional switch 1 has a first gate voltage V applied to a first gate G1 and a second gate G2. Ｇ１Ｓ１ and the second gate voltage V Ｇ２Ｓ２ The first gate voltage V Ｇ１Ｓ１ is the voltage applied between the first gate G1 and the first source S1. The second gate voltage V Ｇ２Ｓ２is the voltage applied between the second gate G2 and the second source S2. The bidirectional on-state is a state in which current passes in both directions (first direction A1 and second direction A2 opposite to first direction A1). The bidirectional off-state is a state in which current passes in both directions. The first diode state is a state in which current passes only in the first direction A1. The second diode state is a state in which current passes only in the second direction A2.

[0028] The semiconductor switch element 2A is in a bidirectional on state when the first gate G1 is in the on state and the second gate G2 is in the on state. The semiconductor switch element 2A is in a bidirectional off state when the first gate G1 is in the off state and the second gate G2 is in the off state. The semiconductor switch element 2A is in a first diode state when the first gate G1 is in the off state and the second gate G2 is in the on state. The semiconductor switch element 2A is in a second diode state when the first gate G1 is in the on state and the second gate G2 is in the off state.

[0029] A dual-gate bidirectional switch 1 configured with a dual-gate GaN-based GIT (gate injection transistor) has voltage-current characteristics as shown in FIG. 4 , where Vg is the gate voltage applied between the gate (e.g., the first gate G1) and the source (e.g., the first source S1) and Ig is the gate current flowing through the gate. Even when the gate voltage Vg is 0 V, the gate is in the on state, but the gate current Ig does not flow. When the gate voltage Vg becomes a positive voltage, the gate current Ig increases as the gate voltage Vg increases. Even when the gate voltage Vg is a negative voltage, the gate is in the on state as long as the gate voltage Vg is greater than the threshold voltage Vth. The gate is in the off state as long as the gate voltage Vg is less than the threshold voltage Vth.

[0030] (2.2) Control System As shown in FIG. 1 , the control system 10 according to the embodiment includes a first gate drive circuit 11, a second gate drive circuit 12, and a controller 13.

[0031] (2.2.1) First Gate Drive Circuit The first gate drive circuit 11 is connected between the first gate G1 and the first source S1.

[0032] 2A , the first gate drive circuit 11 includes a series circuit including a positive power supply E1 and a first switch SW1, and a series circuit including a second switch SW2, a negative power supply E2, and a third switch SW3. The series circuit including the positive power supply E1 and the first switch SW1 is connected between the first gate G1 and the first source S1. The second switch SW2 is connected between the first gate G1 and the first source S1. The series circuit including the negative power supply E2 and the third switch SW3 is connected between the first gate G1 and the first source S1.

[0033] The first gate drive circuit 11 has a pair of output terminals Tmg and Tms, and between the pair of output terminals Tmg and Tms, there is a parallel circuit including a series circuit including a positive power supply E1 and a first switch SW1, and a series circuit including a second switch SW2, a negative power supply E2, and a third switch SW3.

[0034] The positive power supply E1 of the first gate drive circuit 11 is a DC power supply, with its positive terminal connected to the first gate G1 and its negative terminal connected to the first source S1. This allows the first gate drive circuit 11 to apply a positive bias voltage (first positive voltage VP1) between the first gate G1 and the first source S1 of the dual-gate bidirectional switch 1, with the first gate G1 at a higher potential relative to the first source S1. In the first gate drive circuit 11, the positive terminal of the DC power supply constituting the positive power supply E1 is connected to the first gate G1 via a first switch SW1 and a first resistor (gate resistor) R1. In the first gate drive circuit 11, an output terminal Tmg connected to the positive terminal of the positive power supply E1 is connected to the first gate G1, and an output terminal Tms connected to the negative terminal of the positive power supply E1 is connected to the first source S1.

[0035] The second switch SW2 of the first gate drive circuit 11 is connected to the first gate G1 via a second resistor (second gate resistor) R2.

[0036] The negative power supply E2 of the first gate drive circuit 11 is a DC power supply, and its negative electrode is connected to the first gate G1 and its positive electrode is connected to the first source S1. This allows the first gate drive circuit 11 to apply a negative bias voltage (a first negative voltage VN1 smaller than the first threshold voltage Vth1) between the first gate G1 and the first source S1 of the dual-gate bidirectional switch 1, with the first source S1 as the reference and the first gate G1 at a lower potential. In the first gate drive circuit 11, the negative electrode of the DC power supply constituting the negative power supply E2 is connected to the first gate G1 via a third switch SW3 and a third resistor (third gate resistor) R3.

[0037] Each of the first switch SW1, the second switch SW2, and the third switch SW3 of the first gate drive circuit 11 is, for example, a normally-off type semiconductor switch.

[0038] (2.2.2) Second Gate Drive Circuit The second gate drive circuit 12 is connected between the second gate G2 and the second source S2.

[0039] 2B, the second gate drive circuit 12 has the same circuit configuration as the first gate drive circuit 11. In the second gate drive circuit 12, a series circuit including a positive power supply E1 and a first switch SW1 is connected between the second gate G2 and the second source S2. The second switch SW2 is connected between the second gate G2 and the second source S2. A series circuit including a negative power supply E2 and a third switch SW3 is connected between the second gate G2 and the second source S2.

[0040] The second gate drive circuit 12 has a pair of output terminals Tmg and Tms, and between the pair of output terminals Tmg and Tms, there is a parallel circuit including a series circuit including a positive power supply E1 and a first switch SW1, and a series circuit including a second switch SW2, a negative power supply E2, and a third switch SW3.

[0041] The positive power supply E1 of the second gate drive circuit 12 is a DC power supply, with its positive electrode connected to the second gate G2 and its negative electrode connected to the second source S2. This allows the second gate drive circuit 12 to apply a second positive voltage VP2, with the second gate G2 at a higher potential with the second source S2 as the reference, between the second gate G2 and the second source S2 of the dual-gate bidirectional switch 1. In the second gate drive circuit 12, an output terminal Tmg connected to the positive electrode of the positive power supply E1 is connected to the second gate G2, and an output terminal Tms connected to the negative electrode of the positive power supply E1 is connected to the second source S2.

[0042] The second switch SW2 of the second gate drive circuit 12 is connected to the second gate G2 via a second resistor (second gate resistor) R2.

[0043] The negative power supply E2 of the second gate drive circuit 12 is a DC power supply, and its negative electrode is connected to the second gate G2 and its positive electrode is connected to the second source S2. This allows the second gate drive circuit 12 to apply a negative bias voltage (a second negative voltage VN2 smaller than the second threshold voltage Vth2) between the second gate G2 and the second source S2 of the dual-gate bidirectional switch 1, with the second source S2 as the reference and the second gate G2 at a lower potential. In the second gate drive circuit 12, the negative electrode of the DC power supply constituting the negative power supply E2 is connected to the second gate G2 via a third switch SW3 and a third resistor (third gate resistor) R3.

[0044] Each of the first switch SW1, the second switch SW2, and the third switch SW3 of the second gate drive circuit 12 is, for example, a normally-off semiconductor switch.

[0045] (2.2.3) Controller The controller 13 controls the first gate drive circuit 11 and the second gate drive circuit 12 .

[0046] In the control system 10 according to this embodiment, the controller 13 synchronizes the following timings when turning on the dual-gate bidirectional switch 1. That is, as shown in FIG. 5 , the timing at which the first gate drive circuit 11 starts applying a first positive voltage VP1 between the first gate G1 and the first source S1 is synchronized with the timing at which the second gate drive circuit 12 starts applying a voltage higher than the second threshold voltage Vth2 (e.g., a second positive voltage VP2) between the second gate G2 and the second source S2. The controller 13 also controls the first switch SW1, the second switch SW2, and the third switch SW3 of the first gate drive circuit 11.

[0047] Furthermore, when turning on the dual-gate bidirectional switch 1, the controller 13 controls the gate voltage as follows: That is, the controller 13 controls the gate voltage (gate voltage V Ｇ１Ｓ１ or gate voltage V Ｇ２Ｓ２ ) to a positive voltage (first positive voltage VP1 or second positive voltage VP2). Thereafter, the controller 13 sets a voltage (first voltage V1 or second voltage V2) that is smaller than the positive voltage (first positive voltage VP1 or second positive voltage VP2) and larger than the threshold voltage (first threshold voltage Vth1 or second threshold voltage Vth2).

[0048] (2.2.3.1) When the potential of the first source S1 is lower than the potential of the second source S2 When turning on the dual-gate bidirectional switch 1, the controller 13 causes the first gate drive circuit 11 to apply a first positive voltage VP1 between the first gate G1 and the first source S1 for a first period T1, as shown in FIG. 5 , and then applies a first voltage V1 (here, 0 V) ​​that is smaller than the first positive voltage VP1 after the first period T1 has elapsed. The first voltage V1 is greater than the threshold voltage Vth1 of the first gate G1. Here, VP1 > V1 > Vth1 > VN1.

[0049] The controller 13 controls the first switch SW1, the second switch SW2, and the third switch SW3 of the first gate drive circuit 11 at timings shown in FIG. 6, for example.

[0050] When the controller 13 controls the normally-on dual-gate bidirectional switch 1 to the off state, it controls only the third switch SW3 of the first switch SW1, the second switch SW2, and the third switch SW3 to the on state. When turning on the dual-gate bidirectional switch 1, the controller 13 controls the third switch SW3 from on to off, then controls the first switch SW1 from off to on, and after a first fixed time, turns the first switch SW1 off, and then controls the second switch SW2 from off to on. The first period T1 is determined by the on-period of the first switch SW1 (the first fixed time). Here, the first fixed time is determined by the characteristics of the on-resistance between the first gate G1 and the first source S1. When turning on the dual-gate bidirectional switch 1, the controller 13 may turn off the third switch SW3 at the same time as turning on the first switch SW1. Furthermore, the controller 13 may set the timing for turning off the first switch SW1 and the timing for turning on the second switch SW2 to be the same.

[0051] When turning off the dual-gate bidirectional switch 1, the controller 13 controls the second switch SW2 to turn off, and then controls the third switch SW3 to turn on. The controller 13 may turn off the second switch SW2 at the same timing as turning on the third switch SW3.

[0052] Furthermore, when the potential of the first source S1 is lower than the potential of the second source S2 when turning on the dual-gate bidirectional switch 1, the controller 13 causes the second gate drive circuit 12 to apply a second positive voltage VP2 between the second gate G2 and the second source S2 for a second period T2, as shown in FIG. 5 , and then applies a second voltage V2 (e.g., 0 V) ​​smaller than the second positive voltage VP2 after the second period T2 has elapsed. The second voltage V2 is greater than the threshold voltage Vth2 of the second gate G2, where VP2 > V2 > Vth2 > VN2. The second period T2 is a time determined by the characteristics of the on-resistance between the second gate G2 and the second source S2.

[0053] For example, when the controller 13 controls the second gate drive circuit 12, the controller 13 controls the first switch SW1, the second switch SW2, and the third switch SW3 of the second gate drive circuit 12 at the timings shown in FIG. 6 , similar to the first gate drive circuit 11.

[0054] The relationship between the first period T1 and the second period T2 may be T1>T2 or T1<T2.

[0055] (2.2.3.2) When the potential of the second source S2 is lower than the potential of the first source S1 When turning on the dual-gate bidirectional switch 1, the controller 13 causes the second gate drive circuit 12 to apply the second positive voltage VP2 between the second gate G2 and the second source S2 for only the second period T2, and then applies a second voltage V2 (here, 0 V) ​​that is smaller than the second positive voltage VP2 after the second period T2 has elapsed.

[0056] Furthermore, when turning on the dual-gate bidirectional switch 1, the controller 13 causes the first gate drive circuit 11 to apply a first positive voltage VP1 between the first gate G1 and the first source S1 for only a first period T1, and then causes the first gate drive circuit 11 to apply a first voltage V1 (here, 0 V) ​​smaller than the first positive voltage VP1 after the first period T1 has elapsed.

[0057] (2.2.3.3) Controller Configuration The execution entity of the controller 13 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program recorded in the memory of the computer system, thereby realizing the function of the execution entity of the controller 13 in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or stored and provided on a non-transitory storage medium readable by the computer system, such as a memory card, optical disk, or hard disk drive (magnetic disk). The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). Multiple electronic circuits may be integrated into a single chip or distributed across multiple chips. Multiple chips may be integrated into a single device or distributed across multiple devices.

[0058] (4) Advantages (4.1) Control System In the control system 10 according to the embodiment, when turning on the normally-on dual-gate bidirectional switch 1, if the potential of the first source S1 is lower than the potential of the second source S2, the controller 13 controls the first gate drive circuit 11 as follows. That is, the controller 13 causes the first gate drive circuit 11 to apply a first positive voltage VP1 between the first gate G1 and the first source S1 for only a first period T1, and then applies a first voltage V1 that is smaller than the first positive voltage VP1 after the first period T1 has elapsed. This makes it possible for the control system 10 according to the embodiment to suppress current collapse in the normally-on dual-gate bidirectional switch 1.

[0059] Current collapse is a phenomenon in which the on-resistance increases after the dual-gate bidirectional switch 1 is turned off from an off state to an on state. More specifically, in the dual-gate bidirectional switch 1, current collapse occurs when a high voltage (stress voltage) is applied between the first source S1 and the second source S2, and negative charges e － This is a phenomenon in which negative charges e are trapped and the on-resistance increases. As a result of extensive research, the present inventors have obtained experimental results that show that current collapse worsens in a normally-on dual-gate bidirectional switch 1 compared to a normally-off dual-gate bidirectional switch. In the dual-gate bidirectional switch 1, when the first gate G1 is in the off state and the second gate G2 is in the off state, for example, as shown in the schematic diagram of FIG. 7 , even if a negative bias voltage is applied between the second gate G2 and the second source S2, the second gate G2 may have a higher potential than the first source S1 and the first gate G1. In this case, a negative charge e － An electric field is applied between the hole h ＋ The injected holes h ＋ On the other hand, in the example of FIG. 7, the potential of the first gate G1 is low, and holes h ＋ The inventors of the present invention have speculated that this is because the current is difficult to inject, which worsens the current collapse.

[0060] In contrast, as described above, when the controller 13 turns on the normally-on dual-gate bidirectional switch 1, the control system 10 according to the embodiment controls the first gate drive circuit 11 as follows if the potential of the first source S1 is lower than the potential of the second source S2. That is, the control system 10 applies a first positive voltage VP1 from the first gate drive circuit 11 between the first gate G1 and the first source S1 for only a first period T1, and then applies a first voltage V1 smaller than the first positive voltage VP1 after the first period T1 has elapsed. It has been confirmed that the control system 10 according to the embodiment can suppress current collapse in the normally-on dual-gate bidirectional switch 1. This is because the control system 10 according to the embodiment controls the first gate drive circuit 11 to drive holes h from the first gate G1. ＋ It is presumed that this is because it has become easier to inject.

[0061] Furthermore, when turning on the dual-gate bidirectional switch 1, the control system 10 according to the embodiment applies a first positive voltage VP1 between the first gate G1 and the first source S1 for a first period T1, and then applies a first voltage V1 that is smaller than the first positive voltage VP1. Therefore, when the dual-gate bidirectional switch 1 is a dual-gate GIT (e.g., a dual-gate GaN-based GIT), it is possible to suppress power loss due to the flow of the gate current Ig. In particular, the control system 10 according to the embodiment is advantageous in suppressing power loss because the first voltage V1 = 0 V.

[0062] Furthermore, when turning on the dual-gate bidirectional switch 1, the control system 10 according to the embodiment applies a second positive voltage VP2 between the second gate G2 and the second source S2 for only a second period T2, and then applies a second voltage V2 that is smaller than the second positive voltage VP2. Therefore, when the dual-gate bidirectional switch 1 is a dual-gate GIT (e.g., a dual-gate GaN-based GIT), it is possible to suppress power loss due to the flow of the gate current Ig. In particular, the control system 10 according to the embodiment is advantageous in suppressing power loss because the second voltage V2 = 0 V.

[0063] From the viewpoint of suppressing power loss, when the dual-gate bidirectional switch 1 is turned on and then maintained in the on state, the control system 10 according to the embodiment preferably maintains the first gate voltage at the first voltage V1 and the second gate voltage at the second voltage V2.

[0064] (4.2) Switch System The switch system 20 according to the embodiment includes a control system 10 and a dual-gate bidirectional switch 1. This makes it possible for the switch system 20 according to the embodiment to suppress current collapse in the normally-on dual-gate bidirectional switch 1.

[0065] (4.3) Method for Controlling Dual-Gate Bidirectional Switch The control system 10 according to the embodiment can realize the following method for controlling the dual-gate bidirectional switch 1.

[0066] In the control method for the dual-gate bidirectional switch 1, the dual-gate bidirectional switch 1 is a normally-on type dual-gate bidirectional switch 1 having a first gate G1, a first source S1 corresponding to the first gate G1, a second gate G2, and a second source S2 corresponding to the second gate G2. In the control method for the dual-gate bidirectional switch 1, if the potential of the first source S1 is lower than the potential of the second source S2 when the dual-gate bidirectional switch 1 is turned on, a first positive voltage VP1 is applied between the first gate G1 and the first source S1 for a first period T1, and after the first period T1 has elapsed, a first voltage V1 smaller than the first positive voltage VP1 is applied.

[0067] As a result, the control method for the dual-gate bidirectional switch 1 can suppress current collapse in the normally-on type dual-gate bidirectional switch 1.

[0068] The control method for the dual-gate bidirectional switch 1 described above is not limited to being realized by the control system 10 described above.

[0069] (5) Modifications (5.1) First Modification The circuit configuration of the control system 10 according to the first modification of the embodiment is the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described.

[0070] In the control system 10 according to the first modification, when the dual-gate bidirectional switch 1 is turned on, if the potential of the first source S1 is lower than the potential of the second source S2, the controller 13 Ｇ１Ｓ１ and the second gate voltage V Ｇ２Ｓ２ 8A . That is, the controller 13 controls the first gate drive circuit 11 and the second gate drive circuit 12 so that the change in the voltage Vth between the first gate G1 and the first source S1 from the first gate drive circuit 11 starts. Thereafter, the controller 13 controls the second gate drive circuit 12 to start applying a voltage (e.g., a second positive voltage VP2) higher than a threshold voltage (second threshold voltage Vth2) from the second gate G2 and the second source S2 within the first period T1. As a result, in the control system 10 according to the first modification, holes are more easily injected from the first gate G1, making it possible to suppress current collapse.

[0071] (5.2) Second Modification The circuit configuration of the control system 10 according to the second modification of the embodiment is the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0072] In the control system 10 according to the second modification, when the dual-gate bidirectional switch 1 is turned on, if the potential of the second source S2 is higher than the potential of the first source S1, the controller 13 controls the first gate voltage V Ｇ１Ｓ１ and the second gate voltage V Ｇ２Ｓ２8B. That is, the controller 13 controls the second gate drive circuit 11 and the second gate drive circuit 12 to start applying the second positive voltage VP2 between the second gate G2 and the second source S2 from the second gate drive circuit 12, and then starts applying the first positive voltage VP1 between the first gate G1 and the first source S1 from the first gate drive circuit 11 within the second period T2. As a result, in the control system 10 according to the second modification, the negative charge e － The hole h from the second gate G2 ＋ is then applied between the gate (first gate G1) having a relatively low potential and the first source S1, so that current collapse can be further suppressed.

[0073] (5.3) Third Modification The circuit configuration of the control system 10 according to the third modification of the embodiment is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0074] FIG. 9 shows the circuit configurations of the first gate drive circuit 11 and the second gate drive circuit 12 according to the third modified example.

[0075] 1, 2A, and 2B in that the first gate drive circuit 11 and the second gate drive circuit 12 do not each include the first resistor R1, the second resistor R2, and the third resistor R3 as shown in Fig. 9. Therefore, in each of the first gate drive circuit 11 and the second gate drive circuit 12, a series circuit of a positive power supply E1 and a first switch SW1 and a series circuit of a second switch SW2, a negative power supply E2, and a third switch SW3 are connected in parallel. The first gate drive circuit 11a and the second gate drive circuit 12a have the same circuit configuration.

[0076] The control system 10 according to the third modification can have a smaller number of parts than the control system 10 shown in FIGS. 1, 2A, and 2B.

[0077] (5.4) Other Modifications In each of the embodiment and the first to third modifications, the dual-gate bidirectional switch 1 controlled by the control system 10 is not limited to a dual-gate GIT and may be, for example, a dual-gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). However, in each of the following modifications, the dual-gate bidirectional switch 1 controlled by the control system 10 is a dual-gate GIT.

[0078] (5.4.1) Fourth Modification The overall circuit configuration of the control system 10 according to the fourth modification of the embodiment is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0079] 1, 2A, and 2B in that the control system 10 according to the fourth modification includes a first gate drive circuit 11a and a second gate drive circuit 12a as shown in FIG. 10 instead of the first gate drive circuit 11 and the second gate drive circuit 12 in the control system 10 according to the embodiment. The first gate drive circuit 11a and the second gate drive circuit 12a have the same circuit configuration. In the first gate drive circuit 11a and the second gate drive circuit 12a, components similar to those in the first gate drive circuit 11 and the second gate drive circuit 12 are denoted by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0080] The first gate drive circuit 11a and the second gate drive circuit 12a each have a pair of output terminals Tmg and Tms. Between the pair of output terminals Tmg and Tms, each of the first gate drive circuit 11a and the second gate drive circuit 12a includes a series circuit including a positive power supply E1, a first switch SW1, and a first resistor R1, a series circuit including the positive power supply E1, a second switch SW2, and a second resistor R2, and a series circuit including a negative power supply E2, a third switch SW3, and a third resistor R3. The second switch SW2 is connected between a node N1 on a path between the positive electrode of the positive power supply E1 and the first switch SW1 and the second resistor R2. In each of the first gate drive circuit 11a and the second gate drive circuit 12a, the resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2.

[0081] In the first gate drive circuit 11a, the output terminal Tmg is connected to the first gate G1, and the output terminal Tms is connected to the first source S1. Therefore, in the first gate drive circuit 11a, a series circuit including the positive power supply E1, the first switch SW1, and the first resistor R1, a series circuit including the positive power supply E1, the second switch SW2, and the second resistor R2, and a series circuit including the negative power supply E2, the third switch SW3, and the third resistor R3 are connected between the first gate G1 and the first source S1.

[0082] In the second gate drive circuit 12a, the output terminal Tmg is connected to the second gate G2, and the output terminal Tms is connected to the second source S2. Therefore, in the second gate drive circuit 12a, a series circuit including the positive power supply E1, the first switch SW1, and the first resistor R1, a series circuit including the positive power supply E1, the second switch SW2, and the second resistor R2, and a series circuit including the negative power supply E2, the third switch SW3, and the third resistor R3 are connected between the second gate G2 and the second source S2.

[0083] The controller 13 controls the first switch SW1, the second switch SW2, and the third switch SW3 of the first gate drive circuit 11a at the timings shown in Fig. 6, for example, in the same manner as the control of the first gate drive circuit 11 by the controller 13 in the control system 10 according to the embodiment. Therefore, when the dual-gate bidirectional switch 1 is turned on, the first gate voltage V Ｇ１Ｓ１ changes as shown in Fig. 11. In the control system 10 according to the fourth modification, VP1>V1>0V>Vth1>VN1. The resistance value of the second resistor R2 in the first gate drive circuit 11a is determined so as to satisfy, for example, 0V<V1<1V. The resistance value of the second resistor R2 is greater than the resistance value of the first resistor R1.

[0084] 6 , the controller 13 controls the first switch SW1, the second switch SW2, and the third switch SW3 of the second gate drive circuit 12a. Therefore, when the dual-gate bidirectional switch 1 is turned on, the second gate voltage VＧ２Ｓ２ changes as shown in Fig. 11. In the control system 10 according to the fourth modification, VP2 > V2 > 0 V > Vth2 > VN2. The resistance value of the second resistor R2 in the second gate drive circuit 12a is determined so as to satisfy, for example, 0 V < V2 < 1 V. The resistance value of the second resistor R2 is greater than the resistance value of the first resistor R1.

[0085] In the control system 10 according to the fourth modification, when the dual-gate bidirectional switch 1 is turned on, the first switch SW1 and the second switch SW2 of the first gate drive circuit 11a are switched on, and the first gate voltage V is generated depending on the difference in resistance between the first resistor R1 and the second resistor R2. Ｇ１Ｓ１ In the control system 10 according to the fourth modification, when the dual-gate bidirectional switch 1 is turned on, the first switch SW1 and the second switch SW2 of the second gate drive circuit 12a are switched on, and the second gate voltage V is changed depending on the difference in resistance between the first resistor R1 and the second resistor R2. Ｇ２Ｓ２ can be changed.

[0086] (5.4.2) Fifth Modification The overall circuit configuration of the control system 10 according to the fifth modification of the embodiment is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0087] 1, 2A, and 2B in that the control system 10 according to the fifth modification includes a first gate drive circuit 11b and a second gate drive circuit 12b as shown in FIG. 12, instead of the first gate drive circuit 11 and the second gate drive circuit 12 in the control system 10 shown in FIG. 1, 2A, and 2B. The first gate drive circuit 11b and the second gate drive circuit 12b have the same circuit configuration. In the first gate drive circuit 11b and the second gate drive circuit 12b, components similar to those in the first gate drive circuit 11 and the second gate drive circuit 12 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0088] Each of the first gate drive circuit 11b and the second gate drive circuit 12b has a pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11b and the second gate drive circuit 12b has a series circuit connected between the pair of output terminals Tmg and Tms, the series circuit including a positive power supply E1, a first switch SW1, a capacitor C1, and a first resistor R1. Each of the first gate drive circuit 11b and the second gate drive circuit 12b has a second resistor R2 connected in parallel with the series circuit of the capacitor C1 and the first resistor R1. Each of the first gate drive circuit 11b and the second gate drive circuit 12b has a series circuit connected between the pair of output terminals Tmg and Tms, the series circuit including a negative power supply E2, a second switch SW2, and a third resistor R3. In each of the first gate drive circuit 11b and the second gate drive circuit 12b, the resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2.

[0089] In the first gate drive circuit 11b, the output terminal Tmg is connected to the first gate G1, and the output terminal Tms is connected to the first source S1. Therefore, in the first gate drive circuit 11b, a series circuit including a positive power supply E1, a first switch SW1, a capacitor C1, and a first resistor R1, a series circuit including a positive power supply E1, the first switch SW1, and a second resistor R2, and a series circuit including a negative power supply E2, a third switch SW3, and a third resistor R3 are connected between the first gate G1 and the first source S1. In the first gate drive circuit 11b, the capacitor C1, the first resistor R1, and the second resistor R2 form a speed-up circuit. The speed-up circuit is a circuit for turning on the dual-gate bidirectional switch 1 at a faster speed. The impedance of the series circuit including the capacitor C1 and the first resistor R1 is smaller than the impedance of the second resistor R2.

[0090] In the second gate drive circuit 12b, the output terminal Tmg is connected to the second gate G2, and the output terminal Tms is connected to the second source S2. Therefore, in the second gate drive circuit 12b, a series circuit including a positive power supply E1, a first switch SW1, a capacitor C1, and a first resistor R1, a series circuit including a positive power supply E1, the first switch SW1, and a second resistor R2, and a series circuit including a negative power supply E2, a third switch SW3, and a third resistor R3 are connected between the second gate G2 and the second source S2. In the second gate drive circuit 12b, the capacitor C1, the first resistor R1, and the second resistor R2 form a speed-up circuit. The speed-up circuit is a circuit for turning on the dual-gate bidirectional switch 1 at a faster speed. The impedance of the series circuit including the capacitor C1 and the first resistor R1 is smaller than the impedance of the second resistor R2.

[0091] The controller 13 controls the first switch SW1 and the second switch SW2 of the first gate drive circuit 11b. When turning on the dual-gate bidirectional switch 1, the controller 13 controls the first switch SW1 from off to on, controls the first switch SW1 to off after a first fixed time, and then controls the second switch SW2 from off to on. In the fifth modification, the first period T1 is determined by the time from when the first switch SW1 is turned on until charge accumulates in the capacitor C1 and current stops flowing through the capacitor C1, and is set shorter than the first fixed time. When current stops flowing through the capacitor C1, the only current flowing through the first gate G1 is the current flowing from the positive power supply E1 through the first switch SW1 and the second resistor R2. Therefore, when the dual-gate bidirectional switch 1 is turned on, the first gate voltage V Ｇ１Ｓ１changes as shown in FIG. 13 . In the control system 10 according to the fifth modification, VP1≧V1>0 V>Vth1>VN1. The first positive voltage VP1 is applied between the first gate G1 and the first source S1 when a current flows to the first gate G1 through the positive power supply E1, the first switch SW1, the capacitor C1, and the first resistor R1. Therefore, the first positive voltage VP1 decreases over time. When turning on the dual-gate bidirectional switch 1, the controller 13 may turn off the first switch SW1 of the first gate drive circuit 11b at the same timing as turning on the second switch SW2.

[0092] The controller 13 also controls the first switch SW1 and the second switch SW2 of the second gate drive circuit 12a. Therefore, when the dual-gate bidirectional switch 1 is turned on, the second gate voltage V Ｇ２Ｓ２ changes as shown in FIG. 13 . In the control system 10 according to the fifth modification, VP2≧V2>0V>Vth2>VN2. The second positive voltage VP2 is applied between the second gate G2 and the second source S2 when a current flows to the second gate G2 through the positive power supply E1, the first switch SW1, the capacitor C1, and the first resistor R1. Therefore, the second positive voltage VP2 decreases over time. When turning on the dual-gate bidirectional switch 1, the controller 13 may turn off the first switch SW1 of the second gate drive circuit 12b at the same timing as turning on the second switch SW2.

[0093] In the control system 10 according to the fifth modification of the embodiment, the number of switches in each of the first gate drive circuit 11b and the second gate drive circuit 12b can be reduced from three to two compared to the first gate drive circuit 11 and the second gate drive circuit 12, which is advantageous in terms of miniaturization and cost reduction.

[0094] (5.4.3) Sixth Modification The overall circuit configuration of the control system 10 according to the sixth modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0095] The control system 10 according to the sixth modification differs from the control system 10 according to the fifth modification in that each of the first gate drive circuit 11b and the second gate drive circuit 12b of the control system 10 according to the fifth modification includes a CMOS (Complementary Metal-Oxide Semiconductor) inverter 15 as a driver IC as shown in FIG. 14, instead of the series circuit of the positive power supply E1 and the first switch SW1 and the series circuit of the negative power supply E2 and the second switch SW2.

[0096] The CMOS inverter 15 includes an anti-series circuit of a p-channel MOSFET 151 and an n-channel MOSFET 152. In the CMOS inverter 15, the gates of the p-channel MOSFET 151 and the n-channel MOSFET 152 are connected to each other, the drains of the p-channel MOSFET 151 and the n-channel MOSFET 152 are connected to each other, and the source of the p-channel MOSFET 151 is connected to a power supply of, for example, 12 V, and the source of the n-channel MOSFET 152 is connected to a power supply of −12 V. In a switch system 20 including the control system 10, as shown in FIG. 15 , the potential level of the output voltage of the CMOS inverter 15 changes in accordance with the potential of a drive signal input from the controller 13 to the CMOS inverter 15, and the gate voltage Vg changes.

[0097] In the first gate drive circuit 11b, a CMOS inverter 15, which replaces the series circuit of the positive power supply E1 and the first switch SW1, can selectively output a first positive voltage VP1 and a first negative voltage VN1 that is less than the first threshold voltage Vth1.

[0098] In addition, in the second gate drive circuit 12b, a CMOS inverter 15, which replaces the series circuit of the positive power supply E1 and the first switch SW1, can selectively output a second positive voltage VP2 and a second negative voltage VN2 that is less than the second threshold voltage Vth2.

[0099] The control system 10 according to the sixth modification can suppress current collapse in the dual-gate bidirectional switch 1, similar to the control system 10 according to the embodiment.

[0100] (5.4.4) Seventh Modification The overall circuit configuration of the control system 10 according to the seventh modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0101] The control system 10 according to the seventh modification differs from the control system 10 according to the embodiment in that it includes a first gate drive circuit 11c and a second gate drive circuit 12c as shown in FIG. 16 , instead of the first gate drive circuit 11 and the second gate drive circuit 12 in the control system 10 according to the embodiment. The first gate drive circuit 11c and the second gate drive circuit 12c have the same circuit configuration. In the first gate drive circuit 11c and the second gate drive circuit 12c, components similar to those in the first gate drive circuit 11 and the second gate drive circuit 12 are denoted by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0102] Each of the first gate drive circuit 11c and the second gate drive circuit 12c has a pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11c and the second gate drive circuit 12c also has a series circuit of a positive power supply E1, a first switch SW1, a capacitor C1, and a first resistor R1 connected between the pair of output terminals Tmg and Tms, a series circuit of a negative power supply E2 and a second switch SW2 connected in parallel to the series circuit of the positive power supply E1 and the first switch SW1, and a second resistor R2 connected in parallel to the series circuit of the capacitor C1 and the first resistor R1. The resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2.

[0103] In the first gate drive circuit 11c, the output terminal Tmg is connected to the first gate G1, and the output terminal Tms is connected to the first source S1. Therefore, in the first gate drive circuit 11c, a series circuit including a positive power supply E1, a first switch SW1, a capacitor C1, and a first resistor R1, and a series circuit including the positive power supply E1, the first switch SW1, and a second resistor R2 are connected between the first gate G1 and the first source S1. In the first gate drive circuit 11c, a second resistor R2 is connected to the series circuit of the capacitor C1 and the first resistor R1, and the capacitor C1, the first resistor R1, and the second resistor R2 constitute a speed-up circuit. The speed-up circuit is a circuit for turning on the dual-gate bidirectional switch 1 at a higher speed. The impedance of the series circuit of the capacitor C1 and the first resistor R1 is smaller than the impedance of the second resistor R2. In the first gate drive circuit 11c, a series circuit of a negative power supply E2 and a second switch SW2 is connected in parallel to a series circuit of a positive power supply E1 and a first switch SW1.

[0104] In the second gate drive circuit 12c, the output terminal Tmg is connected to the second gate G2, and the output terminal Tms is connected to the second source S2. Therefore, in the second gate drive circuit 12c, a series circuit including a positive power supply E1, a first switch SW1, a capacitor C1, and a first resistor R1, and a series circuit including a positive power supply E1, the first switch SW1, and a second resistor R2 are connected between the second gate G2 and the second source S2. In the second gate drive circuit 12c, a second resistor R2 is connected to the series circuit of the capacitor C1 and the first resistor R1, and the capacitor C1, the first resistor R1, and the second resistor R2 form a speed-up circuit. The speed-up circuit is a circuit for turning on the dual-gate bidirectional switch 1 at a higher speed. The impedance of the series circuit of the capacitor C1 and the first resistor R1 is smaller than the impedance of the second resistor R2. In the second gate drive circuit 12c, a series circuit of a negative power supply E2 and a second switch SW2 is connected in parallel to a series circuit of a positive power supply E1 and a first switch SW1.

[0105] The controller 13 controls the first switch SW1 and the second switch SW2 of the first gate drive circuit 11c. When turning on the dual-gate bidirectional switch 1, the controller 13 controls the first switch SW1 from off to on, and after a first fixed time, controls the first switch SW1 to off, and then controls the second switch SW2 from off to on. The first period T1 is determined by the time from when the first switch SW1 is turned on until charge accumulates in the capacitor C1 and current stops flowing through the capacitor C1, and is set to be shorter than the first fixed time. When current stops flowing through the capacitor C1, current flows from the positive power supply E1 to the first gate G1 through the first switch SW1 and the second resistor R2. Therefore, when turning on the dual-gate bidirectional switch 1, the first gate voltage V Ｇ１Ｓ１ changes as shown in FIG. 13 . In the control system 10 according to the seventh modification, VP1≧V1>0 V>Vth1>VN1. The first positive voltage VP1 is applied between the first gate G1 and the first source S1 when a current flows to the first gate G1 through the positive power supply E1, the first switch SW1, the capacitor C1, and the first resistor R1. Therefore, the first positive voltage VP1 decreases over time. When turning on the dual-gate bidirectional switch 1, the controller 13 may turn off the first switch SW1 of the first gate drive circuit 11c at the same timing as turning on the second switch SW2.

[0106] The controller 13 also controls the first switch SW1 and the second switch SW2 of the second gate drive circuit 12c. Therefore, when the dual-gate bidirectional switch 1 is turned on, the second gate voltage V Ｇ２Ｓ２changes as shown in FIG. 13 . In the control system 10 according to the seventh modification, VP2≧V2>0V>Vth2>VN2. The second positive voltage VP2 is applied between the second gate G2 and the second source S2 when a current flows to the second gate G2 through the positive power supply E1, the first switch SW1, the capacitor C1, and the first resistor R1. Therefore, the second positive voltage VP2 decreases over time. When turning on the dual-gate bidirectional switch 1, the controller 13 may turn off the first switch SW1 of the second gate drive circuit 12c at the same timing as turning on the second switch SW2.

[0107] The control system 10 according to the seventh modification can suppress current collapse in the dual-gate bidirectional switch 1, similar to the control system 10 according to the embodiment.

[0108] (5.4.5) Eighth Modification The overall circuit configuration of the control system 10 according to the eighth modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0109] The control system 10 according to the eighth modification is substantially the same as the control system 10 according to the seventh modification, but differs from the control system 10 according to the seventh modification in that the second gate drive circuit 12c does not have the positive power supply E1 that the first gate drive circuit 11c has, as shown in FIG. 17B.

[0110] In the control system 10 according to the eighth modification, the first switch SW1 of the first gate drive circuit 11c is turned on and the first switch SW1 of the second gate drive circuit 12c is turned on when turning on the dual-gate bidirectional switch 1. In addition, in the control system 10 according to the eighth modification, the first switch SW1 of the first gate drive circuit 11c and the second gate drive circuit 12c is turned off and then the second switch SW2 is turned on when turning off the dual-gate bidirectional switch 1.

[0111] When the control system 10 according to the eighth modification is used, the first gate voltage V Ｇ１Ｓ１ and the second gate voltage V Ｇ２Ｓ２ An example of each waveform is shown in FIG.

[0112] 19 , in a control system according to a comparative example in which the first gate drive circuit 11r and the second gate drive circuit 12r do not have a positive power supply E1 like the second gate drive circuit 12c, the first switch SW1 of the first gate drive circuit 11r is turned on and the first switch SW1 of the second gate drive circuit 12r is turned on when turning on the dual-gate bidirectional switch 1. Furthermore, in the control system according to the comparative example, when turning off the dual-gate bidirectional switch 1, the first switch SW1 of each of the first gate drive circuit 11r and the second gate drive circuit 12r is turned off and then the second switch SW2 is turned on.

[0113] When the control system according to the comparative example is used, the first gate voltage V Ｇ１Ｓ１ and the second gate voltage V Ｇ２Ｓ２ An example of each waveform is shown in FIG.

[0114] In FIG. 21 , the solid line A1 indicates the change over time in the on-resistance when the dual-gate bidirectional switch 1 is turned on using the control system 10 according to the eighth modification, and the solid line A2 indicates the change over time in the on-resistance when the dual-gate bidirectional switch 1 is turned on using the control system according to the comparative example. FIG. 21 also shows the change over time in the on-resistance when the dual-gate bidirectional switch 1 is turned on with a voltage of 400 V applied between the first source S1 and the second source S2 of the dual-gate bidirectional switch 1, with the second source S2 at the high potential. When the dual-gate bidirectional switch 1 is in the on-state, a current of 10 A flows through the dual-gate bidirectional switch 1. The vertical axis of FIG. 21 represents the on-resistance normalized by setting the on-resistance when no current collapse occurs with respect to the solid line A1 to 1. It can be seen from FIG. 21 that the on-resistance is reduced when the dual-gate bidirectional switch 1 is turned on using the control system according to the eighth modification compared to when the dual-gate bidirectional switch 1 is turned on using the control system according to the comparative example. From another perspective, it can be seen that when the dual-gate bidirectional switch 1 is turned on using the control system according to the comparative example, the on-resistance is approximately 50% larger than when the dual-gate bidirectional switch 1 is turned on using the control system according to the eighth modification.

[0115] In contrast, when a DC voltage is applied to the dual-gate bidirectional switch 1 to evaluate the static characteristics of the dual-gate bidirectional switch 1, the first gate voltage V Ｇ１Ｓ１ When the first gate voltage V Ｇ１Ｓ１ The difference in on-resistance was 10% or less when the voltage was set to 3 V. Therefore, when the dual-gate bidirectional switch 1 was turned on using the control system according to the eighth modification in FIG. 21 , the on-resistance was reduced compared to when the dual-gate bidirectional switch 1 was turned on using the control system according to the comparative example, which is thought to be due to the effect of suppressing current collapse.

[0116] (5.4.6) Ninth Modification The overall circuit configuration of the control system 10 according to the ninth modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0117] The control system 10 according to the ninth modification differs from the control system 10 according to the embodiment in that it includes a first gate drive circuit 11d and a second gate drive circuit 12d as shown in FIG. 22 , instead of the first gate drive circuit 11 and the second gate drive circuit 12 in the control system 10 according to the embodiment. The first gate drive circuit 11d and the second gate drive circuit 12d have the same circuit configuration. In the first gate drive circuit 11d and the second gate drive circuit 12d, components similar to those in the first gate drive circuit 11 and the second gate drive circuit 12 are denoted by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0118] Each of the first gate drive circuit 11d and the second gate drive circuit 12d has a pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11d and the second gate drive circuit 12d has a series circuit of a positive power supply E1, a first switch SW1, a first diode D1, a capacitor C1, and a first resistor R1 connected between the pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11d and the second gate drive circuit 12d also has a series circuit of a negative power supply E2 and a second switch SW2 connected in parallel to the series circuit of the positive power supply E1 and the first switch SW1. Each of the first gate drive circuit 11d and the second gate drive circuit 12d also has a second resistor R2 connected in parallel to the series circuit of the first diode D1, the capacitor C1, and the first resistor R1. In addition, each of the first gate drive circuit 11d and the second gate drive circuit 12d has a series circuit including a second diode D2 and a third resistor R3 connected in parallel to a series circuit of a first diode D1, a capacitor C1, and a first resistor R1.

[0119] The anode of the first diode D1 is connected to the positive electrode of the positive power supply E1 via the first switch SW1 and to the negative electrode of the negative power supply E2 via the second switch SW2. The cathode of the second diode D2 is connected to the positive electrode of the positive power supply E1 via the first switch SW1 and to the negative electrode of the negative power supply E2 via the second switch SW2. The resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2. The resistance value of the third resistor R3 is smaller than the resistance value of the second resistor R2. The controller 13 controls the first switch SW1 and the second switch SW2.

[0120] In the control system 10 according to the ninth modification, when the dual-gate bidirectional switch 1 is turned on, the first switch SW1 of the first gate drive circuit 11d is turned on and the first switch SW1 of the second gate drive circuit 12d is turned on.

[0121] In the control system 10, when the dual-gate bidirectional switch 1 is turned on, the controller 13 turns on the first switch SW1 of the first gate drive circuit 11d, thereby charging the first gate G1 from the positive power supply E1 through a path that passes through the first diode D1, the capacitor C1, and the first resistor R1, and applying the first positive voltage VP1. Then, when charge accumulates in the capacitor C1, the control system 10 can supply the gate current Ig through a path that passes through the second resistor R2, thereby applying the first gate voltage V of the dual-gate bidirectional switch 1. Ｇ１Ｓ１ can be made to be the first voltage V1. Here, the larger the resistance value of the second resistor R2, the smaller the gate current Ig can be made, and the smaller the power loss at the first gate G1 can be made.

[0122] In the control system 10, when the dual-gate bidirectional switch 1 is turned on, the controller 13 turns on the first switch SW1 of the second gate drive circuit 12d, thereby charging the second gate G2 from the positive power supply E1 through a path that passes through the first diode D1, the capacitor C1, and the first resistor R1, and applying the second positive voltage VP2. Then, when charge accumulates in the capacitor C1, the control system 10 can supply the gate current Ig through a path that passes through the second resistor R2, thereby applying the second gate voltage V of the dual-gate bidirectional switch 1. Ｇ２Ｓ２ can be set to the second voltage V2. Here, the larger the resistance value of the second resistor R2, the smaller the gate current Ig can be, and the smaller the power loss at the second gate G2 can be.

[0123] Furthermore, in the control system 10 according to the ninth modification, when the dual-gate bidirectional switch 1 is turned off, the first switch SW1 of each of the first gate drive circuit 11 d and the second gate drive circuit 12 d is turned off and then the second switch SW2 is turned on.

[0124] In the control system 10, when the dual-gate bidirectional switch 1 is turned off, the controller 13 turns off the first switch SW1 of the first gate drive circuit 11d and turns on the second switch SW2, thereby discharging the charge of the first gate G1 through a path passing through the second resistor R2 and a path passing through the third resistor R3 and the second diode D2. Thereafter, the first gate voltage V Ｇ１Ｓ１ can be maintained at the first negative voltage VN1.

[0125] In the control system 10, when the dual-gate bidirectional switch 1 is turned off, the controller 13 turns off the first switch SW1 of the second gate drive circuit 12d and turns on the second switch SW2, thereby discharging the charge of the second gate G2 through a path passing through the second resistor R2 and a path passing through the third resistor R3 and the second diode D2. Thereafter, the second gate voltage V Ｇ２Ｓ２ can be maintained at the second negative voltage VN2.

[0126] As described above, in the control system 10 according to the ninth modification, the first gate drive circuit 11d includes a series circuit including a first diode D1, a capacitor C1, and a first resistor R1, and a series circuit including a second diode D2 and a third resistor R3 connected in parallel to the second resistor R2. The second diode D2 is connected in the opposite direction to the first diode D1 with respect to the connection point between the first switch SW1 and the second switch SW2. In other words, the cathode of the second diode D2 is connected to the anode of the first diode D1. This allows the control system 10 according to the ninth modification to separate a path that applies the first positive voltage VP1 when turning on the dual-gate bidirectional switch 1 from a path that adjusts the turn-off speed when turning off the dual-gate bidirectional switch 1. This allows the control system 10 according to the ninth modification to independently control the magnitude of the first positive voltage VP1 and the switch loss during turn-off.

[0127] Furthermore, in the control system 10 according to the ninth modification, the second gate drive circuit 12d includes a series circuit including a first diode D1, a capacitor C1, and a first resistor R1, and a series circuit including a second diode D2 and a third resistor R3 connected in parallel to the second resistor R2. The second diode D2 is connected in the opposite direction to the first diode D1 with respect to the connection point between the first switch SW1 and the second switch SW2. In other words, the cathode of the second diode D2 is connected to the anode of the first diode D1. This allows the control system 10 according to the ninth modification to separate a path that applies the second positive voltage VP2 when turning on the dual-gate bidirectional switch 1 from a path that adjusts the turn-off speed when turning off the dual-gate bidirectional switch 1. This allows the control system 10 according to the ninth modification to independently control the magnitude of the second positive voltage VP2 and the switch loss during turn-off.

[0128] (5.4.7) Tenth Modification The overall circuit configuration of the control system 10 according to the tenth modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0129] 1, 2A, and 2B in that the control system 10 according to the tenth modification includes a first gate drive circuit 11e and a second gate drive circuit 12e as shown in FIG. 23, instead of the first gate drive circuit 11 and the second gate drive circuit 12 in the control system 10 shown in FIG. 1, 2A, and 2B. The first gate drive circuit 11e and the second gate drive circuit 12e have the same circuit configuration. In the first gate drive circuit 11e and the second gate drive circuit 12e, components similar to those in the first gate drive circuit 11 and the second gate drive circuit 12 are designated by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0130] Each of the first gate drive circuit 11e and the second gate drive circuit 12e has a pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11e and the second gate drive circuit 12e has a series circuit of a negative power supply E2, a first switch SW1, a capacitor C1, and a first resistor R1 connected between the pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11e and the second gate drive circuit 12e has a second switch SW2 connected in parallel to the series circuit of the negative power supply E2 and the first switch SW1. Each of the first gate drive circuit 11e and the second gate drive circuit 12e has a second resistor R2 connected in parallel to the series circuit of the capacitor C1 and the first resistor R1. Each of the first gate drive circuit 11e and the second gate drive circuit 12e has a third resistor R3 connected between the pair of output terminals Tmg and Tms. The resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2.

[0131] The controller 13 controls the first switch SW1 and the second switch SW2.

[0132] When turning off the dual-gate bidirectional switch 1, the controller 13 turns on the first switch SW1 of each of the first gate drive circuit 11e and the second gate drive circuit 12e as shown in FIG. 24A. When the dual-gate bidirectional switch 1 is turned off, the gate voltage V of the first gate G1 is Ｇ１Ｓ１ and the gate voltage V of the second gate G2 Ｇ２Ｓ２Assuming that Vgoff is Vgoff, the gate voltage Vgoff converges to a value obtained by dividing the voltage of the negative power supply E2 by the second resistor R2 and the third resistor R3. Assuming that the voltage of the negative power supply E2 is Vdd, the resistance value of the second resistor R2 is r2, and the resistance value of the third resistor R3 is r3, Vgoff converges to a value expressed by the following formula: Vgoff=Vdd×{r3 / (r2+r3)} where Vgoff is smaller than the first threshold voltage Vth1 and the second threshold voltage Vth2.

[0133] For example, if the voltage of the negative power supply E2 is -15 V and the resistance value of the third resistor R3 is twice that of the second resistor R2, then Vgoff is -10 V, the voltage across the second resistor R2 is 5 V, and a voltage of 5 V is applied to the capacitor C1 when no current flows. Here, if the amount of charge on the capacitor C1 is Q, the capacitance of the capacitor C1 is C, and the voltage on the capacitor C1 is V, then a charge determined by Q = CV accumulates in the capacitor C1.

[0134] 24B, when the controller 13 turns on the dual-gate bidirectional switch 1, it turns off the first switch SW1 and turns on the second switch SW2. This allows the first gate drive circuit 11e to discharge part of the positive charge of the capacitor C1 to the first gate G1, so that even if the potential at the connection point between the first switch SW1 and the second switch SW2 is 0 V, the first gate voltage V Ｇ１Ｓ１ can be temporarily set to a first positive voltage VP1 (for example, 3 V). In addition, the second gate drive circuit 12e can discharge a part of the positive charge of the capacitor C1 to the second gate G2, so that the second gate voltage V Ｇ２Ｓ２ can be temporarily set to a second positive voltage VP2 (for example, 3V).

[0135] Therefore, the control system 10 according to the tenth modification can suppress current collapse in the dual-gate bidirectional switch 1, similar to the control system 10 according to the embodiment.

[0136] The control system 10 according to the tenth modification only needs to include the negative power supply E2 as a power supply, and therefore can achieve lower costs than the control system 10 according to the embodiment.

[0137] Each of the first gate drive circuit 11e and the second gate drive circuit 12e in the control system 10 according to the tenth modification uses a capacitor C1 to generate positive voltages (first positive voltage VP1, second positive voltage VP2) from the negative power supply E2. Because the gate capacitance needs to be charged with the charge stored in the capacitor C1, a large capacitance of the capacitor C1 is preferable for generating a positive voltage. The product of the voltage across the capacitor C1 and the capacitance of the capacitor C1 when the dual-gate bidirectional switch 1 is in the off state is preferably greater than the product of the gate voltage in the off state and the gate-source capacitance in the on state of the dual-gate bidirectional switch 1. The capacitance of the capacitor C1 is preferably at least twice the minimum capacitance of the capacitor C1 obtained when the above relationship is expressed as an inequality.

[0138] (5.4.8) Eleventh Modification The overall circuit configuration of the control system 10 according to the eleventh modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0139] The control system 10 according to the eleventh modification differs from the control system 10 shown in Figures 1, 2A, and 2B in that it includes a first gate drive circuit 11f and a second gate drive circuit 12f as shown in Figure 25, instead of the first gate drive circuit 11 and the second gate drive circuit 12 in the control system 10 shown in Figures 1, 2A, and 2B. The first gate drive circuit 11f and the second gate drive circuit 12f have the same circuit configuration. In the first gate drive circuit 11f and the second gate drive circuit 12f, components similar to those in the first gate drive circuit 11 and the second gate drive circuit 12 are denoted by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0140] Each of the first gate drive circuit 11f and the second gate drive circuit 12f has a pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11f and the second gate drive circuit 12f also has a series circuit of a negative power supply E2, a first switch SW1, a capacitor C1, and a first resistor R1 connected between the pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11f and the second gate drive circuit 12f also has a second switch SW2 connected in parallel to the series circuit of the negative power supply E2 and the first switch SW1. Each of the first gate drive circuit 11f and the second gate drive circuit 12f also has a second resistor R2 connected in parallel to the series circuit of the capacitor C1 and the first resistor R1. In each of the first gate drive circuit 11f and the second gate drive circuit 12f, the resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2.

[0141] The control system 10 further includes clamp circuits 14 corresponding to the first gate drive circuit 11f and the second gate drive circuit 12f, respectively. Each of the two clamp circuits 14 is connected between a pair of output terminals Tmg and Tms. The clamp circuit 14 corresponding to the first gate drive circuit 11f is connected between the first gate G1 and the first source S1 and clamps the voltage between the first gate G1 and the first source S1. The clamp circuit 14 corresponding to the second gate drive circuit 12f is connected between the second gate G2 and the second source S2 and clamps the voltage between the second gate G2 and the second source S2.

[0142] The clamp circuit 14 includes, for example, a series circuit of a Zener diode Dz and a resistor Rz. The Zener diode Dz has an anode connected to the output terminal Tmg and a cathode connected to the output terminal Tms via the resistor Rz.

[0143] The controller 13 controls the first switch SW1 and the second switch SW2.

[0144] 26A, when the controller 13 turns off the dual-gate bidirectional switch 1, it turns on the first switch SW1 of each of the first gate drive circuit 11f and the second gate drive circuit 12f. When the dual-gate bidirectional switch 1 is turned off, the gate voltage V of the first gate G1 isＧ１Ｓ１ and the gate voltage V of the second gate G2 Ｇ２Ｓ２ When the gate voltage Vgoff is Vgoff, the gate voltage Vgoff is clamped by the clamp circuit 14. Here, Vgoff is smaller than the first threshold voltage Vth1 and the second threshold voltage Vth2.

[0145] For example, if the voltage of the negative power supply E2 is -15 V, the voltage at the connection point N2 between the first switch SW1 and the second switch SW2 is -15 V, and the clamp voltage by the clamp circuit 14 is -10 V, then Vgoff is -10 V, the voltage across the second resistor R2 is 5 V, and a voltage of 5 V is applied to the capacitor C1 when no current flows. Here, if the amount of charge on the capacitor C1 is Q, the capacitance of the capacitor C1 is C, and the voltage on the capacitor C1 is V, then a charge determined by Q = CV accumulates in the capacitor C1.

[0146] 26B, when the controller 13 turns on the dual-gate bidirectional switch 1, it turns off the first switch SW1 and turns on the second switch SW2. This allows the first gate drive circuit 11f to discharge part of the positive charge of the capacitor C1 to the first gate G1, so that even if the potential of the connection point N2 between the first switch SW1 and the second switch SW2 is 0 V, the first gate voltage V Ｇ１Ｓ１ The second gate drive circuit 12f can temporarily set the second gate voltage V to the first positive voltage VP1 (for example, 3 V). Ｇ２Ｓ２ can be temporarily set to a second positive voltage VP2 (for example, 3V).

[0147] Therefore, the control system 10 according to the eleventh modification can suppress current collapse in the dual-gate bidirectional switch 1, similar to the control system 10 according to the embodiment.

[0148] The control system 10 according to the eleventh modification only needs to include the negative power supply E2 as a power supply, and therefore can achieve lower costs than the control system 10 according to the embodiment.

[0149] The clamp circuit 14 is not limited to a circuit using a Zener diode Dz, and may be configured by connecting a plurality of diodes D14 in series, as shown in Fig. 27. In the clamp circuit shown in Fig. 27, the cathode of the diode D14 that is closest to the output terminal Tmg in terms of the circuit is connected to the output terminal Tmg, and the anode of the diode D14 that is closest to the output terminal Tms in terms of the circuit is connected to the output terminal Tms via a resistor Rz.

[0150] (5.4.9) Twelfth Modification The overall circuit configuration of the control system 10 according to the twelfth modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0151] The control system 10 according to the twelfth modification differs from the control system 10 shown in Figures 1, 2A, and 2B in that it includes a first gate drive circuit 11g and a second gate drive circuit 12g as shown in Figure 28, instead of the first gate drive circuit 11 and the second gate drive circuit 12 in the control system 10 shown in Figures 1, 2A, and 2B. The first gate drive circuit 11g and the second gate drive circuit 12g have the same circuit configuration. In the first gate drive circuit 11g and the second gate drive circuit 12g, components similar to those in the first gate drive circuit 11 and the second gate drive circuit 12 are denoted by the same reference numerals, and descriptions thereof will be omitted where appropriate.

[0152] Each of the first gate drive circuit 11g and the second gate drive circuit 12g has a pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11g and the second gate drive circuit 12g has a series circuit of a negative power supply E2, a first switch SW1, a capacitor C1, a first diode D1, and a first resistor R1 connected between the pair of output terminals Tmg and Tms. Each of the first gate drive circuit 11g and the second gate drive circuit 12g also has a series circuit of a second diode D2 and a second resistor R2 connected in parallel to the series circuit of the first diode D1 and the first resistor R1. Each of the first gate drive circuit 11g and the second gate drive circuit 12g also has a third resistor R3 connected in parallel to the series circuit of the capacitor C1, the first diode D1, and the first resistor R1. In each of the first gate drive circuit 11g and the second gate drive circuit 12g, the anode of the first diode D1 is connected to the capacitor C1, and the cathode of the second diode D2 is connected to the capacitor C1. In each of the first gate drive circuit 11g and the second gate drive circuit 12g, the resistance value of the first resistor R1 is smaller than the resistance value of the second resistor R2.

[0153] The control system 10 further includes clamp circuits 14 corresponding to the first gate drive circuit 11g and the second gate drive circuit 12g, respectively. Each of the two clamp circuits 14 is connected between a pair of output terminals Tmg and Tms. The clamp circuit 14 corresponding to the first gate drive circuit 11g is connected between the first gate G1 and the first source S1 and clamps the voltage between the first gate G1 and the first source S1. The clamp circuit 14 corresponding to the second gate drive circuit 12g is connected between the second gate G2 and the second source S2 and clamps the voltage between the second gate G2 and the second source S2.

[0154] The clamp circuit 14 includes, for example, a series circuit of a Zener diode Dz and a resistor Rz. The Zener diode Dz has an anode connected to the output terminal Tmg and a cathode connected to the output terminal Tms via the resistor Rz.

[0155] The controller 13 controls the first switch SW1 and the second switch SW2.

[0156] In the control system 10 according to the twelfth modification, when the dual-gate bidirectional switch 1 is turned on, the first gate drive circuit 11g charges the first gate G1 through the first diode D1, thereby applying the first positive voltage VP1, and the second gate drive circuit 12g charges the second gate G2 through the first diode D1, thereby applying the second positive voltage VP2.

[0157] In addition, after the control system 10 according to the twelfth modification turns on the dual-gate bidirectional switch 1, the first gate voltage V of the first gate G1 is applied to the first gate G1 through the third resistor R3 of the first gate drive circuit 11g. Ｇ１Ｓ１ At the same time, the second gate voltage V of the second gate G2 is maintained at the first voltage V1 (>first threshold voltage Vth1) through the third resistor R3 of the second gate drive circuit 12g. Ｇ２Ｓ２ is maintained at the second voltage V2 (>second threshold voltage Vth2). As a result, the dual-gate bidirectional switch 1 can be maintained in a steady on state. Therefore, by increasing the resistance of the third resistor R3 of the first gate drive circuit 11g and reducing the gate current Ig flowing through the first gate G1, power loss at the first gate G1 can be reduced. Also, by increasing the resistance of the third resistor R3 of the second gate drive circuit 12g and reducing the gate current Ig flowing through the second gate G2, power loss at the second gate G2 can be reduced.

[0158] The controller 13 turns on the first switch SW1 of each of the first gate drive circuit 11g and the second gate drive circuit 12g when turning off the dual-gate bidirectional switch 1. The gate voltage V of the first gate G1 when the dual-gate bidirectional switch 1 is off is Ｇ１Ｓ１ and the gate voltage V of the second gate G2 Ｇ２Ｓ２ When the gate voltage Vgoff is Vgoff, the gate voltage Vgoff is clamped by the clamp circuit 14. Here, Vgoff is smaller than the first threshold voltage Vth1 and the second threshold voltage Vth2.

[0159] Furthermore, when the dual-gate bidirectional switch 1 is turned off, the charge in the first gate G1 can be discharged through the second diode D2 of the first gate drive circuit 11g, and the charge in the second gate G2 can be discharged through the second diode D2 of the second gate drive circuit 12g.

[0160] Therefore, the control system 10 according to the twelfth modification can suppress current collapse in the dual-gate bidirectional switch 1, similar to the control system 10 according to the embodiment.

[0161] Furthermore, the control system 10 according to the twelfth modification only needs to include the negative power supply E2 as a power supply, and therefore can achieve lower costs than the control system 10 according to the embodiment.

[0162] In the control system 10 according to the twelfth modification, a parallel circuit including a series circuit of a first diode D1 and a first resistor R1 and a series circuit of a second diode D2 and a second resistor R2 is connected to a capacitor C1 in the first gate drive circuit 11g. This allows the path for applying the first positive voltage VP1 to the first gate G1 to be separated from the path for adjusting the turn-off speed, making it possible to independently control the magnitude of the first positive voltage VP1 and the switch loss during turn-off.

[0163] In the control system 10 according to the twelfth modification, a parallel circuit including a series circuit of a first diode D1 and a first resistor R1 and a series circuit of a second diode D2 and a second resistor R2 is connected to a capacitor C1 in the second gate drive circuit 12g. This allows the path for applying the second positive voltage VP2 to the second gate G2 to be separated from the path for adjusting the turn-off speed, making it possible to independently control the magnitude of the second positive voltage VP2 and the switch loss during turn-off.

[0164] In the control system 10 according to the twelfth modification, a configuration in which a resistor Rz is connected to the pair of output terminals Tmg and Tms instead of connecting the series circuit of the Zener diode Dz and resistor Rz may be adopted.

[0165] (5.4.10) Thirteenth Modification The overall circuit configuration of the control system 10 according to the thirteenth modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0166] 29 , the control system 10 according to the thirteenth modification differs from the control system 10 according to the twelfth modification in that the clamp circuits 14 corresponding to the first gate drive circuit 11h and the second gate drive circuit 12h each include a diode D5 connected between the Zener diode Dz and the resistor Rz in the reverse direction to the Zener diode Dz. In the clamp circuits 14, the cathode of the Zener diode Dz is connected to the cathode of the Zener diode Dz, and the anode of the diode D5 is connected to the resistor Rz. In the first gate drive circuit 11h, the anode of the Zener diode Dz is connected to the first gate G1, the cathode of the Zener diode Dz is connected to the cathode of the Zener diode Dz, and the anode of the diode D5 is connected to the first source S1. In the second gate drive circuit 12h, the anode of the Zener diode Dz is connected to the second gate G2, the cathode of the Zener diode Dz is connected to the cathode of the Zener diode Dz, and the anode of the diode D5 is connected to the second source S2.

[0167] In the control system 10 according to the thirteenth modification, the clamp circuit 14 corresponding to the first gate drive circuit 11h includes the diode D5, which makes it possible to prevent a portion of the gate current Ig from leaking through the Zener diode Dz when the first gate drive circuit 11h applies the first positive voltage VP1 to the first gate G1 to turn on the dual-gate bidirectional switch 1, making it easier to increase the first positive voltage VP1. Also, in the control system 10 according to the thirteenth modification, the clamp circuit 14 corresponding to the second gate drive circuit 12h includes the diode D5, which makes it possible to prevent a portion of the gate current Ig from leaking through the Zener diode Dz when the second gate drive circuit 12h applies the second positive voltage VP2 to the second gate G2 to turn on the dual-gate bidirectional switch 1, making it easier to increase the second positive voltage VP2.

[0168] In addition, in the control system 10 according to the thirteenth modification, instead of connecting a series circuit of the Zener diode Dz, the diode D5, and the resistor Rz to the pair of output terminals Tmg and Tms, a configuration in which a series circuit of the diode D5 and the resistor Rz is connected may be adopted.

[0169] (5.4.11) Fourteenth Modification The overall circuit configuration of the control system 10 according to the fourteenth modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0170] 30 , the control system 10 according to the fourteenth modification differs from the control system 10 according to the thirteenth modification in that each of the first gate drive circuit 11i and the second gate drive circuit 12i further includes a series circuit of a third diode D3 and a fourth resistor R4 connected in parallel to the series circuit of a capacitor C1, a second diode D2, and a second resistor R2. In each of the first gate drive circuit 11i and the second gate drive circuit 12i, the cathode of the third diode D3 is connected to the capacitor C1, and the anode of the third diode D3 is connected to the output terminal Tmg via the resistor R4. The series circuit of the third diode D3 and the fourth resistor R4 is connected in parallel to the third resistor R3.

[0171] In the control system 10 according to the fourteenth modification, the first gate drive circuit 11i includes a series circuit of the diode D3 and the resistor R4. This allows the charge on the first gate G1 to be discharged via a path that does not pass through the capacitor C1 when the dual-gate bidirectional switch 1 is turned off. Therefore, the control system 10 according to the fourteenth modification can discharge the charge on the first gate G1 even when, for example, the capacitance of the capacitor C1 is smaller than the capacitance of the first gate G1, making it easier to control the turn-off speed. In the first gate drive circuit 11i, by making the resistance value of the resistor R4 smaller than the resistance value of the second resistor R2, the gate discharge current flowing through the resistor R4 can be made larger than the gate discharge current flowing through the second resistor R2, thereby enabling the turn-off speed to be increased.

[0172] Furthermore, in the control system 10 according to the fourteenth modification, the second gate drive circuit 12i includes a series circuit of the diode D3 and the resistor R4, so that when the dual-gate bidirectional switch 1 is turned off, the charge on the second gate G2 can be discharged through a path that does not pass through the capacitor C1. Therefore, the control system 10 according to the fourteenth modification can discharge the charge on the second gate G2 even when, for example, the capacitance of the capacitor C1 is smaller than the capacitance of the second gate G2, making it easier to control the turn-off speed. In the second gate drive circuit 12i, by making the resistance value of the resistor R4 smaller than the resistance value of the second resistor R2, the gate discharge current flowing through the resistor R4 can be made larger than the gate discharge current flowing through the second resistor R2, thereby enabling the turn-off speed to be increased.

[0173] In each of the first gate drive circuit 11i and the second gate drive circuit 12i, the resistance value of the first resistor R1 is smaller than the resistance value of the third resistor R3. The resistance value of the resistor R4 is smaller than the resistance value of the second resistor R2. The resistance value of the second resistor R2 is smaller than the resistance value of the third resistor R3.

[0174] Furthermore, in the control system 10 according to the fourteenth modification, no current flows through the resistor R4 when the dual-gate bidirectional switch 1 is turned on, and therefore the resistor R4 can be prevented from becoming a factor in power loss when the dual-gate bidirectional switch 1 is in a steady-on state.

[0175] Furthermore, in the control system 10 according to the fourteenth modification, in order for the Zener diode Dz to operate at a constant voltage in the clamp circuits 14 corresponding to each of the first gate drive circuit 11i and the second gate drive circuit 12i, a constant current needs to be continuously passed through the Zener diode Dz, but the capacitor C1 cannot continuously pass a direct current. However, since each of the first gate drive circuit 11i and the second gate drive circuit 12i has a series circuit of the diode D3 and the resistor R4, a constant current can be continuously passed through the Zener diode Dz in a closed circuit including the negative power supply E2, resistor Rz, diode D5, Zener diode Dz, resistor R4, diode D3, and first switch SW1, and the Zener diode Dz can be operated at a constant voltage.

[0176] (5.4.12) Fifteenth Modification The overall circuit configuration of the control system 10 according to the fifteenth modification is substantially the same as that of the control system 10 according to the embodiment (see FIG. 1), and therefore will not be illustrated or described again.

[0177] 31 , the control system 10 according to the fifteenth modification differs from the control system 10 according to the fourteenth modification in that the first gate drive circuit 11j and the second gate drive circuit 12j each include a clamp circuit 14. In each of the first gate drive circuit 11j and the second gate drive circuit 12j, the clamp circuit 14 includes a Zener diode D4 connected between a third diode D3 and a resistor R4. In each of the first gate drive circuit 11j and the second gate drive circuit 12j, a series circuit of a diode D5 and a resistor R5 is connected between a pair of output terminals Tmg and Tms.

[0178] In each of the first gate drive circuit 11j and the second gate drive circuit 12j, the clamp circuit 14 clamps the voltage between the connection point N2 and the connection point N4 when the dual-gate bidirectional switch 1 is in the off state. The connection point N4 is the point where the first resistor R1 and the second resistor R2 are connected. Therefore, in each of the first gate drive circuit 11j and the second gate drive circuit 12j, charge can be stored in the capacitor C1 when the dual-gate bidirectional switch 1 is in the off state. Therefore, when the dual-gate bidirectional switch 1 is turned on, a first positive voltage VP1 can be applied between the first gate G1 and the first source S1, and a second positive voltage VP2 can be applied between the second gate G2 and the second source S2.

[0179] Therefore, the control system 10 according to the fifteenth modification can suppress current collapse, similar to the control system 10 according to the embodiment.

[0180] The clamp circuit 14 is not limited to being configured by the Zener diode D4, but may be configured by a series circuit of a plurality of diodes (for example, Schottky diodes).

[0181] The above embodiment is merely one of various embodiments of the present disclosure, and various modifications can be made to the above embodiment depending on the design and the like as long as the object of the present disclosure can be achieved.

[0182] For example, the dual-gate bidirectional switch 1 may have a recess structure in the surface 115 of the second nitride semiconductor layer 105 directly below each of the first gate G1 and the second gate G2.

[0183] Furthermore, each of the first p-type layer 161 and the second p-type layer 162 in the dual-gate bidirectional switch 1 is not limited to a p-type AlGaN layer, and may be, for example, a p-type GaN layer or a p-type metal oxide semiconductor layer. The p-type metal oxide semiconductor layer is, for example, a NiO layer. The NiO layer may contain, as an impurity, at least one alkali metal selected from the group consisting of lithium, sodium, potassium, rubidium, and cesium. The NiO layer may also contain, for example, a transition metal such as silver or copper that becomes monovalent when added as an impurity.

[0184] Each of the dual-gate bidirectional switches 1 may include one or more nitride semiconductor layers between the buffer layer 103 and the first nitride semiconductor layer 104. The buffer layer 103 is not limited to a single-layer structure, and may have, for example, a superlattice structure.

[0185] Furthermore, the substrate 102 in the dual-gate bidirectional switch 1 is not limited to a silicon substrate, but may be, for example, a GaN substrate, a SiC substrate, a sapphire substrate, or the like.

[0186] (5.4.13) Sixteenth Modification FIG. 32 shows the circuit configuration of a control system according to a sixteenth modification of the embodiment. The control system 40 includes a controller 43, a gate drive circuit 41, and a unidirectional switch element 42 made of a nitride semiconductor device. Unlike a bidirectional switch element, the unidirectional switch element 42 according to the sixteenth modification has only one gate portion made of a pn junction. The control system 40 according to the sixteenth modification also differs from the control systems 10 according to the first embodiment and the first to fifteenth modifications in that it includes only one gate drive circuit 41. The gate drive circuit 41 is connected between the gate G and the source S. A controller 43 controls the gate drive circuit 41. When any of the drive circuits according to the first embodiment to the first to fifteenth modifications is applied to the gate drive circuit 41, a first positive voltage VP1 can be applied between the gate G and the source S when the unidirectional switch element 42 is turned on. This suppresses current collapse. Specifically, when the gate drive circuit of FIG. 25 is applied, the characteristics shown in FIG. 33 are shown. FIG. 33 is a characteristic diagram of the on-resistance of the control system 40 according to the sixteenth modification of the embodiment and a timing chart for explaining the operation of the control system 40. In FIG. 33, when the unidirectional switch element 42 is turned on, the on-resistance between the gate G and the source S becomes Ron. The on-resistance value then gradually decreases, and when a predetermined time (first period T1) has elapsed since the unidirectional switch element 42 was turned on, the resistance value becomes Rg (Rg<R1) and remains constant. When the unidirectional switch element 42 is turned on, if the potential of the source S is lower than the potential of the drain D, the controller 43 controls the gate drive circuit 41 as follows. That is, the controller 43 applies a first positive voltage VP1 from the gate drive circuit 41 between the gate G and the source S for only the first period T1, and then applies a voltage V1 smaller than the first positive voltage VP1 after the first period T1 has elapsed.

[0187] The structure of the unidirectional switch element 42 will be described with reference to the cross-sectional view shown in FIG. 34 . FIG. 34 is a cross-sectional view of the unidirectional switch element 42 taken along a plane perpendicular to the substrate 51 and including the source electrode 55, the drain electrode 56, and the gate electrode 57. The unidirectional switch element 42 is a normally-on single-gate field-effect transistor having a gate G, a source S, and a drain D. The unidirectional switch element 42 includes a substrate 51, a first nitride semiconductor layer 52, a second nitride semiconductor layer 53, a source electrode 55, a gate electrode 57, a drain electrode 56, and a p-type layer 54. The first nitride semiconductor layer 52 is formed on the substrate 51. The second nitride semiconductor layer 53 is formed on the first nitride semiconductor layer 52. The second nitride semiconductor layer 53 has a larger band gap than the first nitride semiconductor layer 52. The source electrode 55, the gate electrode 57, and the drain electrode 56 are formed on the second nitride semiconductor layer 53. The p-type layer 54 is interposed between the gate electrode 57 and the second nitride semiconductor layer 53. The gate G includes the gate electrode 57 and the p-type layer 54. The source S includes a source electrode 55, and the drain D includes a drain electrode 56. The first nitride semiconductor layer 52 and the p-type layer 54 are made of, for example, GaN or AlGaN. The second nitride semiconductor layer 53 is made of, for example, AlGaN. AlGaN refers to a nitride semiconductor having a composition of Al. ｘ Ga １－ｘ The first nitride semiconductor layer 52, the second nitride semiconductor layer 53 and the p-type layer are nitrides having a composition of Al. ｘ Ga １－ｘ―ｙ In ｙ Alternatively, a nitride may be used, where x and y are N (0≦x≦1, 0≦y≦1), with values ​​of x and y being determined for each layer. The substrate 51 is, for example, a Si substrate. The substrate 51 is not limited to a Si substrate, and may be a GaN substrate, a SiC substrate, a sapphire substrate, or the like.

[0188] (Aspects) Based on the above-described embodiments, the present specification discloses the following aspects.

[0189] A control system (10) according to a first aspect is a control system for a normally-on dual-gate bidirectional switch (1). The dual-gate bidirectional switch (1) has a first gate (G1), a first source (S1) corresponding to the first gate (G1), a second gate (G2), and a second source (S2) corresponding to the second gate (G2). The control system (10) includes a first gate drive circuit (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j), a second gate drive circuit (12; 12a; 12b; 12c; 12d; 12e; 12f; 12g; 12h; 12i; 12j), and a controller (13). The first gate drive circuit (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j) is connected between the first gate (G1) and the first source (S1), and the second gate drive circuit (12; 12a; 12b; 12c; 12d; 12e; 12f; 12g; 12h; 12i; 12j) is connected between the second gate (G2) and the second source (S2). The controller (13) controls the first gate drive circuits (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j) and the second gate drive circuits (12; 12a; 12b; 12c; 12d; 12e; 12f; 12g; 12h; 12i; 12j) to turn on the dual-gate bidirectional switch (1), and if the potential of the first source (S1) is lower than the potential of the second source (S2), the controller (13) controls the first gate drive circuits (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j) as follows: That is, the controller (13) applies a first positive voltage (VP1) between the first gate (G1) and the first source (S1) from the first gate drive circuit (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j) for only a first period (T1), and applies a voltage (V1) smaller than the first positive voltage (VP1) after the first period (T1) has elapsed.

[0190] The control system (10) according to the first aspect can suppress current collapse in a normally-on dual-gate bidirectional switch (1).

[0191] In the control system (10) according to the second aspect, in the first aspect, when the potential of the first source (S1) is lower than the potential of the second source (S2) when turning on the dual-gate bidirectional switch (1), the controller (13) controls the second gate drive circuit (12; 12a; 12b; 12c; 12d; 12e; 12f; 12g; 12h; 12i; 12j) as follows: That is, the controller (13) applies a second positive voltage (VP2) from the second gate drive circuit (12; 12a; 12b; 12c; 12d; 12e; 12f; 12g; 12h; 12i; 12j) between the second gate (G2) and the second source (S2) for only a second period (T2), and then applies a voltage (V2) smaller than the second positive voltage (VP2) after the second period (T2) has elapsed.

[0192] In the control system (10) according to the second aspect, it is possible to suppress current collapse in the normally-on type dual-gate bidirectional switch (1).

[0193] In the control system (10) according to the third aspect, in the first or second aspect, the controller (13) turns on the dual-gate bidirectional switch (1) at the same timing as the timing shown in (i) below and the timing shown in (ii).

[0194] (i) The timing at which the first gate drive circuit (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j) starts applying the first positive voltage (VP1) between the first gate (G1) and the first source (S1).

[0195] (ii) The timing at which the second gate drive circuit (12; 12a; 12b; 12c; 12d; 12e; 12f; 12g; 12h; 12i; 12j) starts applying a voltage higher than the threshold voltage between the second gate (G2) and the second source (S2).

[0196] In the control system (10) according to the fourth aspect, in the first or second aspect, when the dual-gate bidirectional switch (1) is turned on, if the potential of the first source (S1) is lower than the potential of the second source (S2), the controller (13) controls the first gate drive circuit (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j) and the second gate drive circuit (12) as follows: That is, the control system (10) starts applying a first positive voltage (VP1) between the first gate (G1) and the first source (S1) from the first gate drive circuit (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j), and then starts applying a voltage higher than the threshold voltage between the second gate (G2) and the second source (S2) from the second gate drive circuit (12) within a first period (T1).

[0197] The control system (10) according to the fourth aspect is configured to transfer holes (h ＋ ) is easily injected, making it possible to suppress current collapse.

[0198] In the control system (10) according to the fifth aspect, in the second aspect, when the dual-gate bidirectional switch (1) is turned on, if the potential of the second source (S2) is higher than the potential of the first source (S1), the controller (13) controls the first gate drive circuit (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j) and the second gate drive circuit (12) as follows: That is, the controller (13) starts application of a second positive voltage (VP2) from the second gate drive circuit (12) between the second gate (G2) and the second source (S2), and then starts application of a first positive voltage (VP1) from the first gate drive circuit (11; 11a; 11b; 11c; 11d; 11e; 11f; 11g; 11h; 11i; 11j) between the first gate (G1) and the first source (S1) within the second period (T2).

[0199] The control system (10) according to the fifth aspect suppresses negative charges near the second gate (G2), which has a relatively higher potential out of the first gate (G1) and the second gate (G2), by injecting holes from the second gate (G2), and then applies a first positive voltage (VP1) between the first gate (G1), which has a relatively lower potential, and the first source (S1), thereby making it possible to further suppress current collapse.

[0200] In a control system (10) according to a sixth aspect, in any one of the first to fifth aspects, the dual-gate bidirectional switch (1) includes a substrate (102), a first nitride semiconductor layer (104), a second nitride semiconductor layer (105), a first source electrode (171), a first gate electrode (181), a second gate electrode (182), a second source electrode (172), a first p-type layer (161), and a second p-type layer (162). The first nitride semiconductor layer (104) is formed on the substrate (102). The second nitride semiconductor layer (105) is formed on the first nitride semiconductor layer (104). The band gap of the second nitride semiconductor layer (105) is larger than the band gap of the first nitride semiconductor layer (104). The first source electrode (171), the first gate electrode (181), the second gate electrode (182), and the second source electrode (172) are formed on the second nitride semiconductor layer (105). The first p-type layer (161) is interposed between the first gate electrode (181) and the second nitride semiconductor layer (105). The second p-type layer (162) is interposed between the second gate electrode (182) and the second nitride semiconductor layer (105). The first gate (G1) includes the first gate electrode (181) and the first p-type layer (161). The second gate (G2) includes the second gate electrode (182) and the second p-type layer (162).

[0201] In a control system (10) according to a seventh aspect, in any one of the first to fifth aspects, the first gate drive circuit (11) has a first series circuit, a second switch (SW2), and a second series circuit connected between the first gate (G1) and the first source (S1). The first series circuit includes a positive power supply (E1) and the first switch (SW1). The second switch (SW2) is connected between the first gate (G1) and the first source (S1). The second series circuit includes a negative power supply (E2) and a third switch (SW3), and is connected between the first gate (G1) and the first source (S1). A controller (13) controls the first switch (SW1), the second switch (SW2), and the third switch (SW3).

[0202] In the control system (10) according to the seventh aspect, the circuit design of the first gate drive circuit (11) becomes easier.

[0203] In a control system (10) according to an eighth aspect, in the sixth aspect, the first gate drive circuit (11a) has a first series circuit, a second series circuit, and a third series circuit, each connected between the first gate (G1) and the first source (S1). The first series circuit is a series circuit including a positive power supply (E1), a first switch (SW1), and a first resistor (R1). The second series circuit is a series circuit including the positive power supply (E1), a second switch (SW2), and a second resistor (R2). The third series circuit is a series circuit including a negative power supply (E2), a third switch (SW3), and a third resistor (R3). The resistance value of the first resistor (R1) is smaller than the resistance value of the second resistor (R2). The controller (13) controls the first switch (SW1), the second switch (SW2), and the third switch (SW3).

[0204] In the control system (10) according to the eighth aspect, the circuit design of the first gate drive circuit (11) becomes easier.

[0205] In a control system (10) according to a ninth aspect, in the sixth aspect, the first gate drive circuit (11b) includes a first series circuit, a second resistor (R2), and a second series circuit, each connected between the first gate (G1) and the first source (S1). The first series circuit is a series circuit including a positive power supply (E1), a first switch (SW1), a capacitor (C1), and a first resistor (R1). The second resistor (R2) is connected in parallel to the series circuit of the capacitor (C1) and the first resistor (R1). The second series circuit is a series circuit including a negative power supply (E2), a second switch (SW2), and a third resistor (R3). The resistance value of the first resistor (R1) is smaller than the resistance value of the second resistor (R2). The controller (13) controls the first switch (SW1) and the second switch (SW2).

[0206] In the control system (10) according to the ninth aspect, the first period (T1) during which the first positive voltage (VP1) is applied is determined by the capacitance of the capacitor (C1).

[0207] In a control system (10) according to a tenth aspect, in the sixth aspect, the first gate drive circuit (11c) includes a first series circuit, a second series circuit, and a second resistor (R2), each connected between the first gate (G1) and the first source (S1). The first series circuit is a series circuit of a positive power supply (E1), a first switch (SW1), a capacitor (C1), and the first resistor (R1). The second series circuit is a series circuit of a negative power supply (E2) and a second switch (SW2), which is connected in parallel to the series circuit of the positive power supply (E1) and the first switch (SW1). The second resistor (R2) is connected in parallel to the series circuit of the capacitor (C1) and the first resistor (R1). The resistance value of the first resistor (R1) is smaller than the resistance value of the second resistor (R2). The controller (13) controls the first switch (SW1) and the second switch (SW2).

[0208] The control system (10) according to the tenth aspect can be made smaller and less expensive than the control system (10) according to the ninth aspect.

[0209] In a control system (10) according to an eleventh aspect, in the sixth aspect, the first gate drive circuit (11d) includes a first series circuit, a second series circuit, a second resistor (R2), and a third series circuit, each connected between the first gate (G1) and the first source (S1). The first series circuit is a series circuit including a positive power supply (E1), a first switch (SW1), a first diode (D1), a capacitor (C1), and a first resistor (R1). The second series circuit is a series circuit including a negative power supply (E2) and a second switch (SW2), which is connected in parallel to the series circuit of the positive power supply (E1) and the first switch (SW1). The second resistor (R2) is connected in parallel to the series circuit of the first diode (D1), the capacitor (C1), and the first resistor (R1). The third series circuit is a series circuit including a second diode (D2) and a third resistor (R3) connected in parallel to the series circuit of the first diode (D1), capacitor (C1), and first resistor (R1). The anode of the first diode (D1) is connected to the positive terminal of the positive power supply (E1) and the negative terminal of the negative power supply (E2). The cathode of the second diode (D2) is connected to the positive terminal of the positive power supply (E1) and the negative terminal of the negative power supply (E2). The resistance value of the first resistor (R1) is smaller than the resistance value of the second resistor (R2). The resistance value of the third resistor (R3) is smaller than the resistance value of the second resistor (R2). The controller (13) controls the first switch (SW1) and the second switch (SW2).

[0210] The control system (10) according to the eleventh aspect can suppress power loss at the first gate (G1) of the dual-gate bidirectional switch (1).

[0211] In a control system (10) according to a twelfth aspect, in the sixth aspect, the first gate drive circuit (11e) includes a first series circuit, a second switch (SW2), a second resistor (R2), and a third resistor (R3), each connected between the first gate (G1) and the first source (S1). The first series circuit is a series circuit of a negative power supply (E2), the first switch (SW1), a capacitor (C1), and the first resistor (R1). The second switch (SW2) is connected in parallel to the series circuit of the negative power supply (E2) and the first switch (SW1). The second resistor (R2) is connected in parallel to the series circuit of the capacitor (C1) and the first resistor (R1). The third resistor (R3) is connected between the first gate (G1) and the first source (S1). The resistance value of the first resistor (r1) is smaller than the resistance value of the second resistor (R2). The controller (13) controls the first switch (SW1) and the second switch (SW2).

[0212] The control system (10) according to the twelfth aspect can generate the first positive voltage (VP1) without using a positive power supply, thereby enabling miniaturization and cost reduction.

[0213] In a control system (10) according to a thirteenth aspect, in the sixth aspect, the first gate drive circuit (11f) includes a first series circuit, a second switch (SW2), and a second resistor (R2), each connected between the first gate (G1) and the first source (S1). The first series circuit is a series circuit of a negative power supply (E2), the first switch (SW1), a capacitor (C1), and the first resistor (R1). The second switch (SW2) is connected in parallel to the series circuit of the negative power supply (E2) and the first switch (SW1). The second resistor (R2) is connected in parallel to the series circuit of the capacitor (C1) and the first resistor (R1). The resistance value of the first resistor (R1) is smaller than the resistance value of the second resistor (R2). The control system (10) further includes a clamp circuit (14). The clamp circuit (14) is connected between the first gate (G1) and the first source (S1) and clamps the voltage between the first gate (G1) and the first source (S1). The controller (13) controls the first switch (SW1) and the second switch (SW2).

[0214] The control system (10) according to the thirteenth aspect can generate the first positive voltage (VP1) without using a positive power supply, thereby enabling miniaturization and cost reduction.

[0215] In a control system (10) according to a fourteenth aspect, in the sixth aspect, the first gate drive circuit (11g; 11h) includes a first series circuit, a second switch (SW2), a second series circuit, and a third resistor (R3), connected between the first gate (G1) and the first source (S1). The first series circuit is a series circuit of a negative power supply (E2), the first switch (SW1), a capacitor (C1), a first diode (D1), and a first resistor (R1). The second switch (SW2) is connected in parallel to the series circuit of the negative power supply (E2) and the first switch (SW1). The second series circuit is connected in parallel to the series circuit of the first diode (D1) and the first resistor (R1), and is a series circuit of a second diode (D2) and a second resistor (R2). The third resistor (R3) is connected in parallel to the series circuit of the capacitor (C1), the first diode (D1), and the first resistor (R1). The anode of the first diode (D1) is connected to the capacitor (C1). The cathode of the second diode (D2) is connected to the capacitor (C1). The resistance value of the first resistor (R1) is smaller than the resistance value of the second resistor (R2). The control system (10) further includes a clamp circuit (14). The clamp circuit (14) is connected between the first gate (G1) and the first source (S1) and clamps the voltage between the first gate (G1) and the first source (S1). The controller (13) controls the first switch (SW1) and the second switch (SW2).

[0216] The control system (10) according to the fourteenth aspect is capable of generating the first positive voltage (VP1) without using a positive power supply, and also facilitates the circuit design of the first gate drive circuit (11g; 11h).

[0217] A control system (10) according to a fifteenth aspect is the same as in the fourteenth aspect, wherein the clamp circuit (14) includes a Zener diode (Dz) and a diode (D5). The anode of the Zener diode (Dz) is connected to the first gate (G1), the cathode of the Zener diode (Dz) is connected to the cathode of the diode (D5), and the anode of the diode (D5) is connected to the first source (S1).

[0218] The control system (10) according to the fifteenth aspect can suppress leakage of part of the gate current through the Zener diode (Dz) when the first positive voltage (VP1) is applied to the first gate (G1), making it easier to increase the first positive voltage (VP1).

[0219] In a control system (10) according to a sixteenth aspect, in the fifteenth aspect, the first gate drive circuit (11i) further includes a series circuit of a third diode (D3) and a fourth resistor (R4) connected in parallel to the series circuit of the capacitor (C1), the second diode (D2), and the second resistor (R2). The cathode of the third diode (D3) is connected to the capacitor (C1).

[0220] The control system (10) according to the sixteenth aspect makes it easier to control the turn-off speed of the dual-gate bidirectional switch (1).

[0221] In a control system (10) according to a seventeenth aspect, in the sixth aspect, the first gate drive circuit (11j) includes a first series circuit, a second switch (SW2), a second series circuit, and a third resistor (R3), connected between the first gate (G1) and the first source (S1). The first series circuit is a series circuit of a negative power supply (E2), the first switch (SW1), a capacitor (C1), a first diode (D1), and a first resistor (R1). The second switch (SW2) is connected in parallel to the series circuit of the negative power supply (E2) and the first switch (SW1). The second series circuit is connected in parallel to the series circuit of the first diode (D1) and the first resistor (R1), and is a series circuit of a second diode (D2) and a second resistor (R2). The third resistor (R3) is connected in parallel to the series circuit of the capacitor (C1), the first diode (D1), and the first resistor (R1). The anode of the first diode (D1) is connected to the capacitor (C1). The cathode of the second diode (D2) is connected to the capacitor (C1). The resistance value of the first resistor (R1) is smaller than the resistance value of the second resistor (R2). The first gate drive circuit (11) further includes a clamp circuit (14). The clamp circuit (14) is connected in parallel to the series circuit of the capacitor (C1), the first diode (D1), and the first resistor (R1). The controller (13) controls the first switch (SW1) and the second switch (SW2).

[0222] The control system (10) according to the seventeenth aspect makes it easier to control the turn-off speed of the dual-gate bidirectional switch (1).

[0223] A control system (10) according to an eighteenth aspect is any one of the first to sixth aspects, wherein the first gate drive circuit (11) includes a CMOS inverter capable of selectively outputting a first positive voltage (VP1) and a negative voltage less than a threshold voltage.

[0224] The switch system (20) according to the nineteenth aspect can suppress current collapse in the normally-on dual-gate bidirectional switch (1).

[0225] In a control method for a dual-gate bidirectional switch according to a twentieth aspect, the dual-gate bidirectional switch (1) is a normally-on type dual-gate bidirectional switch (1) having a first gate (G1), a first source (S1) corresponding to the first gate (G1), a second gate (G2), and a second source (S2) corresponding to the second gate (G2). In the control method for the dual-gate bidirectional switch (1), when the potential of the first source (S1) is lower than the potential of the second source (S2) when the dual-gate bidirectional switch (1) is turned on, a first positive voltage (VP1) is applied between the first gate (G1) and the first source (S1) for a first period (T1), and a voltage (V1) smaller than the first positive voltage (VP1) is applied after the first period (T1) has elapsed.

[0226] The method for controlling a dual-gate bidirectional switch according to the nineteenth aspect makes it possible to suppress current collapse in a normally-on dual-gate bidirectional switch (1).

[0227] A control system (40) according to a twentieth aspect is a control system for a unidirectional switch element (42). The unidirectional switch element (42) is a normally-on single-gate field effect transistor having a gate (G), a source (S), and a drain (D). The unidirectional switch element (42) includes a substrate (51), a first nitride semiconductor layer (52), a second nitride semiconductor layer (53), a source electrode (S), a gate electrode (G), a drain electrode (D), and a p-type layer (54). The first nitride semiconductor layer (52) is formed on the substrate (51). The second nitride semiconductor layer (53) is formed on the first nitride semiconductor layer (52). The second nitride semiconductor layer (53) has a larger band gap than the first nitride semiconductor layer (52). The source electrode (55), the gate electrode (57), and the drain electrode (56) are formed on the second nitride semiconductor layer (62). The p-type layer (54) is interposed between the gate electrode (57) and the second nitride semiconductor layer (53). The gate (G) includes the gate electrode (57) and the p-type layer (52). The source (S) includes a source electrode (55), and the drain (D) includes a drain electrode (56). The control system (40) includes a gate drive circuit (43) and a controller (41). The gate drive circuit (43) is connected between the gate (G) and the source (S). The controller (41) controls the gate drive circuit (43). When turning on the unidirectional switch element (42), if the potential of the source (S) is lower than the potential of the drain (D), the controller (41) applies a first positive voltage from the gate drive circuit (43) between the gate (G) and the source (S) for only a first period, and applies a voltage smaller than the first positive voltage after the first period has elapsed.

[0228] The control system according to the twentieth aspect can suppress current collapse in a unidirectional switch made of a normally-on nitride semiconductor.

[0229] The control system and control method for a dual-gate bidirectional switch disclosed herein can suppress current collapse in a normally-on dual-gate bidirectional switch. Furthermore, the control system and control method for a dual-gate bidirectional switch disclosed herein can suppress current collapse in a unidirectional switch made of a normally-on nitride semiconductor. That is, the control system and control method for a dual-gate bidirectional switch disclosed herein are particularly useful for normally-on switches.

[0230] 1 Dual gate bidirectional switch G1 First gate S1 First source G2 Second gate S2 Second source 10, 40 Control system 11, 11a, 11b, 11c, 11d, 11e, 11f, 11g, 11h, 11i, 11j, 11r First gate drive circuit 12, 12a, 12b, 12c, 12d, 12e, 12f, 12g, 12h, 12i, 12j, 12r Second gate drive circuit 13, 43 Controller 14 Clamp circuit 20 Switch system 161 First p-type layer 162 Second p-type layer 171 First source electrode 172 Second source electrode 181 First gate electrode 182 Second gate electrode C1 Capacitor D1 First diode D2 Second diode D4, Dz Zener diode E1 Positive power supply E2 Negative power supply R1 First resistor R2 Second resistor R3 Third resistor SW1 First switch SW2 Second switch SW3 Third switch T1 First period T2 Second period V1 First voltage V2 Second voltage VP1 First positive voltage VP2 Second positive voltage S Source G Gate D Drain 41 Gate drive circuit 51, 102 Substrate 52, 104 First nitride semiconductor layer 53, 105 Second nitride semiconductor layer 54 P-type layer 55 Source electrode 56 Drain electrode 57 Gate electrode

Claims

1. A control system for a normally-on dual-gate bidirectional switch having a first gate, a first source corresponding to the first gate, a second gate, and a second source corresponding to the second gate, comprising: a first gate drive circuit connected between the first gate and the first source; a second gate drive circuit connected between the second gate and the second source; and a controller that controls the first gate drive circuit and the second gate drive circuit, wherein when turning on the dual-gate bidirectional switch, if the potential of the first source is lower than the potential of the second source, the controller causes the first gate drive circuit to apply a first positive voltage between the first gate and the first source for a first period, and after the first period has elapsed, causes the first gate drive circuit to apply a voltage smaller than the first positive voltage.

2. The control system of claim 1, wherein, when turning on the dual-gate bidirectional switch, the controller causes the second gate drive circuit to apply a second positive voltage between the second gate and the second source for only a second period if the potential of the first source is lower than the potential of the second source, and then applies a voltage smaller than the second positive voltage after the second period has elapsed.

3. The control system according to claim 1 or 2, wherein, when turning on the dual-gate bidirectional switch, the controller synchronizes the timing at which the first gate drive circuit starts applying the first positive voltage between the first gate and the first source with the timing at which the second gate drive circuit starts applying a voltage higher than a threshold voltage between the second gate and the second source.

4. The control system according to claim 1 or 2, wherein when the controller turns on the dual-gate bidirectional switch, if the potential of the first source is lower than the potential of the second source, the controller starts applying the first positive voltage from the first gate drive circuit between the first gate and the first source, and thereafter starts applying a voltage higher than a threshold voltage from the second gate drive circuit between the second gate and the second source within the first period.

5. The control system of claim 2, wherein the controller, when turning on the dual-gate bidirectional switch, starts applying the second positive voltage from the second gate drive circuit between the second gate and the second source if the potential of the second source is higher than the potential of the first source, and then starts applying the first positive voltage from the first gate drive circuit between the first gate and the first source within the second period.

6. The control system according to any one of claims 1 to 5, wherein the dual-gate bidirectional switch comprises: a substrate; a first nitride semiconductor layer formed on the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a first source electrode, a first gate electrode, a second gate electrode, and a second source electrode formed on the second nitride semiconductor layer; a first p-type layer interposed between the first gate electrode and the second nitride semiconductor layer; and a second p-type layer interposed between the second gate electrode and the second nitride semiconductor layer, wherein the first gate includes the first gate electrode and the first p-type layer, and the second gate includes the second gate electrode and the second p-type layer.

7. A control system according to any one of claims 1 to 5, wherein the first gate drive circuit comprises: a series circuit including a positive power supply and a first switch connected between the first gate and the first source; a second switch connected between the first gate and the first source; and a series circuit including a negative power supply and a third switch connected between the first gate and the first source; and the controller controls the first switch, the second switch, and the third switch.

8. The control system of claim 6, wherein the first gate drive circuit comprises: a series circuit including a positive power supply, a first switch, and a first resistor, connected between the first gate and the first source; a series circuit including the positive power supply, a second switch, and a second resistor, connected between the first gate and the first source; and a series circuit including a negative power supply, a third switch, and a third resistor, connected between the first gate and the first source; wherein a resistance value of the first resistor is smaller than a resistance value of the second resistor; and wherein the controller controls the first switch, the second switch, and the third switch.

9. The control system of claim 6, wherein the first gate drive circuit comprises: a series circuit connected between the first gate and the first source and including a positive power supply, a first switch, a capacitor, and a first resistor; a second resistor connected in parallel to the series circuit of the capacitor and the first resistor; and a series circuit connected between the first gate and the first source and including a negative power supply, a second switch, and a third resistor; wherein a resistance value of the first resistor is smaller than a resistance value of the second resistor; and wherein the controller controls the first switch and the second switch.

10. The control system of claim 6, wherein the first gate drive circuit comprises: a series circuit of a positive power supply, a first switch, a capacitor, and a first resistor connected between the first gate and the first source; a series circuit of a negative power supply and a second switch connected in parallel to the series circuit of the positive power supply and the first switch; and a second resistor connected in parallel to the series circuit of the capacitor and the first resistor, wherein a resistance value of the first resistor is smaller than a resistance value of the second resistor, and the controller controls the first switch and the second switch.

11. The control system of claim 6, wherein the first gate drive circuit comprises: a series circuit connected between the first gate and the first source, the series circuit including a positive power supply, a first switch, a first diode, a capacitor, and a first resistor; a series circuit of a negative power supply and a second switch connected in parallel to the series circuit of the positive power supply and the first switch; a second resistor connected in parallel to the series circuit of the first diode, the capacitor, and the first resistor; and a series circuit connected in parallel to the series circuit of the first diode, the capacitor, and the first resistor, the series circuit including a second diode and a third resistor, wherein the anode of the first diode is connected to the positive electrode of the positive power supply and the negative electrode of the negative power supply; the cathode of the second diode is connected to the positive electrode of the positive power supply and the negative electrode of the negative power supply; a resistance value of the first resistor is smaller than a resistance value of the second resistor; and a resistance value of the third resistor is smaller than a resistance value of the second resistor; and the controller controls the first switch and the second switch.

12. The control system of claim 6, wherein the first gate drive circuit comprises: a series circuit of a negative power supply, a first switch, a capacitor, and a first resistor connected between the first gate and the first source; a second switch connected in parallel to the series circuit of the negative power supply and the first switch; a second resistor connected in parallel to the series circuit of the capacitor and the first resistor; and a third resistor connected between the first gate and the first source, wherein a resistance value of the first resistor is smaller than a resistance value of the second resistor, and the controller controls the first switch and the second switch.

13. The control system according to claim 6, wherein the first gate drive circuit comprises: a series circuit of a negative power supply, a first switch, a capacitor, and a first resistor connected between the first gate and the first source; a second switch connected in parallel to the series circuit of the negative power supply and the first switch; and a second resistor connected in parallel to the series circuit of the capacitor and the first resistor, wherein a resistance value of the first resistor is smaller than a resistance value of the second resistor; and further comprises a clamp circuit connected between the first gate and the first source and clamping a voltage between the first gate and the first source; and the controller controls the first switch and the second switch.

14. The control system according to claim 6, wherein the first gate drive circuit comprises: a series circuit of a negative power supply, a first switch, a capacitor, a first diode, and a first resistor connected between the first gate and the first source; a second switch connected in parallel to the series circuit of the negative power supply and the first switch; a series circuit of a second diode and a second resistor connected in parallel to the series circuit of the first diode and the first resistor; and a third resistor connected in parallel to the series circuit of the capacitor, the first diode, and the first resistor, wherein the anode of the first diode is connected to the capacitor and the cathode of the second diode is connected to the capacitor, and the resistance value of the first resistor is smaller than the resistance value of the second resistor, and further comprises a clamp circuit connected between the first gate and the first source and clamping a voltage between the first gate and the first source, and the controller controls the first switch and the second switch.

15. The control system of claim 14, wherein the clamp circuit includes: a Zener diode; and a diode, the anode of the Zener diode being connected to the first gate, the cathode of the diode being connected to the cathode of the Zener diode, and the anode of the diode being connected to the first source.

16. The control system according to claim 15, wherein the first gate drive circuit further comprises a series circuit of a third diode and a fourth resistor connected in parallel with the series circuit of the capacitor, the second diode and the second resistor, and the cathode of the third diode is connected to the capacitor.

17. The control system of claim 6, wherein the first gate drive circuit comprises: a series circuit of a negative power supply, a first switch, a capacitor, a first diode, and a first resistor connected between the first gate and the first source; a second switch connected in parallel to the series circuit of the negative power supply and the first switch; a series circuit of a second diode and a second resistor connected in parallel to the series circuit of the first diode and the first resistor; and a third resistor connected in parallel to the series circuit of the capacitor, the first diode, and the first resistor, wherein the anode of the first diode is connected to the capacitor and the cathode of the second diode is connected to the capacitor, and the resistance value of the first resistor is smaller than the resistance value of the second resistor, the first gate drive circuit further comprises a clamp circuit connected in parallel to the series circuit of the capacitor, the first diode, and the first resistor, and the controller controls the first switch and the second switch.

18. The control system according to any one of claims 1 to 6, wherein the first gate drive circuit includes a CMOS inverter capable of selectively outputting the first positive voltage and a negative voltage less than a threshold voltage.

19. A control method for a normally-on dual-gate bidirectional switch having a first gate, a first source corresponding to the first gate, a second gate, and a second source corresponding to the second gate, the control method comprising: when turning on the dual-gate bidirectional switch, if the potential of the first source is lower than the potential of the second source, applying a first positive voltage between the first gate and the first source for only a first period, and applying a voltage smaller than the first positive voltage after the first period has elapsed.

20. A control system for a unidirectional switch element having a gate, a source, and a drain, the control system comprising: a gate drive circuit; and a controller that controls the gate drive circuit; the unidirectional switch element is a normally-on type single-gate field effect transistor, the field effect transistor comprising: a substrate; a first nitride semiconductor layer formed on the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a source electrode, a gate electrode, and a drain electrode formed on the second nitride semiconductor layer; and a p-type layer interposed between the gate electrode and the second nitride semiconductor layer; the gate includes the gate electrode and the p-type layer; the source includes the source electrode; and the drain includes the drain electrode; the gate drive circuit is connected between the gate and the source; and the controller, when turning on the unidirectional switch element, a control system that applies a first positive voltage between the gate and the source from the gate drive circuit for a first period of time, and applies a voltage smaller than the first positive voltage after the first period has elapsed.

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