Decoupling capacitors in gate cut trenches

Abstract

A method of forming a semiconductor device comprising a first power rail and one or more vertically stacked contact vias connecting the first power rail to a portion of a first decoupling capacitor, the semiconductor device comprising the first decoupling capacitor in a first portion of a semiconductor substrate within a first gate cut trench.

Description

[Technical Field]

[0001] The present invention relates generally to the field of semiconductor memory device technology, and more particularly to forming decoupling capacitors in gate cut trenches under power rails of semiconductor circuits. [Background technology]

[0002] Semiconductor device manufacturing and design continues to push the boundaries of semiconductor device performance, continually packing more circuitry onto semiconductor chips as line widths and spacing between device elements shrink. Traditionally, transistors are formed in a semiconductor substrate and connected to each other by layers of interconnects and power structures formed above the transistors. Conventional power rails, commonly used with memory devices such as static random access memory (SRAM), typically reside in the interconnect layer above the transistors. Conventional power rails in the interconnect layer consume significant real estate, and to meet semiconductor performance requirements, large power guard bands are typically used to address power rail noise. To reduce power rail noise and improve semiconductor device performance, decoupling capacitors, such as metal-insulator-metal capacitors (MIMCAPs) formed in the interconnect layer or deep trench capacitors formed in the insulating layer of a silicon-on-insulator semiconductor substrate, are used to reduce power rail noise and improve semiconductor device performance. Summary of the Invention

[0003]

[0006] Embodiments of the present invention provide a semiconductor structure for a semiconductor device and a method for forming the semiconductor structure, the semiconductor structure comprising a first power rail and one or more vertically stacked contact vias electrically connecting the first power rail to a portion of a first decoupling capacitor in a first portion of a semiconductor substrate within a first gate cut trench.

[0004] Embodiments of the present invention provide a semiconductor structure for a semiconductor device and a method of forming the semiconductor structure, the semiconductor structure comprising: a first gate cut trench in a first portion of a semiconductor substrate under a first power rail; a first metal layer in the first portion of the semiconductor substrate; a dielectric layer on the first metal layer in the first portion of the semiconductor substrate; and a ferroelectric layer on the dielectric layer in the first portion of the semiconductor substrate, on a bottom of a shallow isolation trench above the semiconductor substrate, and within a portion of the gate cut trench.

[0005] Embodiments of the present invention provide a semiconductor structure for a semiconductor device and a method for forming the semiconductor structure, the semiconductor structure comprising: a power rail and a gate cut trench below the power rail; a dielectric layer on a portion of a semiconductor substrate within the gate cut trench; a ferroelectric layer on the dielectric layer and on vertical surfaces of the gate cut trench above the semiconductor substrate; and a metal within the ferroelectric layer.

[0006] These and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a top view of a semiconductor circuit layout having two power rails, according to one embodiment of the present invention. [Figure 2] 2 is a cross-sectional view of a semiconductor structure through section AA' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 3] 2 is a cross-sectional view of a semiconductor structure through section BB' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 4] 2 is a cross-sectional view of a semiconductor structure through section CC' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 5A]2 is a cross-sectional view of a semiconductor structure through section AA' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 5B] 2 is a cross-sectional view of a semiconductor structure through section BB' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 5C] 2 is a cross-sectional view of a semiconductor structure through section CC' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 6A] 2 is a cross-sectional view of a semiconductor structure through section AA' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 6B] 2 is a cross-sectional view of a semiconductor structure through section BB' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 6C] 2 is a cross-sectional view of a semiconductor structure through section AA' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. [Figure 7] 10 is a graph showing the results of a technical computer-aided design (TCAD) analysis of a 4.4 eV work function metal disposed on a ferroelectric material and a 4.9 eV work function metal disposed on a ferroelectric material in the absence of a gate cut trench, according to a second embodiment of the present invention. [Figure 8] 10 is a graph showing the results of a TCAD analysis of a 4.4 eV work function metal disposed on a ferroelectric material and a 4.9 eV work function metal disposed on a ferroelectric material when the gate cut trench depth is 20 nm according to a second embodiment of the present invention. [Figure 9] 10 is a graph showing the results of a TCAD analysis of a 4.4 eV work function metal disposed on a ferroelectric material and a 4.9 eV work function metal disposed on a ferroelectric material when the gate cut trench depth is 20 nm and no silicon dioxide layer is adjacent to the semiconductor substrate in accordance with a second embodiment of the present invention. [Figure 10] 10 is a graph showing peak capacitance versus remanent polarization for various materials and various gate cut trench depths according to a second embodiment of the present invention. [Figure 11]2 is a cross-sectional view through CC' of FIG. 1 forming a semiconductor structure after gate deposition according to one embodiment of the present invention. [Figure 12] 2 is a cross-sectional view through A-A' of FIG. 1 after etching of an interlayer dielectric (ILD), an STI layer, and a gate cut trench through the top of a semiconductor substrate to form a semiconductor structure according to one embodiment of the present invention. [Figure 13] 2 is a cross-sectional view through CC' of FIG. 1 forming a semiconductor structure after forming a layer of dielectric material on a semiconductor substrate according to one embodiment of the present invention. [Figure 14] 2 is a cross-sectional view through CC' of FIG. 1 forming a semiconductor structure after deposition and etching of ferroelectric and metal materials in the gate cut trench according to one embodiment of the present invention. [Figure 15] 2 is a cross-sectional view through CC' of FIG. 1 forming a semiconductor structure after deposition of a dielectric cap material on the semiconductor structure and planarization of the top surface of the semiconductor structure according to one embodiment of the present invention. [Figure 16] 2 is a cross-sectional view through CC' of FIG. 1 forming a semiconductor structure after forming contact vias according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0008] Embodiments of the present invention recognize that power rails typically reside in interconnect layers above transistors. Embodiments of the present invention recognize that power rail noise adversely affects system performance. Power rail noise increases the instantaneous peak drain voltage supply or increases Vdd throughout a noise cycle. Increased power rail noise increases the need for a Vdd guard band, thereby lowering the nominal voltage. Embodiments of the present invention recognize that the larger the guard band, the lower the nominal operating voltage of a semiconductor circuit, and therefore the lower the performance of a given semiconductor circuit design. Embodiments of the present invention recognize that reducing power rail noise can increase the nominal operating voltage of a semiconductor circuit design, thereby improving the performance of the semiconductor circuit design.

[0009] Embodiments of the present invention recognize that decoupling capacitors reduce power rail noise. In some cases, deep trench capacitors or MIMCAPs in the back-end-of-line (BEOL) are used as decoupling capacitors to reduce noise. Embodiments of the present invention recognize that metal-insulator-metal capacitors (MIMCAPs) formed in back-end-of-line (BEOL) semiconductor processes offer lower capacitance density and limited frequency response due to the resistive network of BEOL wiring. Embodiments of the present invention recognize that placing decoupling capacitors with high capacitance density as close as possible to the power rails improves semiconductor chip and system performance.

[0010] Embodiments of the present invention provide a method for forming a decoupling capacitor in a gate cut trench in a semiconductor substrate. The decoupling capacitor in the gate cut trench extends parallel to and below the power rail. To form the decoupling capacitor in the semiconductor substrate below the power rail, the gate cut trench is cut or etched deeper than conventional gate cut trenches. Embodiments of the present invention include a method for forming a decoupling capacitor in the upper part of a semiconductor substrate by performing one or more etches that remove a portion of the gate, a portion of a shallow trench isolation (STI) below the removed portion of the gate, and an upper part of the semiconductor substrate. While gate cut trenches are typically etched through the edge of the gate and extend down to the top surface of the STI, embodiments of the present invention etch the gate cut trench deeper so that the gate cut trench extends into the upper part of the semiconductor substrate. Extending the gate cut trench into the semiconductor substrate allows for the deposition of decoupling capacitor material in the gate cut trench of the semiconductor substrate. Decoupling capacitors formed in deep gate cut trenches in the semiconductor substrate directly below the power rails are closer to the power rails than traditional MIMCAP or traditional deep trench decoupling capacitors.

[0011] Embodiments of the present invention provide decoupling capacitors within the semiconductor substrate using deeper gate cut trenches that reduce power rail noise and are closer to the power rails than MIMCAP or traditional deep trench capacitors. Placing the decoupling capacitors closer to the power rails reduces the resistor-capacitor (RC) circuit delay between the decoupling capacitor and the power rail, improving frequency response. Additionally, decoupling capacitors embedded in the semiconductor substrate allow for smaller power rail guard bands and higher nominal voltages for improved semiconductor circuit performance.

[0012] Embodiments of the present invention provide several different material combinations and semiconductor structures for decoupling capacitors in gate-cut trenches, allowing for process and material design tradeoffs that result in different levels of decoupling capacitor performance. Embodiments of the present invention provide decoupling capacitors in semiconductor substrates with different stack combinations of dielectric, ferroelectric, and metal materials that result in different electrical performance of the decoupling capacitor. Embodiments of the present invention provide dielectric and ferroelectric materials that form the decoupling capacitor. Embodiments of the present invention also provide metal, high-k dielectric, and ferroelectric materials in a metal-ferroelectric-insulator-metal (MFIM) stack that form another decoupling capacitor. Embodiments of the present invention provide a method for forming larger decoupling capacitors in semiconductor substrates by increasing the depth of the gate-cut trench in the semiconductor substrate, thereby improving the capacitance density of the decoupling capacitor.

[0013] An embodiment of the present invention provides a method for forming a decoupling capacitor in a semiconductor substrate. The method includes increasing the etch depth of a gate cut trench using one or more etching processes and a single gate cut etch mask. The method includes performing a standard gate cut trench etch, for example, down to the top of an STI, and then deepening the standard gate cut trench by etching through the STI and continuing into the semiconductor substrate. The one or more etching processes are used to increase the depth of the etched gate cut trench so that the gate cut trench extends into the semiconductor substrate. The method includes etching the gate cut trench below and parallel to where a power rail will be formed in a later step.

[0014] The method further includes forming a layer of dielectric material on the semiconductor substrate surface within the deeper gate cut trench. After forming the layer of dielectric material, a ferroelectric material is deposited within the gate cut trench. A first metal material is deposited within the recess of the gate cut trench (e.g., over the decoupling capacitor). The ferroelectric material and the first metal material are etched to a height below the top surface of the STI. In this method, the dielectric material is deposited within the gate cut trench on the metal material and on the ferroelectric material. Selective etching of the dielectric material at one end of the gate cut trench can be performed together with selective etching of the dielectric material over a central portion of the gate cut trench that contacts the top surface of the gate. Another metal layer is deposited on the semiconductor substrate and within the portion of the gate cut trench from which the dielectric material was removed to form a contact via connecting to the decoupling capacitor and making contact with the gate.

[0015] Embodiments of the present invention provide a method for forming a decoupling capacitor that connects to one end of a power rail and extends parallel to and below the power rail within a semiconductor substrate to reduce power rail noise and improve chip performance.

[0016] 1-6C and 11-16 show exemplary semiconductor structures including two decoupling capacitors, each under a power rail and connected to the power rail at one end. In embodiments of the invention, the semiconductor structures shown in FIGS. 2-5C show a metal-ferroelectric-insulator-semiconductor (MFIS) stack in a gate cut trench. In embodiments of the invention, the semiconductor structures of FIGS. 6A-6C show a metal-ferroelectric-insulator-metal (MFIM) stack in a gate cut trench.

[0017] FIG. 1 illustrates a top view of a semiconductor circuit layout 100 having power rails 3A and 3B according to one embodiment of the present invention. While layout 100 relates to an inverter as a logic cell or device circuit using fins in active region 7, the semiconductor circuit is not limited to layout 100 of an inverter with fins. For example, layout 100 may represent a logic cell or logic gate such as a NOT-AND (NAND) gate or a NOT-OR (NOR) gate. A NAND gate is a logic gate that produces an output that is false only if all inputs are true. A NOR gate as a logic gate or device circuit produces a positive output when both inputs are negative. In other embodiments, other types of semiconductor structures, such as planar structures (e.g., planar field-effect transistors rather than fin field-effect transistors) or nanosheet structures, may be used to form other types of device circuits.

[0018] While FIG. 1 shows two power rails, in other embodiments, three or more power rails are present in the semiconductor circuit or logic cell of layout 100. As shown, FIG. 1 includes views of gate cut mask 1, gate 2A, auxiliary gate 2B, power rails 3A and 3B, via contact 4, trench contact via 5, gate contact via 8, source / drain contact 6 extending under via contact 4, active region 7, first metal layer (M1) line 11, and cross sections A-A', B-B', and C-C' through the semiconductor circuit of layout 100. As shown in FIG. 1, each contact of a pair of trench contact vias 5 connects to one of power rail 3A or power rail 3B. Cross section C-C' of FIG. 4 further shows each of the trench contact vias 5, which connect to decoupling capacitors formed in the gate cut trenches and are connected to one of power rails 3A or 3B by via contact 4. In this way, each of the power rails 3A and 3B connects directly to the decoupling capacitors in the gate cut trenches underneath the power rails 3A and 3B by one of the trench contact vias 5 (shown in FIG. 4).

[0019] Power rails 3A and 3B reside in at least a first metal layer, i.e., M1, and, as known to those skilled in the art, power rails 3A and 3B may reside in one or more metal layers (not shown) above M1. In various embodiments of the present invention, power rails 3A and 3B are considered to include trench contact vias 5, via contacts 4, and metal material (e.g., metal 20 in FIG. 4 ) that underlie and are electrically connected to power rails 3A and 3B. In various embodiments, power rail 3A is a ground power rail. In various embodiments, power rail 3B is a DC power supply (VDD) power rail associated with an n-well. An n-well is a portion of a semiconductor substrate doped with n-type material (e.g., may be part of a p-type field effect transistor (PFET)). In other examples, the ground and VDD functions of power rails 3A and 3B may be swapped (e.g., power rail 3A is a VDD power rail).

[0020] In various embodiments, gate cut mask 1 indicates the location where a portion of gate 2A will be removed, as shown in FIG. 2 . As known to those skilled in the art, gate cut mask 1 can be used to define a cut or etch perpendicular to the direction of gate 2A (e.g., when used to etch gate 2A, gate mask 1 defines the edge of gate 2A). In this manner, when the edge or edge of gate 2A is formed by etching gate 2A using gate cut mask 1, the edge provides gate 2A with enhanced electrical performance compared to a gate not formed using gate cut mask 1. While gate cut mask 1 on auxiliary gate 2B may not be present, other examples show gate cut mask 1 on auxiliary gate 2B as a possible location. In FIG. 1 , one gate cut mask 1 is located below and parallel to each of power rails 3A and 3B.

[0021] As shown, the lines 11 on the left side of the layout 100 may be inputs to the semiconductor circuit shown in the layout 100, and the lines 11 on the right side of the layout 100 may be outputs of the semiconductor circuit. In various embodiments, the active areas 7 at the bottom of the layout 100 are associated with an n-well to form a p-type field effect transistor (PFET). In some embodiments, the active areas 7 at the bottom of the layout 100 are associated with a p-well to form an NFET. Although shown as layout 100 for an inverter, in other embodiments, the decoupling capacitors under the power rails 3A and 3B as shown in FIG. 4 are associated with another type of circuit device, such as a NAND gate, a NOR gate, or a buffer logic gate, but are not limited to these types of semiconductor device circuits or logic cells.

[0022] 2 is a cross-sectional view of a semiconductor structure 200 through section A-A' of the layout 100 shown in FIG. 1 according to one embodiment of the present invention. Section A-A' is parallel to the gate 2A and passes through the gate such that each of the gate cut trenches 10 is perpendicular to and penetrates the gate 2A (e.g., A-A' is within the gate 2A extending parallel to the length or length dimension of the gate 2A). While an interlayer dielectric material (ILD) 29 is shown on one side of the dielectric cap 23 within the gate cut trench 10, in other embodiments, the gate 2A is present on both sides of the dielectric cap 23 above the STI 27.

[0023] As shown, a gate cut trench 10 beneath each of power rails 3A and 3B extends from the top of gate 2A into the top of semiconductor substrate 26 and n-well 25. Gate cut trench 10 includes a dielectric layer 22, a ferroelectric layer 21, metal 20 within ferroelectric layer 21, and a dielectric cap 23 over the metal 20 and a portion of ferroelectric layer 21. Ferroelectric layer 21 and dielectric layer 22 form a decoupling capacitor within gate cut trench 10. The decoupling capacitor has a depth d within semiconductor substrate 26 and n-well 25. Power rails 3A and 3B each lie above and are parallel to the decoupling capacitor formed from ferroelectric layer 21 and dielectric layer 22.

[0024] As shown, FIG. 2 also includes a gate contact via 8, which is stacked vertically below the via contact 4 and connects the gate 2A to a line 11 formed from a portion of the M1 metal layer. A fin 24 overlies a portion of the n-well 25 and a portion of the semiconductor substrate 26. As known to those skilled in the art, the fin 24 may be in the active area 7 (shown in FIG. 1). A shallow trench isolation (STI) 27 overlies a portion of the semiconductor substrate 26 and the n-well 25. An interlayer dielectric layer 29 overlies the gate 2A, over a portion of the STI 27, on and around the dielectric cap 23, and around the gate contact via 8, the via contact 4, the line 11, and the power rails 3A and 3B. As shown, the decoupling capacitor formed by the ferroelectric layer 21 and the dielectric layer 22 may have a depth d and a width w into the semiconductor substrate 26 and the n-well 25.

[0025] A dielectric layer 22 may be on the surface of the semiconductor substrate 26 and the n-well 25 within the gate cut trench 10. A ferroelectric layer 21 may be on the dielectric layer 22 and within a portion of the STI 27 within the gate cut trench 10. The top surface of the ferroelectric layer 21 is below the bottom surface of the gate 2A. A central portion of the gate cut trench 10 may be filled with metal 20. The metal 20 may be surrounded by the ferroelectric layer 21 (e.g., around the sides and bottom of the metal 20) and covered by a dielectric cap 23 that fills the remainder of the gate cut trench 10. The gate cut trench 10 abuts each end of the gate 2A. A decoupling capacitor is formed in the gate cut trench 10 etched to a width w into the gate 2A and in a portion of the ILD 29 that connects to the semiconductor substrate 26 and the n-well 25 to a depth d. In another embodiment, the semiconductor substrate 26 also includes a p-well underneath the fin 24 associated with the power rail 3A.

[0026] 2 extends from the top surface of gate 2A to a depth d into semiconductor substrate 26 and n-well 25. In one embodiment, gate cut trench 10 contacts the top surfaces of semiconductor substrate 25 and n-well 26 but does not extend into semiconductor substrate 26 and n-well 25. As will be described in more detail below, the depth d of gate cut trench 10 changes the capacitance of the decoupling capacitor (e.g., a deeper etched gate cut trench with a greater depth d can provide more capacitance).

[0027] Dielectric layer 22 is within gate cut trench 10 (e.g., overlies gate cut trench 10). Dielectric layer 22 is on the surface of semiconductor substrate 26 and a portion of n-well 25 within gate cut trench 10. As shown, dielectric layer 22 underlies a portion of ferroelectric layer 21. In various embodiments, dielectric layer 22 is a thin layer of silicon dioxide. In other embodiments, dielectric layer 22 is a dielectric material commonly used in gate stacks (e.g., silicon dioxide (SiO2), or a composite stack of hafnium dioxide (HfO2) and silicon oxide (SiOx), or aluminum oxide (Al2O5)).

[0028] As shown, ferroelectric layer 21 and dielectric layer 22 reside within a gate trench etched into substrate 26 and n-well 25. The selection of materials for metal 20, ferroelectric layer 21, and dielectric material, such as dielectric layer 22, determines, at least in part, the capacitance or capacitance density provided by the decoupling capacitor formed by ferroelectric layer 21 and dielectric layer 22. In various embodiments, ferroelectric layer 21 is hafnium zirconium oxide (HZO). In other embodiments, ferroelectric layer 21 is one of lead zirconate titanate (PZT), silicon-doped hafnium oxide (Si:HfO), or barium titanate. However, ferroelectric layer 21 is not limited to these materials and may be another suitable ferroelectric material.

[0029] Metal 20 resides within ferroelectric layer 21 and on its top surface. The top of metal 20 may be below the top of STI 27, below the bottom of gate 2A, and above the top surfaces of semiconductor substrate 26 and n-well 26. As shown, the top of metal 20 is approximately at the center of STI 27. In various embodiments, metal 20 is comprised of one or more metallic materials. As known to those skilled in the art, the work function of a metal depends on the metal's structure, such as the crystal planes at the interface between the work function metal and the dielectric or ferroelectric layer, and the metal's chemical composition. For example, a thin layer of work function metal (WFM) may reside on ferroelectric layer 21 with a bulk metal on the WFM. In this case, metal 20 may be comprised of tungsten metal and a WFM such as titanium nitride or doped aluminum. Metal 20 is not limited to these materials and may be, for example, a metal used in a replacement metal gate process.

[0030] In various embodiments, the selection of materials for the ferroelectric layer 21 and the dielectric layer 22, as well as the depth d and width w of the gate cut trench 10, each affect the capacitance of the decoupling capacitor. The depth d of the gate cut trench 10 during etching of the semiconductor substrate 26, including the gate 2A, the STI 27, and the n-well 25, can affect the capacitance provided by the ferroelectric layer 21 and the dielectric layer 22. In various embodiments, increasing the depth d of the gate cut trench 10 within the semiconductor substrate 26 and the n-well 25 increases the capacitance generated by the decoupling capacitor formed in the gate cut trench 10 (e.g., when the ferroelectric layer 21 and the dielectric layer 22 are composed of the same material). Figures 7 and 8 illustrate the effect of varying the depth d of the gate cut trench 10 on the capacitance density of the decoupling capacitor in the gate cut trench 10.

[0031] The dielectric cap 23 resides above the top surface of the metal 20 and the top surface of the ferroelectric layer 21, surrounding the vertical surfaces of the metal 20 in the gate cut trench 10. As shown, the STI 27 surrounds the bottom of one side of the dielectric cap 23, and the ILD 29 surrounds the outside of the top of the ferroelectric layer 21 and the top of the ferroelectric layer 21. In various embodiments, the gate 2A is adjacent to the top of the inside of the ferroelectric layer 21. As shown, in some embodiments, the ILD 29 is adjacent to the top of the outer (e.g., left and right) portions of the dielectric cap 23, and the gate 2A is adjacent to the top of the inner portion of the dielectric cap 23 (as shown in FIG. 1). In one embodiment (not shown), both sides of the dielectric cap 23 are surrounded by the gate 2A.

[0032] In various embodiments, semiconductor substrate 26 includes an n-well 25 in a portion of semiconductor substrate 26. Semiconductor substrate 26 (e.g., including n-well 25) may be composed of a silicon substrate, a Group IV semiconductor material, a Group III-V semiconductor material, a Group II-VI semiconductor material, or other known semiconductor materials used in semiconductor circuits. In various embodiments, substrate 26 is a wafer or a portion of a wafer. In some embodiments, semiconductor substrate 26 includes one or more of doped regions, undoped regions, or includes doped regions, undoped regions, stressed regions, or defect-rich regions. As illustrated, FIG. 2 includes n-well 25, which is a portion of semiconductor substrate 26 doped with n-type material using known semiconductor processes. In some embodiments, for a p-well (not shown), portions of semiconductor substrate 26 underlying left-most dielectric layer 22 and left-most fin 24, portions of STI 27, are doped. In various embodiments, one or more portions of semiconductor substrate 26 are doped with p-type dopants, n-type dopants, or undoped.

[0033] 3 is a cross-sectional view of a semiconductor structure 300 through section B-B' of the semiconductor circuit layout 100 of FIG. 1 in accordance with one embodiment of the present invention. Section B-B' bisects a region of the layout 100 of FIG. 1 overlying a portion of the active region 7. The semiconductor structure 300 shows the fin 24 of the active region, which connects to one of the power rails 3A or 3B through the source / drain contacts 6 and via contact 4. As shown, the decoupling capacitor formed by the ferroelectric layer 21 and the dielectric layer 22 is outside the active region 7 and is separated by a portion of the STI 27.

[0034] As shown, FIG. 3 also includes a gate cut trench 10 filled with a capacitor dielectric cap 23 at the top of the gate cut trench 10, above the ferroelectric layer 21 and above the metal 20 therein. A dielectric layer 22 is located below the ferroelectric layer 21 and on the surface of a portion of the semiconductor substrate 26 and the n-well 25. A fin 24 is located on the portion of the n-well 25 and the substrate 26, and a shallow trench isolation (STI) 27 is located on the portion of the n-well 25 and the substrate 26. An ILD 29 surrounds the line 11, surrounds portions of the power rails 3A and 3B, surrounds the via contact 4, surrounds portions of the active area 7, and surrounds portions of the dielectric cap 23. The power rails 3A and 3B can provide a supply voltage (e.g., VDD or ground) to the fin 24 in the active area 7 through the via contact 4 and the source / drain contacts 6.

[0035] In some embodiments, the active region 7 is part of a PFET, such as when the portion of the semiconductor substrate 26 below the active region 7 is an n-well that connects to the power rail 3B by source / drain contacts 6 and via contacts 4, as shown.

[0036] The two decoupling capacitors, comprised of the ferroelectric layer 21 and the dielectric layer 22, are essentially the same as the two decoupling capacitors described in detail above with reference to Figure 2. The dielectric cap 23 in Figure 3 is shorter than the dielectric cap 23 in Figure 2 because it is shown below the source / drain contacts 6.

[0037] FIG. 4 is a cross-sectional view of a semiconductor structure 400 through cross section C-C' of the semiconductor circuit layout 100 of FIG. 1 according to one embodiment of the present invention. Cross section C-C' of layout 100 is through one end of power rails 3A and 3B outside of the active area 7. As shown, FIG. 4 includes power rails 3A and 3B connecting to metal 20 within a portion of a decoupling capacitor formed by ferroelectric layer 21 and dielectric layer 22 through via contact 4 and trench contact via 5. The top of gate cut trench 10 is filled with trench contact via 5 on the top surface of metal 20 and on a portion of the top surface of ferroelectric layer 21. The bottom of gate cut trench 10 includes dielectric layer 22 covering the inner surfaces of semiconductor substrate 26 and n-well 25, and dielectric layer 22 is covered by ferroelectric layer 21 extending into gate cut trench 10 along a portion of STI 27. The metal 20 in the gate cut trench 10 is on a portion of the ferroelectric layer 21, with a vertical surface of the metal 20 abutting the ferroelectric layer 21 (e.g., the metal 20 is within the ferroelectric layer 21 and is covered by the trench contact via 5).

[0038] 4 also includes an STI 27 on the exposed portions of semiconductor substrate 26 and n-well 25, and an ILD 29 on STI 27 that surrounds trench contact via 5, via contact 4, power rails 3A and 3B, and a portion of line 11. Via contact 4 is stacked vertically with trench contact via 5 to connect one end of each of power rails 3A and 3B to metal 20 and a decoupling capacitor formed by ferroelectric layer 21 and dielectric layer 22.

[0039] Figure 5A is a cross-sectional view of a semiconductor structure 500A through section AA' of the inverter layout of Figure 1, according to one embodiment of the present invention. Figure 5A illustrates a second embodiment of the present invention.

[0040] As shown, FIG. 5A includes essentially the same elements (e.g., gate 2A, power rails 3A and 3B, via contact 4, line 11, metal 20, ferroelectric layer 21, dielectric layer 22, capacitor dielectric cap 23, fin 24, n-well 25, substrate 26, STI 27, gate contact via 8, and ILD 29) in essentially the same locations as those described in detail above with reference to FIG. 2, except that ferroelectric layer 21 extends to the level of the top surface of dielectric cap 23. In this case, the portion of ferroelectric layer 21 deposited on the top of gate cut trench 10 is not removed (e.g., by etching the top of ferroelectric layer 21), and ferroelectric layer 21 extends to the top surface of dielectric cap 23. As shown in FIG. 5A, ferroelectric layer 21 covers the vertical walls of gate cut trench 10 and the bottom of gate cut trench 10. The dielectric cap 23 is enveloped by the ferroelectric layer 21 (e.g., the dielectric cap 23 is in the vertical plane of the ferroelectric layer 21) rather than extending across the gate cut trench 10 from the gate 2A to the ILD 29 at the top of the gate cut trench 10. By eliminating one or more etching processes to remove the top of the ferroelectric layer 21 in the gate cut trench 10, the semiconductor structure 500A may be easier to manufacture, and the omitted etching processes may reduce yield loss. The semiconductor structure 500A may be formed using semiconductor manufacturing processes that are easier than the manufacturing processes used to form the semiconductor structure 200 of FIG. 2 .

[0041] 5B is a cross-sectional view of a semiconductor structure 500B through section B-B' of the semiconductor circuit layout of FIG. 1 according to one embodiment of the present invention. As shown, FIG. 5B includes essentially the same elements (e.g., power rails 3A and 3B, via contact 4, source / drain contacts 6, active region 7, lines 11, metal 20, ferroelectric layer 21, dielectric layer 22, capacitor dielectric cap 23, fin 24, n-well 25, substrate 26, STI 27, via contact 4, and ILD 29) in the same locations as those described in detail above with reference to FIG. 2, except that ferroelectric layer 21 extends to the level of the top surface of dielectric cap 23. In this case, the portion of ferroelectric layer 21 deposited on top of gate cut trench 10 is not removed (e.g., by etching the top of ferroelectric layer 21) as described above with reference to FIG. 5A. As shown, dielectric cap 23 is slightly smaller (e.g., has a smaller width). By eliminating one or more etching processes to remove the upper portion of the ferroelectric layer 21 in the gate cut trench 10, one or more etching processes can be eliminated and easier semiconductor fabrication processes can be used to form the semiconductor structures 500A, 500B.

[0042] 5C is a cross-sectional view of a semiconductor structure 500C through cross section C-C' of the semiconductor circuit layout of FIG. 1 according to one embodiment of the present invention. FIG. 5C illustrates electrical connections between each of power rails 3A and 3B and a single decoupling capacitor (e.g., ferroelectric layer 21 and dielectric layer 22) via trench contact via 5 and via contact 4. As shown, FIG. 5C includes essentially the same elements (e.g., power rails 3A and 3B, via contact 4, trench contact via 5 connecting metal 20 and via contact 4, line 11, ferroelectric layer 21, dielectric layer 22, semiconductor substrate 26 including n-well 25, STI 27, and ILD 29) in the same locations as those described in detail above with reference to FIG. 2, except that ferroelectric layer 21 extends to the level of the top surface of dielectric cap 23. In this case, as described above with reference to FIG. 5A , the portion of the ferroelectric layer 21 deposited on the top of the gate cut trench 10 is not removed (e.g., by etching the top of the ferroelectric layer 21). As shown, the dielectric cap 23 is slightly smaller (e.g., has a smaller width). By eliminating one or more etching processes to remove the top of the ferroelectric layer 21 in the gate cut trench 10, one or more etching processes can be eliminated and easier semiconductor fabrication processes can be used to form the semiconductor structures 500A, 500B, and 500C. FIG. 5C is essentially the same as FIG. 4 , except that the ferroelectric layer 21 extends around the dielectric cap 23 to contact the via contact 4.

[0043] Figure 6A is a cross-sectional view of a semiconductor structure 600A through section A-A' of the semiconductor circuit layout of Figure 1 according to one embodiment of the present invention. As shown, the material in the gate cut trench 10 can form a metal-ferroelectric-insulator-metal (MFIM) stack. Figure 6A is a third embodiment of the present invention.

[0044] As shown, Figure 6A is essentially the same as Figure 4, except that metal layer 66 covers the inner surfaces of semiconductor substrate 26 and n-well 25 within gate cut trench 10, and another dielectric material (e.g., dielectric material 62) can replace dielectric layer 22. As shown, Figure 6A includes essentially the same elements (e.g., gate 2A, power rails 3A and 3B, via contact 4, line 11, metal 20, ferroelectric layer 21, capacitor dielectric cap 23, fin 24, n-well 25, substrate 26, shallow trench isolation (STI) 27, gate contact via 8, and ILD 29) in the same locations as Figure 2, except that metal layer 66 replaces dielectric layer 22 on semiconductor substrate 26 and n-well 25, and a new dielectric material, dielectric material 62, is below ferroelectric layer 21 and above metal layer 66. As shown, the bottom of the gate cut trench 10 includes a metal layer 66 under the dielectric material 62 , a ferroelectric layer 21 , and a metal 20 within the ferroelectric layer 21 .

[0045] In various embodiments, metal layer 66 is one of titanium-nickel (TiN), titanium-aluminum-carbon (TiAlC), tungsten (W), tungsten-nickel (WN), or tantalum-nickel (TaN). Metal layer 66 is not limited to these metals and may be another material. The thickness of metal layer 66 may range from 3 nm to 10 nm, but is not limited to these thicknesses. As shown, the top surface of metal layer 66 is parallel to the top surfaces of semiconductor substrate 26 and n-well 25.

[0046] Depositing the metal layer 66 in the gate cut trench 10 prevents the formation of a silicon dioxide layer on the semiconductor substrate 26. The MFIM stack including the metal layer 66, which is a metal liner, allows a high-k material having a dielectric constant higher than 3.9 to be used as the dielectric material 62 without an intermediate SiO2 layer on the surface of the semiconductor substrate 26 or n-well 25 in the gate cut trench 10. Examples of materials for the dielectric material 62 can include, but are not limited to, aluminum oxides such as Al2O3, zirconium oxides such as ZrO2, titanium oxides such as TiO2, and tantalum oxides such as Ta2O5.

[0047] In various embodiments, dielectric material 62 is any non-silicon dioxide dielectric material. For example, dielectric material 62 may be one of Ta2O5 or TiO2 dielectric materials that exhibit a Qmax greater than that of silicon dioxide, where Qmax is the maximum charge that can be applied to the dielectric before breakdown. In some embodiments, dielectric material 62 is a high-k dielectric material. The thickness of dielectric material 62 may range from 3 nm to 10 nm, but is not limited to these thicknesses. As shown, the top surface of dielectric material 62 is parallel to the top surface of metal layer 66 and the top surface of semiconductor substrate 26, including n-well 25. Dielectric material 62 may be selected to provide a higher Qmax (e.g., by using a high-k dielectric material), thereby enabling a higher remanent polarization of the material of ferroelectric layer 21.

[0048] In various embodiments, the combination of metal layer 66 and dielectric layer 62 provides the ability to improve the electrical performance of a decoupling capacitor for the same depth d of gate cut trench 10 within semiconductor substrate 26 and n-well 25. An example of the improved electrical performance (e.g., improved capacitance density) provided by metal layer 66 and dielectric material 62 is shown and described below with reference to FIG. 9 . The addition of metal layer 66 and dielectric material 62 can improve the predicted capacitance density for a 20 nm gate cut trench depth to a predicted capacitance density that is two to three times higher. In some embodiments, n+ and / or p+ regions are implanted within the opening of gate cut trench 10 to improve the contact resistance from a well, such as n-well 25, to metal layer 66 as the bottom electrode.

[0049] FIG. 6B is a cross-sectional view of a semiconductor structure 600B through section B-B' of the semiconductor circuit layout of FIG. 1, according to one embodiment of the present invention. As shown, FIG. 6B includes power rails 3A and 3B, via contact 4, source / drain contact 6, active region 7, line 11, metal 20, metal layer 66, ferroelectric layer 21, dielectric material 62, capacitor dielectric cap 23, fin 24, n-well 25, substrate 26, shallow trench isolation (STI) 27, via contact 4, and interlayer dielectric material (ILD) 29. FIG. 6B is essentially the same as FIG. 3, except that metal layer 66 replaces dielectric layer 22 and dielectric material 62 has been added within metal layer 66 within the lower portion of gate cut trench 10. Metal layer 66 acts as a metal liner separating semiconductor substrate 26 and n-well 25 to prevent silicon dioxide from forming on semiconductor substrate 26 within gate cut trench 10. Semiconductor structure 600B shows the bottom of gate cut trench 10 with metal 20 in ferroelectric layer 21 and covered by dielectric cap 23, and dielectric material 62 below ferroelectric layer 21 overlying metal layer 66 in semiconductor substrate 26 and a portion of n-well 25.

[0050] FIG. 6C is a cross-sectional view of a semiconductor structure 600C through section A-A' of the semiconductor circuit layout of FIG. 1 according to one embodiment of the present invention. As shown, FIG. 6C includes power rails 3A and 3B, via contact 4, trench contact via 5 connecting metal layer 66 and via contact 4, line 11, ferroelectric layer 21, dielectric material 62, semiconductor substrate 26 including n-well 25, STI 27, and ILD 29. FIG. 6C is essentially the same as FIG. 4 except that metal layer 66 may be added within semiconductor substrate 26 as a liner and dielectric material 62 may be added over metal layer 66 at the bottom of gate cut trench 10. Metal layer 66 separates dielectric material 62 from semiconductor substrate 26 and n-well 25. As shown, metal layer 66 does not extend to trench contact via 5. A portion of the ferroelectric layer 21 separates the metal layer 66 and a trench contact via 5 that electrically connects to one of the power rails 3A or 3B through a via contact 4.

[0051] FIG. 7 is a graph showing the results of a TCAD analysis of a 4.4 eV work function metal (WFM) disposed on the ferroelectric layer 21 and a 4.9 eV work function metal disposed on the ferroelectric layer 21 in the absence of a gate cut trench, according to a second embodiment of the present invention. In various embodiments, the work function metal is metal 20 of FIGS. 2-4. Technology computer-aided design (TCAD) is a branch of electronic design automation that models semiconductor fabrication and semiconductor circuit operation. As shown in FIGS. 7-9, the TCAD analysis predicts the capacitance density for a particular Vdd power rail voltage, shown as a capacitance versus voltage (CV) curve. The TCAD analysis assumes a 4 nm thickness for the ferroelectric layer 21 and a 1 nm thickness for the dielectric layer 22 (e.g., silicon dioxide). The TCAD analysis predicts a capacitance density of approximately 2.85 μC / cm 2 and a ferroelectric remanent polarization of approximately 3.45 μC / cm 2The dielectric Qmax is used, where Qmax is the maximum amount of charge that can be applied to the dielectric before it breaks down. The single lower line is a baseline prediction for a metal-oxide-semiconductor (MOS) decoupling capacitor containing a 4.4 eV work function metal, a 1 nm silicon dioxide dielectric, and the same geometry as the ferroelectric / dielectric capacitor being simulated as well.

[0052] Typically, 4.4 eV WFM is generally associated with NFET operation, and 4.9 eV WFM is generally associated with PFET operation. In Figure 7, the analysis shows that the depth d of the gate cut trench 10 is zero and the remanent polarization is 2.85 μC / cm 2 (e.g., smaller than silicon dioxide), with a Qmax of approximately 3.45 μC / cm 2 Assume that:

[0053] Each of lines 1a, 1b, 1c, and 1d for a 4.4 eV work function metal on a ferroelectric material (e.g., ferroelectric layer 21) represents a predicted capacitance density associated with a particular possible negative capacitance gradient, which may be associated with a particular material choice (e.g., for ferroelectric layer 21) or different material thicknesses forming the decoupling capacitors shown, for example, in Figures 2, 3, and 4. Each of lines 1a, 1b, 1c, and 1d represents a predicted capacitance density in square microns (µm 2 The graph represents femtofarads (fF) per Ω vs. voltage (V), where voltage is the VDD power rail voltage (e.g., power rail 3A in Figure 1). The peaks of the curves for lines 1a, 1b, 1c, and 1d represent VDD power rail voltages of 0.3 to 0.4 V. The arrows shown on lines 1a, 1b, 1c, and 1d indicate increasing capacitance matching. Moving backward from line 1d to 1a, the negative capacitance gradient of the ferroelectric decreases to achieve an absolute gradient closer to the positive capacitance gradient of the continuous dielectric, with line 1a representing the closest match between these two gradients. The increased capacitance matching increases dQ / dV, which increases the total capacitance of the continuous ferroelectric / dielectric stack.

[0054] Similarly, lines 2a, 2b, 2c, and 2d for a 4.9 eV work function metal on a ferroelectric material (e.g., ferroelectric layer 21) each represent predicted capacitance densities associated with particular possible negative capacitance gradients, which may be associated with particular material choices (e.g., for ferroelectric layer 21) or different material thicknesses forming the decoupling capacitors shown, for example, in Figures 2, 3, and 4. The peaks of the curves for lines 2a, 2b, 2c, and 2d represent voltages of 0.8 to 0.9 V on the VDD power rail.

[0055] FIG. 8 is a graph showing the results of a TCAD analysis of a 4.4 eV work function metal disposed on a ferroelectric material and a 4.9 eV work function metal disposed on a ferroelectric material when the gate cut trench 10 is 20 nm deep, according to a second embodiment of the present invention. FIG. 8 is similar to FIG. 7 , except that the depth d of the gate cut trench 10 is increased from 0 nm to 20 nm. As shown in FIG. 8 , the additional depth of the gate cut trench 10 increases the peak capacitance density of each of lines 3a, 3b, 3c, and 3d for 4.4 eV WFM and lines 4a, 4b, 4c, and 4d for 4.9 eV WFM by more than double the predicted peak capacitance density of FIG. 7 for the same material. According to the TCAD analysis shown in FIG. 8 , a significant improvement in capacitance density can be achieved by increasing the depth of the gate cut trench in the semiconductor substrate to 20 nm.

[0056] FIG. 9 is a graph showing the results of a TCAD analysis of a 4.4 eV work function metal disposed on a ferroelectric material and a 4.9 eV work function metal disposed on a ferroelectric material when the gate cut trench 10 is 20 nm deep and no silicon dioxide layer is adjacent to the semiconductor substrate, according to a third embodiment of the present invention. FIG. 9 relates to an electrical analysis of the structure shown in FIGS. 6A, 6B, and 6C, which includes an MFIM stack in which a metal layer 66 is deposited in the gate cut trench before the dielectric material 62 and ferroelectric layer 21. In this case, the dielectric material 62 does not contact the semiconductor substrate, so no silicon dioxide layer is formed on the semiconductor substrate. Additionally, when the metal layer 66 is deposited on the semiconductor substrate 26, a dielectric material with a higher dielectric constant can be used for the dielectric material 62 (e.g., TaO or TiO), although the dielectric material 62 is not limited to these or other materials with higher dielectric constants.

[0057] Each of the lines 5a, 5b, 5c, and 5d for 4.4 eV WFM represents the predicted capacitance density associated with a particular possible remnant polarization of the ferroelectric layer 21. The particular remnant polarization may be associated with a particular material choice (e.g., for the ferroelectric layer 21) or different material thicknesses forming the decoupling capacitors shown in Figures 2, 3, and 4. Each curve exhibits the same negative capacitance slope. The remnant polarization increases from line 5d to line 5a, and the peak capacitance increases accordingly. A higher remnant polarization of the ferroelectric layer 21 requires a larger Qmax of the dielectric material 62, which typically corresponds to a higher k dielectric layer and the absence of a silicon dioxide interlayer.

[0058] Similarly, lines 6a, 6b, 6c, and 6d for 4.9 eV WFM represent predicted capacitance densities associated with particular remnant polarizations of the ferroelectric layer 21, which may be associated with particular material choices (e.g., for the ferroelectric layer 21) or different material thicknesses for the decoupling capacitor. The depth d of the gate cut trench 10 in FIG. 9 is the same as the gate cut depth in FIG. 8 (e.g., 20 nm). It is important to note that the MFIM stack of materials (e.g., metal 20, ferroelectric layer 21, dielectric material 62, and metal layer 66) within the gate cut trench 10, without SiO2, provides significantly higher maximum peak capacitance densities for each of the sets of lines 5a, 5b, 5c, 5d and 6a, 6b, 6c, 6d compared to the corresponding sets of lines in FIG. 8 (e.g., compared to lines 3a, 3b, 3c, 3d and lines 4a, 4b, 4c, 4d, respectively). For example, as shown in FIG. 9, the peak capacitance density associated with line 6a is more than twice the peak capacitance density of line 4a in FIG.

[0059] FIG. 10 is a graph illustrating peak capacitance versus remanent polarization for various materials and various gate cut trench depths in accordance with a second embodiment of the present invention. As shown, FIG. 10 plots the predicted peak capacitance (fF / μm) at various gate cut trench depths (e.g., ranging from 0 nm to 40 nm). 2 ) and various ferroelectric remanent polarization (Pr) (μC / cm 2 ) and (Qmax). Also shown in Figure 10 are the dielectric polarization limits (Qmax) for several materials, such as SiO2, Ta2O5, and TiO2. It is important to note that Figure 10 shows the theoretical potential to increase the peak capacitance density of a material by increasing the depth of the gate cut trench 10 or by using a material that can provide a higher Qmax.

[0060] Comparing the peak capacitance densities shown in Figures 7, 8, 9, and 10, it is readily determined that the peak capacitance density in Figure 7, which has a 0 nm gate cut trench, is significantly improved in Figures 8-10, which have deeper gate cut trenches (e.g., larger d), and that adding a metal layer or liner under the dielectric layer (e.g., metal layer 66 under dielectric material 62) can further improve the peak capacitance density and prevent SiO2 formation on the semiconductor material forming gate cut trench 10.

[0061] Furthermore, looking at FIG. 10, in some cases, when a metal liner (e.g., metal layer 66) is present, a different dielectric material, such as TiO2, can accommodate a higher Pr and theoretically provide a much higher peak capacitance density in a 40 nm deep gate cut trench 10 than a dielectric material, such as SiO2.

[0062] As shown in Figures 7-10, embodiments of the present invention provide the ability to significantly improve peak capacitance density using decoupling capacitors that include various semiconductor structures described with reference to Figures 1-6C. Embodiments of the present invention illustrate several design tradeoffs and material choices that can impact and improve the peak capacitance density provided to the power rail by the decoupling capacitor. Increasing the capacitance provided to the power rail can reduce power rail noise, thereby improving device performance.

[0063] Figures 11-16 illustrate one method of forming the semiconductor circuit shown in layout 100 of Figure 1. In particular, the method described with respect to Figures 11-16 pertains to the semiconductor structure 400 shown in Figure 4, in which power rails 3A and 3B electrically connect to decoupling capacitors formed by ferroelectric layer 21 and dielectric layer 22 in gate cut trench 10.

[0064] Figure 11 is a cross-sectional view through CC' of Figure 1, forming a semiconductor structure 1100 after deposition of a layer of ILD 29, according to one embodiment of the present invention. As shown, Figure 11 includes ILD 29 over semiconductor substrate 26 and STI 27 over n-well 25 in semiconductor substrate 26. Semiconductor structure 1100 is formed by known semiconductor processes, including n-type doping of a portion of semiconductor substrate 26 and deposition of STI 27 over semiconductor substrate 26 and n-well 25. A deposition method, such as atomic layer deposition (ALD) or CVD, deposits a layer of ILD 29 over STI 27 to form semiconductor structure 1100. Optionally, chemical-mechanical polishing (CMP) of ILD 29 may be performed.

[0065] FIG. 12 is a cross-sectional view through CC' of FIG. 1 forming a semiconductor structure 1200 after etching a portion of the ILD 29, a portion of the STI 27, and the gate cut trench 10 through the top of the semiconductor substrate 26 and n-well 25, in accordance with one embodiment of the present invention.

[0066] 1 , one or more photolithography processes using the gate cut mask 1 shown in FIG. 1 and a known gate cut etching process are used to selectively etch the ILD 29, a portion of the STI 27, and the upper portion of the semiconductor substrate 26 and n-well 25 to form the gate cut trench 10. For example, one or more reactive ion etches (RIE) are used to etch the semiconductor substrate 26 and the portion of the n-well 25 to the depth d and width w shown. For example, one or more RIE etches using the gate cut mask 1 can be used to etch the gate trench 10 through the ILD 29, the STI 27, the semiconductor substrate 26, and the upper portion of the n-well 25. As shown in FIG. 10 , the depth d of the gate cut trench 10 in the semiconductor substrate 26 and n-well 25 affects the resulting capacitance density.

[0067] As shown in FIG. 12 , the selective RIE etch can remove two defined portions of ILD 29, two portions of STI 27 below the removed portions of ILD 29, and portions of semiconductor substrate 26 and n-well 25 below the removed portions of ILD 29. Conventional gate cut trenches typically use STI 27 as an etch stop (i.e., conventional gate cut trenches are not etched into portions of semiconductor substrate 26 or n-well 25). In embodiments of the present invention, gate cut trench 10 is etched to a deeper height than conventional gate cut trenches. While a typical gate cut trench extends a gate, such as gate 2A, to above or on top of STI 27, in various embodiments of the present invention, the etching process forming gate cut trench 10 removes portions of semiconductor substrate 26 and n-well 25, as well as portions of STI 27 and ILD 29, as defined by etch mask 1 of FIG. 1 .

[0068] 13 is a cross-sectional view through A-A' of FIG. 1 forming a semiconductor structure 1300 after formation of a dielectric layer 22 over the semiconductor substrate 26 and n-well 25 in the gate cut trench 10 in accordance with one embodiment of the present invention. As shown, the dielectric layer 22 covers the exposed surfaces of the semiconductor substrate 26 and n-well 25 in the gate cut trench 10. The dielectric layer 22 is deposited or grown by known semiconductor fabrication processes such as, for example, oxidation or atomic layer deposition (ALD). The thickness of the dielectric layer 22 may range from 1 nm to 4 nm, but is not limited to these thicknesses.

[0069] 14 is a cross-sectional view through A-A' of FIG. 1 after deposition and etching of ferroelectric layer 21 and metal 20 within gate cut trench 10, forming semiconductor structure 1400, in accordance with one embodiment of the present invention. Ferroelectric layer 21 is deposited within gate cut trench 10 on the exposed surfaces of dielectric layer 22, STI 27, and gate 2A by known semiconductor fabrication processes, such as atomic layer deposition (ALD) or another conformal deposition process. The thickness of ferroelectric layer 21 may range from 2 nm to 5 nm, but is not limited to these thicknesses.

[0070] Metal 20 may be deposited on ferroelectric layer 21 within gate cut trench 10. For example, metal 20 may be deposited by one or more known deposition processes (e.g., ALD, CVD, etc.). As previously mentioned, in some embodiments, metal 20 is comprised of thin layers of a work function metal and a bulk metal (e.g., titanium nitride and tungsten). In this case, two deposition processes may be performed.

[0071] After the deposition of the metal 20, another selective etching process using, for example, RIE or wet etching, is performed to selectively remove the ferroelectric layer 21 and portions of the metal 20 above the gate cut trench 10. As shown in Figure 14, after this etching process, the top surfaces of the ferroelectric layer 21 and the metal 20 are below the bottom surface of the STI 27 and above the top surfaces of the semiconductor substrate 26 and the n-well 25. For example, after etching, the top surfaces of the ferroelectric layer 21 and the metal 20 may be approximately halfway between the bottom surface of the STI 27 and the top surfaces of the semiconductor substrate 26 and the n-well 25.

[0072] FIG. 15 is a cross-sectional view through A-A′ of FIG. 1 , forming a semiconductor structure 1500 after depositing a contact material on the semiconductor structure 1500 and planarizing the top surface of the semiconductor structure 1500, according to one embodiment of the present invention. Using a known deposition process, such as ALD or CVD, the gate cut trench 10 is first filled with a dielectric cap 23 that extends the entire length of the gate cut trench 10. A patterning step is then performed to form a contact via opening through the dielectric cap 23 and expose the top surface of the metal 20. Using a known deposition process, such as ALD or CVD, a layer of contact material (e.g., tungsten, titanium, etc.) can be deposited on the semiconductor structure 1500 (e.g., on the ILD 29, STI 27, ferroelectric layer 21, and exposed surfaces of the metal 20 in the gate cut trench 10). The metal deposit completely fills the gate cut trench 10 and covers the top surface of the semiconductor structure 1500.

[0073] After depositing the layer of contact material for the trench contact via 5 on the semiconductor structure 1500, a planarization process such as chemical mechanical polishing (CMP) can be performed. The CMP can remove the contact material from the top surface of the ILD 29, removing the upper portion of the ILD 29. The remaining contact material in the gate cut trench 10 forms the trench contact via 5.

[0074] FIG. 16 is a cross-sectional view through C-C′ of FIG. 1 , forming a semiconductor structure 1600 after formation of via contact 4 and power rails 3A and 3B, according to one embodiment of the present invention. Another layer of ILD 29 can be deposited on semiconductor structure 1600 using known contact and via formation processes. Selective etching of ILD 29 using photolithography and conventional etching processes, such as RIE, wet chemical etching, or other etching processes, removes portions of ILD 29 that reside above trench contact via 5. A contact material is deposited on semiconductor structure 1600, filling the area or via hole formed by removing the portions of ILD 29, to form via contact 4. CMP of semiconductor structure 1600 removes the contact material from the top surface of ILD 29 to complete via contact 4.

[0075] Using back-end-of-line (BEOL) processes, power rails 3A and 3B can be formed on via contact 4. For example, another deposition of ILD 29 can be performed on top of via contact 4 and ILD 29. Another CMP can be performed to planarize the top surface of the deposited ILD 29. Deposition of a first metal layer (M1) can be performed using known BEOL deposition processes, followed by selective etching of M1 to form power rails 3A and 3B.

[0076] As shown in semiconductor structure 1600, a decoupling capacitor formed in gate cut trench 10 by dielectric layer 22 and ferroelectric layer 21 connects to one end of each of power rails 3A and 3B through metal 20, trench contact via 5, and via contact 4. Power rails 3A and 3B can each be considered to include via contact 4, trench contact via 5, and metal 20. In some embodiments, power rail 3B over n-well 25 can be the top electrode of a PFET, and n-well 25 can be the bottom electrode of a PFET. In other embodiments, power rail 3B is not limited to a PFET (e.g., n-well 25 can be a p-well forming an NFET).

[0077] As known to those skilled in the art, some variations or different orders of the method steps associated with Figures 11-16 are possible to achieve semiconductor structure 1600 (e.g., differences in when the ILD layer is formed and when the etching is performed, etc.). Additionally, as known to those skilled in the art, processes similar to those described to form semiconductor structure 1600 can be used to form semiconductor structures 200, 300, 500A, 500B, and 500C. Additionally, as known to those skilled in the art, semiconductor structures 600A, 600B, and 600C can be formed with some new materials (e.g., metal layer 66 and dielectric material 62) and slight modifications to the processes described with respect to Figures 11-16.

[0078] The description of various embodiments of the present disclosure is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, their practical applications or technical improvements over technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A semiconductor structure comprising: a first power rail; one or more vertically stacked contact vias connecting the first power rail to a portion of a first decoupling capacitor, the first decoupling capacitor being in a first portion of a semiconductor substrate within a first gate cut trench; and 1. A semiconductor structure comprising:

2. 10. The semiconductor structure of claim 1 wherein said first decoupling capacitor in said first portion of said semiconductor substrate within said first gate cut trench comprises a first dielectric layer in said first portion of said semiconductor substrate within said first gate cut trench.

3. 3. The semiconductor structure of claim 2 wherein said first decoupling capacitor in said first portion of said semiconductor substrate within said first gate cut trench comprises a layer of ferroelectric material on said first dielectric layer in said first portion of said semiconductor substrate within said first gate cut trench and on a portion of an isolation trench.

4. 4. The semiconductor structure of claim 3 wherein said first decoupling capacitor comprises said ferroelectric material and said first dielectric layer.

5. 2. The semiconductor structure of claim 1 wherein said first decoupling capacitor in said first portion of the semiconductor substrate within said first gate cut trench underlies and is parallel to said first power rail.

6. 4. The semiconductor structure of claim 3 wherein a metal electrically contacts said ferroelectric layer.

7. 7. The semiconductor structure of claim 6 wherein said one or more vertically stacked contact vias connecting said first power rail connect to a top surface of said metal that electrically contacts said ferroelectric layer.

8. 7. The semiconductor structure of claim 6 wherein said metal in electrical contact with said ferroelectric layer electrically connects said first decoupling capacitor in said first portion of said semiconductor substrate within said first gate cut trench to said first power rail.

9. 7. The semiconductor structure of claim 6 wherein a top surface of said metal in electrical contact with said ferroelectric material is above a top surface of said semiconductor substrate and below a top surface of an isolation trench overlying said semiconductor substrate.

10. 4. The semiconductor structure of claim 3 wherein said dielectric layer is a layer of silicon dioxide.

11. a second power rail; and one or more vertically stacked contact vias connecting the second power rail to a portion of a second decoupling capacitor, the second decoupling capacitor being in a second portion of the semiconductor substrate within a second gate cut trench, the second gate cut trench passing through an isolation trench in one or more portions of the semiconductor substrate and passing through a gate overlying the isolation trench in the one or more portions of the semiconductor substrate, the second isolation trench extending into the second portion of the semiconductor substrate; one or more active device regions in a third portion of the semiconductor substrate adjacent to the first portion of the semiconductor substrate and in a fourth portion of the semiconductor substrate adjacent to the second portion of the semiconductor substrate, wherein the second portion of the semiconductor substrate and the fourth portion of the semiconductor substrate adjacent to the second portion of the semiconductor substrate are doped with one of an n-type dopant or a p-type dopant; 10. The semiconductor structure of claim 1 further comprising:

12. 1. A semiconductor structure comprising: a first gate cut trench in a first portion of the semiconductor substrate below the first power rail; a first metal layer in the first portion of the semiconductor substrate; a first dielectric layer on the first metal layer in the first portion of the semiconductor substrate; a ferroelectric layer on the first dielectric layer on the first metal layer in the first portion of the semiconductor substrate, on a bottom of an isolation trench above the semiconductor substrate, and within a portion of the first gate cut trench; 1. A semiconductor structure comprising:

13. a second metal in electrical contact with the ferroelectric layer; a third metal material on a first portion of the second metal in electrical contact with the ferroelectric layer, the third metal material underlying the first power rail; a second dielectric material on a second portion of the second metal in electrical contact with the ferroelectric layer, the second dielectric material covering the exposed portion of the second metal in electrical contact with the ferroelectric layer and covering the exposed portion of the ferroelectric layer; the third metal material on the first portion of the second metal in electrical contact with the ferroelectric layer, and an electrical connection to the power rail; 13. The semiconductor structure of claim 12 further comprising:

14. 13. The semiconductor structure of claim 12, wherein said first metal layer in said first portion of said semiconductor substrate, said dielectric layer on said first metal layer, and said ferroelectric layer on said dielectric layer on said first metal layer in said first portion of said semiconductor substrate extending in said first gate cut trench above said first portion of said semiconductor substrate form a decoupling capacitor.

15. 14. The semiconductor structure of claim 13, wherein said first metal layer in said first portion of said semiconductor substrate, said dielectric layer on said first metal layer, said ferroelectric layer, and said second metal in electrical contact with said ferroelectric layer form a metal-ferroelectric-insulator-metal stack.

16. 13. The semiconductor structure of claim 12, wherein a top of said first gate cut trench in said first portion of said semiconductor substrate is flush with a top of a gate, and one or more portions of said gate comprise one or more active device regions in one or more second portions of said semiconductor substrate.

17. 17. The semiconductor structure of claim 16, wherein at least a portion of the one or more second portions of the semiconductor substrate underlying the one or more active device regions are doped with at least one of an n-type dopant or a p-type dopant.

18. a second gate cut trench in a second portion of the semiconductor substrate below the second power rail; a first metal layer on the second portion of the semiconductor substrate; a dielectric layer on the first metal layer in the second portion of the semiconductor substrate; a ferroelectric layer on the dielectric layer on the first metal layer in the second portion of the semiconductor substrate and on a bottom of an isolation trench within a portion of the second gate cut trench, the isolation trench being above the semiconductor substrate adjacent to the second gate cut trench; 13. The semiconductor structure of claim 12 further comprising:

19. 1. A semiconductor structure comprising: Power rail and a gate cut trench below the power rail; a dielectric layer on a portion of the semiconductor substrate within the gate cut trench; a ferroelectric layer on the dielectric layer and on the vertical surfaces of the gate cut trench above the semiconductor substrate; a metal in electrical contact with the ferroelectric layer; 1. A semiconductor structure comprising:

20. 20. The semiconductor structure of claim 19 further comprising an electrical connection between said metal electrically contacting said ferroelectric layer and said power rail, said connection comprising one or more contact vias between said metal electrically contacting said ferroelectric layer and said power rail.

21. 20. The semiconductor structure of claim 19, wherein said gate cut trench under said power rail extends through a gate, through an isolation trench on said semiconductor substrate, through a top portion of said semiconductor substrate, and beneath an interlayer dielectric material.

22. 1. A method for forming a decoupling capacitor in a semiconductor substrate, comprising: performing one or more first etching processes to remove a portion of the first interlayer dielectric overlying an isolation trench on the semiconductor substrate, to remove a portion of the isolation trench underlying the removed first interlayer dielectric, and to remove an upper portion of the semiconductor substrate underlying the removed portion of the isolation trench to form a gate cut trench; depositing a layer of dielectric material over a remainder of the semiconductor substrate below the removed isolation trench forming the gate cut trench; depositing a layer of ferroelectric material over the dielectric material and over a remaining portion of the isolation trench above the semiconductor substrate; depositing a first metal on the ferroelectric layer; A method comprising:

23. etching an upper portion of the ferroelectric layer and an upper portion of the first metal on the ferroelectric layer, wherein a surface of the ferroelectric layer and a surface of the first metal are above the semiconductor substrate and below an upper surface of the isolation trench; depositing a dielectric cap over the second metal layer and the first interlayer dielectric material; performing a first chemical mechanical polishing to remove a portion of the dielectric cap on the first interlayer dielectric material; performing one or more second etching processes to remove at least a portion of the dielectric cap on the first metal to expose a portion of the first metal and form a contact via opening; depositing the second metal layer in the contact via opening, on the exposed portion of the first metal on the ferroelectric layer, and on the first inter-layer dielectric material; performing a second chemical mechanical polishing to remove a portion of the second metal layer over the first interlayer dielectric material; depositing a layer of a second interlayer dielectric material over the first interlayer dielectric material and a remaining portion of the second metal layer; selectively etching a portion of the second interlayer dielectric material; depositing a third metal layer over the second interlayer dielectric material and the second metal layer; removing the third metal layer overlying the second interlayer dielectric material to form a via contact; depositing a fourth metal layer; etching the fourth metal layer to form a power rail over each of the via contacts; 23. The method of claim 22, further comprising:

24. A device circuit, at least one power rail; a gate cut trench under each of the at least one power rail extending into a portion of a semiconductor substrate, the gate cut trench under one of the at least one power rail extending into a doped region of the semiconductor substrate forming a well; an insulating layer on the portion of the semiconductor substrate; the insulating layer on the portion of the semiconductor substrate and a ferroelectric layer on the side of the bottom of the gate cut trench; A device circuit comprising:

25. a first metal layer on the ferroelectric layer; one or more vertically stacked contacts connecting a first metal layer to the at least one power rail, the insulating layer and the ferroelectric layer forming a decoupling capacitor in the gate cut trench beneath each of the at least one power rail; a bottom metal electrode in direct contact with the doped region of the semiconductor substrate and the bottom surface of the insulating layer; a top metal electrode electrically connected to the ferroelectric layer and the power rail; 25. The device circuit of claim 24, further comprising:

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