Field effect transistor manufacturing method and semiconductor device

Abstract

To provide a method for manufacturing a plurality of FETs with desired characteristics by a coating method.SOLUTION: A method for manufacturing a plurality of field-effect transistors on a surface of a substrate, comprises a step of inkjet coating of a semiconductor material, the inkjet coating is performed while moving the inkjet head with respect to the substrate and changing the number of droplets and / or a droplet spacing according to a predetermined condition, for each point on the substrate where the field-effect transistor is to be formed.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a field effect transistor and a semiconductor device. [Background technology]

[0002] In recent years, field effect transistors (FETs) using organic semiconductors and / or carbon materials for the semiconductor layer have been actively studied. These materials can be handled in solution, so a wet film formation method can be used to coat or print a solution containing the semiconductor material. The wet film formation method can avoid high-temperature processes, making it possible to manufacture devices on plastic substrates at low temperatures and at low cost. In addition, the wet film formation method is expected to have higher material utilization efficiency and less environmental impact than the conventional vacuum film formation process using photolithography, because the film formation and patterning processes can be performed simultaneously.

[0003] On the other hand, when FETs constituting displays and circuits have characteristic variations (e.g., variation in drive current value), it becomes difficult to realize stable circuit operation according to design specifications. For this reason, for example, in a technology for forming a semiconductor layer by a coating method, a method has been considered in which, after forming a plurality of structures including one or more of a gate electrode, a gate insulating layer, a source electrode, and a drain electrode, physical quantities such as the width of the one or more electrodes and the thickness of the gate insulating layer are measured, and the coating amount of the semiconductor material to be applied to the structures is adjusted based on the measured physical quantities (see, for example, Patent Document 1). This method reduces characteristic variations due to formation variations such as the width and length of the channel and the thickness of the insulating layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2020 / 080109 Summary of the Invention [Problem to be solved by the invention]

[0005] FETs that make up displays and circuits are required to exhibit certain characteristics (for example, drive current value) according to their role. Even FETs of the same size and shape have different characteristics depending on the amount and density of the semiconductor material applied.

[0006] In order to achieve the desired characteristics for each FET, it is conceivable to adjust the amount of semiconductor material applied for each FET by applying the method described in Patent Document 1. However, with the method described in Patent Document 1, increasing the amount of application simply results in larger droplets, and depending on the shape of the structure, the semiconductor material may overlap adjacent structures, making it difficult to adjust the amount properly.

[0007] In view of the above problems, an object of the present invention is to provide a small-sized semiconductor device by manufacturing a plurality of FETs having desired characteristics by a coating method. [Means for solving the problem]

[0008] The present invention is a method for manufacturing a plurality of field effect transistors on a surface of a substrate, comprising a step of inkjet coating a semiconductor material, in which the inkjet coating is performed while moving an inkjet head relative to the substrate, and varying the number of droplets and / or the droplet spacing in accordance with predetermined conditions for each location on the substrate where a field effect transistor is to be formed. Effect of the Invention

[0009] According to the present invention, it is possible to manufacture a plurality of FETs having desired characteristics on a substrate. In particular, even if the substrate has an area where the FETs are densely packed and the distance between the semiconductor layers is narrow, it is possible to manufacture FETs having desired characteristics. Furthermore, the manufacturing method of the present invention makes it possible to obtain a semiconductor device having a small size. [Brief description of the drawings]

[0010] [Figure 1] Schematic cross-sectional view showing an example of a FET manufacturing method [Diagram 2] FIG. 1 is a schematic diagram showing an outline of a method for manufacturing a FET according to a first embodiment of the present invention; [Diagram 3] Schematic diagram showing an example of inkjet coating of semiconductor material onto a channel region [Figure 4] Schematic diagram showing different coating conditions of semiconductor material on structures with the same size channel region [Diagram 5] FIG. 1 is a schematic diagram showing an example of the bottom surface of an inkjet head having a plurality of nozzles. [Figure 6] Schematic diagram showing the difference in the state of semiconductor material application to structures with different channel region sizes [Figure 7] Schematic cross-sectional view of the dashed line XY in FIG. [Figure 8] Schematic diagram showing an example of a structure in which source electrodes and drain electrodes are arranged alternately. [Figure 9] A schematic plan view and a schematic cross-sectional view of a FET to show the object of measurement of the physical quantity [Figure 10] 1 is a schematic plan view showing a part of a semiconductor device in which a plurality of FETs are arranged at equal intervals in both the X direction and the Y direction. [Figure 11] 1 is a schematic plan view showing a part of a semiconductor device in which a plurality of FETs are arranged at equal intervals in both the X and Y directions. [Figure 12] A schematic plan view showing the relationship between the center positions of rectangles inscribed by the regions of semiconductor material of a transistor of interest and an adjacent transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments of the present invention will be described in detail. Note that the present invention is not limited to the following embodiments, and various modifications are possible within the scope of the invention as long as the object of the invention can be achieved and the gist of the invention is not deviated from.

[0012] (FET manufacturing method using inkjet coating method) 1 is a schematic cross-sectional view showing an example of a method for manufacturing a FET in which a semiconductor layer is formed by an inkjet coating method. First, (a) a lower conductive film 2 is formed on a substrate 1. Examples of a method for forming the lower conductive film 2 include a resistance heating deposition method, an electron beam method, a sputtering method, a plating method, and a CVD method. Examples of a method for forming the lower conductive film 2 include a method in which a paste containing a conductor and a photosensitive organic component is applied onto a substrate by a known coating method such as an inkjet method, a printing method, an ion plating method, a blade coating method, a slit die coating method, a screen printing method, a bar coater method, a casting method, a print transfer method, and a dip and pull-up method, and then the coating film is dried to remove the solvent.

[0013] As the material for the lower conductive film 2, silver, copper and gold are preferable from the viewpoint of conductivity, and silver is more preferable from the viewpoint of cost and stability.

[0014] Next, (b) the lower conductive film 2 is patterned to form a gate electrode 3. At this time, although not shown, a lower wiring for connecting to other circuits or an antenna can also be formed. As a patterning method, patterning by known photolithography is preferable. If the lower conductive film 2 is not photosensitive, known patterning using a photoresist can be used. If the lower conductive film 2 is formed by applying a paste containing a conductor and a photosensitive organic component onto a substrate, the photosensitive conductive film can be photolithographically processed. In this way, a gate electrode 3, which is a conductive pattern, is formed on the substrate 1.

[0015] Next, (c) a gate insulating layer 4 is formed on the gate electrode 3. The method for producing the gate insulating layer 4 is not particularly limited, but an example thereof includes a method in which a raw material composition is applied onto a substrate on which the gate electrode 3 is formed, and the coating film obtained by drying the composition is heat-treated as necessary. Examples of the application method include known application methods such as a blade coating method, a slit die coating method, a screen printing method, a bar coater method, a mold method, a print transfer method, a dipping and pulling method, and an inkjet method.

[0016] At this time, although not shown in the figure, the gate insulating layer 4 is removed to form a contact hole in the portion connecting the lower wiring and the upper wiring described later. If the gate insulating layer 4 is obtained using a paste containing a photosensitive organic component in the process (c), the contact hole can be formed by patterning using photolithography.

[0017] Next, (d) droplets of semiconductor material 5 are deposited by inkjet coating so as to cover the channel region on the gate insulating layer 4. The channel region refers to the range in which the network formed by the semiconductor material connects the source electrode and the drain electrode. The distance between the source electrode and the drain electrode is the length in the direction in which the carriers move, and is called the channel length. Meanwhile, the length between the source electrode and the drain electrode in the direction perpendicular to the channel length is called the channel width.

[0018] Next, (e) the semiconductor material 5 is dried to form the semiconductor layer 6. Examples of the drying method include known drying methods such as a hot air oven, a hot plate, infrared rays, and vacuum drying. In this manner, the semiconductor layer 6 is formed on the gate insulating layer 4.

[0019] Next, (f) an upper conductive film 7 is formed on the gate insulating layer 4. The upper conductive film 7 can be formed by the same method as the method for forming the lower conductive film 2. However, from the viewpoint of enabling pattern processing of electrodes by photolithography and further improving productivity, a method in which a paste containing a conductor and a photosensitive organic component is applied onto a substrate, and then the applied film is dried to remove the solvent is preferred.

[0020] Finally, (g) the upper conductive film 7 is patterned to form a source electrode 8 and a drain electrode 9. At this time, although not shown, upper wiring for connection to other circuits or an antenna can also be formed.

[0021] 1 is a bottom-gate FET, but may be a top-gate FET, in which case the FET can be manufactured by appropriately changing the order of steps (a) to (g).

[0022] In the case of a top-gate type and top-contact type FET, steps (d) and (e) are performed in a state where the gate electrode, source electrode, and drain electrode are not yet formed. Therefore, if the substrate expands or contracts due to the influence of heat or the like applied to the substrate during the subsequent steps (a) to (c), (f), and (g), the position of the semiconductor layer also expands or contracts in response to the expansion or contraction of the substrate, so that it is necessary to correct the processing position of the structure in each step. In the case of other types of FET, inkjet coating is possible while taking into consideration the expansion or contraction of the substrate as described below, and it is preferable that the coating can be performed on the channel region.

[0023] 1 is a top-contact type FET (a structure in which the source electrode and the drain electrode are disposed above the semiconductor layer), but a bottom-contact type FET (a structure in which the source electrode and the drain electrode are disposed below the semiconductor layer) may also be used. In this case, the FET can be manufactured by carrying out steps (f) and (g) before steps (d) and (e).

[0024] The above-described method for manufacturing a FET can be applied to the method for manufacturing a FET according to each of the following embodiments of the present invention.

[0025] (Embodiment 1) The method for manufacturing a FET according to the first embodiment of the present invention includes a step of forming a plurality of structures, each including at least one of a gate electrode, a source electrode, and a drain electrode, and then inkjet-coating each of the structures with a semiconductor material, the inkjet coating being performed while moving an inkjet head relative to the substrate, and varying the number of droplets and / or the droplet spacing for each structure in accordance with predetermined conditions, thereby manufacturing a plurality of FETs on a surface of a substrate.

[0026] FIG. 2 is a schematic diagram showing an outline of a method for manufacturing a FET according to the first embodiment of the present invention. As shown in FIG. 2(a), a substrate 1 is fixed on a stage 20. A plurality of structures 10 are formed on the substrate 1. The structures 10 include one or more of a gate electrode, a source electrode, and a drain electrode, and will eventually become FETs. A camera 21 captures an image of the structures 10 and / or the alignment marks 11. From the captured image and the camera coordinates at the time of capturing the image, a calculation unit (not shown) calculates the coordinates to be inkjet coated. This determines, for each structure 10, a "predetermined condition" regarding the number of droplets and / or the droplet interval when performing inkjet coating. In addition, although only the structures 10 and the alignment marks 11 are depicted on the substrate 1, circuit wiring, capacitors, etc. may also be arranged.

[0027] One example of a method for fixing the substrate 1 onto the stage 20 is to provide suction holes or a porous chuck in the stage 20 and evacuate the stage 20.

[0028] An example of calculation of the coating coordinates of the structure 10 will be described. First, a calculation device (such as a PC) that performs image processing and calculation of the coating position coordinates is prepared, and standard image data of the structure 10 and / or the alignment mark 11 is registered in advance. Then, the standard image data is matched against an image captured by the camera 21 to detect the position (coordinates) of the image. The image can be matched using a known pattern matching method that compares information on geometric shapes such as normalized correlation or the contours of the images. Then, the coating position coordinates are corrected using the coordinate data obtained by pattern matching. The coordinate correction may be performed by correcting the coordinates of the inkjet nozzle, or may be performed by moving the substrate during inkjet coating to correct the coordinates.

[0029] When the number of structures 10 is small or when high accuracy of the coating position of the semiconductor material is required, a method of capturing an image of each of the structures 10 and calculating the coating center coordinates of each of the structures 10 from the acquired image is preferable. On the other hand, when the number of structures 10 on the substrate 1 is large or when high accuracy of the coating position of the semiconductor material is not a high priority, a method of correcting the coating position using the alignment mark 11 is preferable.

[0030] When the alignment mark 11 is used to correct the coating position, for example, the coating direction, coating width direction, and angle deviation between the substrate and the inkjet head can be corrected by reading two diagonal points of the alignment mark 11. In addition, when the expansion and contraction rate of the substrate 1 is large, correction may be performed based on the ratio between the distance between the alignment marks acquired by the camera 21 and the distance between the registered alignment marks. Furthermore, by reading four points of the alignment mark 11, correction according to the shape of the distortion, such as trapezoidal distortion, can be performed. When positional accuracy is required, the alignment mark 11 may be arranged at multiple points with a narrow pitch. Then, by registering the coordinates of the alignment mark 11 and each structure 10 in advance from CAD data or the like in a PC, the coating position center of each structure 10 is calculated from the relative positional relationship between the acquired coordinates of the alignment mark 11 and each structure 10.

[0031] After calculating the application position center, the droplet interval in the matrix and the number of droplets are specified for each of the structures 10, and application position coordinates are assigned to each droplet from the application position center.

[0032] 2(b), the inkjet head 22 or the stage 20 is moved in one direction while the semiconductor material is discharged from the nozzles of the inkjet head 22 to the coordinates to be coated. Although an example of a sheet of substrate 1 is shown, a roll film or the like may also be used. In that case, coating while moving the inkjet head 22 is preferable because it is less likely to cause wrinkles in the roll film.

[0033] In addition, in order to improve the accuracy of the coating position, a function for offsetting the ejection position in the coating direction may be provided. The offset is, for example, to eliminate a certain distance deviation that occurs in the coating direction due to the relationship between the distance between the substrate and the nozzle of the inkjet head, the coating speed, and the ink ejection speed. The ink ejection speed depends on the characteristics of the ink, but generally, by setting it to 5 to 10 m / s, stable ejection without satellites (scattering of small droplets) can be achieved. For example, when the relative movement speed between the substrate 1 and the inkjet head 22 is 100 mm / s, the distance between the substrate 1 and the lower surface of the inkjet head 22 is 1 mm, and the ink ejection speed is 5 m / s, the time from when the ink is ejected to when it lands on the substrate is 0.2 ms. During this time, the ink advances in the coating direction by 100 mm / s x 0.2 ms = 20 μm, so by offsetting this value, the coating position accuracy is improved and the channel region can be covered with a smaller amount of droplets.

[0034] The droplet interval in the coating direction will be described. The droplet interval in the present invention refers to the distance between the centers of adjacent droplets among the droplets to be discharged. The minimum droplet discharge interval is determined by one cycle time of the drive voltage waveform during droplet discharge, taking into consideration the relative movement speed between the substrate 1 and the inkjet head 22 and the drive frequency of the head. One cycle time is determined taking into consideration the time to deform the piezo element and the time to stabilize the meniscus formed on the lower surface of the nozzle, but differs depending on the structure of the inkjet head. For example, if the lower limit of the droplet discharge cycle is 50 μs and the nozzle movement speed is 100 mm / s, the lower limit of the minimum droplet discharge interval is 100 μs×10 mm / s=1 μm, and if it is 100 μs×100 mm / s, it is 10 μm. If it is set shorter than the lower limit of the droplet discharge cycle, the droplets cannot be discharged stably, and the discharge amount varies and satellites occur.

[0035] FIG. 3 shows a schematic diagram in which six droplets 12 of an ink (hereinafter referred to as "semiconductor ink") in which a semiconductor material is dissolved in a solution are ejected onto a channel region 14 to form a coalesced droplet (hereinafter referred to as a "combined droplet") 13.

[0036] In FIG. 3( a ), six droplets 12 are dispensed in a substantially straight line in the longitudinal direction 23 of the channel region 14 to form a united droplet 13 .

[0037] In Fig. 3(b) and (c), three droplets are discharged in the channel width direction and two droplets are discharged in the channel length direction, for a total of six droplets, at appropriate droplet intervals. In the case of Fig. 3(b), the combined droplets 13 cover the channel region, so that a FET with the expected characteristics is formed. However, when droplets are discharged at the droplet intervals shown in Fig. 3(c), the droplets 12 do not merge, depending on the contact angle between the substrate 1 and the droplets 12 of the semiconductor ink and the amount of the semiconductor ink discharged. Therefore, a so-called coffee ring, which is a ring-shaped evaporation residue of each droplet 12 after drying, is formed on the channel region 14. The density of the semiconductor material becomes high around the coffee ring, and the semiconductor material becomes sparse and dense in the channel region 14, so that a FET with characteristics different from the expected one is formed. In this way, some of the multiple FETs formed on the substrate are completed as expected, while others have unexpected characteristics. Therefore, the number of droplets and the droplet interval conditions shown in Fig. 3(c) cannot be adopted.

[0038] In the present invention, as shown in FIG. 3(a), it is preferable from the viewpoint of production efficiency to move the inkjet head relative to the substrate in the longitudinal direction of the channel region 14 formed in the structure. At this time, it is sufficient that the inkjet head and the inkjet head are in a relative moving relationship, and either one of them may be moved, or both may be moved. The number of droplets to be deposited on the substrate and one structure 10 depends on the volatility of the semiconductor ink, but it is preferable to adjust it to a range in which the droplets are united within 1 second at the latest. As an example, if 50 droplets are deposited at a deposition speed of 10 mm / s with a droplet interval of 1 μm, it is completed in about 1 μm / (10 mm / s)×49 droplet intervals+deposition time 0.1 ms=5 ms from the start of ejection of the first droplet, so there is no problem.

[0039] The droplet interval is preferably 2 to 100 μm, and more preferably 5 to 30 μm. The shape of the coalesced droplet approaches a perfect circle when the droplet interval is narrowed, and becomes elliptical when the droplet interval is widened. When the aspect ratio of the structure 10 (channel region 14 therein) is not 1, it is better to widen the droplet interval from the viewpoint of reducing material loss. The lower limit of the droplet interval is determined by the product of one cycle time of the driving voltage waveform during droplet ejection and the coating speed, and therefore depends on the head performance, and is preferably 2 μm or more from the viewpoint of maintaining an appropriate coating speed. If the droplet interval is too wide, adjacent droplets 12 cannot form a coalesced droplet 13, so the droplet interval is preferably 100 μm or less.

[0040] The number of droplets is preferably 5 or more from the viewpoint of applying a predetermined amount without increasing the droplet interval too much, and is preferably 100 or less from the viewpoint of not forming a united droplet larger than necessary.

[0041] For example, when the semiconductor layer 6 is made of carbon nanotubes, the amount of carbon nanotubes in the semiconductor layer 6, specifically, 1 μm of the semiconductor layer 6, can be adjusted by correcting the droplet interval and / or the number of droplets before coating. 2 By adjusting the total length of the carbon nanotubes per unit area, the drive current value of the FET can be set to a desired value.

[0042] Figure 4 is a schematic diagram showing the difference in the shape of merged droplets when semiconductor ink is applied to structures having the same size of channel region formed, with the number of droplets and / or the droplet spacing being changed depending on the size of the channel region.

[0043] In FIG. 4(a), six droplets 12 are discharged in the longitudinal direction 23 of the channel region 14 to form a combined droplet 13. In FIG. 4(b), the number of droplets is the same as in FIG. 4(a), but the droplet intervals between the droplets 12 are increased to form a combined droplet 13. By adjusting the droplet intervals, the shape of the combined droplet 13 can be changed, and the combined droplet 13 can be applied so as not to overlap the channel region 14 of adjacent structures. In FIG. 4(c), four droplets 12 are discharged to form a combined droplet 13. Compared to FIG. 4(a), the number of droplets is smaller and the droplet intervals are increased, and the number of droplets and the droplet intervals are adjusted to a range that can cover the channel region 14, and the application is thin and spread. By applying in this manner, the amount of semiconductor material applied on the channel region 14 is reduced, making it possible to adjust the concentration of the semiconductor material. Furthermore, by selecting the shape of the combined droplet 13 to match the channel region 14, material loss can be reduced. The shape of the combined droplet 13 is preferably selected in consideration of the shape of the channel region 14 and the accuracy of the inkjet application position, so that the shape can cover the channel region.

[0044] FIG. 5 is a schematic diagram showing an example of an inkjet head underside 24 having multiple nozzles. In general, as shown in FIG. 5(a), multiple nozzles 25 are arranged at a constant nozzle pitch Np on the underside of an inkjet head 22 for industrial use, and are often arranged in two or more rows. In this case, the droplet interval in the coating width direction is Np / number of rows. If it is necessary to further narrow the droplet interval, as shown in FIG. 5(b), the droplet interval can be further narrowed by coating while shifting the angle of the inkjet head 22 by θ with respect to the coating width direction. Since the nozzle pitch in the coating width direction is Np×cosθ, the larger the angle θ is within a range not exceeding 90 degrees, the narrower the droplet interval in the coating width direction can be. However, since it is necessary to shift the ejection timing for each nozzle by the angle θ, the ejection timing is offset for each nozzle according to the angle.

[0045] By using the inkjet coating method described above, it is possible to perform inkjet coating on a substrate 1 on which a plurality of structures 10 are formed, as shown in FIG. 2(a). When the plurality of structures 10 have the same shape and the droplet interval and / or the number of droplets are all the same, the command is very simple, and the calculation time for the discharge position is short. In FIG. 2(a), the structures 10 are arranged at regular intervals in both the coating direction and the coating width direction, but it is not necessary to inkjet coat all of the structures. Depending on the formation of the semiconductor layer 6, it is also possible to intentionally prevent part of the logic circuit from operating or to perform a different circuit operation. In addition, the structures 10 may be arranged in a gapped manner, or wiring or capacitors for connecting circuits may be arranged on the substrate.

[0046] In the method for manufacturing the FET according to the first embodiment, the structures formed on the substrate may be composed of structures having the same size of the channel region formed therein, but it is preferable to have two or more structures having different sizes of the channel region formed therein. The drive current value depends on the channel width and the channel length. For example, when circuits having different functions, such as a rectifier circuit and a memory circuit, are formed in the substrate, it is necessary to obtain different drive current values. Therefore, the channel width and the channel length are designed to be different for each structure of the circuit, and the droplet interval and / or the number of droplets are selected so as to cover the channel region of each of the different structures, thereby making it possible to obtain a desired drive current value for each structure.

[0047] In this case, by varying the number of droplets and / or the droplet spacing depending on the size of the channel region, multiple FETs can be fabricated on the surface of the substrate.

[0048] Fig. 6 is a schematic diagram showing the difference in the shape of a combined droplet when semiconductor ink is applied to two types of structures having different sizes of channel regions formed, with the number of droplets and / or the interval between droplets being changed according to the size of the channel region. Fig. 7 is a schematic cross-sectional view of the dashed line XY portion in Fig. 6. In all of Figs. 6(a) to (c), application is performed in the longitudinal direction 23. The structures shown in Figs. 6(a) and 6(b) are structures having different sizes of channel regions 14 (here, channel widths).

[0049] 6 and 7(a), six droplets 12 are discharged in the longitudinal direction 23 of the channel region 14 to form a united droplet 13. However, even if the droplet interval and number of droplets in Fig. 6(a) are applied to the structure in Fig. 6 and 7(b), it is not possible to cover the entire channel region 14. Therefore, by changing the droplet interval and number of droplets, it is possible to cover the channel region 14.

[0050] 6 and 7(b), the droplet intervals are the same, and 10 droplets 12 are ejected to form a combined droplet 13. The droplet 13 has an elliptical shape that is long in the longitudinal direction 23, and the height 15 of the combined droplet 13 is higher by the amount corresponding to the increase in the number of droplets.

[0051] In Figs. 6 and 7(c), the number of droplets is the same as in Figs. 6 and 7(a), but the droplets are discharged with a wider interval to form a coalesced droplet 13. The coalesced droplet 13 has an elliptical shape that is long in the longitudinal direction 23, but the number of droplets (amount of application) is the same as in Figs. 6 and 7(a), so the diameter of the coalesced droplet 13 in the direction perpendicular to the longitudinal direction 23 is smaller. When the number of droplets is the same and the droplet interval is wider, the droplets are thinly spread in the longitudinal direction 23, so the height 15 of the coalesced droplet 13 is lower. Note that the droplet height when the droplet interval and / or the droplet number are changed is also affected by the contact angle between the insulating layer 4 and the semiconductor material, so in practice, it is preferable to vary the droplet interval and / or the droplet number within the area range covering the channel region and determine the conditions for a desired current value (Id).

[0052] To evaluate whether the desired current value has been obtained, any known device capable of measuring the IV characteristics of a FET can be used to measure the source-drain current (Id) vs. source-drain voltage (Vsd) characteristics when the gate voltage (Vg) is changed.

[0053] Although not shown in FIGS. 6 and 7, both the droplet spacing and the number of droplets may be adjusted to change the density of the semiconductor material while covering the channel region 14.

[0054] In order to change the density of the semiconductor material for each structure, two or more types of semiconductor inks with different concentrations of the semiconductor material may be used. However, from the viewpoint of production efficiency, it is preferable to standardize the type of semiconductor ink and adjust the density of the semiconductor material by the droplet interval and / or the number of droplets.

[0055] Another example of a structure applicable to the present invention is shown in Fig. 8. Fig. 8 is a schematic diagram showing an example of a structure in which source electrodes 8 and drain electrodes 9 are arranged alternately. In the case of a structure 10 having a channel region 14 with a complex shape as shown in Figs. 8(a) and (b), the larger of the maximum height Cx and maximum width Cy of the channel region 14 may be interpreted as the longitudinal direction.

[0056] According to the above-described first embodiment, the number of droplets and / or the interval between droplets are changed according to a predetermined condition when applying a semiconductor material to a substrate on which a plurality of FETs are formed, so that a plurality of FETs having desired characteristics can be manufactured on the substrate. In addition, since the number of droplets and / or the interval between droplets are adjusted, even in a substrate having an area in which FETs are densely packed and the distance between the semiconductor layers is narrow, it is possible to prevent the semiconductor layers of adjacent FETs from overlapping each other. In addition, since it is possible to adjust the droplet shape so as to cover the channel region, it is not necessary to assume that the droplet shape is a perfect circle and to make the aspect ratio of the structure close to 1, and it is also possible to make the structure long in the application direction, for example. This increases the degree of freedom in designing not only the shape of the structure itself but also the wiring and the like.

[0057] Furthermore, when there are two or more structures with different sizes of the channel region formed, the number of droplets and / or the droplet interval are adjusted according to the size of the channel region of each structure, so that a desired driving current value can be obtained for each structure. In addition, the constraints due to the coating shape in the design of the structure can be alleviated.

[0058] In addition, in display applications, it is common to provide partitions with a height of about 1 to 100 μm and adjust the concentration and height after formation by increasing or decreasing the amount of ink filled in the area surrounded by the partitions. In contrast, in the present application, the droplet spacing and / or the number of droplets are adjusted to control the shape of the combined droplet 13 and adjust the concentration and height of the semiconductor material on the channel region 14, so no partitions are required.

[0059] (Embodiment 2) The FET manufacturing method according to the second embodiment of the present invention is a FET manufacturing method according to the above-mentioned first embodiment, which includes the steps of measuring physical quantities based on one or more of the gate electrode, the gate insulating layer, the source electrode, and the drain electrode at each of the multiple structures or at representative points before inkjet coating, and correcting the number of droplets to be applied to each structure and / or the droplet intervals based on the measured physical quantities of the structures.

[0060] As described in the first embodiment, in the process of manufacturing the structure 10, manufacturing variations may occur in one or more of the gate electrode 3, the gate insulating layer 4, the source electrode 8, and the drain electrode 9. According to the second embodiment, therefore, it is possible to correct the deviation of the coating position coordinates due to such manufacturing variations.

[0061] 9(a) shows a schematic plan view of the FET, and FIG.9(b) shows a schematic cross-sectional view of the dashed line XY portion of FIG.9(a). Physical quantities to be measured include the width 30 of the gate electrode 3, the length 31 of the gate electrode 3, the distance 32 between the source electrode 8 and the drain electrode 9, the length 33 of the source electrode 8 and / or the drain electrode 9, the width 34 of the overlapping portion between the gate electrode 3 and the source electrode 8 and / or the drain electrode 9, the film thickness 35 of the gate electrode 3, the surface roughness of the gate electrode 3, the density of the gate electrode 3, the refractive index of the gate electrode 3, the film thickness 37 of the source electrode 8 and / or the drain electrode 9, the surface roughness of the source electrode 8 and / or the drain electrode 9, the density of the source electrode 8 and / or the drain electrode 9, the refractive index of the source electrode 8 and / or the drain electrode 9, the roughness of the gate electrode end in the channel region, the roughness of the source electrode 8 and / or the drain electrode end in the channel region, the film thickness 35 of the gate insulating layer, the surface roughness of the gate insulating layer, the density of the gate insulating layer, the refractive index of the gate insulating layer, and the like, but there are no particular limitations as long as the drive current value of the FET changes.

[0062] Among these, the width 30 of the gate electrode, the length 31 of the gate electrode, the distance 32 from the source electrode and / or drain electrode, the length 33 of the source electrode and / or drain electrode, and the film thickness 36 of the gate insulating layer are preferable because they can be measured at any step after the gate electrode, the gate insulating layer, the source electrode, or the drain electrode are formed, and further, they can be measured in-line, non-destructively, and in a short time.

[0063] Furthermore, the structure 10 for measuring a physical quantity is not limited to a FET as long as it is based on one or more of the gate electrode 3, the gate insulating layer 4, the source electrode 8, and the drain electrode 9 of a FET. For example, a test pattern formed for measuring a physical quantity may be the target for measurement.

[0064] The width, length, interval, and electrode edge roughness can be measured by an optical microscope, a scanning electron microscope (SEM), or the like. The film thickness can be measured by an atomic force microscope, an ellipsometry method, or the like. The refractive index can be measured by a spectroscopic ellipsometry method, or the like. The length of the overlapping portion between the gate electrode and the source electrode and / or the drain electrode can be measured by observing the cross section shown in FIG. 9(b) by an SEM, and measuring the length of the overlapping portion between the gate electrode 3 and the source electrode 8 or the drain electrode 9. The surface roughness can be measured by measuring the surface roughness of the insulating layer or the electrode using a surface shape measuring device. The measurement method is not limited to the above, but any method can be used as long as it can measure physical quantities by the same method for multiple FETs and calculate the amount of variation in the physical quantities for each FET.

[0065] The measured value may be an absolute value of the physical quantity of the measurement object, or may be a deviation of the measurement object from a reference value.

[0066] The droplet interval and / or the number of droplets of the semiconductor material may be corrected based on one physical quantity, or may be corrected based on two or more physical quantities.

[0067] Here, the method of correcting the droplet interval and / or the number of droplets may be to correct the absolute value of the droplet interval and / or the number of droplets based on the measured physical quantity, or to correct from the reference droplet interval and / or the number of droplets based on the deviation of the measured physical quantity from the reference value. In addition, the droplet interval and / or the number of droplets may be appropriately determined according to the specifications of the FET based on the droplet interval and / or the number of droplets that can cover the channel region by experiments or the like so that the driving current value of the FET becomes a predetermined value. For example, if the film thickness of the gate insulating layer is thinner than the reference value, the driving current value becomes larger than the predetermined value. Therefore, in order to make the driving current value a predetermined value, it is necessary to lower the droplet height of the semiconductor material, and a method of widening the droplet interval and / or reducing the number of droplets is considered. However, this is not limited to the above-mentioned method, and it is preferable to determine the correction value by experiments or the like.

[0068] (Modification) As a modification of the second embodiment, there is a method of measuring the physical quantity at a representative point of the structure and adjusting the droplet interval and / or droplet amount, rather than measuring the physical quantity of the structure for each of the multiple FETs formed on the surface of the substrate 1 and adjusting the droplet interval and / or droplet amount. In this method, for example, the substrate 1 is partitioned into two or more regions each having multiple structures 10 (the structures 10 are provided with one or more of the gate electrode 3, the gate insulating layer 4, the source electrode 8 and / or the drain electrode 9), and the physical quantity is measured and the droplet interval and / or droplet number are corrected for one of the structures in the region (this is set as a representative point in the region), and the semiconductor material 5 is applied to all the structures 10 in the region with the corrected droplet interval and / or droplet number. This method is preferable because it requires a short measurement time.

[0069] According to the second embodiment and its variations described above, physical quantities based on the structure, etc. are measured, and the number of droplets of semiconductor material and / or the intervals between droplets are corrected accordingly before application, so that a plurality of FETs with desired characteristics can be manufactured on a substrate.

[0070] The following describes matters commonly applied to the methods for manufacturing FETs according to the present embodiment.

[0071] (FET) The FETs manufactured by the method of the present invention are a plurality of FETs provided on a substrate and each having at least a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode.

[0072] <Substrate> The material used for the substrate is not particularly limited, but it is sufficient that at least the surface on which the electrodes are arranged is insulating. For example, inorganic materials such as glass, sapphire, alumina sintered body, silicon wafer, and the like, and materials in which the surfaces of these materials are coated with an oxide film, and organic materials such as polyimide, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, polyvinylidene fluoride, polysiloxane, polyvinylphenol (PVP), polyester, polycarbonate, polysulfone, polyethersulfone, polyethylene, polypropylene, polyphenylene sulfide, polyparaxylene, and cellulose are preferably used, but are not limited to these.

[0073] <Gate electrode, source electrode, drain electrode, and wiring> The gate electrode, source electrode, drain electrode and wiring may be any conductive material that can be generally used as an electrode. Examples of such conductive materials include conductive metal oxides such as tin oxide, indium oxide and indium tin oxide (ITO). In addition, examples of such conductive materials include metals such as platinum, gold, silver, copper, iron, tin, zinc, aluminum, indium, chromium, lithium, sodium, potassium, cesium, calcium, magnesium, palladium, molybdenum, amorphous silicon and polysilicon, alloys of a plurality of metals selected from these, and inorganic conductive materials such as copper iodide and copper sulfide. In addition, examples of such conductive materials include polythiophene, polypyrrole, polyaniline, a complex of polyethylenedioxythiophene and polystyrenesulfonic acid, and conductive polymers whose conductivity has been improved by doping with iodine or the like. In addition, examples of such conductive materials include carbon materials and materials containing an organic component and a conductor.

[0074] A material containing an organic component and a conductor increases the flexibility of the electrode, and has good adhesion and electrical connection even when bent. The organic component is not particularly limited, but may be a monomer, an oligomer or a polymer, a photopolymerization initiator, a plasticizer, a leveling agent, a surfactant, a silane coupling agent, an antifoaming agent, a pigment, etc. From the viewpoint of improving the bending resistance of the electrode, an oligomer or a polymer is preferable. However, the conductive material of the electrode and the wiring is not limited to these. These conductive materials may be used alone, or a plurality of materials may be laminated or mixed.

[0075] Furthermore, the width and thickness of the electrodes and the spacing between each electrode (e.g., the spacing between the source electrode and the drain electrode) can be set arbitrarily depending on the specifications of the FET. For example, it is preferable to set the width of each electrode to 5 μm or more and 1 mm or less. It is preferable to set the thickness of each electrode to 0.01 μm or more and 100 μm or less. It is preferable to set the spacing between the source electrode and the drain electrode to 1 μm or more and 500 μm or less. However, these sizes are not limited to those mentioned above.

[0076] Furthermore, the width and thickness of the wiring are also arbitrary. Specifically, the thickness of the wiring is preferably set to 0.01 μm or more and 100 μm or less. The width of the wiring is preferably set to 5 μm or more and 500 μm or less. However, these sizes are not limited to the above.

[0077] <Gate insulating layer> The material used for the gate insulating layer is not particularly limited, but may include inorganic materials such as silicon oxide and alumina; organic polymer materials such as polyimide, polyvinyl alcohol, polyvinyl chloride, polyethylene terephthalate, polyvinylidene fluoride, polysiloxane, and polyvinylphenol (PVP); or a mixture of inorganic material powder and organic material. Among them, those containing an organic compound containing a bond between a silicon atom and a carbon atom are preferred from the viewpoint of adhesion to a substrate or an electrode. Also preferred are those containing an organic compound containing a bond between a silicon atom and a carbon atom and a metal compound containing a bond between a metal atom and an oxygen atom.

[0078] The thickness of the gate insulating layer is preferably set to 0.05 μm or more and 5 μm or less, and more preferably set to 0.1 μm or more and 1 μm or less. By setting the thickness within this range, it becomes easy to form a uniform thin film.

[0079] The insulating layer may be a single layer or multiple layers. In addition, one layer may be formed from multiple insulating materials, or multiple insulating layers may be formed by laminating multiple insulating materials.

[0080] <Semiconductor layer> The material used for the semiconductor layer is not particularly limited as long as it exhibits semiconducting properties, and may be any material to which an inkjet coating process can be applied. Preferred examples include organic semiconductors and / or carbon materials.

[0081] In particular, carbon materials are preferable, and specific examples thereof include carbon nanotubes (hereinafter, referred to as CNT), graphene, and fullerene, with CNT being preferable in terms of suitability for coating processes and high mobility.

[0082] As the CNT, any of the following may be used: single-walled CNT in which one carbon film (graphene sheet) is wound in a cylindrical shape; double-walled CNT in which two graphene sheets are wound concentrically; and multi-walled CNT in which multiple graphene sheets are wound concentrically. Two or more of these may be used. From the viewpoint of exhibiting semiconductor properties, it is preferable to use single-walled CNT, and it is more preferable that the single-walled CNT contains 90% by weight or more of semiconducting single-walled CNT. It is even more preferable that the single-walled CNT contains 95% by weight or more of semiconducting single-walled CNT.

[0083] The content ratio of semiconducting single-walled CNTs can be calculated from the absorption area ratio of the visible-near infrared absorption spectrum. CNTs can be obtained by methods such as the arc discharge method, the chemical vapor deposition method (CVD method), and the laser ablation method.

[0084] Among them, CNT is preferred as the material used for the semiconductor layer because of the ease of forming the semiconductor layer. Furthermore, CNTs having a conjugated polymer attached to at least a part of the surface (hereinafter referred to as CNT composite) are particularly preferred because they have excellent dispersion stability in a solution and can provide high mobility. Here, the conjugated polymer refers to a compound whose repeating unit has a conjugated structure and has a degree of polymerization of 2 or more.

[0085] The state where a conjugated polymer is attached to at least a part of the surface of a CNT means that the conjugated polymer covers a part or the entire surface of the CNT. It is speculated that the reason why a conjugated polymer can cover a CNT is because the π-electron clouds derived from each conjugated structure overlap and interact with each other. Whether a CNT is covered with a conjugated polymer can be determined by checking whether the reflected color of the covered CNT approaches that of the conjugated polymer from that of the uncovered CNT. The presence of the deposit and the mass ratio of the deposit to the CNT can be quantitatively identified by elemental analysis such as X-ray photoelectron spectroscopy (XPS).

[0086] By attaching a conjugated polymer to at least a portion of the CNT surface, it becomes possible to uniformly disperse CNTs in a solution without impairing the high electrical properties of CNTs. In addition, it becomes possible to form a uniformly dispersed CNT film by coating a dispersion in which CNTs are uniformly dispersed. This makes it possible to achieve high semiconducting properties.

[0087] Methods for attaching a conjugated polymer to CNT include (I) a method of adding CNT to a molten conjugated polymer and mixing it, (II) a method of dissolving a conjugated polymer in a solvent, adding CNT to the solution, and mixing it, (III) a method of adding a conjugated polymer to a solution in which CNT has been preliminarily dispersed in a solvent using ultrasonic waves or the like, and (IV) a method of putting a conjugated polymer and CNT in a solvent, and mixing the mixture by irradiating ultrasonic waves, etc. In the present invention, a combination of multiple methods may be used.

[0088] In the present invention, the length of the CNT is preferably shorter than the set source electrode-drain electrode interval. The average length of the CNT depends on the source electrode-drain electrode interval, but is preferably 2 μm or less, more preferably 0.5 μm or less. Since commercially available CNTs generally have a distribution in length and may contain CNTs longer than the source electrode-drain electrode interval, it is preferable to add a process of making the CNT shorter than the source electrode-drain electrode interval. For example, a method of cutting the CNT into short fibers by acid treatment with nitric acid, sulfuric acid, or the like, ultrasonic treatment, or freeze-pulverization is effective. In addition, it is more preferable to use separation by a filter in order to improve purity.

[0089] Furthermore, the diameter of the CNT is not particularly limited, but is preferably 0.5 nm or more and 100 nm or less, and more preferably 1 nm or more and 50 nm or less.

[0090] Examples of the conjugated polymer that coats the CNT include polythiophene polymers, polypyrrole polymers, polyaniline polymers, polyacetylene polymers, poly-p-phenylene polymers, poly-p-phenylenevinylene polymers, and thiophene-heteroarylene polymers having thiophene units and heteroaryl units in the repeating units, and two or more of these may be used. The above polymers may be those in which a single monomer unit is arranged, those in which different monomer units are block copolymerized, those in which random copolymerization is performed, and those in which graft polymerization is performed.

[0091] The semiconductor layer may be a mixture of a CNT composite and an organic semiconductor. By uniformly dispersing the CNT composite in the organic semiconductor, it is possible to achieve high mobility while maintaining the properties of the organic semiconductor itself.

[0092] The semiconductor layer may further include an insulating material, such as the insulating material composition of the present invention, or a polymer material such as poly(methyl methacrylate), polycarbonate, or polyethylene terephthalate, but is not limited to these.

[0093] The semiconductor layer may be a single layer or multiple layers, and the thickness is preferably 1 nm to 200 nm, more preferably 100 nm or less. By setting the thickness within this range, it becomes easier to form a uniform thin film, and furthermore, it is possible to suppress the source-drain current that cannot be controlled by the gate voltage, and to increase the on-off ratio of the FET. The thickness can be measured by an atomic force microscope, ellipsometry, etc.

[0094] (Applicability of the element) The FET manufacturing method described in the embodiment of the present invention is applicable to ICs in various electronic devices, wireless communication devices such as RFID tags, TFT arrays for displays, sensors, and tamper detection systems.

[0095] <Wireless communication device> Next, a wireless communication device including a FET fabricated by the manufacturing method of the present invention will be described. This wireless communication device is a device that communicates information using radio waves, such as a product tag, an anti-shoplifting tag, various tickets, and smart cards.

[0096] The wireless communication device includes at least the above-mentioned FET and an antenna. More specifically, the wireless communication device includes a power generation unit that rectifies a modulated wave signal received from the outside by the antenna and supplies power to each unit, a demodulation circuit that demodulates the modulated wave signal and sends it to a control circuit, a modulation circuit that modulates data sent from the control circuit and sends it to the antenna, and a control circuit that writes the data demodulated by the demodulation circuit to a memory circuit and reads data from the memory circuit and transmits it to the modulation circuit, and each circuit unit is electrically connected. The memory circuit may further include a read-only memory unit to which information is written during manufacturing, or a non-volatile rewritable memory unit such as an EEPROM (Electrically Erasable Programmable Read-Only Memory) or a FeRAM (Ferroelectric Random Access Memory).

[0097] As an example of a semiconductor device that can be applied to a wireless communication device according to an embodiment of the present invention, the following wireless communication semiconductor device is given: Note that, in this embodiment, the portion of the wireless communication device other than the antenna is referred to as the semiconductor device.

[0098] A plurality of organic field effect transistors are provided on a surface of a substrate, A rectangle is drawn having sides parallel to one side of the substrate (this is the X-direction) and perpendicular thereto (this is the Y-direction) so as to inscribe an area in which a semiconductor material is present in each organic field-effect transistor, and the length of the side of the rectangle in the X-direction is defined as LX and the length of the side in the Y-direction is defined as LY; Let Sx be the X-direction component and Sy be the Y-direction component of the line segment connecting the center of the rectangle of a certain organic field effect transistor (this will be referred to as the "transistor of interest", and LX will have a length of LX1 and LY will have a length of LY1) to the center of the rectangle of an adjacent organic field effect transistor (this will be referred to as the "adjacent transistor", and LX will have a length of LX2 and LY will have a length of LY2), In a relationship between the target transistor and an adjacent transistor among the adjacent transistors, at least one of Sx and Sy is 500 μm or less, (LX1+LX2) / 2 <Sx または (LY1+LY2) / 2<Sy A semiconductor device that satisfies the above conditions.

[0099] FIG. 10 is a plan view showing an example of such a semiconductor device, in which a plurality of organic field effect transistors 41a to 41f and 42a to 42f are arranged at equal intervals in both the X and Y directions.

[0100] Here, when the organic field-effect transistor 41a in the upper left is regarded as the target transistor, the adjacent transistors are two transistors 42a and 42c. The rectangle in which the existence region (=unified droplet) of the semiconductor material covering the channel region of the target transistor 41a is inscribed is as shown in FIG. 10, and has sides consisting of lengths LX1 and LY1 respectively. Also, the rectangle in which the existence region of the semiconductor material covering the channel region of the adjacent transistor 42c below is inscribed is as shown in FIG. 10, and has sides consisting of lengths LX2 and LY2 respectively. At this time, the X-direction component of the center-to-center distance between the rectangles of the target transistor 41a and the adjacent transistor 42c is Sx, which is 500 μm or less. And as can be seen from the fact that the relationship (LX1 + LX2) / 2 < Sx holds in FIG. 10, the semiconductor layer of the target transistor 41a is independent without interfering with the adjacent transistor 42c.

[0101] Next, the rectangle in which the existence region of the semiconductor material covering the channel region of the adjacent transistor 42a on the right is inscribed is as shown in FIG. 10, and has sides consisting of lengths LX2 and LY2 respectively. At this time, the X-direction component of the center-to-center distance between the rectangles of the target transistor 41a and the adjacent transistor 42a is Sy, which is 500 μm or less. And as can be seen from the fact that the relationship (LY1 + LY2) / 2 < Sy holds in FIG. 10, the semiconductor layer of the target transistor 41a is independent without interfering with the adjacent transistor 42a. Thus, in the relationship between the target transistor and the adjacent transistor in which at least one of Sx and Sy is 500 μm or less among the adjacent transistors, by satisfying the condition (LX1 + LX2) / 2 < Sx or (LY1 + LY2) / 2 < Sy, even when the distance between the transistors is narrow, all the transistors can exist independently without interfering with each other's semiconductor layers.

[0102] FIG. 11 is a top view showing another example of such a semiconductor device, in which a plurality of organic field effect transistors 43a to 43i and 44a to 44d are arranged at equal intervals with one gap each with respect to the grids in the X direction and Y direction described by the dashed lines. For example, when the organic field effect transistor 44a is taken as the target transistor, the adjacent transistors include transistors 43a, 43b, 43d, 43e, 44b, and 44c. Among them, for example, in the relationship with the adjacent transistor 43b, the X component Sx and the Y component Sy of the center-to-center distance of the rectangle are represented as shown in FIG. 11, and (LX1 + LX2) / 2 < Sx and (LY1 + LY2) / 2 < Sy are satisfied. If such a relationship holds in the relationship between the target transistor and an adjacent transistor in which at least one of Sx and Sy is 500 μm or less among the adjacent transistors, all the transistors can exist independently without interfering with each other's semiconductor layers even when the distance between the transistors is narrow.

[0103] FIG. 12 is a schematic plan view showing the relationship of the center positions of the rectangles in which the regions where the semiconductor materials of the target transistor and the adjacent transistors are present are inscribed. When the position of the target transistor is fixed at the center of FIG. 12, the region where the center position of the rectangle of the adjacent transistor with respect to the target transistor exists is divided into regions I to IV according to the relationship between Sx, Sy and LX1, LX2, LY1, LY2. Region I: (LX1 + LX2) / 2 < Sx, but (LY1 + LY2) / 2 < Sy is not satisfied. Region II: (LY1 + LY2) / 2 < Sy, but (LX1 + LX2) / 2 < Sx is not satisfied. Region III: (LX1 + LX2) / 2 < Sx and (LY1 + LY2) / 2 < Sy. Region IV: Neither (LX1 + LX2) / 2 < Sx nor (LY1 + LY2) / 2 < Sy is satisfied.

[0104] In the cases of Regions I to III, it can be seen that the rectangles in which the regions where the semiconductor materials ( = coalesced droplets) covering each other's channel regions of the target transistor and the adjacent transistors are inscribed are formed without overlapping.

[0105] On the other hand, in the case of Region IV, a part of the rectangle in which the existing regions of the semiconductor materials of each other are inscribed overlaps. That is, the semiconductor layers of each other may interfere. The fact that the semiconductor layers of each other interfere means that the coalescing droplets at the time of semiconductor formation interfere, and at this point, the shapes of both droplets become distorted. As a result, variations occur in the CNT density formed on the channel. Therefore, an FET with characteristics different from those expected is formed.

[0106] As a means to avoid this, Sx or Sy may be increased, but the circuit size will increase. If the circuit size increases, it will not only affect the manufacturing efficiency but also be difficult to apply to product applications that require a small size.

[0107] In contrast, the means taken in the semiconductor device described above is, as described above, to form LX1, LY1, LX2, and LY2 so that (LX1 + LX2) / 2 < Sx or (LY1 + LY2) / 2 < Sy. That is, for the X-direction component Sx and the Y-direction component Sy of the line segment connecting the centers of the rectangles in which the existing regions of the semiconductor materials of each organic field-effect transistor are inscribed, the droplet interval and the number of droplets are selected so as to obtain appropriate X1, Y1, X2, and Y2. As a result, it becomes possible to apply the semiconductor ink in consideration of Sx and Sy and form a semiconductor layer. Therefore, even when the center-to-center distance of the channel regions of each organic field-effect transistor is small, miniaturization is possible.

[0108] The inlay size used for product tags including apparel and the like varies in height and width, but generally ranges from 500 to 1000 mm 2 and is widely circulated. The antenna part occupies about half of this, and it is necessary to form a semiconductor circuit in the remaining area of 250 to 500 mm 2 .

[0109] On the other hand, a semiconductor circuit is composed of approximately 1,000 FETs, as well as wiring, capacitors, etc., and when forming a semiconductor circuit such as that of the present invention while taking into account the above-mentioned inlay size, a major challenge is how to efficiently arrange the FETs.

[0110] For example, if 40 FETs are arranged at equal intervals with Sx and Sy of 500 μm each, the area will be approximately 20 mm square. If both Sx and Sy exceed 500 μm, the circuit size will also become large, limiting its applications. Since wiring and capacitors must be arranged in addition to FETs, it is necessary to arrange FETs at this interval. Furthermore, if FETs with different characteristics are desired in a semiconductor circuit, for example, for the power generation unit and the memory unit, there is a high possibility that the channel region will be changed, and multiple FETs with different channel regions will be formed. In this way, FETs with different channel regions must be formed at close intervals in the semiconductor circuit, and this is determined by the formation of the semiconductor layer.

[0111] As a method for forming semiconductors, other than inkjet coating, for example, screen printing can be mentioned, but it is difficult to control the amount of coating, and the positional accuracy is also poor, and when printing with a plate of about 500 mm x 500 mm, including plate deterioration and plate lot variations, the deviation is about ±150 μm. Therefore, when the channel size is about 200 to 300 μm square, Sx and Sy will be 500 μm or more when covered with semiconductor ink.

[0112] In the present invention, the size can be reduced by selecting the number of droplets and the interval between droplets to form a semiconductor layer using an inkjet coating method, taking into consideration Sx, Sy and the channel region.

[0113] The region where the semiconductor material exists can be obtained by using a Raman microscope to acquire an image of the distribution of the organic semiconductor material covering the channel region, followed by image processing such as binarization. If the coffee ring occurs at a level that can be observed with a microscope, it can also be obtained by acquiring an image with a microscope and then performing image processing such as binarization. Then, a rectangle is drawn with sides parallel to the X direction, which is parallel to the coating on the substrate, and the Y direction, which is perpendicular to the coating, so as to inscribe the region where the semiconductor material exists, and the length of the side in the X direction of the rectangle is calculated as LX, and the length of the side in the Y direction is calculated as LY. EXAMPLES

[0114] Next, examples of the present invention will be described. Note that the present invention is not limited to the following examples. The evaluation methods in the examples will be described in the following [1] to [2]. The distance between structures refers to the distance between the centers of the channel regions of adjacent structures.

[0115] [1] Measurement of the shape of a rectangle inscribed in the area where semiconductor material exists To obtain the density distribution of organic components using a Raman microscope inVia (Renishaw), a semiconductor laser of 523 nm was used as the light source, and the G band derived from organic semiconductor materials (e.g., 1590 cm for CNT) was used. -1 ) and 1611 cm -1 The distribution of CNTs formed by the coalesced droplets was obtained by acquiring Raman mapping images of the CNTs (derived from PET). The G-band image obtained was then binarized with an absolute intensity of 100 counts as a threshold value, and small particles (noise) that were generated after binarization were removed to obtain the area where the semiconductor material exists covering the channel region. A rectangle was then drawn with sides parallel to the X direction, which is parallel to the coating on the substrate, and the Y direction, which is perpendicular to the coating, so as to inscribe the area where the semiconductor material exists. The length of the side in the X direction of the rectangle was calculated as LX, and the length of the side in the Y direction was calculated as LY. The ratio of LX to LY, LX / LY, was calculated as the aspect ratio.

[0116] [2] Evaluation of FET Id average value and variability The source-drain current (Id)-source-drain voltage (Vsd) characteristics of 20 FETs were measured when the gate voltage (Vg) was changed. The measurements were performed in air using a Semiconductor Characterization System Model 4200-SCS (Keithley Instruments, Inc.). The average value and standard deviation of Id at Vg=-5V when Vsd=-5V was changed from Vg=+5V to -5V were calculated for the 20 FETs, and evaluation was performed according to the following criteria. A: The standard deviation is within 20% of the average value. B: The standard deviation is greater than 20% from the mean.

[0117] (Preparation of photosensitive paste) Synthesis example 1; Compound P1 (photosensitive organic component) Copolymerization ratio (by mass): ethyl acrylate (hereinafter, "EA") / 2-ethylhexyl methacrylate (hereinafter, "2-EHMA") / styrene (hereinafter, "St") / glycidyl methacrylate (hereinafter, "GMA") / acrylic acid (hereinafter, "AA") = 20 / 40 / 20 / 5 / 15.

[0118] In a reaction vessel in a nitrogen atmosphere, 150 g of diethylene glycol monoethyl ether acetate (hereinafter, "DMEA") was charged, and the temperature was raised to 80°C using an oil bath. A mixture consisting of 20 g of EA, 40 g of 2-EHMA, 20 g of St, 15 g of AA, 0.8 g of 2,2'-azobisisobutyronitrile, and 10 g of DMEA was added dropwise over 1 hour. After the dropwise addition was completed, the polymerization reaction was carried out for another 6 hours. Then, 1 g of hydroquinone monomethyl ether was added to stop the polymerization reaction. Subsequently, a mixture consisting of 5 g of GMA, 1 g of triethylbenzylammonium chloride, and 10 g of DMEA was added dropwise over 0.5 hours. After the dropwise addition was completed, the addition reaction was carried out for another 2 hours. The obtained reaction solution was purified with methanol to remove unreacted impurities, and further dried in vacuum for 24 hours to obtain compound P1.

[0119] Synthesis example 2; Compound P2 (photosensitive organic component) Copolymerization ratio (by mass): bifunctional epoxy acrylate monomer (Epoxy Ester 3002A; manufactured by Kyoeisha Chemical Co., Ltd.) / bifunctional epoxy acrylate monomer (Epoxy Ester 70PA; manufactured by Kyoeisha Chemical Co., Ltd.) / GMA / St / AA=20 / 40 / 5 / 20 / 15.

[0120] In a reaction vessel in a nitrogen atmosphere, 150g of DMEA was charged and heated to 80°C using an oil bath. A mixture consisting of 20g of epoxy ester 3002A, 40g of epoxy ester 70PA, 20g of St, 15g of AA, 0.8g of 2,2'-azobisisobutyronitrile and 10g of DMEA was added dropwise over 1 hour. After completion of the dropwise addition, the polymerization reaction was carried out for another 6 hours. Then, 1g of hydroquinone monomethyl ether was added to stop the polymerization reaction. Subsequently, a mixture consisting of 5g of GMA, 1g of triethylbenzylammonium chloride and 10g of DMEA was added dropwise over 0.5 hours. After completion of the dropwise addition, the addition reaction was carried out for another 2 hours. The obtained reaction solution was purified with methanol to remove unreacted impurities, and further dried in vacuum for 24 hours to obtain compound P2.

[0121] Synthesis example 3; Compound P3 (photosensitive organic component) Urethane modification of compound P2 Compound P3 (polymerizable component: polymer having a polymerizable unsaturated group) 100g of DMEA was charged into a reaction vessel in a nitrogen atmosphere, and the temperature was raised to 80°C using an oil bath. A mixture consisting of 10g of photosensitive component P2, 3.5g of n-hexyl isocyanate, and 10g of DMEA was added dropwise to the reaction vessel over a period of 1 hour. After the addition was completed, the reaction was continued for another 3 hours. The resulting reaction solution was purified with methanol to remove unreacted impurities, and then vacuum dried for 24 hours to obtain compound P3 having a urethane bond.

[0122] Preparation Example 1: Photosensitive Paste A In a 100 ml clean bottle, 16 g of the compound P1 obtained above, 4 g of compound P3, 2 g of light acrylate BP-4EA (Kyoeisha Chemical Co., Ltd.), 4 g of photopolymerization initiator OXE-01 (BASF Japan Ltd.), 0.6 g of acid generator SI-110 (Sanshin Chemical Industry Co., Ltd.), and 10 g of γ-butyrolactone (Mitsubishi Gas Chemical Co., Ltd.) were added and mixed with a rotation-revolution vacuum mixer "Awatori Rentaro" (registered trademark) (ARE-310; Thinky Co., Ltd.) to obtain 34.6 g of photosensitive resin solution 1 (solid content 78.5% by mass). 8.0 g of the obtained photosensitive resin solution 1 was mixed with 42.0 g of Ag particles having an average particle size of 0.06 μm, and kneaded using a three-roller "EXAKT M-50" (trade name, EXAKT Co., Ltd.) to obtain 50 g of photosensitive paste A.

[0123] (Preparation of semiconductor solution) In preparing the semiconductor solution, first, 1.0 mg of CNT (CNI, single-walled CNT, purity 95%) was added to a chloroform solution (10 ml) containing 2.0 mg of P3HT (Aldrich, poly(3-hexylthiophene)), and the mixture was ultrasonically stirred for 4 hours at 20% output using an ultrasonic homogenizer (Tokyo Rikakikai, VCX-500) while cooling on ice. This process was repeated 10 times to obtain CNT dispersion A11 (CNT composite concentration in solvent: 0.96 g / l).

[0124] Next, the CNT dispersion A11 was filtered using a membrane filter (pore size 10 μm, diameter 25 mm, Millipore Omnipore Membrane) to remove CNT composites with a length of 10 μm or more. 50 ml of o-DCB (Wako Pure Chemical Industries, Ltd.) was added to the filtrate obtained by this, and then the low boiling point solvent chloroform was distilled off using a rotary evaporator, thereby replacing the solvent with o-DCB to obtain CNT dispersion B11. 30 ml of ethylene glycol monophenyl ether (Toho Chemical Industry Co., Ltd.) was added to CNT dispersion B11 (10 ml), thereby obtaining semiconductor solution A (CNT composite concentration relative to the solvent was 0.03 g / l).

[0125] (Example of gate insulating layer solution preparation) In the example of preparing the gate insulating layer, a gate insulating layer solution A was prepared. Specifically, first, methyltrimethoxysilane (61.29 g (0.45 mol)), 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane (12.31 g (0.05 mol)), and phenyltrimethoxysilane (99.15 g (0.5 mol)) were dissolved in 203.36 g of propylene glycol monobutyl ether (boiling point 170°C). Water (54.90 g) and phosphoric acid (0.864 g) were added to this while stirring. The solution obtained by this was heated at a bath temperature of 105°C for 2 hours, and the internal temperature was raised to 90°C to distill off a component mainly consisting of by-produced methanol. Next, the solution was heated at a bath temperature of 130°C for 2 hours, and the internal temperature was raised to 118°C to distill off a component mainly consisting of water and propylene glycol monobutyl ether. The mixture was then cooled to room temperature to obtain a polysiloxane solution with a solid content of 26.0% by weight. The weight average molecular weight of the polysiloxane in the obtained polysiloxane solution was 6,000.

[0126] Next, 10 g of the obtained polysiloxane solution was weighed out, and 54.4 g of propylene glycol monoethyl ether acetate (hereinafter referred to as PGMEA) was mixed with this, and the mixture was stirred at room temperature for 2 hours. In this way, a gate insulating layer solution was obtained.

[0127] Example 1 In Example 1, a part of a wireless communication device including a plurality of field effect transistors having a bottom gate-top contact structure as shown in FIG. 1 was fabricated on a substrate.

[0128] Specifically, first, 100 nm of copper was vacuum-deposited on the entire surface of a resin substrate 1 (width 300 mm, length 420 mm, film thickness 50 μm) made of PET film by resistance heating. Photoresist (product name "LC100-10cP", manufactured by Rohm and Haas Co., Ltd.) was printed on the entire surface by slit coating, and then heated and dried in a hot air drying oven at 100 °C for 4 minutes. The photoresist film thus produced was exposed to light at an exposure dose of 60 mJ / cm through a photomask with an effective mask size of 280 mm × 400 mm on which a gate electrode was designed. 2 (Equivalent to a wavelength of 365 nm) The photomask was designed as follows: Gate electrode width: 10μm Channel length: 10μm Channel width: 1500μm Inkjet coating direction channel size Cx: 300μm Inkjet coating width direction channel size Cy: 300μm Distance between adjacent structures: Center-to-center distance Sx of the channel area in the inkjet coating direction: 800 μm Center-to-center distance between channel regions in the inkjet coating width direction Sy: 500 μm Number of FETs in the inkjet coating direction: 50 Number of FETs arranged in the inkjet coating width direction: 30 After exposure, the substrate was developed with a 2.38% by weight aqueous solution of tetramethylammonium hydroxide for 30 seconds, and then washed with water for 1 minute. The substrate was then etched with mixed acid (product name: SEA-5, manufactured by Kanto Chemical Co., Ltd.) for 30 seconds, and then washed with water for 30 seconds. The substrate was immersed in AZ Remover 100 (product name, manufactured by AZ Electronic Materials Co., Ltd.) for 2 minutes to remove the resist, washed with water for 30 seconds, removed water droplets with an air knife, and then heated and dried in a hot air drying oven at 80°C for 60 seconds to form a gate electrode 3 (Figure 1(b)).

[0129] Thereafter, a gate insulating layer solution that would become the gate insulating layer was continuously printed over the entire surface by slit coating, and the resultant was heat-treated in a hot air drying furnace under air atmosphere at 100°C for 3 minutes, and then in an IR drying furnace under nitrogen atmosphere at 150°C for 20 minutes, thereby forming a gate insulating layer 4 with a thickness of 300 nm (Figure 1(c)).

[0130] On the substrate on which the gate insulating layer was formed as described above, one Konica Minolta inkjet head KM1024i-MHE was used to perform inkjet coating by adjusting the head angle so that the nozzle pitch of the inkjet head was matched to the distance between adjacent structures to be coated (Fig. 5(b)). The coating conditions were a coating speed of 50 mm / s, 30 droplets, and droplet spacing of 5 μm. Only one nozzle was used to discharge one structure, and the droplets were applied in one straight line (one row). The driving voltage waveform was also adjusted in advance to a discharge speed of 6 m / s.

[0131] After coating, it was confirmed that the combined droplets covered the entire channel regions on the adjacent structures, and that the combined droplets on the adjacent structures were independent and did not interfere with each other.

[0132] Then, the semiconductor layer containing CNT was obtained on the channel region by heat treatment at 150°C for 5 minutes in a nitrogen atmosphere in an IR drying furnace. In addition, a rectangle with parallel sides was drawn so that the coating direction was the X direction and the direction perpendicular to this was the Y direction, so as to inscribe the region where the semiconductor material exists. As a result, the length of the side in the X direction of the rectangle was 418 μm and the length of the side in the Y direction of the rectangle was 330 μm for both adjacent structures. In addition, Id was measured for 20 FETs formed in the same manner, and the average value and standard deviation σ were calculated. The measurement and evaluation results are shown in Table 1.

[0133] Example 2 In Example 2, two Konica Minolta inkjet heads KM1024i-MHE were used, and both head angles were adjusted to the same angle so that the nozzle pitch of the inkjet heads was matched to the distance between adjacent structures on the coating target, and inkjet coating was performed (FIG. 5(b)). The two inkjet heads were shifted by 30 μm in the coating width direction when coating was performed. 15 droplets were discharged from each nozzle of the two heads, with droplet spacing of 10 μm, and droplets were applied in two rows per structure. Other conditions and evaluations were the same as those described above, and the coating conditions, measurement results, and evaluation results are shown in Table 1.

[0134] Example 3 In Example 3, the channel size Cx of one of the adjacent structures was 350 μm, Cy was 250 μm, the number of droplets was 40, and the droplet interval was 15 μm. The channel size of the other structure and the coating conditions on the structure were the same as in Example 1. In other words, the structure shown in FIG. 10 was repeated. The coating conditions were set differently for each structure, and the coalesced droplets were also different. The coating conditions, the rectangular size inscribed by the semiconductor material existing region and its aspect ratio, and the evaluation of Id are the results of a FET with a channel size of Cx 350 μm and Cy 250 μm. The other conditions and evaluations were the same as in Example 1, and the coating conditions, measurement results, and evaluation results are shown in Table 1.

[0135] Example 4 In Example 4, the channel size Cx of one of the adjacent structures was set to 350 μm and Cy to 250 μm, and coating was performed under coating conditions of 40 droplets and a droplet interval of 5 μm. The channel size of the other structure and the coating conditions on the structure were the same as in Example 1. The coating conditions, the rectangular size inscribed by the semiconductor material presence region and its aspect ratio, and the evaluation of Id are the results of a FET with a channel size of Cx 350 μm and Cy 250 μm. The other conditions and evaluations were the same as in Example 1, and the coating conditions, measurement results, and evaluation results are shown in Table 1.

[0136] Example 5 In Example 5, the channel size Cx of one of the adjacent structures was 350 μm, Cy was 250 μm, the number of droplets was 20, and the droplet interval was 15 μm. The channel size of the other structure and the coating conditions on the structure were the same as in Example 1. The distance between the adjacent structures was 450 μm in the inkjet coating direction Sx and 350 μm in the coating width direction Sy. The coating conditions, the rectangular size inscribed by the semiconductor material existing region and its aspect ratio, and the evaluation of Id are the results of a FET with a channel size of Cx 350 μm and Cy 250 μm. The other conditions and evaluations were the same as in Example 1, and the coating conditions, measurement results, and evaluation results are shown in Table 1.

[0137] Comparative Example 1 In Comparative Example 1, inkjet coating is the same as in Example 5, except that the substrate and head are stopped while the inkjet coating is performed. In other words, the specified number of droplets are simply discharged to the same location while stopped, and there is no concept of inkjet droplet spacing. The coating conditions, the rectangular size inscribed by the semiconductor material presence area and its aspect ratio, and the evaluation of Id are the results of a FET with channel sizes of Cx 350 μm and Cy 250 μm. The other conditions and evaluations are the same as in Example 1, and the coating conditions, measurement results, and evaluation results are shown in Table 1.

[0138] Comparative Example 2 In Comparative Example 2, coating was performed under the same conditions as Comparative Example 1, except that the number of droplets was 30. The coating conditions, the size of the rectangle inscribed by the semiconductor material region and its aspect ratio, and the evaluation of Id are the results of a FET with channel sizes of Cx 350 μm and Cy 250 μm. The other conditions and evaluations were the same as in Example 1, and the coating conditions, measurement results, and evaluation results are shown in Table 1.

[0139] [Table 1]

[0140] In Example 1, the substrate is fixed and inkjet coating is performed while the head is moving, so the concept of droplet spacing arises compared to a state in which the substrate and head are stationary. By providing droplet spacing, the aspect ratio is 1.27, but even if the droplet shape is changed, the variation in Id value is small, and it is clear that a good FET is obtained without affecting the characteristics.

[0141] In Example 2, the aspect ratio is changed compared to Example 1. In Example 1, the droplet spacing and number of droplets are controlled only in one row in the coating direction, and while it is possible to control the shape in the coating direction, the control range in the coating width direction is narrow. In contrast, by providing two heads and shifting the heads by a specified distance in the coating width direction, it becomes possible to provide droplet spacing in the coating width direction as well (two rows), and it becomes possible to select a droplet shape that is particularly wide in the coating width direction.

[0142] From the results of Example 3, it can be seen that according to the method of the present invention, even when the channel regions of adjacent structures are different, by selecting different numbers of droplets and droplet spacing, it is possible to cover each channel region and prevent the merged droplets from interfering with each other.

[0143] In Example 4, the average value of Id is about twice as large as that in Example 3. In other words, even for FETs with the same channel length and channel width, by forming coalesced droplets under different application conditions, a difference in CNT density occurs on the channel region, making it possible to select the average Id value. As a result, for example, as described in the second embodiment, when there is some variation in the physical quantity of the structure and the Id value of the FET also varies, it becomes possible to reduce the variation in Id by controlling the CNT density according to the amount of variation in the physical quantity.

[0144] In Example 5, the area in which the combined droplets are formed outside the channel region is smaller than in Example 3. In other words, ink loss can be reduced by selecting the application conditions.

[0145] Furthermore, for example, if a FET with an average Id of 200 μA is desired, in a coating method in which the aspect ratio of the combined droplets cannot be selected as in Comparative Example 1, the combined droplet size can only be reduced by simply changing the number of droplets, and the combined droplets will not be able to cover the entire channel, resulting in a very large variation in Id value due to the coffee ring described above. Therefore, when the channel size Cx ≠ Cy, it becomes necessary to change the ink concentration. Furthermore, when coating a structure with different channel sizes, there are cases where it is not possible to form the channel in a single coating.

[0146] Furthermore, for example, when an FET with an average Id of 300 μA is desired, in Comparative Example 2, the only way is to simply increase the size of the coalesced droplets by the number of droplets, so that the coalesced droplets interfere with the coalesced droplets on the adjacent structures, resulting in a distorted droplet shape. This causes variation in the CNT density formed on the channel. This corresponds to the result of drawing rectangles with parallel sides in the application (X) direction and in the application (Y) direction perpendicular to the application for adjacent FETs so as to inscribe the presence areas of the respective semiconductor materials, resulting in the rectangles overlapping. Therefore, it becomes necessary to increase Sx or Sy, which increases the circuit size. If the circuit size increases, it will affect the manufacturing efficiency and will be difficult to apply to product applications that require small sizes.

[0147] These problems can be solved by applying the present invention. In other words, to obtain FETs with Id values ​​of 200 μA and 300 μA by forming semiconductor layers with different CNT densities on the same structure, if the conditions of Examples 1 and 4 are applied, it is possible to form a FET with little variation in Id even if the structure pitch is Sx 450 μm and Sy 350 μm.

[0148] In this way, the aspect ratio of the combined droplets can be controlled by selecting the coating conditions (number of droplets, droplet interval) in the present invention, which allows the channel region to be covered without waste, leading to reduced ink loss, smaller integrated circuits, and thus smaller wireless communication devices. [Explanation of symbols]

[0149] 1: Substrate 2: Lower conductive film 3: Gate electrode 4: Gate insulation layer 5: Semiconductor materials 6: Semiconductor layer 7: Upper conductive film 8: Source electrode 9: Drain electrode 10: Structure 11: Alignment mark 12:Droplet 13: Coalescing droplet 14: Channel region 15: Height of coalesced droplets 16: Rectangle inscribed in the region where semiconductor material exists 20: Stage 21: Camera 22: Inkjet head 23:Longitudinal 24: Inkjet head bottom 25: Nozzle 30: Gate electrode width 31: Length of gate electrode 32: Distance between source and drain electrodes 33: Length of the source electrode and drain electrode in the direction parallel to the gate electrode 34: Width of overlapping portion between gate electrode and source electrode and / or drain electrode 35: Gate electrode thickness 36: Thickness of gate insulating layer 37: Thickness of source and drain electrodes 41a to 41f: transistors 42a to 42f: Transistors 43a to 43i: transistors 44a to 44d: Transistors

Claims

1. 1. A method for fabricating a plurality of field effect transistors on a surface of a substrate, comprising the steps of: inkjet applying a semiconductor material; The inkjet coating is performed while moving an inkjet head relative to the substrate. For each location on the substrate where a field effect transistor is to be formed, The number of droplets and the interval between droplets are changed according to predetermined conditions. A method for manufacturing a field effect transistor.

2. the step of ink-jet-coating the semiconductor material is a step of forming a plurality of structures including at least one of a gate electrode, a source electrode, and a drain electrode, and then ink-jet-coating the semiconductor material onto each of the structures; The inkjet coating is performed for each structure while changing the number of droplets and the interval between droplets according to predetermined conditions. A method for producing a field effect transistor according to claim 1.

3. 3. The method for manufacturing a field effect transistor according to claim 2, wherein the plurality of structures include two or more types of structures each having a channel region formed therein that is different in size, and the number of droplets and the droplet interval are changed according to the size of the channel region.

4. 4. The method for producing a field effect transistor according to claim 2, wherein the inkjet coating is performed while moving the inkjet head relative to the substrate in a longitudinal direction of a channel region to be formed in the structure.

5. 5. The method for producing a field effect transistor according to claim 2, wherein at least a portion of the source electrodes and the drain electrodes are arranged in a staggered manner.

6. Prior to the inkjet coating, measuring a physical quantity based on at least one of the gate electrode, source electrode, and drain electrode formed, at each of the plurality of structures or at a representative point; correcting the number of droplets and the interval between droplets to be applied to each structure based on the measured physical quantity of each structure; The method for producing a field effect transistor according to any one of claims 2 to 5, comprising:

7. The method for producing a field effect transistor according to any one of claims 1 to 6, wherein the semiconductor material includes at least one selected from the group consisting of an organic semiconductor, a carbon nanotube, graphene, and a fullerene.

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