Low-power cryo-CMOS circuits with non-volatile threshold voltage offset compensation

Abstract

A system and method relating to a low-power cryo-CMOS circuit with non-volatile threshold voltage offset compensation is provided. The system includes a plurality of devices configured to operate in a cryogenic environment, wherein a first distribution of threshold voltages of the plurality of devices has a first value representing a measure of threshold voltage spread. The system further includes control logic coupled to each of the plurality of devices, the control logic configured to change the threshold voltage of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value representing a lower variation between the threshold voltages of the plurality of devices.

Description

[Background technology]

[0001] Semiconductor-based integrated circuits used in electronic devices, such as digital processors, contain digital circuits based on complementary metal-oxide semiconductor (CMOS) technology. A further approach to the use of processors and related components based on CMOS technology is the use of superconducting logic-based devices. Superconducting logic-based devices can also be used to process quantum information, such as qubits. Summary of the Invention

[0002] In one aspect, the disclosure relates to a system including a plurality of devices configured to operate in a cryogenic environment, a first distribution of threshold voltages of the plurality of devices having a first value indicative of a measure of a threshold voltage spread, the system may further include control logic coupled to each of the plurality of devices, the control logic configured to modify the threshold voltages of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value indicative of the measure of the threshold voltage spread, the second value representing a lower variation between the threshold voltages of the plurality of devices.

[0003] In another aspect, the present disclosure relates to a method in a system having a plurality of devices with associated threshold voltages, the method may include determining a variation among threshold voltages of the plurality of devices while operating an integrated circuit in a cryogenic environment, each of the plurality of devices having a floating gate, the method may further include modifying the threshold voltages of at least a subset of the plurality of devices by (1) injecting charge into the respective floating gates or (2) removing charge from the respective floating gates, such that the variation among the threshold voltages of the plurality of devices is reduced.

[0004] In yet another aspect, the disclosure relates to a system including a first integrated circuit having quantum devices including a plurality of qubit gates, the quantum devices configured to operate at a cryogenic temperature. The system may further include a second integrated circuit configured to operate at the cryogenic temperature, the first integrated circuit coupled to the second integrated circuit. The second integrated circuit may include a plurality of devices, a first distribution of threshold voltages of the plurality of devices having a first value indicative of a measure of a threshold voltage spread. The second integrated circuit may further include control logic coupled to each of the plurality of devices, the control logic configured to change the threshold voltage of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value indicative of a measure of the threshold voltage spread, the second value representing a lower variation between the threshold voltages of the plurality of devices.

[0005] This Summary is provided to introduce some concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. [Brief description of the drawings]

[0006] The present disclosure is not limited in the accompanying drawings, which are illustrated by way of example, and in which like reference numerals refer to like elements, and in which elements are illustrated for simplicity and clarity and have not necessarily been drawn to scale. [Figure 1] 1 illustrates a device with threshold voltage offset compensation according to an example. [Diagram 2] 1 illustrates another device with threshold voltage offset compensation according to an example. [Diagram 3] 1 illustrates yet another device with threshold voltage offset compensation, according to an example. [Figure 4] 1 illustrates a system including a device with threshold voltage offset compensation according to an example. [Diagram 5] 1 shows a histogram illustrating the distribution of threshold voltages before and after offset compensation. [Figure 6] 1 shows a flow chart of a method according to an example. [Figure 7] 1 illustrates a system for controlling quantum bits, according to an example. [Figure 8] 1 illustrates a common substrate containing a cryogenic CMOS control chip, a qubit chip, and a resonator chip, according to an example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Modern computing technology is limited by the power dissipated and heat generated by computation, primarily with complementary metal-oxide semiconductor (CMOS) field-effect transistors. The power consumed by a transistor (P) is divided into a static (leakage) component and a dynamic component associated with the charging and discharging of device and interconnect capacitances C (P=CV 2 f), where V is voltage and f is the clock frequency. Many processors and memory subsystems limit the clock rate to keep power consumption at a manageable level.

[0008] In data center applications, one possible approach to address power consumption is to cool transistors, thereby first reducing their static leakage (by freezing the mobile carriers and the thermally activated transport in the subthreshold region), and then by taking advantage of the increased carrier mobility that results from the suppression of electron-photon scattering when the temperature is reduced. The increased mobility leads to a steeper transition between the on and off states of the transistor, narrowing the supply voltage required to cover the device operating range. Cryogenic operation offers further dynamic power savings by reducing the supply needs to suppress the subthreshold swing, i.e., the thermally activated transport that remains when the transistor is biased below threshold.

[0009] However, cryocomputing introduces at least two challenges. First, the threshold voltage V TH rises and a higher supply voltage V DD This threshold voltage V TH The increase in V can be compensated for to some extent by adjusting the dopant concentration and dielectric thickness during fabrication at the foundry. However, such transistors do not perform as well at ambient temperatures that are not cryogenic. Second, and much more limiting, the threshold voltage V across the transistors is TH The variation in threshold voltage V TH This means that the power supply voltage can only be reduced as far as allowed by the variation in Vth = 1.0; that is, a sufficient voltage swing is required to ensure that all transistors can be switched from the fully off to the fully on state. Cryogenic cooling increases carrier mobility by suppressing photon scattering, but atomic-scale disorder increases scattering and the threshold voltage Vth across the die. TH This can lead to the creation of offset charges that cause large variations in threshold voltage V. Furthermore, as temperatures are lowered and device feature sizes are reduced, the threshold voltage fluctuations become larger. These limitations mean that in many situations, cryogenic cooling of CMOS devices is generally not a viable approach to net power savings, given the power cost to produce the cooling. However, the threshold voltage V TH If the offset charge issue could be addressed so that the distribution could be made tighter, the increased mobility and increased transconductance at low temperatures could lead to significant power savings.

[0010] A particular example of the present disclosure seeks to address the variation in threshold voltage of transistors by actively compensating for offset charges at cryogenic temperatures. To this end, various mechanisms may be used, including Fowler-Nordheim tunneling (FNT) and hot carrier injection (HCI). An example FNT process may involve tunneling charge through a thin dielectric by application of a large voltage bias (e.g., several volts). An electric field may also be added to the gate capacitance by creating carriers with energies above the band gap of the dielectric, effectively enabling over-barrier transport. These hot carrier states can be created with a large electric field in the FET channel, injecting carriers into the gate capacitance with energies well above the Fermi level (in the deep overdrive limit). Both through-barrier (FNT) and over-barrier (HCI) processes can be used to non-volatilely modify the charge on a floating gate capacitor. Thus, in such examples, the charge state remains even without an external power source after charge is added or removed.

[0011] FIG. 1 illustrates a device 100 with threshold voltage offset compensation according to an example. The device 100 may be formed on a substrate 102. The device 100 may further include a p-type region 104, an n-type region 106, and another n-type region 108. In this example, the device 100 is formed to function as an NPN transistor. However, the device 100 may be another type of transistor (e.g., a PNP transistor), a thyristor, a thermistor, or any other semiconductor switch or device operated in a manner similar to a transistor. Furthermore, the device 100 may be a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), an insulated gate field effect transistor (IGFET), or any other type of transistor. The device 100 may also be formed using semiconductor processing steps including the formation of various layers as part of a wafer that is separated into dies that are then packaged in the form of an integrated circuit package. The semiconductor processing steps may include the use of techniques such as plasma enhanced vapor deposition (PVD), chemical vapor deposition (CVD), dry or wet etching, and other such techniques. Using such techniques, or other suitable semiconductor fabrication techniques, features including sources, drains, and gates may be formed.

[0012] Continuing to refer to FIG. 1 , a stack 120 may be formed. The stack 120 may include a control gate 122 and a floating gate 124. The stack 120 may further include a control dielectric layer 126 that may be formed between the control gate 122 and the floating gate 124. The stack 120 may further include a tunnel dielectric layer 128 that may be formed between the floating gate 124 and a top surface of the channel 110. The control gate 122 may be formed using polysilicon, a metal, a metal alloy, or other suitable material. The floating gate 124 may function as a layer configured to store a controllable amount of charge. Materials such as silicon nitride, polysilicon, silicon, or germanium may be used. In certain examples, nanocrystals may be used to store the charge. The control dielectric layer 126 may be formed using any suitable dielectric material. In one example, the control dielectric layer 126 may be formed as an oxide / nitride / oxide (ONO) stack. The tunnel dielectric layer 128 may also be formed using any suitable dielectric material, such as silicon dioxide or silicon nitride. A high-k dielectric stack may also be used. The dimensions of the various layers and regions are not drawn to scale, and in one example, the tunnel dielectric layer 128 may be configured to be thin enough that stored electrons or holes may tunnel through the tunnel dielectric layer 128 under application of appropriate voltages to the various terminals of the device 100. Although not shown in FIG. 1, sidewalls may be formed adjacent each side of the stack 120. Although FIG. 1 shows a particular number and type of layers formed as part of the stack 120, the stack 120 may include additional layers or fewer layers, if desired.

[0013] 1, device 100 may have several terminals that may be coupled to receive different voltages. As an example, device 100 may have: (1) a source voltage (V S) that is coupled to the drain of device 100 (e.g., n-type region 108); D ) that is coupled to a control gate (e.g., control gate 122) of device 100; G ), and (4) a trimming voltage (V TRIM ) in this example. TRIM ) can be supplied via an external circuit and used to initially adjust the offset charge. TRIM ) may be used to add or subtract charge from the gate capacitance via FNT and / or HCl. In one example, this additional connection may be located on a separate routing layer and connected to the transistor through a via or other routing structure formed in a substrate associated with device 100.

[0014] With respect to the operation of device 100, appropriate voltages coupled through the terminals of device 100 may be used to inject charge into or remove charge stored on floating gate 124. As an example, in a first phase, a high trimming voltage (V TRIM) (e.g., a few volts) is applied to the control gate 122 and simultaneously a high drain voltage (V D ) may be applied to the drain region of device 100. As a result, electrons may be injected into floating gate 124 during the first phase. In a second phase, holes formed in other parts of device 100 may be removed. As an example, a certain voltage (lower than the trimming voltage applied during the first phase) may be applied to control gate 122 and simultaneously a negative drain voltage (V D) may be applied to the drain region of device 100. As a result, during the second phase, holes formed in certain regions of device 100 may be removed. The second phase may only be required if device 100 is formed as a semiconductor-on-insulator (SOI) device, because if device 100 were formed as a bulk device, the holes could be removed through the well electrode.

[0015] Trimming voltage (V TRIM To reduce the capacitance effects of routing structures for routing the trim voltage (V), such structures may be disconnected from device 100 after the trim operation. Additionally, control circuitry used for the trim operation may also be permanently disconnected from device 100. As an example, e-fuses or other such techniques may be used to permanently disconnect the trim voltage (V) from device 100 after the trim operation is completed. TRIM ) can burn out the connection to receive it.

[0016] FIG. 2 illustrates a device 200 with threshold voltage offset compensation according to an example. Similar to device 100, device 200 may be formed on a substrate 202. Device 200 may further include a p-type region 204, an n-type region 206, and another n-type region 208. In this example, device 200 is formed to function as an NPN transistor. However, device 200 may be other types of transistors (e.g., PNP transistors), thyristors, thermistors, or any other semiconductor switch or device operated in a manner similar to a transistor. Furthermore, device 200 may be a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), an insulated gate field effect transistor (IGFET), or any other type of transistor. Device 200 may also be formed using semiconductor processing steps including the formation of various layers as part of a wafer that is separated into dies that are then packaged in the form of an integrated circuit package. Semiconductor processing may include the use of techniques such as plasma enhanced vapor deposition (PVD), chemical vapor deposition (CVD), dry or wet etching, and other such techniques. Using such techniques or other suitable semiconductor manufacturing techniques, features including sources, drains, and gates may be formed.

[0017] 2, a stack 220 may be formed. The stack 220 may include a control gate 222 and a floating gate 224. The stack 220 may further include a control dielectric layer 226 that may be formed between the control gate 222 and the floating gate 224. The stack 220 may further include a tunnel dielectric layer 228 that may be formed between the floating gate 224 and a top surface of the channel 210. The control gate 222 may be formed using polysilicon, a metal, a metal alloy, or other suitable material. The floating gate 224 may function as a layer configured to store a controllable amount of charge. Materials such as silicon nitride, polysilicon, silicon, or germanium may be used. In certain examples, nanocrystals may be used to store the charge. The control dielectric layer 226 may be formed using any suitable dielectric material. In one example, the control dielectric layer 226 may be formed as an oxide / nitride / oxide (ONO) stack. The tunnel dielectric layer 228 may also be formed using any suitable dielectric material, such as silicon dioxide or silicon nitride. A high-k dielectric stack may also be used. The dimensions of the various layers and regions are not drawn to scale, and in one example, the tunnel dielectric layer 228 may be configured to be thin enough that stored electrons or holes may tunnel through the tunnel dielectric layer 228 under application of appropriate voltages to the various terminals of the device 200. Although not shown in FIG. 2, sidewalls may be formed adjacent each side of the stack 220. Although FIG. 2 shows a particular number and type of layers formed as part of the stack 220, the stack 220 may include additional layers or fewer layers, if desired.

[0018] 2, device 200 may have several terminals that may be coupled to receive different voltages. As an example, device 200 may have: (1) a source voltage (V S), (2) a terminal for receiving a drain voltage (V D ), and (3) a terminal for receiving a gate voltage (V G ) In this example, a control gate 222 is used to first set charge via tunneling at a high voltage, and then the same gate is used for standard transistor gating at a lower voltage.

[0019] With respect to the operation of device 200, appropriate voltages coupled through the terminals of device 200 may be used to inject charge into or remove charge stored on floating gate 224. As an example, in a first phase, a high voltage (e.g., several volts) is applied to control gate 222 and simultaneously a high drain voltage (V D ) may be applied to the drain region of device 200. As a result, electrons may be injected into floating gate 224 during the first phase. In a second phase, holes formed in other parts of device 200 may be removed. As an example, a certain voltage (lower than the voltage applied to the control gate during the first phase) may be applied to control gate 222 while a negative drain voltage (V D ) may be applied to the drain region of device 200. As a result, during the second phase, holes formed in certain regions of device 200 may be removed. The second phase may only be required if device 200 is formed as a semiconductor-on-insulator (SOI) device, because if device 200 were formed as a bulk device, the holes could be removed through the well electrode.

[0020] FIG. 3 illustrates a device 300 with threshold voltage offset compensation according to an example. The device 300 may be formed on a substrate 302. The device 300 may further include a p-type region 304, an n-type region 306, and another n-type region 308. In this example, the device 300 is formed to function as an NPN transistor. However, the device 300 may be another type of transistor (e.g., a PNP transistor), a thyristor, a thermistor, or any other semiconductor switch or device operated in a manner similar to a transistor. Furthermore, the device 300 may be a metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), an insulated gate field effect transistor (IGFET), or any other type of transistor. The device 300 may also be formed using semiconductor processing steps including the formation of various layers as part of a wafer that is separated into dies that are then packaged in the form of an integrated circuit package. The semiconductor processing steps may include the use of techniques such as plasma enhanced vapor deposition (PVD), chemical vapor deposition (CVD), dry or wet etching, and other such techniques. Using such techniques, or other suitable semiconductor fabrication techniques, features including sources, drains, and gates may be formed.

[0021] Continuing to refer to FIG. 3, a stack 320 may be formed. The stack 320 may include a control gate 322 and a floating gate 324. The stack 320 may further include a control dielectric layer 326 that may be formed between the control gate 322 and the floating gate 324. The stack 320 may further include a tunnel dielectric layer 328 that may be formed between the floating gate 324 and a top surface of the channel 310. Sidewalls 332 and 334 may be formed adjacent to the sidewalls of the stack 320. Additionally, a second, split control gate 330 may be formed. The control gate 322 and the split control gate 330 may be formed using polysilicon, metal, metal alloy, or other suitable material. The floating gate 324 may function as a layer configured to store a controllable amount of charge. Materials such as silicon nitride, polysilicon, silicon, or germanium may be used. In certain examples, nanocrystals may be used to store the charge. The control dielectric layer 326 may be formed using any suitable dielectric material. In one example, the control dielectric layer 326 may be formed as an oxide / nitride / oxide (ONO) stack. The tunnel dielectric layer 328 may also be formed using any suitable dielectric material, such as silicon dioxide or silicon nitride. A high-k dielectric stack may also be used. The dimensions of the various layers and regions are not drawn to scale, and in one example, the tunnel dielectric layer 328 may be configured to be thin enough that stored electrons or holes may tunnel through the tunnel dielectric layer 328 under application of appropriate voltages to the various terminals of the device 300. Although FIG. 3 shows a particular number and type of layers formed as part of the stack 320, the stack 320 may include additional layers or fewer layers, if desired.

[0022] 3, device 300 may have several terminals that may be coupled to receive different voltages. As an example, device 300 may have: (1) a source voltage (V S) that is coupled to the drain of device 300 (e.g., n-type region 308); D ) that is coupled to a first control gate (e.g., control gate 322) of device 300; G ), and (4) a terminal for receiving a trimming voltage (V TRIM ) in this example. TRIM ) can be supplied via an external circuit and used to initially adjust the offset charge. TRIM ) can be used to add or remove charge from the gate capacitance via FNT and / or HCl. In this example, control gate 330 is used to first set the charge via tunneling at a high voltage, and then control gate 322 is used for standard transistor gating at a lower voltage.

[0023] With respect to the operation of device 300, appropriate voltages coupled through the terminals of device 300 may be used to inject charge into or remove charge stored on floating gate 324. As an example, in a first phase, a high trimming voltage (V TRIM) (e.g., a few volts) is applied to the control gate 330, and at the same time a high drain voltage (V D ) may be applied to the drain region of device 300. As a result, electrons may be injected into floating gate 324 during the first phase. In a second phase, holes formed in other parts of device 300 may be removed. As an example, a certain voltage (lower than the trimming voltage applied during the first phase) may be applied to control gate 330 while a negative drain voltage (V D) may be applied to the drain region of device 300. As a result, during the second phase, holes formed in certain regions of device 300 may be removed. The second phase may only be required if device 300 is formed as a semiconductor-on-insulator (SOI) device, because if device 300 were formed as a bulk device, the holes could be removed through the well electrode.

[0024] FIG. 4 illustrates a system 400 having control logic 450 associated with threshold voltage offset compensation, according to an example. System 400 may include one or more of a processor, memory, CPU, GPU, FPGA, or any other type of device used in an information processing system. In this example, system 400 may include one or more integrated circuits, each of which may be packaged as a single integrated circuit. At least a subset of the integrated circuits included in system 400 may include any of the types of devices described with respect to FIG. 1, FIG. 2, and FIG. 3. System 400 may include processing core(s) 410, volatile memory 420, non-volatile memory 430, other blocks 440, and control logic 450.

[0025] Continuing to refer to FIG. 4, control logic 450 may include components configured to control threshold voltage offset compensation. In this example, control logic 450 may include a finite state machine (FSM) 452, a control & status register 454, and a charge pump 456. FSM 452 may be configured to control charge pump 456 via bus 455. Control & status register 454 may include registers that may be written to and read by FSM 452. As an example, the control register may include fields that define information regarding the type of voltage waveform(s) to be generated by charge pump 456. Thus, charge pump 456 may be configured to generate voltage waveforms under the control of FSM 452. Additionally, charge pump 456 may be configured to generate multiple voltage waveforms simultaneously such that appropriate voltages may be coupled to various terminals associated with device 100, device 200, or device 300. 4 illustrates system 400 as including a particular number of components, system 400 may include additional or fewer components. Also, instead of FSM 452, charge pump 456 may be controlled using instructions programmed into a non-volatile memory, such as a NOR flash memory.

[0026] Circuits built from these devices can operate in standard mode (without offset trimming) as well as in a low power mode where the supply voltage is reduced after a trimming procedure. This procedure may involve measuring the threshold voltage of the transistor and adding or removing charge from the floating gate capacitance to adjust the threshold voltage to some predetermined value. The trimming procedure may be performed using control logic 450. In this example, all transistors in the circuit undergo this calibration, but the process need only be performed after the initial cooling of the chip to cryogenic temperatures. At a sufficiently low temperature, the calibrated charge on the floating gate can remain indefinitely. The calibration process may be performed as fast as possible for convenience, but may also accommodate serial low clock rate execution if power consumption must be minimized.

[0027] 4, only a subset of the components of system 400 may include devices with threshold voltage offset compensation. Also, volatile memory 420 may have devices with threshold voltages designed differently than the devices included in non-volatile memory 430. Thus, different components, whether on the same substrate or on different substrates, may have different threshold voltage offset compensation.

[0028] FIG. 5 illustrates histograms 510 and 550 showing the distribution of threshold voltages of devices (e.g., either device 100, device 200, or device 300) before and after offset compensation. In this example, the vertical axis of each of histograms 510 and 550 shows the number of devices that are subject to threshold voltage offset compensation. In one example, the number of devices can correspond to all of the transistors on an integrated circuit. Alternatively, the number of devices can correspond to a portion of an integrated circuit. By actively adjusting the threshold voltages of the transistors, nearly all of the transistors in the circuit have similar threshold voltages. If the distribution of threshold voltages can be narrowed, the power supply voltage can be reduced and dynamic power consumption can be reduced by an order of magnitude of square. In one example, a first distribution of threshold voltages of the devices can have a first value that indicates a measure of the spread of the threshold voltages. Using control logic 450 of FIG. 4, the threshold voltages of each of the devices can be changed such that the first distribution is changed to a second distribution having a second value of the measure of the threshold voltage spread, the second value indicating a lower variation between the threshold voltages of the devices. The measure of spread may be selected from among the variance, the standard deviation, or the range.

[0029] FIG. 6 illustrates a flow chart 600 of a method according to an example. Step 610 can include determining the variation between threshold voltages of a plurality of devices while operating an integrated circuit in a cryogenic environment, each of the plurality of devices having a floating gate. An initial part of this process can involve measuring a transistor threshold voltage for each of the devices. Control logic 450 can be used to measure the threshold voltages. Taking these measurements can determine a measure of the spread of the distribution of threshold voltages for the plurality of devices. The measure of spread can be selected from among variance, standard deviation, or range. In an example, instead of measuring the threshold voltage of each device, a surrogate for the variation of threshold voltages can be used. As an example, control logic 450 can be configured to measure an error rate associated with a signal processed by the device. By performing an error rate analysis across a large number of circuits, a correlation between the variation of threshold voltages and the error rate can be established. Thus, the error rate can be used as a surrogate as part of the step of determining the variation between threshold voltages.

[0030] Step 620 may include modifying the threshold voltages of at least a subset of the devices by (1) injecting charge into or (2) removing charge from the respective floating gates so that the variation between the threshold voltages of the devices is reduced. Depending on the device type (e.g., device 100, device 200, or device 300), the corresponding process described above may be used. To adjust the threshold voltage to some predetermined value, control logic 450 may be used to add or remove charge from the floating gate capacitance. In this example, all transistors in the circuit undergo this calibration, but the process need only be performed after the initial cooling of the chip to cryogenic temperatures. As explained above, advantageously, a smaller variation between the threshold voltages of the transistors may allow the power supply voltage to be reduced. This in turn may reduce the dynamic power consumption by the circuit by an order of magnitude of square.

[0031] In a particular example, the devices described herein can be included in a low-power cryogenic CMOS interface for controlling qubit gates. Controlling a quantum device requires the generation of a large number of static and dynamic voltage signals, ideally at cryogenic temperatures closely integrated with the quantum device. As used in this disclosure, the term "cryogenic temperature(s)" means any temperature below 300 Kelvin. This is a major challenge, given that the cryo-environment strongly constrains the power consumption of active electronics. Furthermore, it is also necessary to couple a large number of voltage signals to the qubit gates in the quantum computing device. This is because potentially thousands of wires need to be connected to the voltage sources to drive the qubit gates in the quantum computing device. Also, qubits have traditionally been controlled with room temperature pulse generators that must generate large signals that are attenuated in the cryostat. The power required to overcome this attenuation, and even more so to drive the cable impedance, is an impediment to scaling quantum computers.

[0032] A particular example described in this disclosure relates to a cryogenic control circuit and architecture for quantum computing devices. The control architecture includes an integrated circuit control chip including cryogenic control circuitry tightly integrated with the qubit plane. As an example, the control chip can be wire bonded or flip-chip mounted to the qubit plane. The control chip also stores charge on the capacitors (including the interconnect capacitance) to generate the voltage bias. A single digital-to-analog converter can be used to set the charge on each capacitor, which remains at cryo-temperatures for a long time due to the extremely low leakage paths at these temperatures. Refreshing the charge can be done periodically on a time scale commensurate with the qubit operation. Challenges related to heat arising from decay are addressed by providing a "charge shuffle" circuit that moves charge between the capacitors to generate voltage pulses. The tight integration between the cryogenic CMOS control chip and the qubit plane reduces capacitance as much as possible. This tight integration, for example through chip stack packaging techniques, can dramatically reduce capacitance, which can impact power consumption.

[0033] A qubit plane may include topological computing gates that may operate at about 20 millikelvin (~20mK). Quantum computing devices may process quantum information, such as qubits. Qubits may be implemented using a variety of physical systems, including photons, electrons, Josephson junctions, quantum dots, or heterostructures. A quantum state may be encoded as a spin orientation, a spin as part of a qubit, charge, energy, another aspect of an excitation stage, or a topological phase of a superconducting material. An example qubit may operate based on either a low frequency DC signal (e.g., bias current) or a high frequency radio frequency signal (e.g., 10 GHz signal), or a combination of both. In certain examples, microwave signals may be used to control a superconducting device, including, for example, the state of a quantum bit (qubit). Certain implementations of quantum bit (qubit) gates may require high frequency microwave signals.

[0034] FIG. 7 illustrates a system 700 for controlling qubits, according to an example. In this example, system 700 can include multiple stages, each of which can be configured to operate at a different temperature. Thus, system 700 can include stages 710, 730, and 750. Stage 710 can include components configured to operate at cryogenic temperatures (e.g., below 300 Kelvin). Stage 730 can include components configured to operate at temperatures below 300 Kelvin and up to 4 Kelvin. Stage 750 can include components configured to operate at or near 20 milliKelvin (mK). Stage 710 can include a microcontroller 712 (or microprocessor), a digital-to-analog converter (DAC) 714, a signal generator 716, and a measurement device 718. Microcontroller 712 can generate control signals configured to control the qubits and other aspects of system 700. The DAC 714 may receive digital control signals from the microcontroller 712 (or from other components) and convert them to analog form. These analog signals may then be transmitted to other stages as needed. The signal generator 716 may include microwave signal generators and other clock signal generators as needed. The measurement equipment 718 may include instrumentation such as a spectrum analyzer. In one example, the microcontroller 712 (or microprocessor), digital-to-analog converter (DAC) 714, signal generator 716, and measurement equipment 718 may each include the aforementioned devices to enable lowering the power consumed by such components.

[0035] Continuing to refer to FIG. 7, stage 730 may include components configured to interconnect stage 710 with stage 750 in a manner that reduces thermal load and enables efficient connection between components at room temperature and components at 20 milliKelvin (mK). Thus, in this example, stage 730 may include component 732, interconnect 734, interconnect 736, and interconnect 738. In one example, component 732 may be implemented as (one or more) high electron mobility transistor (HEMT) low noise amplifiers. Interconnects 734, 736, and 738 may be implemented as cables having conductors such as, for example, niobium and copper. These conductors may be insulated within the interconnects using a suitable dielectric material such as, for example, polyimide.

[0036] Still referring to FIG. 7, stage 750 may include coupler 752, readout multiplex 754, high-speed control multiplex 756, and qubit 760. Coupler 752 may couple a signal from a signal generator (e.g., signal generator 716) to readout multiplex 754. Coupler 752 may also direct reflected signals to component 732. Readout multiplex 754 and high-speed control multiplex 756 may be implemented on a single control chip (sometimes referred to as a cryogenic control CMOS chip). In one example, readout multiplex 754 may be implemented using a superconducting material, such as niobium, on an inert substrate, such as sapphire. The readout multiplex 754 chip may include a plurality of inductive, capacitive, and resistive elements of suitable size to form a bank (or banks) of resonators. At cryogenic temperatures, the resonator circuits become superconducting, producing resonators with high Q values. This may provide an efficient low-loss frequency multiplexing mechanism. In one example, a cryogenic CMOS control chip (e.g., an ASIC fabricated using semiconductor technology such as CMOS) may be mounted on the same substrate as the quantum bits (e.g., quantum bit 760) and configured to operate at the same cryogenic temperature as the quantum bits (e.g., 20 mK).

[0037] 8 illustrates a common substrate 800 including a cryogenic CMOS control chip 810, a qubit chip 850, and a resonator chip 880, according to an example. The cryogenic CMOS control chip 810 may be coupled to contact pads (e.g., contact pads 822 and 824) via wire bonds (e.g., wire bonds 812 and 814). The cryogenic CMOS control chip 810 may further be coupled to contact pads (e.g., contact pads 826 and 828) via wire bonds (e.g., wire bonds 816 and 818). The cryogenic CMOS control chip 810 may further be coupled to other contacts (e.g., contacts 834 and 836) via wire bonds (e.g., wire bonds 830 and 832). The qubit chip 850 may be coupled to contact pads (e.g., contact pads 856 and 858) via wire bonds (e.g., wire bonds 852 and 854). Qubit chip 850 may be coupled to resonator chip 880 via wire bonds (e.g., wire bonds 860 and 862). Resonator chip 880 may be coupled to contacts (e.g., contacts 890 and 892) via wire bonds (e.g., wire bonds 882 and 884). While this example shows close integration between the control chip and the qubits via wire bonds, other techniques may be used. As an example, the control chip may be flip-chip bonded to a substrate with the qubits. Alternatively, package-on-package, system-in-package, or other multi-chip assemblies may be used.

[0038] Although the above description refers to quantum devices, the systems described herein can be implemented to support any service or application that can be provided via a combination of computing, networking, and storage resources, such as via a data center or other infrastructure for delivering the service or application. The described aspects can also be implemented in a cloud computing environment. Cloud computing can refer to a model that enables on-demand network access to a shared pool of configurable computing resources. For example, cloud computing can be deployed in a market to provide ubiquitous and convenient on-demand access to a shared pool of configurable computing resources. The cloud computing model can be configured with various characteristics, such as on-demand self-service, broad network access, resource pooling, rapid elasticity, and measured service. The cloud computing model may be used to expose various service models such as, for example, Hardware as a Service ("HaaS"), Software as a Service ("SaaS"), Platform as a Service ("PaaS"), and Infrastructure as a Service ("IaaS"), etc. The cloud computing model may also be deployed using different deployment models such as, for example, private cloud, community cloud, public cloud, and hybrid cloud.

[0039] In summary, in one aspect, the present disclosure relates to a system including a plurality of devices configured to operate in a cryogenic environment, a first distribution of threshold voltages of the plurality of devices having a first value indicative of a measure of a threshold voltage spread, the system may further include control logic coupled to each of the plurality of devices, the control logic configured to modify the threshold voltages of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value indicative of the measure of the threshold voltage spread, the second value representing a lower variation between the threshold voltages of the plurality of devices.

[0040] The measure of spread may be selected from among a variance, a standard deviation, or a range. Each of the plurality of devices may have a floating gate. The system may include a charge pump, each of the plurality of devices having a terminal for receiving a trimming voltage via the charge pump, and the control logic is further configured to modify a threshold voltage of each of the plurality of devices by either injecting charge into or removing charge from the floating gate.

[0041] The system may include a charge pump, each of the plurality of devices having a gate terminal for receiving a voltage via the charge pump, and the control logic further configured to alter a threshold voltage of each of the plurality of devices by either injecting charge onto or removing charge from the floating gate.

[0042] The system may include a charge pump, each of the plurality of devices having a terminal coupled to the split gate for receiving a trimming voltage via the charge pump, and the control logic may be further configured to modify a threshold voltage of each of the plurality of devices by either injecting charge into or removing charge from the floating gate. The control logic may be further configured to determine the threshold voltage of each of the plurality of devices.

[0043] In another aspect, the present disclosure relates to a method in a system having a plurality of devices with associated threshold voltages, the method may include determining a variation among threshold voltages of the plurality of devices while operating an integrated circuit in a cryogenic environment, each of the plurality of devices having a floating gate, the method may further include modifying the threshold voltages of at least a subset of the plurality of devices by (1) injecting charge into the respective floating gates or (2) removing charge from the respective floating gates, such that the variation among the threshold voltages of the plurality of devices is reduced.

[0044] Determining the variation may include determining a measure of spread selected from among a variance, a standard deviation, or a range. Determining the variation between threshold voltages may include determining an error rate associated with an operation associated with the integrated circuit. Determining the variation between threshold voltages may include determining the threshold voltages of each of the plurality of devices.

[0045] Altering the threshold voltage of each of the plurality of devices may include applying a voltage via a terminal for receiving a trimming voltage. Altering the threshold voltage of each of the plurality of devices may include applying a voltage via a gate terminal.

[0046] In yet another aspect, the disclosure relates to a system including a first integrated circuit having quantum devices including a plurality of qubit gates, the quantum devices configured to operate at a cryogenic temperature. The system may further include a second integrated circuit configured to operate at the cryogenic temperature, the first integrated circuit coupled to the second integrated circuit. The second integrated circuit may include a plurality of devices, a first distribution of threshold voltages of the plurality of devices having a first value indicative of a measure of a threshold voltage spread. The second integrated circuit may further include control logic coupled to each of the plurality of devices, the control logic configured to change the threshold voltage of each of the plurality of devices such that the first distribution is changed to a second distribution having a second value indicative of a measure of the threshold voltage spread, the second value representing a lower variation between the threshold voltages of the plurality of devices.

[0047] The measure of spread may be selected from among a variance, a standard deviation, or a range. Each of the plurality of devices may have a floating gate. The system may include a charge pump, each of the plurality of devices having a terminal for receiving a trimming voltage via the charge pump, and the control logic is further configured to modify a threshold voltage of each of the plurality of devices by either injecting charge into or removing charge from the floating gate.

[0048] The system may include a charge pump, each of the plurality of devices having a gate terminal for receiving a voltage via the charge pump, and the control logic further configured to alter a threshold voltage of each of the plurality of devices by either injecting charge onto or removing charge from the floating gate.

[0049] The system may include a charge pump, each of the plurality of devices having a terminal coupled to the split gate for receiving a trimming voltage via the charge pump, and the control logic may be further configured to modify a threshold voltage of each of the plurality of devices by either injecting charge into or removing charge from the floating gate. The control logic may be further configured to determine the threshold voltage of each of the plurality of devices.

[0050] It should be understood that the methods, modules, and components illustrated herein are merely exemplary. For example, without limitation, exemplary types of superconducting devices may include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), complex programmable logic devices (CPLDs), and the like.

[0051] Also, in an abstract but still definite sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Thus, two components combined herein to achieve a particular functionality can be viewed as being "associated" with one another such that the desired functionality is achieved, regardless of architecture or intermediate components. Similarly, two components so associated can also be viewed as being "operably connected" or "coupled" with one another to achieve the desired functionality.

[0052] Those skilled in the art will also recognize that the boundaries between the functions of the processes described above are merely exemplary, and that the functions of multiple processes may be combined into a single process and / or the functions of a single process may be distributed among additional processes, and that alternative embodiments may include multiple instances of a particular process, and that the order of processes may be altered in various other embodiments.

[0053] While the present disclosure provides illustrative examples, various modifications and variations can be made without departing from the scope of the present disclosure as set forth in the following claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Benefits, advantages, or solutions to problems discussed herein with respect to the illustrative examples are not intended to be construed as critical, necessary, or essential features or elements of any or all of the claims.

[0054] Additionally, the terms "a" or "an," as used herein, are defined as one or more than one. Moreover, the use of an introductory phrase, e.g., "at least one" or "one or more," in a claim should not be construed as implying that the introduction of another claim element with the indefinite article "a" or "an" limits a particular claim containing such introduced claim element to an invention containing only one of such elements, even if that same claim contains both the introductory phrase "one or more" or "at least one" and an indefinite article, e.g., "a" or "an." Similarly, the use of definite articles.

[0055] Unless otherwise indicated, terms such as "first" and "second" are used to arbitrarily distinguish between the elements that such terms describe, and thus are not necessarily intended to indicate a temporal or other priority of such elements.

Claims

1. 1. A system for interfacing with a qubit gate, comprising: a plurality of devices configured to operate in a cryogenic environment, each of the plurality of devices having a floating gate, a first distribution of threshold voltages of the plurality of devices having a first value indicating a measure of the spread of the threshold voltages; control logic coupled to each of the plurality of devices, the control logic configured to modify the threshold voltage of each of the plurality of devices by either injecting charge onto or removing charge from the floating gate such that the first distribution is changed to a second distribution having a second value of the measure of the spread of threshold voltages, the second value representing a lower variation between the threshold voltages of the plurality of devices; A system having

2. The system of claim 1 , wherein the measure of spread is selected from among a variance, a standard deviation, or a range.

3. 2. The system of claim 1, wherein the system comprises a charge pump, each of the plurality of devices having a terminal for receiving a trimming voltage via the charge pump, and the control logic is further configured to apply a voltage via the terminal for receiving a trimming voltage to change the threshold voltage of each of the plurality of devices.

4. 2. The system of claim 1, wherein the system comprises a charge pump, each of the plurality of devices having a gate terminal for receiving a voltage via the charge pump, and the control logic is further configured to apply a voltage via the gate terminal to modify the threshold voltage of each of the plurality of devices.

5. 2. The system of claim 1, wherein the system further comprises a charge pump, each of the plurality of devices having a terminal coupled to a split gate for receiving a trimming voltage via the charge pump, and the control logic further configured to apply a voltage via the terminal coupled to the split gate to modify the threshold voltage of each of the plurality of devices.

6. The system of claim 1 , wherein the control logic is further configured to determine a threshold voltage for each of the plurality of devices.

7. 1. A method in a system having a plurality of devices having associated threshold voltages, comprising: determining a variation between threshold voltages of the plurality of devices while operating the integrated circuit in a cryogenic environment, each of the plurality of devices having a floating gate; modifying threshold voltages of at least a subset of the plurality of devices by (1) injecting charge into or (2) removing charge from the respective floating gates such that variation among threshold voltages of the plurality of devices is reduced; How to have that.

8. The method of claim 7 , wherein the determining the variability comprises determining a measure of spread selected from among a variance, a standard deviation, or a range.

9. 8. The method of claim 7, wherein the determining the variation between the threshold voltages comprises determining an error rate associated with an operation associated with the integrated circuit.

10. The method of claim 7 , wherein the determining the variation between the threshold voltages comprises determining a threshold voltage for each of the plurality of devices.

11. The method of claim 7 , wherein the modifying the threshold voltage of each of the plurality of devices comprises applying a voltage via a terminal for receiving a trimming voltage.

12. The method of claim 7 , wherein the altering the threshold voltage of each of the plurality of devices comprises applying a voltage through a gate terminal.

13. a first integrated circuit having a quantum device including a plurality of qubit gates, the quantum device configured to operate at cryogenic temperatures; a second integrated circuit configured to operate at the cryogenic temperature, the first integrated circuit being coupled to the second integrated circuit, the second integrated circuit comprising: a plurality of devices, each of the plurality of devices having a floating gate, a first distribution of threshold voltages of the plurality of devices having a first value indicating a measure of the spread of the threshold voltages; and control logic coupled to each of the plurality of devices, the control logic configured to modify the threshold voltage of each of the plurality of devices by either injecting charge into or removing charge from the floating gate such that the first distribution is changed to a second distribution having a second value of the measure of the spread of threshold voltages, the second value representing a lower variation between the threshold voltages of the plurality of devices; a second integrated circuit having A system having

14. The system of claim 13 , wherein the measure of spread is selected from among a variance, a standard deviation, or a range.

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