Integrated circuit structure having linerless self-forming barrier - Patents.com

Abstract

To provide integrated circuit structures having linerless self-forming barriers, and methods of fabricating integrated circuit structures having linerless self-forming barriers.SOLUTION: An integrated circuit structure includes a dielectric material 152 above a substrate 150. An interconnect structure 154 / 156 is in a trench in the dielectric material 152. The interconnect structure 154A / 156A includes a conductive fill material 158A and a two-dimensional (2D) crystalline liner 160. The 2D crystalline liner 160 is in direct contact with the dielectric material 152 and with the conductive fill material 158A. The 2D crystalline liner 160 includes the same metal species as the conductive fill material 158A.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure are in the field of integrated circuit structures, and more particularly, integrated circuit structures having a linerless self-forming barrier. [Background technology]

[0002] Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features allows for an increased density of functional units on the limited area of ​​a semiconductor chip.

[0003] For example, shrinking transistor size allows an increased number of memory or logic devices to be integrated on a chip, resulting in the production of products with increased capacity. However, the push to ever greater capacity is not without challenges. The need to optimize the performance of each device is becoming increasingly important. In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more widely used as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on substrates, either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure. However, multi-gate transistors have not been able to be scaled without causing impacts. As the dimensions of these building blocks of microelectronic circuits decrease, and as the sheer number of building blocks manufactured in a given area increases, constraints on the semiconductor processes used to manufacture these building blocks become greater.

[0004] The performance of a thin film transistor (TFT) can vary depending on a number of factors. For example, the efficiency with which a TFT can operate can vary depending on the TFT's subthreshold swing, which characterizes the amount of change in gate-source voltage required to achieve a given change in drain current. A smaller subthreshold swing allows the TFT to be turned off with a lower leakage value when the gate-source voltage drops below the TFT's threshold voltage. A conventional theoretical lower limit at room temperature for a TFT's subthreshold swing is 60 millivolts per decade change in drain current.

[0005] Variabilities in traditional and currently known manufacturing processes may limit the ability to advance further, for example, to the 10 nanometer node or sub-10 nanometer node range, and as a result, the manufacture of functional components required for future technology nodes may require the introduction of new methods or the integration of new technologies into or replacement of current manufacturing processes. [Brief description of the drawings]

[0006] [Figure 1] A cross-sectional view of an interconnect structure is shown.

[0007] [Diagram 2] 1A-1D illustrate cross-sectional views of the formation of an interconnect structure having a linerless self-forming barrier according to one embodiment of the present disclosure.

[0008] [Figure 3A] 1 illustrates a cross-section of a thin film integrated circuit structure having a linerless self-forming barrier according to one embodiment of the present disclosure.

[0009] [Figure 3B] 1 illustrates a perspective cross-sectional view of an array of thin film integrated circuit structures having a linerless self-forming barrier according to one embodiment of the present disclosure, where the array is adjacent to a logic area.

[0010] [Figure 4A] 1 shows a cross-sectional view taken along the gate "width" of a planar thin film integrated circuit structure having a linerless self-forming barrier according to one embodiment of the present disclosure.

[0011] [Figure 4B] 1 shows a cross-sectional view taken along the gate "width" of a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure.

[0012] [Figure 4C] 1A-1D show perspective and straight line cross-sectional views of a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 4D] 1A-1D show perspective and straight line cross-sectional views of a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 4E] 1A-1D show perspective and straight line cross-sectional views of a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure.

[0013] [Figure 5A] 1 shows an oblique three-dimensional view of another thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to another embodiment of the present disclosure.

[0014] [Figure 5B] 5B shows a partial plan view of the thin film integrated circuit structure of FIG. 5A according to another embodiment of the present disclosure.

[0015] [Figure 6] 1 shows an oblique three-dimensional view of another thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to another embodiment of the present disclosure.

[0016] [Figure 7A]1A-1D show cross-sectional and plan views of various stages of a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 7B] 1A-1D show cross-sectional and plan views of various stages of a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 7C] 1A-1D show cross-sectional and plan views of various stages of a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 7D] 1A-1D show cross-sectional and plan views of various stages of a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 7E] 1A-1D show cross-sectional and plan views of various stages of a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 7F] 1A-1D show cross-sectional and plan views of various stages of a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 7G] 1A-1D show cross-sectional and plan views of various stages of a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. [Figure 7H] 1A-1D show cross-sectional and plan views of various stages of a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure.

[0017] [Figure 8A] 1 illustrates a cross-sectional view of a non-planar semiconductor device according to one embodiment of the present disclosure.

[0018] [Figure 8B] 8B illustrates a plan view of the semiconductor device of FIG. 8A cut along axis a-a' according to one embodiment of the present disclosure.

[0019] [Figure 9] 1A-1D show cross-sectional views of the formation of a buried channel structure.

[0020] [Figure 10] 1A-1D illustrate cross-sectional views of the formation of a buried channel structure with a protective self-forming barrier according to one embodiment of the present disclosure.

[0021] [Figure 11A] FIG. 2 is a top view of a wafer and die including one or more thin film transistors having a linerless self-forming barrier according to one or more of the embodiments disclosed herein. [Figure 11B] FIG. 2 is a top view of a wafer and die including one or more thin film transistors having a linerless self-forming barrier according to one or more of the embodiments disclosed herein.

[0022] [Figure 12] FIG. 1 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more thin film transistors having a linerless self-forming barrier according to one or more of the embodiments disclosed herein.

[0023] [Figure 13] FIG. 1 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more thin film transistors having a linerless self-forming barrier according to one or more of the embodiments disclosed herein.

[0024] [Figure 14] 1 illustrates a computing device according to an embodiment of the present disclosure; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] An integrated circuit structure having a linerless self-forming barrier and a method for manufacturing the integrated circuit structure having a linerless self-forming barrier are described. In the following description, numerous specific details are described, such as specific material and tool technology regimes, to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that the embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as single or dual damascene processing, have not been described in detail so as not to unnecessarily obscure the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. In some cases, various steps will be described as multiple separate steps and then in a manner that is most helpful to understanding the present disclosure, however, the order of description should not necessarily be interpreted to suggest that the order of these steps is followed. In particular, the steps do not have to be performed in the order presented.

[0026] Certain terms may also be used in the following description for reference purposes only and are not intended to be limiting. For example, terms such as "top," "bottom," "upper," "lower," "bottom," and "top" refer to directions within the referenced drawings. Terms such as "front," "back," "back," and "side" describe the orientation and / or location of parts of a component within any consistent frame of reference that is made clear by reference to the text and associated drawings that describe the component under discussion. Such terms may include those specifically mentioned above, derivatives thereof, and words of similar import.

[0027] The embodiments described herein may relate to semiconductor processing and construction at the substrate end of line (FEOL). FEOL is the first part of integrated circuit (IC) manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL generally encompasses everything up to but not including the deposition of metal interconnect layers. After the last FEOL step, the result is typically a wafer with isolated (e.g., no wires) transistors.

[0028] The embodiments described herein may relate to semiconductor processing and structures at the back-end of the interconnect (BEOL). BEOL is the second part of IC manufacturing where the individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with the wiring, e.g., metallization layers, on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections. In the BEOL part of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added at the BEOL.

[0029] The embodiments described below may be applied to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, while example processing schemes may be illustrated using a FEOL processing context, such approaches may also be applied to BEOL processes. Similarly, while example processing schemes may be illustrated using a BEOL processing context, such approaches may also be applied to FEOL processes.

[0030] One or more embodiments described herein relate to structures and architectures for fabricating integrated circuit structures with self-forming barrier layers. The embodiments may include or relate to one or more back-end transistors, semiconducting oxide materials, thin film transistors, gate electrodes, and system-on-chip (SoC) technologies. One or more embodiments may be implemented to provide high performance back-end transistors that potentially increase monolithic integration of back-end logic plus memory in SoCs of future technology nodes.

[0031] According to one embodiment of the present disclosure, the linerless self-forming barrier is described with respect to a conductive structure, such as a conductive structure including copper (Cu), tungsten (W), and / or cobalt (Co). The embodiments described herein may be implemented to fabricate an interconnect structure (e.g., a linerless single damascene or dual damascene structure in direct contact with an interlayer dielectric (ILD) material), a contact for a transistor structure (e.g., as a layer in direct contact with a semiconductor oxide), or a gate electrode (e.g., to change the work function of the gate electrode). In one embodiment, the barrier layer described herein has the same metal species as the fill material. The barrier layer described herein may provide one or more benefits of adhesion, electromigration, and / or resistivity.

[0032] To illustrate the situation, conductive interconnects typically rely on liners and barriers to prevent copper (Cu) diffusion into the substrate or adjacent ILD materials. However, such structures may be associated with high costs (e.g., resistance and space). Conventional approaches may require multiple optimization steps, such as optimizing the liner and barrier, and optimizing the fill and polish approach. Conventional approaches may also be associated with multiple depositions to achieve thin liner and barrier layers, which may be time consuming and an implementation bottleneck.

[0033] In certain embodiments described herein, as an example implementation, atomically thin two-dimensional (2D) crystals are formed to prevent Cu diffusion. By exposing Cu to a gas such as forming gas (N2 / H2), a 2D material can be formed at the Cu interface. Such a self-forming barrier approach eliminates the need to separately deposit a liner or barrier, because the formed 2D Cu crystals can be used as a barrier.

[0034] Advantages of implementing the embodiments described herein include the use of a self-forming barrier to eliminate the need to deposit a liner or barrier. The barrier can be formed simply by using a fill metal (e.g., Cu) upon exposure to a gas such as forming gas. The embodiments can be implemented to minimize space and resistance at the bottom of the vias and sidewalls of the interconnect. The embodiments can be implemented to form a thin 2D barrier.

[0035] To provide context, FIG. 1 shows a cross-sectional view of an interconnect structure.

[0036] 1, an ILD material 102 is above a substrate 100. An interconnect structure 104 / 106 is within the ILD material 102. The interconnect structure 104 / 106 may include a conductive line 104 above a conductive via 106. The interconnect structure 104 / 106 includes a liner 108, a barrier 110, and a conductive fill 112.

[0037] In contrast to FIG. 1, FIG. 2 illustrates a cross-sectional view of the formation of an interconnect structure having a linerless self-forming barrier according to one embodiment of the present disclosure.

[0038] 2, portion (a), an ILD material 152 is above a substrate 150. An interconnect structure 154 / 156 is within the ILD material 152. The interconnect structure 154 / 156 may include a conductive line 154 above a conductive via 156. The interconnect structure 154 / 156 includes a conductive fill 158. In one embodiment, the conductive fill 158 is a copper fill.

[0039] Referring to part (b) of FIG. 2, the structure of part (a) is processed to form an interconnect structure 154A / 156A having a processed filler 158A and a 2D crystalline liner or barrier 160. In an exemplary embodiment, the 2D crystalline liner or barrier 160 is formed by annealing the structure of part (a) of FIG. 2 in a growth gas (e.g., by exposing it to forming gas (N2 / H2)) at a temperature of about 45° C. and for a duration of about 1 hour). In one embodiment, the 2D crystalline liner or barrier 160 is a Cu barrier formed in the conductive filler 158 using only Cu present.

[0040] 2, in accordance with one embodiment of the present disclosure, an integrated circuit structure includes a dielectric material 152 above a substrate 150. An interconnect structure 154A / 156A resides in a trench in the dielectric material 152. The interconnect structure 154A / 156A includes a conductive fill material 158A and a two-dimensional (2D) crystalline liner 160. The 2D crystalline liner 160 is in direct contact with the dielectric material 152 and the conductive fill material 158A. The 2D crystalline liner 160 includes the same metal species as the conductive fill material 158A.

[0041] In one embodiment, the 2D crystalline liner 160 is a single layer. In one embodiment, the 2D crystalline liner 160 has a thickness less than 5 nanometers.

[0042] In one embodiment, the metallic species is copper. In one embodiment, the metallic species is cobalt. In one embodiment, the metallic species is tungsten.

[0043] In one embodiment, as shown, a 2D crystalline liner 160 is further on the top surface of the interconnect structure 154A / 156A. In one embodiment, the interconnect structure 154A / 156A includes a conductive line 154A over a conductive via 156A.

[0044] In another aspect, the 2D crystalline liner is included in the conductive contact.As an example structure, Figure 3A shows a cross-section of a thin film integrated circuit structure having a linerless self-forming barrier according to one embodiment of the present disclosure.

[0045] 3A, an integrated circuit structure 300 includes a semiconducting oxide material 302 above a gate electrode 304. A pair of conductive contacts 308 (as shown in the dashed box) are directly above a first region of the semiconducting oxide material 302. A second region of the semiconducting oxide material 302 is between the pair of conductive contacts 308. The second region of the semiconducting oxide material 302 may include or be included in a channel region of a thin film transistor.

[0046] In one embodiment, the integrated circuit structure 300 further includes a gate dielectric layer 306 between the gate electrode 304 and the semiconducting oxide material 302. In one such embodiment, as shown, the gate dielectric layer 306 is or includes a layer of high-k dielectric material directly above the semiconducting oxide material 302.

[0047] An insulating structure 310, such as an interlevel dielectric layer, is included between each of the pair of conductive contacts 308. The insulating structure 310 is above, and may be directly above, the second region of semiconducting oxide material 302. An isolation structure 311 may be included on either side of the pair of conductive contacts 308, as shown. The isolation structure 311 may include one or more dielectric layers.

[0048] In one embodiment, the gate electrode 304 is a bottom gate electrode above a conductive line 312, such as an interconnect line. In one embodiment, an etch stop layer 314 is between the gate electrode 304 and the conductive line 312. A conductive via 316 is in an opening in the etch stop layer 314, as shown, electrically coupling the gate electrode 304 to the conductive line 312. The conductive line 312 may be formed above an additional etch stop layer 318 and / or an interlevel dielectric (ILD) layer 320, such as a low-k ILD layer.

[0049] According to one embodiment of the present disclosure, each of the pair of conductive contacts 308 includes a conductive fill material 308B and a two-dimensional (2D) crystalline liner 308A. The 2D crystalline liner 308A is in direct contact with the semiconducting oxide material 302 and the conductive fill material 308B. The 2D crystalline liner 308A includes the same metal species as the conductive fill material 308B.

[0050] In one embodiment, the 2D crystalline liner 308A is a single layer. In one embodiment, the 2D crystalline liner 308A has a thickness less than 5 nanometers. In one embodiment, not shown, the 2D crystalline liner 308A is further on top of the conductive fill material 308B.

[0051] In one embodiment, the metallic species is copper. In one embodiment, the metallic species is cobalt. In one embodiment, the metallic species is tungsten.

[0052] In one embodiment, the semiconducting oxide material 302 comprises a material selected from the group consisting of indium gallium zinc oxide, tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, and tungsten oxide.

[0053] As an example configuration of multiple integrated circuit structures of the type of Figure 3A, Figure 3B shows a perspective cross-sectional view of an array of thin film integrated circuit structures having a linerless self-forming barrier according to one embodiment of the present disclosure, where the array is adjacent to a logic region. Referring to Figure 3B, a layout 350 includes a thin film transistor array 352 adjacent to a logic region 354. Each of the thin film transistors of the thin film transistor array 352 can be the same as or similar to the integrated circuit structure 300 described in connection with Figure 3A.

[0054] In another aspect, there is an increasing demand for next-generation SoCs to monolithically integrate BEOL transistors for logic functions in higher metal layers. Such BEOL transistors typically have lower thermal budgets than front-end transistors due to the higher thermal sensitivity of back-end materials. Also, the performance of such transistors can be significantly limited due to the low channel mobility of BEOL compatible channel materials such as IGZO (Indium Gallium Zinc Oxide).

[0055] According to one or more embodiments described herein, non-planar BEOL compatible thin film transistors (TFTs) are fabricated by effectively increasing the transistor width (and thus increasing the drive strength and performance) for a given projected area. TFTs fabricated using such architectures may exhibit improved thin film transistor gate control, stability, and performance. Applications of such systems may include, but are not limited to, back-end (BEOL) logic, memory, or analog applications. The embodiments described herein may include non-planar structures that effectively increase the transistor width (relative to planar devices) by integrating devices of unique architectures.

[0056] To provide a benchmark, FIG. 4A shows a cross-sectional view taken along the gate "width" of a planar thin film integrated circuit structure having a linerless self-forming barrier according to one embodiment of the present disclosure.

[0057] With reference to FIG. 4A, a planar TFT 400 is formed above a substrate 402, for example, above an insulating layer 404 above the substrate, as shown. The planar TFT 400 includes a channel material 406, such as a semiconducting oxide material. A gate electrode 408 is formed on a gate dielectric layer 414 that is formed on the channel material 406. The gate electrode 408 may include a fill material 410 on a work function layer 412, as shown. As shown, the gate electrode 408 may expose a region 416 of the channel material 406 and the gate dielectric layer 414. Alternatively, the channel material 406 and the gate dielectric layer 414 have the same lateral dimensions as the gate electrode 408. It should be understood that the source / drain regions are in and out of the page of the diagram of FIG. 4A.

[0058] 4A, the planar TFT 400 has an effective gate width that is the length of the planar channel material 406 between locations A and B'. The TFT 400 is sometimes referred to herein as a planar BEOL field effect transistor (FET).

[0059] As a first example of a structure with a relatively increased transistor width (e.g., relative to the structure of FIG. 4A ), FIG. 4B shows a cross-sectional view taken along the gate “width” of a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier in accordance with one embodiment of the present disclosure.

[0060] 4B, as shown, a non-planar TFT 450 is formed above a substrate 452, for example, on an insulating layer 454 above the substrate. A pair of dielectric fins 455 are on the insulating layer 454. The non-planar TFT 450 includes a semiconducting oxide material 456, or a similarly suitable channel material. The semiconducting oxide material 456 is conformal with the pair of dielectric fins 455 and with exposed portions of the insulating layer 454 between the pair of dielectric fins 455. A gate electrode 458 is formed on a gate dielectric layer 464 that is formed on the semiconducting oxide material 456. The gate electrode 458 may include a fill material 460 on the work function layer 462 as shown. The gate electrode 458 may expose a region 466 of the semiconducting oxide material 456 and the gate dielectric layer 464 as shown. Alternatively, the semiconducting oxide material 456 and the gate dielectric layer 464 have the same lateral dimensions as the gate electrode 458. It should be understood that the source / drain regions are in and out of the page of the diagram of FIG. 4B.

[0061] As illustrated in Figure 4B, the non-planar TFT 450 has an effective gate width that is the length of the conformal semiconducting oxide material 456 between locations A' and B', i.e., the complete length including the top of the dielectric fin 455 and the upper undulating portion of the sidewalls. The TFT 450 is sometimes referred to herein as a planar BEOL field effect transistor (FET). In comparison to Figure 4A, the structure of Figure 4B highlights the advantage of the non-planar architecture to the increased effective gate width, referred to herein as the relative increased width.

[0062] To highlight other aspects of non-planar TFT topography, Figures 4C, 4D, and 4E show perspective and straight line cross-sectional views of a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure. It should be understood that for simplicity, one dielectric fin is shown in Figures 4C through 4E. The embodiment may include a single device fabricated on top of one (Figure 4C), two (Figure 4B), or more such dielectric fins.

[0063] 4C-4E, an integrated circuit structure 470 includes a dielectric fin 455 on an insulator layer 454 above a substrate 452. The dielectric fin 455 has a top and sidewalls. A semiconducting oxide material 456, or a similarly suitable channel material, is on the top and sidewalls of the dielectric fin 455. A gate electrode 458 is above a first portion of the semiconducting oxide material 456 on the top and sidewalls of the dielectric fin 455. The gate electrode 458 has a first side opposite a second side. A first conductive contact (left 474) is adjacent a first side of the gate electrode 458 and above a second portion of the semiconducting oxide material 456 on the top and sidewalls of the dielectric fin 455. A second conductive contact (right 474) is adjacent a second side of the gate electrode 458 and above a third portion of the semiconducting oxide material 456 on the top and sidewalls of the dielectric fin 455. In one embodiment, the first and second conductive contacts 474 each include a conductive fill material and a two-dimensional (2D) crystalline liner, where the 2D crystalline liner includes the same metal species as the conductive fill material, such as the configuration described in connection with FIG. 3A.

[0064] In one embodiment, as illustrated in Figures 4C-4E, the integrated circuit structure 470 further includes a gate dielectric layer 464 between the gate electrode 458 and a first portion of the semiconducting oxide material 456 on the top and sidewalls of the dielectric fin 455. In one embodiment, the integrated circuit structure 470 further includes a first dielectric spacer (left 472) between the first conductive contact 474 and a first side of the gate electrode 458, the first dielectric spacer 472 being above a fourth portion of the semiconducting oxide material 456 on the top and sidewalls of the dielectric fin 455. As illustrated in Figures 4C and 4E, a second dielectric spacer (right 472) is between the second conductive contact 474 and a second side of the gate electrode 458, the second dielectric spacer 472 being above a fifth portion of the second semiconducting oxide material 456 on the top and sidewalls of the dielectric fin 455. In one such embodiment, as also illustrated in Figures 4C and 4E, the gate dielectric layer 464 is further lined with first and second dielectric spacers 472.

[0065] 4B-4E collectively, according to one embodiment of the present disclosure, an integrated circuit structure 450 or 470 includes an insulator structure 455 above a substrate 452. The insulator structure 455 has a topography that varies along a plane (ab) parallel to the global plane of the substrate 452. A semiconducting oxide material 456 is on the insulator structure 455. The semiconducting oxide material 456 is conformal with the topography of the insulator structure 455. A gate electrode 458 is above a first portion of the semiconducting oxide material 456 on the insulator structure 455. The gate electrode 458 has a first side opposite a second side. A first conductive contact (left 474) is adjacent to a first side of the gate electrode 458. The first conductive contact 474 is above a second portion of the semiconducting oxide material 456 on the insulator structure 455. A second conductive contact (right 474) is adjacent to a second side of the gate electrode 458. A second conductive contact 474 overlies the third portion of the semiconducting oxide material 456 on the insulator structure 455 .

[0066] In one embodiment, the insulator structure 450 or 470 includes one or more dielectric fins 455. Each of the dielectric fins 455 has a top and sidewalls. A semiconducting oxide material 456 is on each of the top and sidewalls of each of the dielectric fins 455. In one embodiment, the insulator structure 455 (such as fin 455) is comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. In one embodiment, the insulator structure 455 is comprised of a low-k dielectric material.

[0067] In one embodiment, the dielectric fins described herein may be fabricated as a grid structure, with the term "grid" being used herein to refer to a closely spaced grid structure. In such an embodiment, traditional lithography does not directly allow for a tight pitch. For example, a traditional lithography based pattern may be formed first, but the pitch may be divided by two using a spacer mask pattern as known in the art. Furthermore, the original pitch may be divided by four by a second spacer mask pattern. Thus, the grid-like patterns described herein may have dielectric fins spaced at a constant pitch and with a constant width. The patterns may be fabricated by pitch division by two or pitch division by four, or by other pitch division approaches. In one embodiment, each of the dielectric fins 455 is squared off (as shown) or has rounded corners.

[0068] In one embodiment, as shown, the gate dielectric layer 464 is between the gate electrode 458 and the first portion of the semiconducting oxide material 456 on the insulator structure 455. In one such embodiment, the gate dielectric layer 464 comprises a layer of high-k dielectric material directly above the semiconducting oxide material 456.

[0069] In one embodiment, a first dielectric spacer (first 472) is between the first conductive contact (first 474) and a first side of the gate electrode 458, and the first dielectric spacer (first 472) is above a fourth portion of the semiconducting oxide material 456 on the insulator structure 455. A second dielectric spacer (second 472) is between the second conductive contact (second 474) and a second side of the gate electrode 458, and the second dielectric spacer (second 472) is above a fifth portion of the semiconducting oxide material 456 on the insulator structure 455. In one such embodiment, a gate dielectric layer 464 is between the gate electrode 458 and the first portion of the semiconducting oxide material 456 on the insulator structure 455. The gate dielectric layer 464 is further aligned with the first dielectric spacer (first 472) and the second dielectric spacer (second 472). In certain such embodiments, the gate dielectric layer 464 comprises a layer of high-k dielectric material directly above the semiconducting oxide material 456 .

[0070] In one embodiment, the semiconducting oxide material 456 comprises indium gallium zinc oxide (IGZO). In one embodiment, the semiconducting oxide material 456 comprises a material selected from the group consisting of tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, and tungsten oxide. In one embodiment, the gate dielectric layer 464 comprises a high-k dielectric material layer directly over the semiconducting oxide material 456. In an alternative embodiment, the channel material is not a semiconducting oxide material, but rather a polycrystalline silicon layer.

[0071] As a second example of a structure with relatively increased transistor width, Figure 5A shows an oblique three-dimensional view of another thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to another embodiment of the present disclosure, and Figure 5B shows a plan view of a portion of the thin film integrated circuit structure of Figure 5A.

[0072] 5A and 5B, an integrated circuit structure 500 includes an insulator structure 550 above a substrate 502. The insulator structure 550 may be formed on an insulator layer 504 as shown. The insulator structure 550 has a first trench 552 therein, the first trench 552 having sidewalls and a bottom. A semiconducting oxide material 506, or a similarly suitable channel material, is in the first trench 552 of the insulator structure 550. The semiconducting oxide material 506 is conformal with the sidewalls and bottom of the first trench 552. A gate dielectric layer 514 is on the semiconducting oxide material 506 of the first trench 552. The gate dielectric layer 514 is conformal with the semiconducting oxide material 506, which is conformal with the sidewalls and bottom of the first trench 552. A gate electrode 508 is on the gate dielectric layer 514 of the first trench 552. The gate electrode 508 has a first side opposite a second side and has an exposed top surface. A first conductive contact (left 554) is laterally adjacent to a first side of the gate electrode 508. The first conductive contact (left 554) is on a first portion of the semiconductive oxide material 506 conformal to the sidewall of the first trench 552. A second conductive contact (right 554) is laterally adjacent to a second side of the gate electrode 508. The second conductive contact (right 554) is on a second portion of the semiconductive oxide material 506 conformal to the sidewall of the first trench 552. It should be understood that the conductive contact 554 shows only a front portion of the first trench 552 for clarity of illustration. In one embodiment, the conductive contact 554 extends entirely or substantially entirely along the first trench 552 for maximum source / drain contact area and maintains a relatively small effective gate length. In one embodiment, the first and second conductive contacts 554 each include a conductive fill material and a two-dimensional (2D) crystalline liner, where the 2D crystalline liner includes the same metal species as the conductive fill material, such as the configuration described in connection with FIG. 3A.

[0073] In one embodiment, as shown, the insulator structure 550 is a single layer of ILD material. In another embodiment, the insulator structure 550 is a stack of alternating dielectric layers, such as those described in connection with Figures 7A through 7H.

[0074] In one embodiment, as shown, a third conductive contact 558 is over and in contact with the exposed top surface of the gate electrode 508. In one embodiment, as shown, the first conductive contact (left 554) is in a second trench 570 of the insulator structure 550 and the third conductive contact (right 554) is in a third trench 572 of the insulator structure 550. In one embodiment, as shown, the third conductive contact 558 is coupled to a conductive line 560, which may be a word line. In one embodiment, as shown, the first and second conductive contacts 554 are coupled to corresponding conductive lines 556.

[0075] 5A-5B, in one embodiment, the non-planar back-end FET architecture uses the vertical length (depth) of the first trench 552 to increase the effective width of the transistor, i.e., the depth of the first trench 552 is the Z of the TFT, and the effective width (Weff) is relatively increased by setting Z to the trench depth.

[0076] In one embodiment, the semiconducting oxide material 506 comprises indium gallium zinc oxide (IGZO). In one embodiment, the semiconducting oxide material 506 comprises a material selected from the group consisting of tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, and tungsten oxide. In one embodiment, the gate dielectric layer 514 comprises a layer of high-k dielectric material directly over the semiconducting oxide material 506. In an alternative embodiment, the channel material is not a semiconducting oxide material, but rather a layer of polycrystalline silicon.

[0077] As a third example of a structure with relatively increased transistor width, FIG. 6 shows an oblique three-dimensional view of another thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier in accordance with another embodiment of the present disclosure.

[0078] With reference to FIG. 6, an integrated circuit structure 600 includes an insulator structure 650 above a substrate 602. The insulator structure 650 may be formed on an insulator layer 604, as shown. The insulator structure 650 has a first trench 652 therein, the first trench 652 having sidewalls and a bottom. The insulator structure 650 has a topography that varies along a plane perpendicular to the global plane of the substrate 602. In one such embodiment, as shown, the insulator structure 650 has a corrugated topography that varies along a plane perpendicular to the global plane of the substrate 602. In certain such embodiments, as shown, the corrugated topography is present in a single layer of ILD material. In another particular such embodiment, the corrugated topography is present in a configuration of alternating dielectric layers, such as those described in connection with FIGS. 7A through 7H.

[0079] A semiconducting oxide material 606, or a similarly suitable channel material, is in a first trench 652 of the insulator structure 650. The semiconducting oxide material 606 is conformal with the sidewalls and bottom of the first trench 652, i.e., conformal with the topography of the insulator structure 650. A gate dielectric layer 614 is on the semiconducting oxide material 606 in the first trench 652. The gate dielectric layer 614 is conformal with the semiconducting oxide material 606, which is conformal with the sidewalls and bottom of the first trench 652. A gate electrode 608 is on the gate dielectric layer 614 in the first trench 652. The gate electrode 608 has a first side opposite a second side and has an exposed top surface. A first conductive contact (left 654) is laterally adjacent a first side of the gate electrode 608. A first conductive contact (left 654) is on a first portion of the semiconductive oxide material 606 conformal to the sidewall of the first trench 652. A second conductive contact (right 654) is laterally adjacent a second side of the gate electrode 608. The second conductive contact (right 654) is on a second portion of the semiconductive oxide material 606 conformal to the sidewall of the first trench 652. In one embodiment, the conductive contact 654 extends entirely or substantially entirely along the first trench 652 for maximum source / drain contact area and to maintain a relatively small effective gate length. In one embodiment, the first and second conductive contacts 654 each include a conductive fill material and a two-dimensional (2D) crystalline liner, where the 2D crystalline liner includes the same metal species as the conductive fill material, such as the configuration described in connection with FIG. 3A.

[0080] In one embodiment, as shown, a third conductive contact 658 is over and in contact with the exposed top surface of the gate electrode 608. In one embodiment, as shown, the first conductive contact (left 654) is in a second trench 670 of the insulator structure 650 and the third conductive contact (right 654) is in a third trench 672 of the insulator structure 650. In one embodiment, as shown, the third conductive contact 658 is coupled to a conductive line 660, which may be a word line. In one embodiment, as shown, the first and second conductive contacts 654 are coupled to corresponding conductive lines 656.

[0081] 6, in one embodiment, a non-planar back-end FET architecture uses the vertical length (depth) of the first trench 652, including the additional length provided by the corrugation, to increase the effective width of the transistor. That is, the length of the first trench 652 is the Z of the TFT, and the effective width (Weff) is relatively increased by setting Z to the depth or length along the corrugated first trench 652.

[0082] In one embodiment, the semiconducting oxide material 606 comprises indium gallium zinc oxide (IGZO). In one embodiment, the semiconducting oxide material 606 comprises a material selected from the group consisting of tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, and tungsten oxide. In one embodiment, the gate dielectric layer 614 comprises a layer of high-k dielectric material directly over the semiconducting oxide material 606. In an alternative embodiment, the channel material is not a semiconducting oxide material, but rather a layer of polycrystalline silicon.

[0083] The above TFT non-planar architectures 450, 470, 500 and 600 according to one embodiment of the present disclosure provide a more effective width for the transistors on a scaled projected area, and in one embodiment, the drive strength and performance of such transistors are improved over state-of-the-art planar BEOL transistors.

[0084] As an exemplary processing scheme, Figures 7A through 7H show cross-sectional and plan views of various stages in a method for fabricating a thin film integrated circuit structure having a relatively increased width and a linerless self-forming barrier according to one embodiment of the present disclosure.

[0085] 7A, a stack of dielectric layers 704 is formed above a substrate 700, and possibly an insulating layer 702 formed on or above the substrate 700. The stack of dielectric layers 704 includes alternating dielectric layers 704A and 704B of different compositions. In one embodiment, the stack of dielectric layers 704 is a stack of alternating silicon dioxide and silicon nitride layers.

[0086] Referring to Figure 7B, an opening 706 is formed in the stack of dielectric layers 704 to form a once-patterned stack of dielectric layers 704'. In one embodiment, the structure of Figure 7B is used without the process described below in connection with Figure 7C to arrive at a structure such as TFT 300.

[0087] Referring to Figure 7C, corrugations forming corrugated openings 708 are achieved by exposing the structure of Figure 7B to an etching process that recesses layer 704A and selectively layer 704B. The selective etching process provides a twice-patterned stack 704'' of dielectric layers. The twice-patterned stack 704'' of dielectric layers can be used to reach structures such as TFT 400.

[0088] Referring to Figure 7D, a conductive contact 710, such as a source / drain contact, is formed in the opening 708 of the structure of Figure 7C. The conductive contact may be formed, for example, by a deposition or growth process.

[0089] 7E, openings 712 are formed between the conductive contacts 710 to form a triple patterned stack 704''' of dielectric layers. The openings 712 expose the corrugated surfaces of the conductive contacts 710.

[0090] 7F, a semiconductor oxide layer 606, or other suitable channel material, is formed in the openings 712 along the exposed surfaces of the conductive contacts 710. In one embodiment, the semiconductor oxide layer 606 is formed conformally with the corrugated surfaces of the conductive contacts 710, as shown.

[0091] 7G, a gate dielectric layer 614 is formed in the opening 712. The gate dielectric layer 614 overlies and is conformal with the semiconductor oxide layer 606.

[0092] Referring to Figure 7H, a gate electrode 608 is formed in the opening 712. The gate electrode 608 overlies and is conformal with a gate dielectric layer 614. The structure of Figure 7G may be included as part of the TFT 600 described in connection with Figure 6.

[0093] It should be understood that the layers and materials described by the embodiments herein are typically formed on or above the underlying semiconductor substrate 402, 452, 502, 602, 700 or the substrate below the ILD layer 120 (e.g., as a FEOL layer). In other embodiments, the layers and materials described by the embodiments herein are typically formed on or above the underlying device layer of an integrated circuit (e.g., as a BEOL layer) above the underlying semiconductor substrate 402, 452, 502, 602, 700 or the substrate below the ILD layer 320. In one embodiment, the underlying semiconductor substrate represents a typical workpiece used to manufacture integrated circuits. Semiconductor substrates often include wafers or other parts of silicon or other semiconductor materials. Suitable semiconductor substrates include, but are not limited to, monocrystalline silicon, polycrystalline silicon, and silicon-on-insulator (SOI), as well as similar substrates formed of other semiconductor materials. Semiconductor substrates often include transistors, integrated circuits, and the like, depending on the manufacturing stage. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Additionally, although not shown, the structures described herein may be fabricated on lower low-level interconnect (BEOL) interconnect layers.

[0094] If the insulator layer 454, 504, 604 or 702 is optionally used, the insulator layer 454, 504, 604 or 702 may be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of portions of the gate structure from the underlying bulk substrate or interconnect layer. For example, in one embodiment, the insulator layer 454, 504, 604 or 702 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon doped silicon nitride, etc. In a particular embodiment, the insulator layer 454, 504, 604 or 702 is a low-k dielectric layer of the underlying BEOL layer.

[0095] In one embodiment, the semiconducting oxide material 302, 406, 456, 506 or 606, and thus the channel material of the TFT, comprises an IGZO layer having a gallium to indium ratio of 1:1, a gallium to indium ratio of greater than 1 (e.g., 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, or 10:1), or a gallium to indium ratio of less than 1 (e.g., 1:2, 1:3, 1:4, 1:5, 1:6, 1:7, 1:8, 1:9 or 1:10). Low indium content IGZO may refer to IGZO that contains more gallium than indium (e.g., a gallium to indium ratio greater than 1:1), and may also be referred to as high gallium content IGZO. Similarly, low gallium content IGZO may refer to IGZO that contains more indium than gallium (e.g., a gallium to indium ratio less than 1:1), and may also be referred to as high indium content IGZO. In another embodiment, the semiconducting oxide material 302, 406, 456, 506, or 606 is or includes a material such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, zinc indium oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In an alternative embodiment, polycrystalline silicon is used as the channel material instead of the semiconducting oxide material. In one embodiment, whatever the composition, the channel material has a thickness between 5 nanometers and 30 nanometers.

[0096] In one embodiment, the semiconducting oxide material 302, 406, 456, 506 or 606 is an amorphous, crystalline or quasicrystalline oxide semiconductor, such as an amorphous, crystalline or quasicrystalline oxide semiconductor IGZO layer. The semiconducting oxide material 302, 406, 456, 506 or 606 can be formed using a low temperature deposition process, such as physical vapor deposition (PVD) (e.g., sputtering), atomic layer deposition (ALD) or chemical vapor deposition (CVD). The possibility of depositing the semiconducting oxide material 302, 406, 456, 506 or 606 at a temperature low enough to be compatible with back-end manufacturing processes represents a particular advantage. The semiconducting oxide material 302, 406, 456, 506 or 606 can be deposited on sidewalls or conformed to any desired structure with precise thickness, allowing the fabrication of transistors with any desired shape.

[0097] In one embodiment, the gate electrode 304, 408, 458, 508 or 608 comprises at least one P-type work function metal or N-type work function metal, depending on whether the integrated circuit device 300, 400, 450, 470, 500 or 600 is included in a P-type or N-type transistor. In a P-type transistor, metals that may be used for the gate electrode 304, 408, 458, 508 or 608 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). In an N-type transistor, metals that may be used for the gate electrode 304, 408, 458, 508 or 608 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additionally, metal layers may be included for other purposes, such as acting as a barrier layer. In some implementations, the gate electrode 304, 408, 458, 508, or 608 may be configured with a "U" shaped structure that includes a bottom that is substantially parallel to the top surface of the substrate and two sidewall portions that are substantially perpendicular to the surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions that are substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode may be configured with a combination of U-shaped and planar, non-U-shaped structures. For example, the gate electrode may be comprised of one or more U-shaped metal layers formed on one or more planar, non-U-shaped layers.

[0098] In one embodiment, the gate dielectric layer 306, 414, 464, 514, or 614 is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 306, 414, 464, 514, or 614 is composed of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead tantalum scandium oxide, lead zinc niobate, or combinations thereof. In some implementations, as illustrated in Figures 4C and 4E, the gate dielectric 306, 414, 464, 514, or 614 may be composed of a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0099] In some embodiments, the semiconducting oxide material 302, 406, 456, 506 or 606 may be in contact with the gate dielectric layer 306, 414, 464, 514 or 614, respectively, and the configuration may place the IGZO layer in contact with the high-k metal oxide layer. In other embodiments, an intermediate material may be disposed between the semiconducting oxide material 302, 406, 456, 506 or 606 and the gate dielectric layer 306, 414, 464, 514 or 614. In some embodiments, the IGZO layer may include multiple regions of IGZO having different material properties. For example, the IGZO layer may include a low indium content IGZO close to (e.g., in contact with) the high-k gate dielectric layer and a high indium content IGZO close to (e.g., in contact with) the high-mobility semiconducting oxide channel material. High indium content IGZO may offer higher mobility and poorer interface characteristics relative to low indium content IGZO, while low indium content IGZO may offer lower mobility but wider band gap, lower gate leakage, and improved interface characteristics relative to high indium content IGZO.

[0100] In one embodiment, the dielectric spacers 472 are formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The process of forming sidewall spacers is well known in the art and generally includes deposition and etching steps. In some embodiments, multiple spacer pairs may be used. For example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate electrode 472.

[0101] In one embodiment, the conductive contacts 308, 474, 554 or 654 act as contacts to or directly act as source / drain regions of the TFT. The conductive contacts 308, 474, 554 or 654 can be spaced apart a distance that is the gate length of the transistor 300, 400, 450, 470, 500 or 600. In one embodiment, the conductive contacts 558 or 658 directly contact the gate electrode. In some embodiments, the gate length is between 7 and 30 nanometers. In one embodiment, the conductive contacts 308, 474, 554, 558, 654 or 658 include one or more layers of metals and / or metal alloys, examples of which are described above in connection with FIG. 3A.

[0102] In one embodiment, the interconnect lines described herein, such as the interconnect line 312 (upper layer via 314), 556, 560, 656, or 660 (and, in some cases, the lower or upper layer via structures), are comprised of one or more metals or conductive structures that include metals. Conductive interconnect lines may also be referred to in the art as wiring, wires, lines, metals, interconnect lines, or simply interconnects. In certain embodiments, each of the interconnect lines includes a barrier layer and a conductive fill material. In one embodiment, the barrier layer is comprised of a metal nitride material, such as tantalum nitride or titanium nitride. In one embodiment, the conductive fill material is comprised of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof.

[0103] The interconnect lines described herein may be fabricated as a lattice structure, where the term "lattice" is used herein to refer to a closely spaced lattice structure. In such an embodiment, traditional lithography does not directly allow for a tight pitch. For example, a pattern based on traditional lithography may be formed first, but the pitch may be divided by two using a spacer mask pattern as known in the art. Furthermore, the original pitch may be divided by four by a second spacer mask pattern. Thus, the lattice pattern described herein may have conductive lines spaced at a constant pitch and having a constant width. The pattern may be fabricated by pitch division by two or pitch division by four, or by other pitch division approaches.

[0104] In one embodiment, the ILD materials described herein, such as ILD material 550 or 650, are composed of or include a layer of a dielectric or insulator material. Examples of suitable dielectric materials include, but are not limited to, silicon oxide (e.g., silicon dioxide (SiO2)), doped silicon oxide, fluorinated silicon oxide, carbon doped silicon oxide, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0105] In one aspect, the gate electrode and gate dielectric layer, e.g., gate electrode 304, 408, 458, 508 or 608 and gate dielectric layer 306, 414, 464, 514 or 614, may be fabricated by a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with a permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed in this process, rather than being carried over from a previous process. In one embodiment, the dummy gate is removed by a dry etch or wet etch process. In one embodiment, the dummy gates are comprised of polycrystalline silicon or amorphous silicon and are removed using a dry etch process including the use of SF6. In another embodiment, the dummy gates are comprised of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is comprised of silicon nitride and is removed with a wet etch including aqueous phosphoric acid.

[0106] In one embodiment, one or more approaches described herein essentially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at the structure described herein. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in certain such embodiments, at least a portion of the annealing is performed after the permanent gate structure, e.g., the gate dielectric layer, is formed. The annealing is performed before the formation of the permanent contact.

[0107] It should be understood that not all aspects of the process described above need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, the dummy gate does not need to be formed at all prior to fabricating the gate contact above the active portion of the gate stack. The gate stack described above may in fact be a permanent gate stack as initially formed. Additionally, the process described herein may be used to fabricate one or more semiconductor devices. One or more embodiments may be particularly useful for fabricating semiconductor devices at the ten nanometer (10 nm) technology node or smaller.

[0108] In one embodiment, as used throughout this description, the lithography process is performed using 193 nm immersion lithography (i193), extreme ultraviolet (EUV) and / or electron beam direct write (EBDW) lithography, or the like. Positive tone or negative tone resists may be used. In one embodiment, the lithography mask is a three-layer mask consisting of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In certain such embodiments, the topographic masking portion is a carbon hard mask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

[0109] In another aspect, the performance of a thin film transistor (TFT) may vary depending on the carrier mobility of the components in the TFT. For example, a material with higher carrier mobility is capable of moving carriers more rapidly in response to a given electric field than a material with lower carrier mobility. Thus, high carrier mobility may be associated with improved performance. Although shown and described above as a single semiconductor oxide layer, in accordance with the embodiments described herein, a layer of semiconductor oxide, such as a layer of IGZO, is between the high-k gate dielectric material and the high mobility semiconductor oxide channel material. IGZO has a relatively low mobility (approximately 10 cm 2 / Vs), while the subthreshold swing of IGZO can be close to the conventional theoretical lower limit. In some embodiments, a thin layer of IGZO can be directly interfaced with the channel material of choice and sandwiched between the channel material and the high-k dielectric. The use of IGZO at the interface between the gate stack and the channel can achieve one or more of a number of advantages. For example, the IGZO interface can have a relatively small number of interface traps where carriers can be trapped and released, impeding performance. TFTs including an IGZO layer as the second semiconducting oxide material can exhibit desirably low gate leakage. When IGZO is used as an interface to a non-IGZO semiconducting oxide channel material (e.g., a thin film oxide semiconductor material with higher mobility than IGZO), the benefits of the higher mobility channel material can be realized simultaneously with the good gate oxide interface properties provided by IGZO. According to one or more embodiments described herein, a gate channel configuration based on a dual semiconducting oxide layer channel allows the use of a wider array of thin film transistor channel materials while achieving more desirable gate control than is achievable using conventional approaches.

[0110] In one embodiment, the addition of a second thin-film semiconductor around the first TFT material may provide one or more of the following: mobility enhancement, particularly improvement of short channel effects (SCE) when all conduction occurs in the second material. The second TFT material may be selected for strong oxygen bonding capability to stabilize the TFT when exposed to downstream processing. According to one embodiment, a higher mobility semiconducting oxide material is effectively surrounded by a lower mobility material semiconducting oxide that is more oxygen stable. The resulting structure may limit the negative effects of downstream high temperature or aggressive processing steps on the inner TFT material by having a highly stable outer material. An expanded set of materials that may be selected to simultaneously maximize stability and mobility may be realized using such dual-material architectures.

[0111] In another aspect, the gate electrode structure includes a 2D crystalline liner, for example as a work function layer of the gate electrode structure. As an example of a completed device as cut through a single gate line, FIG. 8A shows a cross-sectional view of a non-planar semiconductor device according to one embodiment of the present disclosure. FIG. 8B shows a top view of the semiconductor device of FIG. 8A cut along the a-a' axis according to one embodiment of the present disclosure. Although only one gate line is shown, it should be understood that multiple gate lines can be included in the integrated circuit structure.

[0112] 8A, a semiconductor structure or device 800 is formed from a substrate 802 and includes a non-planar active area (e.g., a fin structure including a protruding fin portion 804 and a sub-fin region 805) formed within an isolation region 806. A gate line 808 is disposed over the multiple protruding portions 804 of the non-planar active area as well as over a portion of the isolation region 806. As shown, the gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, the gate line 808 may also include a dielectric cap layer 854. Further seen from this perspective are a gate contact 814 and an overlying gate contact via 816, along with an overlying metal interconnect 860, all of which are disposed in a multiple interlayer dielectric stack or layer 870. The gate contact 814 is formed within an opening formed in the dielectric cap layer 854. 8A, in one embodiment, the gate contact 814 is disposed over the isolation region 806 but not over the non-planar active region, while in another embodiment, the gate contact 814 is disposed over the non-planar active region.

[0113] In one embodiment, the gate electrode 850 includes a conductive fill material and a two-dimensional (2D) crystalline liner. The 2D crystalline liner is in direct contact with the conductive fill material. The 2D crystalline liner includes the same metal species as the conductive fill material. In one such embodiment, the 2D crystalline liner has a different work function than the conductive fill material. In certain such embodiments, the 2D crystalline liner is a work function setting layer of the gate electrode 850. In one embodiment, the 2D crystalline liner is a single layer. In one embodiment, the 2D crystalline liner has a thickness less than 5 nanometers. In one embodiment, the metal species is copper. In one embodiment, the metal species is cobalt. In one embodiment, the metal species is tungsten.

[0114] 8B, gate line 808 is shown as being disposed above the plurality of protruding fin portions 804. Source and drain regions 804A and 804B of the plurality of protruding fin portions 804 can be seen in this perspective view. In one embodiment, source and drain regions 804A and 804B are doped portions of the original material of the plurality of protruding fin portions 804. In another embodiment, the material of the plurality of protruding fin portions 804 is removed and replaced with another semiconductor material, for example by epitaxial deposition. In either case, source and drain regions 804A and 804B may extend below the level of dielectric layer 806, i.e., into sub-fin region 805.

[0115] In one embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a FinFET or a Tri-Gate device. In one such embodiment, the corresponding semiconductor channel region is comprised of or formed in a three-dimensional object. In one such embodiment, the gate electrode stack of the multiple gate lines 808 encompasses at least a top surface and a pair of sidewalls of the three-dimensional object.

[0116] Referring again to FIG. 8A, the configuration of the semiconductor structure or device 800 places the gate contact on multiple isolation regions. Such a configuration may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has multiple contact structures that contact multiple portions of the gate electrode formed above the active region. Generally, prior to (e.g., in addition to) forming a gate contact structure (such as a via) above the active portion of the gate and in the same layer as the trench contact via, one or more embodiments of the present disclosure include first using a gate-aligned trench contact process. Such a process may be implemented to form a trench contact structure for the manufacture of a semiconductor structure, e.g., the manufacture of an integrated circuit. In one embodiment, the trench contact pattern is formed to align with an existing gate pattern. In contrast, conventional approaches typically include additional lithography processes with critical alignment of the lithographic contact pattern to the existing gate pattern in combination with selective contact etching. For example, conventional processes may include patterning of a poly(gate) grid along with separate patterning of contact features.

[0117] In another embodiment, thin film crystal formation for passivation interconnects is described.To provide context, Figure 9 shows a cross-sectional view of the formation of a buried channel structure.

[0118] 9, part (a), a dielectric layer 902 overlies a substrate 900. An active channel 904 resides in the dielectric layer 902. A conductive contact 906, such as a copper contact, is coupled to the active channel 904.

[0119] Referring to part (b) of Figure 9, upon annealing the structure of part (a) of Figure 9 with hydrogen or oxygen, the active channel region 904 may become a damaged active region 904A having a damaged region 905 therein, as represented by arrow 910 in part (b) of Figure 9.

[0120] 9, the buried active channel (e.g., semiconductor channel) may degrade when subjected to various edge anneals due to H or O 2 diffusing along the contact sidewalls, leading to damaged buried active channel material. It may not be practical to create a perfect seal with sidewalls that can prevent H or O 2 diffusion to achieve repeatable full Cu fill.

[0121] In contrast to FIG. 9, FIG. 10 illustrates a cross-sectional view of the formation of a buried channel structure with a protective self-forming barrier, according to one embodiment of the present disclosure.

[0122] 10, part (a), a dielectric layer 1002 overlies a substrate 1000. An active channel 1004 is in the dielectric layer 1002. A conductive contact 1006, such as a copper contact, is coupled to the active channel 1004.

[0123] Referring to part (b) of FIG. 10, a process such as forming gas anneal is used to form a top 2D crystalline layer 1006B and the remaining copper filling 1006A.

[0124] Referring to part (c) of Figure 10, during hydrogen or oxygen annealing of the structure in part (b) of Figure 10, the active channel region 1004 is protected from damage by the top 2D crystal layer 1006B, as represented by arrows 1010 in part (c) of Figure 10.

[0125] Referring to FIG. 10, the top 2D crystal layer 1006B may be atomically thin and prevent diffusion of elements into the active channel 1004. The top 2D crystal layer 1006B may be formed by processing the fill material 1006 or by depositing at a temperature compatible with BEOL processing. Furthermore, such a top 2D crystal layer 1006B may effectively expand by filling the empty areas along the sidewalls of the contact 1006. Such an atomically thin barrier may be grown using the top of the Cu region (e.g., by self-passivation). The crystal may expand to close any gaps (e.g., from amorphous to crystalline) to provide high quality passivation and / or sealing.

[0126] In another aspect, the integrated circuit structure described herein can be included in an electronic device. As a first example of an apparatus that can include one or more of the TFTs disclosed herein, Figures 11A and 11B are top views of a wafer and a die that include one or more thin film transistors with linerless self-formed barrier according to any one of the embodiments disclosed herein.

[0127] 11A and 11B, the wafer 1100 may be composed of a semiconductor material and may include one or more dies 1102 having integrated circuit (IC) structures formed on a surface of the wafer 1100. Each of the dies 1102 may be a repeating unit of a semiconductor product including any suitable IC (e.g., an IC including one or more structures such as structures 300, 400, 450, 470, 500, or 600). After fabrication of the semiconductor product is completed (e.g., after fabrication of structures 300, 400, 450, 470, 500, or 600), the wafer 1100 may undergo a singulation process in which each of the dies 1102 are separated from one another to provide separate "chips" of the semiconductor product. In particular, devices including the TFTs disclosed herein may take the form of the wafer 1100 (e.g., unsingulated) or the form of the dies 1102 (e.g., singulated). The die 1102 may include one or more transistors and / or support circuitry for transmitting electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer 1100 or die 1102 may include memory devices (e.g., static random access memory (SRAM) devices, logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. A plurality of these devices may be combined on a single die 1102. For example, a memory array formed by a plurality of memory devices may be formed on the same die 1102 as a processing device or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0128] FIG. 12 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more thin film transistors having a linerless self-forming barrier according to one or more of the embodiments disclosed herein.

[0129] 12, IC device 1200 may be formed on substrate 1202 (e.g., wafer 1100 of FIG. 11A) and may be included in a die (e.g., die 1102 of FIG. 11B), which may be standalone or may be included in a wafer. Some examples of materials from which substrate 1202 may be formed are described above in connection with substrate 402, 452, 502, 602, 700 or the substrate below ILD layer 320, although any material that can serve as a foundation for IC device 1200 may be used.

[0130] The IC device 1200 may include one or more device layers, such as a device layer 1204, disposed on a substrate 1202. The device layer 1204 may include features of one or more transistors 1240 (e.g., TFTs as described above) formed on the substrate 1202. The device layer 1204 may include, for example, one or more source and / or drain (S / D) regions 1220, a gate 1222 that controls current flow of the transistor 1240 between the S / D regions 1220, and one or more S / D contacts 1224 that transmit electrical signals between the S / D regions 1220. The transistor 1240 may include additional features, such as device isolation regions, gate contacts, and the like, which are not shown for purposes of clarity. The transistor 1240 is not limited to the types and configurations illustrated in FIG. 12, but may include a wide variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include fin-based transistors, such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors. In particular, one or more transistors 1240 take the form of transistors 300, 400, 450, 470, 500, or 600. Thin film transistors such as 300, 400, 450, 470, 500, or 600 may be particularly advantageous when used in metal layers of microprocessor devices for embedded dynamic random access memory (DRAM circuits), analog circuits, logic circuits, or memory circuits, and may be formed along existing complementary metal oxide semiconductor (CMOS) processes.

[0131] Electrical signals, such as power and / or input / output (I / O) signals, may be transmitted to and / or from transistors 1240 of device layer 1204 through one or more interconnect layers (shown in FIG. 12 as interconnect layers 1206-1210) disposed on device layer 1204. For example, electrically conductive features (e.g., gate 1222 and S / D contacts 1224) of device layer 1204 may be electrically coupled with interconnect structures 1228 of interconnect layers 1206-1210. One or more interconnect layers 1206-1210 may form an interlayer dielectric (ILD) stack 1219 of IC device 1200.

[0132] The interconnect structures 1228 may be arranged in the interconnect layers 1206-1210 to transmit electrical signals according to a wide variety of designs (notably, the configuration is not limited to the particular configuration of the interconnect structures 1228 illustrated in Figure 12. Although a particular number of interconnect layers 1206-1210 are illustrated in Figure 12, embodiments of the disclosure include IC devices having more or fewer interconnect layers than are illustrated.

[0133] In some embodiments, the interconnect structures 1228 may include trench structures 1228a (sometimes referred to as "lines") and / or via structures 1228b filled with an electrically conductive material, such as a metal. The trench structures 1228a may be arranged to transmit electrical signals in a direction of a plane substantially parallel to the surface of the substrate 1202 when the device layer 1204 is formed. For example, the trench structures 1228a may transmit electrical signals in a direction into and out of the page from the perspective of FIG. 12. The via structures 1228b may be arranged to transmit electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1202 when the device layer 1204 is formed. In some embodiments, the via structures 1228b may electrically couple together trench structures 1228a of different interconnect layers 1206-1210.

[0134] The interconnect layers 1206-1210 may include a dielectric material 1226 disposed between the interconnect structures 1228, as shown in Figure 12. In some embodiments, the dielectric material 1226 disposed between the interconnect structures 1228 of different ones of the interconnect layers 1206-1210 may have different compositions, while in other embodiments, the composition of the dielectric material 1226 between the different interconnect layers 1206-1210 may be the same. In either case, such a dielectric material may be referred to as an interlayer dielectric (ILD) material.

[0135] A first interconnect layer 1206 (referred to as metal 1 or "M1") may be formed directly on the device layer 1204. In some embodiments, as shown, the first interconnect layer 1206 may include trench structures 1228a and / or via structures 1228b. The trench structures 1228a of the first interconnect layer 1206 may be coupled to contacts (e.g., S / D contacts 1224) of the device layer 1204.

[0136] A second interconnect layer 1208 (referred to as metal 2 or "M2") may be formed directly over the first interconnect layer 1206. In some embodiments, the second interconnect layer 1208 may include a via structure 1228b coupling a trench structure 1228a of the second interconnect layer 1208 with a trench structure 1228a of the first interconnect layer 1206. Although the trench structures 1228a and the via structures 1228b are delineated within each interconnect layer for clarity purposes (e.g., within the second interconnect layer 1208), in some embodiments the trench structures 1228a and the via structures 1228b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0137] A third interconnect layer 1210 (referred to as metal 3 or "M3") (and additional interconnect layers, if desired) may be formed successively on the second interconnect layer 1208 according to similar techniques and configurations described in connection with the second interconnect layer 1208 or the first interconnect layer 1206.

[0138] The IC device 1200 may include a solder resist material 1234 (e.g., polyimide or similar material) and one or more bond pads 1236 formed on the interconnect layers 1206-1210. The bond pads 1236 may be electrically coupled to the interconnect structure 1228 and configured to transmit electrical signals of the transistor 1240 to other external devices. For example, solder bonds may be formed on the one or more bond pads 1236 to mechanically and / or electrically couple a chip including the IC device 1200 to another component (e.g., a circuit board). The IC device 1200 may have alternative configurations for transmitting electrical signals from the interconnect layers 1206-1210 other than those illustrated in other embodiments. For example, the bond pads 1236 may be replaced with or further include other similar features (e.g., posts) that transmit electrical signals to external components.

[0139] FIG. 13 is a cross-sectional side view of an integrated circuit (IC) device assembly that may include one or more thin film transistors having a linerless self-forming barrier according to one or more of the embodiments disclosed herein.

[0140] 13, an IC device assembly 1300 includes a component having one or more integrated circuit structures described herein. The IC device assembly 1300 includes a number of components disposed on a circuit board 1302 (which may be, for example, a motherboard). The IC device assembly 1300 includes components disposed on a first side 1340 of the circuit board 1302 and on an opposing second side 1342 of the circuit board 1302. In general, components may be disposed on one or both of the sides 1340 and 1342. In particular, any suitable one of the components of the IC device assembly 1300 may include a number of TFT structures 300, 400, 450, 470, 500, or 600 disclosed herein.

[0141] In some embodiments, the circuit board 1302 may be a printed circuit board (PCB) that includes multiple metal layers isolated from each other by layers of dielectric material and electrically interconnected by conductive vias. Any one or more of the metal layers may be formed (optionally in conjunction with other metal layers) to carry electrical signals between components coupled to the circuit board 1302 in a desired circuit pattern. In other embodiments, the circuit board 1302 may be a non-PCB substrate.

[0142] The IC device assembly 1300 shown in Figure 13 includes a package-on-interposer structure 1336 that is coupled to a first surface 1340 of a circuit board 1302 by a bonding component 1316. The bonding component 1316 may electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302 and may include solder balls (as shown in Figure 13), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical bonding structure.

[0143] The package-on-interposer structure 1336 may include an IC package 1320 coupled to the interposer 1304 by a bonding component 1318. The bonding component 1318 may take any suitable form for the application, such as those described above with reference to the bonding component 1316. Although a single IC package 1320 is shown in FIG. 13, multiple IC packages may be coupled to the interposer 1304. It should be understood that additional interposers may be coupled to the interposer 1304. The interposer 1304 may provide an intermediate substrate used to bridge the circuit board 1302 and the IC package 1320. The IC package 1320 may be or include, for example, a die (die 1102 in FIG. 11B), an IC device (e.g., IC device 1200 in FIG. 12), or any other suitable component. In general, the interposer 1304 may spread connections to a wider pitch or reroute connections to different connections. For example, the interposer 1304 may couple an IC package 1320 (e.g., a die) to a ball grid array (BGA) of the mating component 1316 for coupling to the circuit board 1302. In the embodiment shown in FIG. 13, the IC package 1320 and the circuit board 1302 are attached to opposing sides of the interposer 1304. In other embodiments, the IC package 1320 and the circuit board 1302 may be attached to the same side of the interposer 1304. In some embodiments, three or more components may be interconnected by the interposer 1304.

[0144] The interposer 1304 may be formed of epoxy, fiberglass reinforced epoxy, ceramic materials, or polymeric materials such as polyimide. In some implementations, the interposer 1304 may be formed of alternating rigid or flexible materials that may include the same materials described above used for semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through silicon vias (TSVs) 1306. The interposer 1304 may further include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 1304. The package-on-interposer structure 1336 may take the form of any of the package-on-interposer structures known in the art.

[0145] The IC device assembly 1300 may include an IC package 1324 coupled to a first surface 1340 of the circuit board 1302 by a coupling component 1322. The coupling component 1322 may take the form of any of the embodiments described above with reference to the coupling component 1316, and the IC package 1324 may take the form of any of the embodiments described above with reference to the IC package 1320.

[0146] 13 includes a package-on-package structure 1334 coupled to a second surface 1342 of a circuit board 1302 by a coupling component 1328. The package-on-package structure 1334 includes an IC package 1326 and an IC package 1332 coupled together by a coupling component 1330 such that the IC package 1326 is disposed between the circuit board 1302 and the IC package 1332. The coupling components 1328 and 1330 may take the form of any of the embodiments of the coupling component 1316 described above, and the IC packages 1326 and 1332 may take the form of any of the embodiments of the IC package 1320 described above. The package-on-package structure 1334 may be configured according to any one of the package-on-package structures known in the art.

[0147] The embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be manufactured. Additionally, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), cellular telephones, personal electronic devices, and the like. The integrated circuits may be coupled with buses and other components of the system. For example, a processor may be coupled with a memory, a chipset, and the like by one or more buses. Each of the processors, memories, and chipsets may potentially be manufactured using the approaches disclosed herein.

[0148] 14 illustrates a computing device 1400 according to one embodiment of the present disclosure. The computing device 1400 houses a substrate 1402. The substrate 1402 may include a number of components, including, but not limited to, a processor 1404 and at least one communication chip 1406. The processor 1404 is physically and electrically coupled to the substrate 1402. In some implementations, the at least one communication chip 1406 is also physically and electrically coupled to the substrate 1402. In further implementations, the communication chip 1406 is part of the processor 1404.

[0149] Depending on its application, computing device 1400 may include multiple other components that may or may not be physically and electrically coupled to substrate 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0150] The communications chip 1406 enables wireless communications for transferring data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data using modulated electromagnetic radiation through a non-solid medium. The term is not intended to imply that the devices involved do not include any wires, although in some embodiments the devices involved may not include wires. The communications chip 1406 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The computing device 1400 may include multiple communication chips 1406. For example, a first communication chip 1406 may be dedicated to short-range wireless communication such as Wi-Fi® and Bluetooth®, and a second communication chip 1406 may be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, etc.

[0151] The processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404. In some implementations of the present disclosure, the integrated circuit die of the processor includes one or more thin film transistors having a linerless self-forming barrier according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or part of a device that processes electronic data from a number of registers and / or memory and converts the electronic data into other electronic data that can be stored in the registers and / or memory.

[0152] The communications chip 1406 also includes an integrated circuit die packaged within the communications chip 1406. In accordance with another implementation of an embodiment of the present disclosure, the integrated circuit die of the communications chip includes one or more thin film transistors having a linerless self-forming barrier in accordance with an implementation of an embodiment of the present disclosure.

[0153] In a further implementation, another component contained within computing device 1400 may include an integrated circuit die including one or more thin film transistors having a linerless self-forming barrier according to an implementation of an embodiment of the present disclosure.

[0154] In various implementations, computing device 1400 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder, In further implementations, computing device 1400 may be any other electronic device that processes data.

[0155] Accordingly, embodiments described herein include an integrated circuit structure having a linerless self-forming barrier, and a method of fabricating an integrated circuit structure having a linerless self-forming barrier.

[0156] The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations and examples of the disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0157] These variations may be made to the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the present disclosure should be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0158] Exemplary embodiment 1: An integrated circuit structure includes a dielectric material above a substrate. An interconnect structure is in a trench in the dielectric material. The interconnect structure includes a conductive fill material and a two-dimensional (2D) crystalline liner. The 2D crystalline liner is in direct contact with the dielectric material and in direct contact with the conductive fill material. The 2D crystalline liner includes the same metal species as the conductive fill material.

[0159] Exemplary embodiment 2: In the integrated circuit structure of exemplary embodiment 1, the 2D crystalline liner is a single layer.

[0160] Exemplary embodiment 3: In the integrated circuit structure of exemplary embodiment 1 or 2, the 2D crystalline liner has a thickness less than 5 nanometers.

[0161] Exemplary embodiment 4: In the integrated circuit structure of exemplary embodiment 1, 2 or 3, the metal species is copper.

[0162] Exemplary embodiment 5: In the integrated circuit structure of exemplary embodiment 1, 2 or 3, the metal species is cobalt.

[0163] Exemplary embodiment 6: In the integrated circuit structure of exemplary embodiment 1, 2 or 3, the metal species is tungsten.

[0164] Exemplary Embodiment 7: The integrated circuit structure of exemplary embodiment 1, 2, 3, 4, 5 or 6, wherein the 2D crystalline liner is further on the top surface of the interconnect structure.

[0165] Exemplary Embodiment 8: In the integrated circuit structure of exemplary embodiment 1, 2, 3, 4, 5, 6 or 7, the interconnect structure includes a conductive line over the conductive via.

[0166] Exemplary embodiment 9: An integrated circuit structure includes a semiconducting oxide material above a gate electrode. A pair of conductive contacts is on a first region of the semiconducting oxide material, and a second region of the semiconducting oxide material is between the pair of conductive contacts. Each pair of conductive contacts includes a conductive fill material and a two-dimensional (2D) crystalline liner. The 2D crystalline liner is in direct contact with the semiconducting oxide material and in direct contact with the conductive fill material. The 2D crystalline liner includes the same metal species as the conductive fill material.

[0167] Exemplary embodiment 10: In the integrated circuit structure of exemplary embodiment 9, the 2D crystalline liner is a single layer.

[0168] Exemplary embodiment 11: In the integrated circuit structure of exemplary embodiment 9 or 10, the 2D crystalline liner has a thickness less than 5 nanometers.

[0169] Exemplary embodiment 12: In the integrated circuit structure of exemplary embodiment 9, 10 or 11, the metal species is copper.

[0170] Exemplary Embodiment 13: The integrated circuit structure of Exemplary Embodiments 9, 10 or 11, wherein the metal species is cobalt.

[0171] Exemplary Embodiment 14: The integrated circuit structure of exemplary embodiments 9, 10 or 11, wherein the metal species is tungsten.

[0172] Exemplary embodiment 15: In the integrated circuit structure of exemplary embodiment 9, 10, 11, 12, 13 or 14, the semiconducting oxide material comprises a material selected from the group consisting of indium gallium zinc oxide, tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide and tungsten oxide.

[0173] Exemplary Embodiment 16: The integrated circuit structure of Exemplary Embodiment 9, 10, 11, 12, 13, 14 or 15, further comprising a gate dielectric layer between the gate electrode and the semiconducting oxide material.

[0174] Exemplary Embodiment 17: The integrated circuit structure of Exemplary Embodiment 16, wherein the gate dielectric layer comprises a layer of high-k dielectric material directly overlying a semiconducting oxide material.

[0175] Exemplary embodiment 18: An integrated circuit structure includes a semiconductor fin. A gate electrode is above the semiconductor fin. The gate electrode includes a conductive fill material and a two-dimensional (2D) crystalline liner. The 2D crystalline liner is in direct contact with the conductive fill material. The 2D crystalline liner includes the same metal species as the conductive fill material. The 2D crystalline liner has a different work function than the conductive fill material.

[0176] Exemplary embodiment 19: In the integrated circuit structure of exemplary embodiment 18, the 2D crystalline liner is a single layer.

[0177] Exemplary Embodiment 20: In the integrated circuit structure of exemplary embodiment 18 or 19, the 2D crystalline liner has a thickness less than 5 nanometers.

[0178] Exemplary embodiment 21: In the integrated circuit structure of exemplary embodiment 18, 19 or 20, the metal species is copper.

[0179] Exemplary Embodiment 22: In the integrated circuit structure of Exemplary Embodiments 18, 19 or 20, the metallic species is cobalt.

[0180] Exemplary Embodiment 23: In the integrated circuit structure of Exemplary Embodiments 18, 19 or 20, the metal species is tungsten.

Claims

1. Providing a dielectric material having a trench over a substrate; providing an interconnect structure in the trench in the dielectric material; Equipped with The step of providing an interconnect structure includes: providing a conductive fill material in the trenches of the dielectric material; after the step of providing the conductive fill material, annealing in a growth gas containing elements that react with the conductive fill material to form a two-dimensional (2D) crystalline liner to provide the 2D crystalline liner; having said 2D crystalline liner is in direct contact with said dielectric material and said conductive fill material, said 2D crystalline liner comprising the same metal species and said elements of said growth gas as said conductive fill material; A method for manufacturing integrated circuit structures.

2. The method of claim 1 , wherein the 2D crystalline liner is a single layer.

3. The method of claim 1 or 2, wherein the 2D crystalline liner has a thickness less than 5 nanometers.

4. A method for manufacturing an integrated circuit structure as claimed in any one of claims 1 to 3, wherein the metal species is copper.

5. A method for manufacturing an integrated circuit structure as claimed in any one of claims 1 to 3, wherein said metallic species is cobalt.

6. A method for manufacturing an integrated circuit structure as claimed in any one of claims 1 to 3, wherein the metal species is tungsten.

7. The method of claim 1 , wherein the 2D crystalline liner is further on a top surface of the interconnect structure.

8. The method of claim 1 , wherein the interconnect structure comprises a conductive line over a conductive via.

9. A method for manufacturing an integrated circuit structure as claimed in any one of claims 1 to 8, wherein the growth gas comprises a forming gas.

10. providing a semiconducting oxide material over a gate electrode; providing a conductive contact over the semiconducting oxide material; Equipped with The step of providing a conductive contact comprises: providing a conductive fill material above the semiconducting oxide material; after the step of providing the conductive fill material, annealing in a growth gas containing elements that react with the conductive fill material to form a two-dimensional (2D) crystalline liner to provide the 2D crystalline liner; having said 2D crystalline liner is in direct contact with said semiconducting oxide material and said conductive fill material, said 2D crystalline liner comprising the same metal species as said conductive fill material and said elements of said growth gas; A method for manufacturing integrated circuit structures.

11. The method of claim 10, wherein the 2D crystalline liner is a single layer.

12. A method for fabricating an integrated circuit structure as claimed in claim 10 or 11, wherein the 2D crystalline liner has a thickness less than 5 nanometers.

13. A method for manufacturing an integrated circuit structure as claimed in any one of claims 10 to 12, wherein the metal species is copper.

14. A method for manufacturing an integrated circuit structure as claimed in any one of claims 10 to 12, wherein the metal species is cobalt.

15. A method for manufacturing an integrated circuit structure as claimed in any one of claims 10 to 12, wherein the metal species is tungsten.

16. 16. A method for fabricating an integrated circuit structure as claimed in any one of claims 10 to 15, wherein the semiconducting oxide material comprises a material selected from the group consisting of indium gallium zinc oxide, tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide and tungsten oxide.

17. A method for fabricating an integrated circuit structure as claimed in any one of claims 10 to 16, further comprising a gate dielectric layer between the gate electrode and the semiconducting oxide material.

18. 20. The method of claim 17, wherein said gate dielectric layer comprises a layer of high-k dielectric material directly over said semiconducting oxide material.

19. A method for manufacturing an integrated circuit structure as claimed in any one of claims 10 to 18, wherein the growth gas comprises a forming gas.

20. providing a semiconductor fin; providing a gate electrode over the semiconductor fin; Equipped with The step of providing the gate electrode comprises: providing a conductive fill material above the semiconductor fin; annealing in a growth gas containing elements that react with the conductive fill material to form a two-dimensional (2D) crystalline liner to provide the 2D crystalline liner; having the 2D crystalline liner is in direct contact with the conductive fill material, the 2D crystalline liner comprises the same metal species and the elements of the growth gas as the conductive fill material, and the 2D crystalline liner has a different work function than the conductive fill material; A method for manufacturing integrated circuit structures.

21. The method of claim 20, wherein the 2D crystalline liner is a single layer.

22. A method for fabricating an integrated circuit structure as claimed in claim 20 or 21, wherein the 2D crystalline liner has a thickness less than 5 nanometers.

23. A method for manufacturing an integrated circuit structure as claimed in any one of claims 20 to 22, wherein the metal species is copper.

24. A method for manufacturing an integrated circuit structure as claimed in any one of claims 20 to 22, wherein the metal species is cobalt.

25. A method for manufacturing an integrated circuit structure as claimed in any one of claims 20 to 22, wherein the metal species is tungsten.

26. A method for producing an integrated circuit structure as claimed in any one of claims 20 to 25, wherein the growth gas comprises a forming gas.

Images