Calibrating Majorana qubits by exploring topological degeneracy

Abstract

A method for use with a topological quantum computing device is provided. The method may include setting a plurality of device parameters for a qubit architecture including a plurality of Majorana Zero Modes (MZMs). The method may further include adjusting the plurality of device parameters at least in part by determining whether the plurality of MZMs have ground state degeneracy. If it is determined that the plurality of MZMs do not exhibit ground state degeneracy, altering the plurality of device parameters may further include altering one or more device parameters of the plurality of device parameters. If it is determined that the plurality of MZMs exhibit ground state degeneracy, the method may further include altering one or more parameters of a measurement device coupled to the qubit architecture.

Description

[Technical Field]

[0001]

[0001] Background technology Topological qubits are a type of qubit that has been the focus of recent quantum computing research. Each topological qubit may have Majorana zero modes (MZMs), which may be formed, for example, at the junction between a semiconductor and a superconductor. A measurement device may be coupled to each MZM included in the qubit. When a topological quantum computing device is used, a gate may be applied to the topological qubit by performing a series of measurements on the qubit. Each of these measurements may be a joint parity operator measurement on two or more MZMs included in the qubit. Thus, quantum computing may be performed by applying a series of joint parity measurements to the MZMs included in the topological qubit. Summary of the Invention

[0002] According to one aspect of the present disclosure, a method for use with a topological quantum computing device is provided. The method may include setting a plurality of device parameters for a qubit architecture including a plurality of Majorana Zero Modes (MZMs). The method may further include adjusting the plurality of device parameters at least in part by determining whether the plurality of MZMs have ground state degeneracy. If it is determined that the plurality of MZMs do not exhibit ground state degeneracy, altering the plurality of device parameters may further include altering one or more device parameters of the plurality of device parameters. If it is determined that the plurality of MZMs do not exhibit ground state degeneracy, the method may further include altering one or more parameters of a measurement device coupled to the qubit architecture.

[0003] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. Moreover, the claimed subject matter is not limited to implementations that solve any or all of the disadvantages discussed in any part of this disclosure. [Brief explanation of the drawings]

[0003] [Figure 1]

[0004] FIG. 1 illustrates a schematic diagram of a topological quantum computing device including a qubit architecture according to an example embodiment. [Figure 2A]

[0005] FIG. 2A illustrates exemplary qubit architectures with Majorana tetron configurations that may be included in the topological quantum computing device of FIG. 1. [Figure 2B]FIG. 2B illustrates an exemplary qubit architecture based on a Majorana-Tetron configuration that may be included in the topological quantum computing device of FIG. [Figure 3A]

[0006] Figure 3A shows exemplary qubit architectures with Majorana hexon configurations that may be included in the topological quantum computing device of Figure 1. [Figure 3B] FIG. 3B illustrates an exemplary qubit architecture based on a Majorana hexon configuration that may be included in the topological quantum computing device of FIG. [Figure 4A]

[0007] FIG. 4A shows a flowchart of an example method that can be used with the topological quantum computing device of FIG. [Figure 4B]

[0008] FIG. 4B illustrates steps of the method of FIG. 4A that may be performed to set one or more device parameters of the qubit architecture. [Figure 4C]

[0009] Figure 4C illustrates steps of the method of Figure 4A that can be performed to determine, based on one or more conductance measurements, whether multiple Majorana zero modes included in a qubit architecture exhibit ground state degeneracy. [Figure 4D]

[0010] FIG. 4D illustrates steps of the method of FIG. 4A that may be performed when determining whether multiple Majorana zero modes exhibit ground state degeneracy. [Figure 4E]

[0011] FIG. 4E illustrates steps of the method of FIG. 4A that may be performed to determine whether multiple Majorana zero modes included in a qubit architecture exhibit ground state degeneracy based on one or more charge measurements. [Figure 5]

[0012] Figure 5 shows a schematic diagram of an exemplary computing environment in which the topological quantum computing device of Figure 1 may be implemented. DETAILED DESCRIPTION OF THE INVENTION

[0004]

[0013] When a topological quantum computing device is constructed, each topological qubit included in the topological quantum computing device may have its own set of device parameters that affect the usability of that topological qubit for performing operations. Exemplary parameters may include one or more plunger gate voltages, one or more cutter gate voltages, one or more quantum dot voltages, or external magnetic field strength, as described in further detail below. The values ​​of such parameters may affect the amount of noise introduced into the qubit system when a measurement is performed. For example, noise may be introduced into the qubit system via quasiparticle poisoning, pairwise dephasing, or hybridization. In some regions of the parameter space, the amount of measurement noise may exceed an acceptable noise threshold level. Therefore, if the parameters of a topological qubit lie within such regions of the parameter space, the topological qubit may not be usable for performing accurate quantum computing.

[0005]

[0014] The fabrication process for topological qubits included in topological quantum computing devices can perform testing procedures on the topological qubits to determine whether the device parameters of those qubits are within an acceptable region of parameter space. If the topological qubit is outside the acceptable region, the parameters of the topological qubit can be altered. Current methods for testing and modifying the parameters of topological qubits typically involve either detecting the presence of MZM pairs in individual topological superconducting wires or testing the properties of the full qubit. However, when these existing methods are used to test the behavior of a qubit, it can require multiple parameters to be adjusted to bring the topological qubit into the desired region of parameter space. Furthermore, qubit parameters can have complex interdependencies, which can make the qubit testing and parameter adjustment process more difficult and expensive.

[0006]

[0015] To address the above difficulties, a topological quantum computing device 10 is provided, as shown schematically in the example of FIG. 1. The topological quantum computing device 10 may include a qubit architecture 70 including multiple MZMs 12. It will be appreciated that a qubit architecture is a three-dimensional physical structure in which one or more qubits are instantiated during operation of the topological quantum computing device 10. Each MZM 12 may be formed, for example, at a junction between a semiconductor 14 and a superconductor 16, each of which may be formed as a wire. Multiple superconducting wires may form a superconducting island within which each of the MZMs 12 is formed. The qubit architecture 70 may be, for example, a Majorana tetron including four MZMs as part of the qubit and two ancillary MZMs. As another example, the qubit architecture 70 may be a Majorana hexon including six MZMs as part of the qubit and two ancillary MZMs. Other numbers of qubit MZMs or auxiliary MZMs may alternatively be included in qubit architecture 70.

[0007]

[0016] Additionally, qubit architecture 70 may include one or more cutter gates 18 and one or more plunger gates 20. The one or more cutter gates 18 and one or more plunger gates 20 can be opened or closed to set voltages applied to various portions of qubit structure 70 and to open or close junctions between semiconductor 14 and superconductor 16. Additionally, cutter gates 18 may be used to open or close electrical connections between regions of semiconductor 14. Each plunger gate 20 can be positioned proximate to a semiconductor or superconducting wire between two MZMs 12 included in qubit structure 70. As described in more detail below, plunger gates 20 positioned proximate to the superconducting wire can be used to adjust the topological phase of each of the MZMs 12 by adjusting the plunger gate voltages 52 of those plunger gates.

[0008]

[0017] The topological quantum computing device 10 may further include a measurement device 30. The measurement device 30 may include a plurality of quantum dots 32 coupled to a qubit architecture 70. Each quantum dot 32 included in the measurement device 30 may be electrically coupled to a corresponding pair of MZMs 12. The quantum dots 32 may be coupled to the qubit architecture 70 by a plurality of electrical leads. In some examples, the qubit architecture 70 may have a substantially planar shape. In such examples, the plurality of electrical leads may include a plurality of planar leads 22 disposed within the plane of the qubit architecture 70. Additionally or alternatively, the quantum dots 32 may be coupled to the qubit architecture 70 by a plurality of non-planar leads 24 extending in a direction perpendicular to the plane of the qubit architecture 70. In some examples, a bias voltage may be applied to the qubit architecture 70 via a plurality of electrical leads. The individual quantum dot voltages 58 of the quantum dots 32 may be adjusted by adjusting the plunger gate voltages 52 of the plunger gates 20 located in close proximity to the electrical leads connected to those quantum dots 32.

[0009]

[0018] The topological quantum computing device 10 may further include a qubit controller 40. For example, the qubit controller 40 may be a classical computing device including a processor and a memory. The qubit controller 40 may be configured to send control signals to the qubit architecture 70, which may include modifications to device parameters 50 of the qubit architecture 70. Additionally, the qubit controller 40 may be further configured to receive measurement results 34 from the measurement device 30.

[0010]

[0019] 2A-3B illustrate an exemplary qubit architecture 70 that may be included in the topological quantum computing device 10. The qubit architecture 70A of FIG. 2A may be included in a grid of multiple qubits. FIG. 2A illustrates an exemplary qubit architecture 70A in which the qubit is formed by a Majorana-tetron, which includes a first MZM 12A, a second MZM 12B, a third MZM 12C, and a fourth MZM 12D as qubit MZMs, and a fifth MZM 12E and a sixth MZM 12F as auxiliary MZMs. MZMs 12A, 12B, 12C, 12D, 12E, and 12F are all formed at the junction between the semiconductor 14 and the superconductor 16. Additionally, multiple planar leads 22 and multiple non-planar leads 24 are connected to the qubit structure 70A. Planar leads 22 and non-planar leads 24 can electrically couple MZM 12 to measurement device 30. Qubit structure 70A further includes a plurality of cutter gates 18 and a plurality of plunger gates 20, which can be opened and closed by qubit controller 40.

[0011]

[0020] 2A, measurement device 30 includes multiple quantum dots 32 located within a semiconductor wire, which is shown extending perpendicular to the superconducting wire from which MZMs 12A, 12B, 12C, 12D, 12E, and 12F are formed. Each quantum dot 32 has an individual quantum dot voltage 58 that can be controlled by setting the individual plunger gate voltages 52 and cutter gate voltages 54 of the plunger gate 20 and cutter gate 18 located proximate to that quantum dot 32.

[0012]

[0021] 2B shows another example qubit architecture 70B having a Majorana-Tetron configuration. In the example of FIG. 2B, each lead connecting qubit architecture 70B to measurement device 30 is a non-planar lead 24.

[0013]

[0022] FIG. 3A shows another example qubit architecture 70C having a Majorana hexon configuration. Qubit architecture 70C includes a first MZM 12A, a second MZM 12B, a third MZM 12C, a fourth MZM 12D, a fifth MZM 12E, and a sixth MZM 12F as qubit MZMs. Qubit architecture 70C also includes a seventh MZM 12G and an eighth MZM 12H as auxiliary MZMs. Qubit architecture 70C is coupled to qubit controller 40 by multiple planar leads 22 and multiple non-planar leads 24. As in the example of FIGS. 2A-2B, multiple quantum dots 32 are included in qubit architecture 70C of FIG. 3A as part of measurement device 30.

[0014]

[0023] 3B shows another example qubit architecture 70D having a Majorana hexon configuration. In the example of FIG. 3B, each lead connecting qubit architecture 70D to measurement device 30 is a non-planar lead 24.

[0015]

[0024] Referring again to FIG. 1 , qubit controller 40 may be configured to set a plurality of device parameters 50 for qubit architecture 70 to preliminary values. Fine-tuning of these device parameters 50 may be performed later, as described in further detail below. The plurality of device parameters 50 may include one or more plunger gate voltages 52 for one or more individual plunger gates 20 included in qubit architecture 70. The plurality of device parameters 50 may additionally or alternatively include one or more cutter gate voltages 54 for one or more individual cutter gates 18 included in qubit architecture 70. Additionally or alternatively, the plurality of device parameters 50 may further include the strength of an external magnetic field 56 applied to qubit architecture 70. In other embodiments, qubit architecture 70 may have one or more other device parameters 50.

[0016]

[0025] When the qubit controller 40 sets the preliminary values ​​of the device parameters 50, the measurement device 30 may be configured to perform one or more zero-bias peak measurements 60, correlated zero-bias peak measurements 62, or nonlocal conductance measurements 64 on the qubit architecture 70. The zero-bias peak measurements 60 may return the value of conductance across the semiconductor-superconductor boundary where the MZM 12 is formed when the bias voltage of the semiconductor 14 is set to zero. The zero-bias peak measurements 60 may be local conductance measurements performed between electrical leads connected to two MZMs 12 included in the same superconducting wire. The correlated zero-bias peak measurements 62 may return the relationship between the conductance values ​​of the two MZMs 12 when the bias voltage is set to zero. For example, the correlated zero-bias peak measurements 62 may return the difference between the respective zero-bias peak conductance values ​​for the first MZM 12 and the second MZM 12. A nonlocal conductance measurement 64 can return the value of the energy gap in the semiconductor 14 .

[0017]

[0026] Qubit controller 40 may be further configured to set a plurality of device parameters 50 for qubit architecture 70 based, at least in part, on results of one or more zero-bias peak measurements 60, correlated zero-bias peak measurements 62, or nonlocal conductance measurements 64. Using one or more zero-bias peak measurements 60, correlated zero-bias peak measurements 62, or nonlocal conductance measurements 64, qubit controller 40 may identify a region of parameter space in which MZM 12 operates in a topological mode (i.e., a mode in which an MZM is formed at the junction between semiconductor 14 and superconductor 16) rather than a trivial mode (i.e., a mode in which the junction between semiconductor 14 and superconductor 16 does not function as an MZM). Qubit controller 40 may be configured to identify a topological phase boundary between the topological and trivial regions and may be further configured to set initial values ​​of device parameters 50 such that each of MZMs 12 is in the topological region. Thus, qubit controller 40 can narrow the range over which device parameter 50 is adjusted when tuning qubit architecture 70. A preliminary value of device parameter 50 may be set for each superconducting wire at the end where the pair of MZMs 12 is located.

[0018]

[0027] The zero-bias peak measurement 60, the correlated zero-bias peak measurement 62, and the nonlocal conductance measurement 64 each have individual measurement signatures that can be indicative of topological modes. A zero bias peak measurement 60 can indicate that the junction between the semiconductor 14 and the superconductor 16 is in a topological mode when a conductance measurement performed on the semiconductor wire has a peak at or near zero bias voltage. A correlated zero-bias peak measurement 62 can indicate that the junction is in a topological mode when both ends of the semiconductor wire have a peak conductance value at or near zero bias voltage. Nonlocal conductance measurements 64 can show a phase transition from trivial to topological modes when the energy gap in the bulk of the semiconductor wire closes and then reopens as the strength of the external magnetic field 56 increases.

[0019]

[0028] In some examples, when qubit controller 40 sets initial values ​​for device parameters 50, qubit controller 40 may be configured to perform zero-bias peak measurements 60 and correlated zero-bias peak measurements 62 over a large area of ​​parameter space. Qubit controller 40 may be further configured to identify regions of parameter space having the above-described zero-bias peak and correlated zero-bias peak signatures. Furthermore, qubit controller 40 may be further configured to test for topological phase transition signatures using nonlocal conductance measurements 64, as described above.

[0020]

[0029] In some examples, as shown in FIGS. 2A-3B, the qubit architecture 70 can include at least one Josephson junction 26 connecting the superconductor 16 to a grounded electrical lead. In the examples of FIGS. 2A-3B, the grounded electrical lead is a nonplanar lead 24. Each Josephson junction 26 can be formed by a semiconductor wire and a cutter gate 18 disposed between two superconducting wires. A cutter gate voltage 54 of the cutter gate 18 can be controlled by the qubit controller 40 to set the strength of the Josephson coupling between the superconductor 16 and ground. When the cutter gate 18 is open, the superconductor 16 from which the MZM 12 is formed can be grounded. When the cutter gate 18 is closed, the superconductor 16 is isolated from ground, thus preventing quasiparticle current from flowing through the Josephson junction 26.

[0021]

[0030] In examples in which qubit architecture 70 includes Josephson junctions 26, qubit controller 40 may be configured to connect superconductor 16 included in qubit architecture 70 to ground via Josephson junctions 26 and then perform one or more zero-bias peak measurements 60 while superconductor 16 is grounded. Qubit controller 40 may also be configured to set device parameters 50 for qubit architecture 70 and decouple superconductor 16 from ground based, at least in part, on one or more zero-bias peak measurements 62, as described above. One or more zero-bias peak measurements 60 may be performed when the qubit architecture is grounded, while a ground state degeneracy test, described below, may be performed when qubit architecture 70 is decoupled from ground. Using Josephson junctions to ground and de-ground qubit architecture 70 may avoid grounding qubit architecture 70 via MZM 12.

[0022]

[0031] In some examples, other types of junctions may be used instead of Josephson junctions to ground qubit architecture 70 before performing one or more zero-bias peak measurements 60. In such examples, the junctions may be formed without using any other superconductors in addition to superconductor 16 of the superconducting island. Similar to Josephson junctions 26, the junctions may inhibit quasiparticle current from flowing from the superconducting island to ground when the junctions are closed.

[0023]

[0032] Following setting the initial values ​​of the device parameters 50, the qubit controller 40 may be further configured to calibrate the plurality of device parameters 50. Calibrating the plurality of device parameters 50 may include determining whether the plurality of MZMs 12 included in the qubit architecture 70 exhibit ground state degeneracy. Further, if it is determined that the plurality of MZMs 12 do not exhibit ground state degeneracy, the calibration may include adjusting the device parameters 50 to achieve at least approximate degeneracy of the ground states of the plurality of MZMs 12. For a system of N MZM pairs, the ground state degeneracy may be 2 N~1 It will be appreciated that the minimum number of MZM pairs is two, and thus detecting ground state degeneracy between multiple MZMs typically involves detecting ground state degeneracy between four or more MZMs. Because the system has applicability not only to tetrons but also to hexons, octons, and possibly higher order configurations, it will be appreciated that ground state degeneracy may alternatively be determined between four, six, or eight MZMs, or possibly more.

[0024]

[0033] If qubit architecture 70 has a degenerate or approximate degenerate basis state, then qubit architecture 70 may be usable to perform an operation. Thus, by determining whether each MZM 12 in qubit architecture 70 has a degenerate basis state, qubit controller 40 can test the usability of qubit architecture 70 without having to determine the values ​​of numerous properties of qubit architecture 70. Furthermore, existing methods for testing whether a qubit is usable may be prone to returning false positives. However, as discussed in more detail below, measurement signatures related to ground state degeneracy are unlikely to occur in qubit architectures that are not operating in a topological regime.

[0025]

[0034] In some examples, the qubit controller 40 may be configured to determine whether the plurality of MZMs 12 exhibit ground state degeneracy, at least in part, by determining whether the topological Kondo effect occurs for a subset of the plurality of MZMs 12. To determine whether the topological Kondo effect occurs for the MZMs 12, the qubit controller 40 may be further configured to measure the conductance 36 between a first MZM 12 of the plurality of MZMs 12 and a second MZM 12 of the plurality of MZMs 12. This conductance measurement may be performed when the first MZM 12, the second MZM 12, and at least a third MZM 12 of the plurality of MZMs 12 are connected to their respective electrical leads, for example, by opening cutter gates 18 disposed between the MZMs 12 and the electrical leads. When the conductance 36 is measured, a bias voltage may be applied to one electrical lead, and the other electrical lead is grounded.

[0026]

[0035] The qubit controller 40 may be further configured to determine whether the plurality of MZMs 12 exhibits ground state degeneracy based on the conductances 36. This determination may be made by determining whether the topological Kondo effect occurs for the plurality of MZMs 12. The topological Kondo effect occurs at a Kondo temperature T K The Kondo temperature is the topological gap A of the superconductor16. p and charge energy E c When the topological Kondo effect occurs, the Coulomb blockade effect is suppressed. As the temperature of the quantum architecture 70 tends to zero, the conductance between two electrical leads i and j tends to a constant value G i≠j = G0 / M, where G0 = 2e 2 / h, where e is the charge of an electron, h is Planck's constant, and M is the number of MZM12s connected to the electrical leads.

[0027]

[0036] The above conductance equation can be valid when M>2. When M=2, G i≠j Measuring a conductance value of G = G may be insufficient to determine that multiple MZMs 12 exhibit ground state degeneracy because, for M = 2, there are trivial states in addition to topological states that may have a conductance of G. Thus, as described above, qubit controller 40 may be configured to connect at least a third MZM 12 to a respective electrical lead when conductance measurements are performed. For example, the third MZM 12 may be grounded by opening a cutter gate 18 located proximate to the third MZM 12. After the cutter gate 18 connected to the third MZM 12 is opened, conductance 36 decreases to G i≠j = G / 3. The qubit controller 40 determines whether the conductance 36 is equal to G i≠j Qubit controller 40 may be configured to determine that MZM 12 exhibits ground state degeneracy when conductance 36 has the above value, or to output ground state degeneracy decision 66 indicating that MZM 12 does not exhibit ground state degeneracy when conductance 36 has some other value.

[0028]

[0037] In some examples, qubit controller 40 may be further configured to isolate the third MAM 12 from its respective electrical leads and measure the change in conductance 36 when the third MZM 12 is isolated. Thus, the value of M may be initially set to 3 and then reduced to 2. The change in conductance 36 when M is reduced to 2 may be used by qubit controller 40 when making ground state degeneracy determination 66. Alternatively, the value of M may be initially set to 2 and then increased to 3 by connecting the third MZM 12 to its respective electrical leads.

[0029]

[0038] In some examples, qubit controller 40 may be further configured to perform multiple conductance measurements when different sets of MZMs 12 are connected to the respective terminals. For example, each of these conductance measurements may be performed when three MZMs 12 are connected to the electrical leads such that M = 3. Based on the results of the multiple conductance measurements, qubit controller 40 may be further configured to identify one or more MZMs 12 among the multiple MZMs 12 that do not contribute to the degeneracy of the ground state.

[0030]

[0039] When qubit controller 40 determines whether MZM 12 exhibits ground state degeneracy based on the conductance measurement, qubit controller 40 may be further configured to calculate a temperature-dependent correction to conductance 36. With this correction, conductance 36 may be given by:

[0031]

number

[0032]

[0040] In some examples, charge sensing may additionally or alternatively be performed to determine whether multiple MZMs 12 exhibit ground state degeneracy. In this example, measurement device 30 may further include a charge sensor 33 capable of measuring charge 38 associated with qubit architecture 70. For example, charge sensor 33 may be a quantum dot or a quantum point contact. When charge sensing is used to test for ground state degeneracy, qubit controller 40 may be configured to vary a plunger gate voltage 52 of one or more plunger gate voltages 52. Using charge sensor 33 included in measurement device 30, qubit controller 40 may be further configured to measure a change in charge 38 associated with a superconductor included in qubit architecture 70 when plunger gate voltage 52 is varied. The change in charge 38 may be a change in the charge of a superconducting island formed by a superconducting wire.

[0033]

[0041] The qubit controller 40 may then determine whether the plurality of MZMs 12 exhibit ground state degeneracy based on the change in charge 38. The ground state degeneracy determination 66 is performed by E c < p This can be done based on the change in charge 38 when E c is the charging energy of the superconductor 16, and D R is the topological gap of the superconductor 16. If the MZM 12 exhibits ground state degeneracy, the charge 38 in the superconductor 16 may vary according to the equation:

[0034]

number

[0035]

number

[0036]

[0042] If the qubit controller 40 determines that at least one MZM 12 of the plurality of MZMs 12 does not contribute to ground state degeneracy (i.e., the plurality of MZMs does not exhibit ground state degeneracy or exhibits ground state degeneracy that is lower than expected for the number of MZMs included in the qubit architecture), the qubit controller 40 may be further configured to alter one or more device parameters 50 of the plurality of device parameters 50. In examples in which the plurality of device parameters 50 includes one or more plunger gate voltages 52, altering the one or more device parameters 50 may include altering the plunger gate voltages 52 of plunger gates 20. The plunger gates 20 whose plunger gate voltages 52 are altered may be plunger gates 20 located proximate to the first and second MZMs 12 or may be plunger gates 20 located proximate to another pair of MZMs 12. The plunger gate voltage 52 can be varied so that the conductance 36 measured for the pair approaches the topological conductance value G / M. i≠j = G0 / M yields the theoretically largest conductance, which occurs when the MZMs exhibit ground-state degeneracy and δG = 0, but higher conductance values ​​may be reached in some parameter-space regions outside the topological region.

[0037]

[0043] In some examples, qubit controller 40 may additionally or alternatively be configured to modify one or more plunger gate voltages 52 by altering one or more cutter gate voltages 54 or the strength of external magnetic field 56 applied to qubit architecture 70 when qubit controller 40 determines that the plurality of MZMs 12 do not exhibit ground state degeneracy. For example, qubit controller 40 may determine that the charging energy E of qubit architecture 70 is degenerate when at least one MZM 12 included in qubit architecture 70 is out of topological configuration. c To reduce this, the cutter gate 18 included in the Josephson junction 26 can be configured to be open.

[0038]

[0044] In some examples, qubit controller 40 may be further configured to calculate a value of a cost function 68 based on measurement results 34. Cost function 68 may be a function of the measured conductance value for each pair of MZMs 12 for which a conductance measurement is performed. For example, cost function 68 may be a function of the measured conductance 36 for each pair and the theoretical topological conductance G for that pair: i≠jThe cost function 68 may be a least-squares function of the difference between (i) and (ii). The qubit controller 40 may be further configured to apply an optimization technique, such as gradient descent, stochastic optimization, reinforcement learning, or some other optimization technique, to the cost function 68. When the qubit controller 40 applies one of these optimization techniques to the cost function 68, the qubit controller 40 may be configured to perform multiple parameter update iterations. In each parameter update iteration, the qubit controller 40 may be configured to perform conductance measurements for one or more pairs of MZMs 12, as described above. The qubit controller 40 may then calculate the value of the cost function 68 using the measured conductance values ​​as inputs. The qubit controller 40 may further be configured to adjust the values ​​of one or more of the device parameters 50 based on the calculated value of the cost function 68 according to the specified optimization technique. In addition to the current value of the cost function 68, the optimization technique may take as input one or more previous values ​​of the cost function 68 calculated during previous iterations. For example, if qubit controller 40 is configured to use gradient descent, qubit controller 40 may calculate one or more estimated derivatives of cost function 68 based on the current value of cost function 68 and one or more previous values ​​of cost function 68.

[0039]

[0045] As described above, by altering the device parameters 50 of the qubit architecture 70, the qubit controller 40 can be configured to calibrate the device parameters 50 so that each MZM 12 operates in a topological configuration and is thereby usable to perform computations. If a plurality of MZMs 12 are determined to exhibit ground state degeneracy (i.e., if each MZM 12 of the plurality of MZMs 12 is determined to contribute to the ground state degeneracy), the qubit controller 40 may further be configured to alter one or more measurement device parameters of a measurement device 30 coupled to the qubit architecture 70. The one or more measurement device parameters may include individual quantum dot voltages 58 of the plurality of quantum dots 32 coupled to the MZMs 12. In some examples, other parameters of the measurement device 30 may additionally or alternatively be altered.

[0040]

[0046] By calibrating measurement device 30 separately from MZM 12, qubit controller 40 can avoid having to consider dependencies between device parameters 50 and measurement device parameters. Thus, calibrating device parameters 50 and measurement device parameters separately can reduce the number of parameters that need to be changed and the area of ​​parameter space that needs to be searched to obtain a usable qubit.

[0041]

[0047] A method 100 for testing and varying parameters of a qubit architecture is provided, as shown in the exemplary flowchart of FIG. 4A. The steps of method 100 may each be performed in the topological quantum computing device 10 of FIG. 1 or in a topological quantum computing device having some other configuration. In step 102, method 100 may include setting device parameters for a qubit architecture including multiple MZMs. The device parameters may include, for example, one or more plunger gate voltages, one or more cutter gate voltages, or the strength of an external magnetic field. The parameter values ​​set in step 102 may be initial values ​​that can be adjusted in later steps of method 100.

[0042]

[0048] In some examples, step 102 includes pre-screening steps performed to select regions of parameter space within which further adjustments to device parameters may be made. These pre-screening steps are shown in the example of FIG. 4B. In some examples, step 102 may include, in step 102A, connecting a superconductor included in the qubit architecture to ground through a junction. For example, the junction may include a cutter gate that can be opened to connect the superconductor to ground. The junction may be a Josephson junction in some examples, or may be some other type of junction.

[0043]

[0049] In step 102B, step 102 may further include performing one or more zero-bias peak measurements, correlated zero-bias peak measurements, or nonlocal conductance measurements on the qubit architecture. Each of these measurements may be performed using a measurement device coupled to an MZM of the qubit architecture. The zero-bias peak measurement may return a value of conductance across the semiconductor-superconductor boundary where the MZM is formed when the bias voltage of the semiconductor is set to zero. The correlated zero-bias peak measurement may return a relationship between the conductance values ​​of the two MZMs when the bias voltage is set to zero. The nonlocal conductance measurement may return a value of the energy gap in the semiconductor wire.

[0044]

[0050] In step 102C, step 102 may further include setting a plurality of device parameters for the qubit architecture based at least in part on results of one or more zero-bias peak measurements, correlated zero-bias peak measurements, or nonlocal conductance measurements. The one or more zero-bias peak measurements, correlated zero-bias peak measurements, and nonlocal conductance measurements may each have a corresponding measurement signature indicating that junctions between one or more superconductors and one or more semiconductors in the qubit architecture form an MZM. When the device parameters are set based on results of the zero-bias peak measurements, correlated zero-bias peak measurements, or nonlocal conductance measurements, the qubit controller may be configured to identify a topological boundary between a topological region of parameter space and a trivial region of parameter space based on the measurement results. The parameters of the qubit architecture can then be set so that the qubit architecture operates within the topological region. Thus, in step 102C, qubit architectures can be pre-screened to select preliminary parameter values ​​that will allow the qubit system to operate within the topological region.

[0045]

[0051] In step 102D, step 102 may further include disconnecting the superconductor from ground. For example, in instances where the qubit architecture has a junction that includes a cutter gate, the superconductor can be disconnected from ground by closing the cutter gate. When the superconductor is disconnected from ground, quasiparticle current can be prevented from flowing into the superconductor.

[0046]

[0052] Returning to FIG. 4A, method 100 may further include calibrating a plurality of device parameters in step 104. In step 106, step 104 may include determining whether the plurality of MZMs exhibit ground state degeneracy. The plurality of MZMs may be used to perform quantum computing if the plurality of MZMs exhibit ground state degeneracy. Once step 106 is performed, it is possible to identify one or more MZMs that contribute to the ground state degeneracy and / or one or more MZMs that do not contribute to the ground state degeneracy.

[0047]

[0053] 4C illustrates exemplary steps of method 100 that may be performed during step 106 when determining whether the plurality of MZMs exhibit ground state degeneracy. In step 106A, step 106 may include measuring conductance between a first MZM of the plurality of MZMs and a second MZM of the plurality of MZMs when a first MZM, a second MZM, and at least a third MZM of the plurality of MZMs are connected to respective electrical leads. The conductance may be measured between electrical leads connected to the first MZM and the second MZM. Once the conductance is measured, a bias voltage may be applied to the first or second electrical lead, while the other electrical lead is grounded. In step 106B, step 106 may further include determining whether the plurality of MZMs exhibit ground state degeneracy based on the conductance. This determination may be made at least in part by comparing the measured conductance to a theoretical value of the conductance for a pair of MZMs when the MZMs exhibit ground state degeneracy.

[0048]

[0054] Determining whether the MZMs exhibit ground state degeneracy based on the measured conductance may further include, in step 106C, disconnecting the third MZM from its respective electrical leads. The third MZM may be disconnected by closing a cutter gate connected to the third MZM. In step 106D, determining whether the MZMs exhibit ground state degeneracy may further include measuring a change in conductance when the third MZM is disconnected. Following measuring the conductance when the third MZM is disconnected from its respective electrical leads, the presence or absence of ground state degeneracy may be determined by comparing the measured conductance value with the disconnected third MZM to a theoretical conductance value expected for a qubit architecture with the third MZM connected when the pair has ground state degeneracy.

[0049]

[0055] Returning to FIG. 4A , calibrating the plurality of device parameters in step 104 may further include altering one or more of the plurality of device parameters if it is determined in step 108 that the plurality of MZMs do not exhibit ground state degeneracy (i.e., in response to determining that the plurality of MZMs do not exhibit ground state degeneracy). For example, as shown in FIG. 4C , if the presence or absence of ground state degeneracy of the MZMs is determined based on conductance measurements, step 108 may include step 108A. If the MZMs do not exhibit ground state degeneracy in step 108A, method 100 may further include setting a plunger gate voltage of one or more plunger gates so that the conductance more closely approximates the conductance value of the topological configuration. Thus, the plurality of MZMs may be brought into the topological configuration by bringing the conductance between the pair of MZMs closer to the theoretical maximum conductance. Additionally or alternatively to varying the plunger gate voltage, varying the one or more device parameters may further include varying one or more of a cutter gate voltage or an external magnetic field strength.

[0050]

[0056] In some examples, as shown in FIG. 4D , in step 106E, calibrating the plurality of device parameters may include calculating a value of a cost function. For example, if method 100 includes measuring one or more conductance values, the value of the cost function may be calculated based, at least in part, on the one or more conductance values. Further, in step 108B, step 108 may further include varying the plurality of device parameters based on the value of the cost function. Determining whether the plurality of MZMs exhibit ground state degeneracy and varying the one or more device parameters may be repeated over multiple iterations, as shown in steps 106 and 108. For example, the cost function may be used in an optimization technique such as gradient descent, stochastic optimization, reinforcement learning, or any other optimization technique that is applied over multiple iterations to set values ​​of the device parameters.

[0051]

[0057] As shown in FIG. 4E, determining whether the plurality of MZMs exhibit ground state degeneracy in step 106 may include performing one or more charge measurements on the qubit architecture, in addition to or instead of the one or more conductance measurements described above. In step 106F, step 106 may further include varying a plunger gate voltage of at least one plunger gate included in the qubit architecture. In step 106G, step 106 may further include measuring a change in charge in a superconductor included in the qubit architecture as the plunger gate voltage is varied. The change in charge in the superconductor may be measured using a charge sensor included in the measurement device. In step 106H, step 106 may further include determining whether the plurality of MZMs exhibit ground state degeneracy based on the change in charge.

[0052]

[0058] Returning to FIG. 4A , method 100 may further include step 110, which may be performed if it is determined that the multiple MZMs exhibit ground state degeneracy (i.e., in response to determining that the multiple MZMs exhibit ground state degeneracy). Step 110 may include altering one or more measurement device parameters of a measurement device coupled to the qubit architecture. In examples where the measurement device includes multiple quantum dots coupled to the MZMs, altering the one or more measurement device parameters may include altering individual quantum dot voltages of the quantum dots. Other measurement device parameters may additionally or alternatively be altered during step 110.

[0053]

[0059] In the above-described systems and methods, when a topological quantum computing device is constructed, a topological qubit is evaluated for its usefulness in the topological quantum computing device. Furthermore, measurement device parameters of a measurement device configured to perform measurements on the qubit and device parameters of the qubit can be adjusted to values ​​suitable for performing quantum computing. Using the above-described systems and methods, the qubit architecture and the measurement device can be separately tested and calibrated, allowing such calibration and testing to be performed more quickly and reliably than existing testing and calibration methods.

[0054]

[0060] In some embodiments, the methods and processes described herein may be coupled to a computing system of one or more computing devices. In particular, such methods and processes may be implemented as computer application programs or services, application programming interfaces (APIs), libraries, and / or other computer program products.

[0055]

[0061] FIG. 5 schematically illustrates a non-limiting embodiment of a computing system 200 capable of implementing one or more of the methods and processes described above. The computing system 200 is shown in simplified form. The computing system 200 may embody the topological quantum computing device 10 shown in FIG. 1 above. The computing system 200 may take the form of one or more personal computers, server computers, tablet computers, home entertainment computers, networked computing devices, gaming devices, mobile computing devices, mobile communication devices (e.g., smartphones), and / or other computing devices, as well as wearable computing devices such as smart watches and head-mounted augmented reality devices.

[0056]

[0062] Computing system 200 includes a logical processor 202, a volatile memory 204, and a non-volatile storage device 206. Computing system 200 may optionally include a display subsystem 208, an input subsystem 210, a communication subsystem 212, and / or other components not shown in FIG.

[0057]

[0063] Logical processor 202 includes one or more physical devices configured to execute instructions. For example, a logical processor may be configured to execute instructions that are part of one or more applications, programs, routines, libraries, objects, components, data structures, or other logical constructs. Such instructions may be implemented to perform a task, implement a data type, transform the state of one or more components, achieve a technical effect, or otherwise arrive at a desired result.

[0058]

[0064] A logical processor may include one or more physical processors (hardware) configured to execute software instructions. Additionally or alternatively, a logical processor may include one or more hardware logic circuits or firmware devices configured to execute hardware-implemented logic or firmware instructions. The processors of logical processor 202 may be single-core or multi-core, and the instructions executed thereon may be configured for sequential, parallel, and / or distributed processing. Individual components of a logical processor may optionally be distributed among two or more separate devices, which may be remotely located and / or configured for cooperative processing. Aspects of a logical processor may be virtualized and executed by remotely accessible networked computing devices configured in a cloud computing configuration. In such cases, it will be understood that these virtualized aspects are executed on various physical logical processors of various different machines.

[0059]

[0065] Non-volatile storage device 206 includes one or more physical devices configured to hold instructions executable by a logical processor to implement the methods and processes described herein, such that when such methods and processes are executed, the state of non-volatile storage device 206 can be transformed, for example, to hold different data.

[0060]

[0066] The non-volatile storage device 206 may include removable and / or internal physical devices. The non-volatile storage device 206 may include optical memory (e.g., CD, DVD, HD-DVD, Blu-ray disc, etc.), semiconductor memory (e.g., ROM, EPROM, EEPROM, FLASH memory, etc.), and / or magnetic memory (e.g., hard disk drive, floppy disk drive, tape drive, MRAM, etc.), or other mass storage device technologies. The non-volatile storage device 206 may include non-volatile, dynamic, static, read / write, read-only, sequential access, position-addressable, file-addressable, and / or content-addressable devices. It will be understood that the non-volatile storage device 206 is configured to retain instructions even when power to the non-volatile storage device 206 is interrupted.

[0061]

[0067] Volatile memory 204 may include physical devices including random access memory. Volatile memory 204 is typically utilized by logical processor 202 to temporarily store information during the processing of software instructions. It will be understood that volatile memory 204 typically does not continue to store instructions if power to volatile memory 204 is interrupted.

[0068] Forms of logic processor 202, volatile memory 204, and non-volatile storage device 206 may be integrated together into one or more hardware logic components, which may include, for example, field programmable gate arrays (FPGAs), program and application specific integrated circuits (PASICs / ASICs), program and application specific standard products (PSSPs / ASSPs), systems on chips (SOCs), and complex programmable logic devices (CPLDs).

[0062]

[0069] The terms “module,” “program,” and “engine” may be used to describe an aspect of computing system 200 that is typically implemented in software by a processor to perform a specific function using a portion of volatile memory, where the function includes a transformation that specifically configures the processor to perform the function. Thus, a module, program, or engine may be instantiated via logical processor 202 using a portion of volatile memory 204 to execute instructions held by non-volatile storage device 206. It will be understood that different modules, programs, and / or engines may be instantiated from the same application, service, code block, object, library, routine, API, function, etc. Similarly, the same module, program, and / or engine may be instantiated from different applications, services, code blocks, objects, routines, APIs, functions, etc. The terms “module,” “program,” and “engine” may encompass each or groups of executable files, data files, libraries, drivers, scripts, database records, etc.

[0063]

[0070] If included, the display subsystem 208 can be used to present a visual representation of the data maintained by the non-volatile storage device 206. The visual representation can take the form of a graphical user interface (GUI). As the methods and processes described herein modify the data maintained by the non-volatile storage device and then transform the state of the non-volatile storage device, the state of the display subsystem 208 can likewise be transformed to visually represent the underlying data change. The display subsystem 208 can include one or more display devices utilizing virtually any type of technology. Such display devices may be combined with the logic processor 202, the volatile memory 204, and / or the non-volatile storage device 206 in a shared enclosure, or such display devices may be peripheral display devices.

[0064]

[0071] If included, the input subsystem 210 may include or interface with one or more user input devices, such as a keyboard, mouse, touch screen, or game controller. In some embodiments, the input subsystem may include or interface with selected natural user input (NUI) components. Such components may be integrated or peripheral, and input translation and / or processing may be handled on-board or off-board. Exemplary NUI components may include microphones for speech and / or voice recognition; infrared, color, stereo, and / or depth cameras for machine vision and / or gesture recognition; head trackers, eye trackers, accelerometers, and / or gyroscopes for motion detection and / or intent recognition; electric field detection components for assessing brain activity; and / or any other suitable sensors.

[0065]

[0072] If included, communications subsystem 212 can be configured to communicatively couple the various computing devices described herein with each other and with other devices. Communications subsystem 212 may include wired and / or wireless communications devices compatible with one or more different communications protocols. As a non-limiting example, communications subsystem 212 may be configured to communicate over a wired or wireless local or wide area network, such as a wireless telephone network or a HDMI over a Wi-Fi connection. In some embodiments, communications subsystem 212 can enable computing system 200 to send and receive messages to and / or from other devices over a network, such as the Internet.

[0066]

[0073] The following paragraphs describe several aspects of the present disclosure. According to one aspect of the present disclosure, a method for use with a topological quantum computing device is provided. The method may include setting a plurality of device parameters for a qubit architecture including a plurality of Majorana Zero Modes (MZMs). The method may further include tuning the plurality of device parameters at least in part by determining whether the plurality of MZMs exhibit ground state degeneracy and, if it is determined that the plurality of MZMs do not exhibit the ground state degeneracy, altering one or more device parameters of the plurality of device parameters. The method may further include, if it is determined that the plurality of MZMs exhibit ground state degeneracy, altering one or more measurement device parameters of a measurement device coupled to the qubit architecture.

[0067]

[0074] According to this aspect, determining whether the plurality of MZMs exhibit ground state degeneracy may include measuring conductance between a first MZM of the plurality of MZMs and a second MZM of the plurality of MZMs when a first MZM, a second MZM, and at least a third MZM of the plurality of MZMs are connected to respective electrical leads. Determining whether the plurality of MZMs exhibit ground state degeneracy may further include determining whether the plurality of MZMs exhibit ground state degeneracy based on the conductance.

[0068]

[0075] According to this aspect, the plurality of device parameters can include one or more plunger gate voltages for one or more individual plunger gates included in the qubit architecture.

[0069]

[0076] According to this aspect, altering the one or more device parameters can include setting a plunger gate voltage of a plunger gate of the one or more plunger gates such that the conductance more closely approximates a conductance value of the topological configuration.

[0070]

[0077] According to this aspect, determining whether the plurality of MZMs exhibit ground state degeneracy may further include disconnecting a third MZM from its respective electrical lead and measuring a change in conductance when the third MZM is disconnected.

[0071]

[0078] According to this aspect, the method may further include calculating a value of a cost function based at least in part on the conductance. The method may further include varying a plurality of device parameters based on the value of the cost function.

[0072]

[0079] According to this aspect, the plurality of device parameters may include one or more cutter gate voltages for one or more individual cutter gates included in the qubit architecture.

[0073]

[0080] According to this aspect, the plurality of device parameters can include the strength of an external magnetic field applied to the qubit architecture.

[0074]

[0081] According to this embodiment, the one or more measured device parameters may include individual quantum dot voltages of multiple quantum dots coupled to the MZM.

[0075]

[0082] According to this aspect, the method may further include performing one or more zero-bias peak measurements, correlated zero-bias peak measurements, or non-local conductance measurements on the qubit architecture. The method may further include setting device parameters of the qubit architecture based at least in part on results of the one or more zero-bias peak measurements, correlated zero-bias peak measurements, or non-local conductance measurements.

[0076]

[0083] According to this aspect, determining whether the plurality of MZMs exhibit ground state degeneracy can include varying a plunger gate voltage of at least one plunger gate included in the qubit architecture. Determining whether the plurality of MZMs exhibit ground state degeneracy can further include measuring a change in charge in a superconductor included in the qubit architecture when the plunger gate voltage is varied.

[0077]

[0084] According to another aspect of the present disclosure, a topological quantum computing device is provided, including a qubit architecture including a plurality of Majorana Zero Modes (MZMs). The topological quantum computing device may further include a qubit controller configured to set a plurality of device parameters for the qubit architecture. The qubit controller may be further configured to adjust the plurality of device parameters at least in part by determining whether the plurality of MZMs exhibit ground state degeneracy and, if it is determined that the plurality of MZMs do not exhibit ground state degeneracy, altering one or more device parameters of the plurality of device parameters. The qubit controller may be further configured to alter one or more measurement device parameters of a measurement device coupled to the qubit architecture if it is determined that the plurality of MZMs exhibit ground state degeneracy.

[0078]

[0085] According to this aspect, the plurality of device parameters may include at least one of: one or more plunger gate voltages for one or more individual plunger gates included in the qubit architecture; one or more cutter gate voltages for one or more individual cutter gates included in the qubit architecture; and a strength of an external magnetic field applied to the qubit architecture.

[0079]

[0086] According to this aspect, the qubit controller may be configured to determine whether the plurality of MZMs exhibit ground state degeneracy, at least in part, by measuring conductance between a first MZM of the plurality of MZMs and a second MZM of the plurality of MZMs when a first MZM, a second MZM, and at least a third MZM of the plurality of MZMs are connected to their respective electrical leads. The qubit controller may be further configured to determine whether the plurality of MZMs exhibit ground state degeneracy based on the conductance.

[0080]

[0087] According to this aspect, altering the one or more device parameters can include setting a plunger gate voltage of a plunger gate of the one or more plunger gates such that the conductance more closely approximates a conductance value of the topological configuration.

[0081]

[0088] According to this aspect, the qubit controller may be further configured to determine whether the plurality of MZMs exhibits ground state degeneracy, at least in part, by decoupling the third MZM from its respective electrical lead and measuring a change in conductance when the third MZM is decoupled.

[0082]

[0089] According to this aspect, the qubit controller may be configured to determine whether the plurality of MZMs exhibit ground state degeneracy, at least in part, by varying a plunger gate voltage of one or more plunger gates; measuring a change in charge in a superconductor included in the qubit architecture when the plunger gate voltage is varied; and determining whether the plurality of MZMs exhibits ground state degeneracy based on the change in charge.

[0083]

[0090] According to this aspect, the qubit controller may be further configured to perform one or more zero-bias peak measurements, correlated zero-bias peak measurements, or non-local conductance measurements on the qubit architecture. The qubit controller may be further configured to set device parameters of the qubit architecture based at least in part on results of the one or more zero-bias peak measurements, correlated zero-bias peak measurements, or non-local conductance measurements.

[0084]

[0091] According to this aspect, the measurement device may include a plurality of quantum dots coupled to the qubit architecture, and the one or more measurement device parameters may include a quantum dot voltage for each of the plurality of quantum dots.

[0085]

[0092] According to another aspect of the present disclosure, a topological quantum computing device is provided, including a qubit architecture including a plurality of Majorana Zero Modes (MZMs). The topological quantum computing device may further include a qubit controller configured to connect a superconductor included in the qubit architecture to ground via a junction. The qubit controller may be further configured to perform one or more zero-bias peak measurements on the qubit architecture. The qubit controller may be further configured to set a plurality of device parameters for the qubit architecture based, at least in part, on the one or more zero-bias peak measurements. The qubit controller may be further configured to decouple the superconductor from ground. The qubit controller may be further configured to calibrate the plurality of device parameters, at least in part, by determining whether the plurality of MZMs exhibit ground state degeneracy; and, if it is determined that the plurality of MZMs do not exhibit ground state degeneracy, modify one or more of the device parameters. The qubit controller may be further configured to alter one or more measurement device parameters of a measurement device coupled to the qubit architecture when the plurality of MZMs is determined to exhibit degeneracy of the basis states.

[0086]

[0093] It will be understood that the configurations and / or approaches described herein are exemplary in nature, and that, since many variations are possible, these specific embodiments or examples should not be considered in a limiting sense. The particular routines or methods described herein may represent one or more of any number of processing strategies. Thus, various operations illustrated and / or described may be performed in the order illustrated and / or described, in other orders, in parallel, or omitted. Similarly, the order of the processes described above may be changed.

[0087]

[0094] The subject matter of this disclosure includes all novel and non-obvious combinations and subcombinations of the various processes, systems, and configurations, as well as other features, functions, operations, and / or properties disclosed herein, and any and all equivalents thereof.

Claims

1. 1. A method for use with a topological quantum computing device, comprising: setting a plurality of device parameters for a qubit architecture including a plurality of semiconductor-superconductor junctions, the plurality of semiconductor-superconductor junctions configured to produce a plurality of Majorana Zero Modes (MZMs), the plurality of device parameters being respectively selected from the group consisting of a plunger gate voltage, a cutter gate voltage, and an external magnetic field strength; at least partially adjusting the plurality of device parameters; determining whether the plurality of semiconductor-superconductor junctions exhibit ground state degeneracy by measuring charge or conductance in the qubit architecture; and by altering one or more device parameters of the plurality of device parameters in response to determining that the plurality of semiconductor-superconductor junctions do not exhibit degeneracy of the ground state; and altering one or more measurement device parameters of a measurement device coupled to the qubit architecture in response to determining that the plurality of semiconductor-superconductor junctions exhibit degeneracy of the ground state; wherein the one or more measured device parameters include one or more quantum dot voltages; and The method, wherein varying the one or more device parameters and varying the one or more measurement device parameters includes performing a search over a range of each of the device parameters and the measurement device parameters.

2. 10. The method of claim 1, wherein determining whether the plurality of semiconductor-superconductor junctions exhibit the ground state degeneracy comprises: measuring conductance between a first semiconductor-superconductor junction of the plurality of semiconductor-superconductor junctions and a second semiconductor-superconductor junction of the plurality of semiconductor-superconductor junctions when the first semiconductor-superconductor junction, the second semiconductor-superconductor junction, and at least a third semiconductor-superconductor junction of the plurality of semiconductor-superconductor junctions are each connected to an electrical lead; and determining whether the plurality of semiconductor-superconductor junctions have degeneracy of the ground state based on the conductance; A method comprising:

3. 3. The method of claim 2, wherein altering the one or more device parameters comprises setting a plunger gate voltage of a plunger gate toward a conductance value of a topological form.

4. 3. The method of claim 2, wherein determining whether the plurality of semiconductor-superconductor junctions exhibit degeneracy of the ground state comprises: disconnecting the third semiconductor-superconductor junction from its respective electrical lead; and measuring the change in conductance when the third semiconductor-superconductor junction is disconnected; A method comprising:

5. 3. The method of claim 2, wherein: calculating a value of a cost function based at least in part on the conductance; and modifying the plurality of device parameters based on the value of the cost function; A method comprising:

6. 10. The method of claim 1, wherein the one or more measured device parameters include a quantum dot voltage, which is a voltage across a plurality of quantum dots coupled to the semiconductor-superconductor junction.

7. 10. The method of claim 1, further comprising: performing one or more zero-bias peak measurements, correlated zero-bias peak measurements, or non-local conductance measurements on the qubit architecture; and setting the device parameters of the qubit architecture based at least in part on results of the one or more zero-bias peak measurements, correlated zero-bias peak measurements, or non-local conductance measurements; A method comprising:

8. 10. The method of claim 1, wherein determining whether the plurality of semiconductor-superconductor junctions exhibit degeneracy of the ground state comprises: modifying a plunger gate voltage of at least one plunger gate included in the qubit architecture; measuring a change in charge in a superconductor included in the qubit architecture when the plunger gate voltage is changed; and determining whether the plurality of semiconductor-superconductor junctions exhibit degeneracy of the ground state based on the change in charge; A method comprising:

9. 1. A topological quantum computing device comprising: A qubit architecture including a plurality of semiconductor-superconductor junctions, the plurality of semiconductor-superconductor junctions configured to produce a plurality of Majorana Zero Modes (MZMs); and Classical computing devices; wherein the classical computing device comprises: setting a plurality of device parameters for the qubit architecture, the plurality of device parameters being respectively selected from the group consisting of a plunger gate voltage, a cutter gate voltage, and an external magnetic field strength; at least partially adjusting the plurality of device parameters; determining whether the plurality of semiconductor-superconductor junctions exhibit ground state degeneracy by measuring charge or conductance in the qubit architecture; and by altering one or more device parameters of the plurality of device parameters in response to determining that the plurality of semiconductor-superconductor junctions do not exhibit degeneracy of the ground state; and altering one or more measurement device parameters of a measurement device coupled to the qubit architecture in response to determining that the plurality of semiconductor-superconductor junctions exhibit degeneracy of the ground state; and The one or more measured device parameters include one or more quantum dot voltages; and 10. A topological quantum computing device, wherein varying the one or more device parameters and varying the one or more measured device parameters comprises searching over a range of the device parameters and the measured device parameters, respectively.

10. 10. The topological quantum computing device of claim 9, wherein the classical computing device comprises: determining, at least in part, whether the plurality of semiconductor-superconductor junctions exhibit degeneracy of the ground state; measuring conductance between a first semiconductor-superconductor junction of the plurality of semiconductor-superconductor junctions and a second semiconductor-superconductor junction of the plurality of semiconductor-superconductor junctions when the first semiconductor-superconductor junction, the second semiconductor-superconductor junction, and at least a third semiconductor-superconductor junction of the plurality of semiconductor-superconductor junctions are each connected to an electrical lead; and determining whether the plurality of semiconductor-superconductor junctions have degeneracy of the ground state based on the conductance; A topological quantum computing device configured to:

11. 10. The topological quantum computing device of claim 9, wherein the classical computing device comprises: determining, at least in part, whether the plurality of semiconductor-superconductor junctions exhibit degeneracy of the ground state; Varying a plunger gate voltage of one or more plunger gates; measuring a change in charge in a superconductor included in the qubit architecture when the plunger gate voltage is changed; and determining whether the plurality of semiconductor-superconductor junctions exhibit degeneracy of the ground state based on the change in charge; A topological quantum computing device configured to:

Images