Quantum circuit construction using simultaneous entanglement gates in a trapped-ion quantum computer

Abstract

1. A method of performing a computation using an ion trap quantum computing system comprising a classical computer, a system controller, and a quantum processor, the method comprising: computing, by the classical computer, a circuit that implements a selected set of gate operations using one or more Efficient Arbitrary Simultaneous Entanglement (EASE) gates; implementing, by the system controller, the computed circuit on the quantum processor; measuring, by the system controller, a population of qubit states in the quantum processor; and outputting, by the classical computer, the population of qubit states measured in the quantum processor.

Description

[Technical Field]

[0001] (Government Rights) This invention was made with government support under 70NANB16H168 awarded by the National Institute of Standards and Technology. The government has certain rights in this invention.

[0002] The present disclosure relates generally to methods for performing computations in ion trap quantum computers, and more particularly to methods for constructing quantum circuits using efficient arbitrary simultaneous entangling (EASE) gates. [Background technology]

[0003] Quantum computers have been shown to improve the performance of certain computational tasks compared to what classical computers can accomplish. Traditionally, quantum algorithms used to perform such computational tasks have been compiled by a set of universal gates, including single-qubit gates and two-qubit gates, executed sequentially. However, even the various quantum computing architectures available today do not utilize simultaneous (parallel) computation, similar to the single-instruction, multiple-data (SIMD) processing used in classical computing, and therefore require longer than desired computation times.

[0004] Therefore, there is a need for parallel processing methods for performing efficient quantum computations. Summary of the Invention

[0005] An embodiment of the present disclosure provides a method for performing a computation using an ion trap quantum computing system comprising a classical computer, a system controller, and a quantum processor, the method including: computing, by the classical computer, a circuit that implements a selected set of gate operations using one or more Efficient Arbitrary Simultaneous Entanglement (EASE) gates; implementing, by the system controller, the computed circuit on the quantum processor; measuring, by the system controller, a population of qubit states in the quantum processor; and outputting, by the classical computer, the population of qubit states measured at the quantum processor.

[0006]

[0006] Embodiments of the present disclosure also provide an ion trap quantum computing system. The ion trap quantum computing system includes a quantum processor including qubits, each qubit including a trapped ion having two hyperfine states; one or more lasers configured to illuminate the trapped ions in the quantum processor with a laser beam; a classical computer; and a system controller. The classical computer is configured to perform operations including computing a circuit that implements a selected set of gate operations using one or more Efficient Arbitrary Simultaneous Entanglement (EASE) gates. The system controller is configured to execute a control program for controlling the one or more lasers to perform operations on the quantum processor, including implementing the computed circuit on the quantum processor and measuring a population of qubit states in the quantum processor. The classical computer is further configured to output the population of qubit states measured in the quantum processor.

[0007]

[0006] Embodiments of the present disclosure further provide an ion trap quantum computing system comprising: a classical computer; a quantum processor including qubits, each qubit including a trapped ion having two hyperfine states; a non-volatile memory having instructions stored therein; a system controller configured to execute a control program for controlling one or more lasers to perform operations on the quantum processor; and a non-volatile memory having instructions stored therein. The instructions, when executed by the one or more processors, cause the ion trap quantum computing system to perform operations including: computing, by the classical computer, circuits that implement a selected set of gate operations using one or more Efficient Arbitrary Simultaneous Entanglement (EASE) gates; implementing, by the system controller, the computed circuits on the quantum processor; measuring, by the system controller, a population of qubit states in the quantum processor; and outputting, by the classical computer, the population of qubit states measured in the quantum processor. [Brief explanation of the drawings]

[0008] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure briefly summarized above can be set forth by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and should not be considered as limiting its scope, since the present disclosure may admit of other equally effective embodiments.

[0009] [Figure 1] FIG. 1 is a partial view of an ion trap quantum computer according to one embodiment. [Figure 2] 1 shows a schematic diagram of an ion trap for confining ions in chains, according to one embodiment. [Figure 3]1 shows a schematic energy diagram of each ion in a chain of trapped ions, according to one embodiment. [Figure 4] 4A, 4B, and 4C show some schematic collective transverse motion mode structures of a chain of five trapped ions. [Figure 5] 5A and 5B show schematic diagrams of the motional sideband spectrum and motional modes of each ion, according to one embodiment. [Figure 6] 1 shows a flowchart illustrating a method used to construct a circuit that implements a CZ gate layer operating on n qubits, according to one embodiment. [Figure 7] 1 shows a flowchart illustrating a method used to construct a circuit that implements a CNOT gate layer operating on n qubits without ancillary qubits, according to one embodiment. [Figure 8] 1 shows a flowchart illustrating a method used to construct a circuit implementing a CNOT gate layer operating on n qubits with n / 2 ancillary qubits, according to one embodiment. [Figure 9] 1 shows a flowchart illustrating a method used to construct a circuit implementing a Cn-1Z gate operating on n qubits (n=5, 6), according to one embodiment. [Figure 10] 1 shows a flowchart illustrating a method used to construct a circuit that implements a Cn-1Z gate operating on n qubits using 2n ancillary qubits, according to one embodiment. [Figure 11] 1 shows a flowchart illustrating a method used to construct a circuit that implements a qubit permutation gate that operates on n qubits, according to one embodiment. [Figure 12] 1 shows a flowchart illustrating a method used to construct a circuit that implements a controlled SWAP gate operating on n qubits, according to one embodiment.

[0010] For ease of understanding, the same reference numerals are used, where possible, to designate identical elements common to the figures. The figures and the following description use a Cartesian coordinate system including an X-axis, a Y-axis, and a Z-axis. For convenience, directions represented by arrows in the figures are assumed to be positive directions. It is believed that elements disclosed in some embodiments may be beneficially utilized in other implementations without specific specification. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0001] Embodiments described herein generally relate to methods and systems for constructing quantum circuits using efficient arbitrary simultaneous entanglement (EASE) gates in quantum computers, such as ion trap quantum computers. Similar to single instruction, multiple data (SIMD) processing used in conventional computing, parallel processing using EASE gates provides a more efficient quantum computation process.

[0012] An overall system capable of performing quantum computations using trapped ions includes a classical computer, a system controller, and a quantum processor. The classical computer performs support and system control tasks, including selecting a quantum algorithm to execute using a user interface such as a graphics processing unit (GPU), compiling the selected quantum algorithm into a series of quantum circuits, converting the series of quantum circuits into laser pulses to be applied to the quantum processor, and precalculating parameters to optimize the laser pulses using a central processing unit (CPU). Software programs for performing the tasks of decomposing and executing the quantum algorithm are stored in nonvolatile memory within the classical computer. The quantum processor includes trapped ions coupled to various hardware, including a laser for manipulating the internal hyperfine states (qubit states) of the trapped ions and an acousto-optic modulator for reading out the internal hyperfine states (qubit states). The system controller receives precalculated parameters for the laser pulses from the classical computer at the beginning of execution of the selected algorithm on the quantum processor, controls the various hardware associated with controlling any and all aspects used to execute the selected algorithm on the quantum processor, and returns readouts of the quantum processor and, therefore, the resulting output of the quantum computation to the classical computer at the end of execution of the algorithm.

[0013] (General hardware configuration) 1 is a schematic partial view of an ion trap quantum computing system 100, or simply system 100, according to one embodiment. System 100 includes a classical (digital) computer 102 and a system controller 104. Other components of system 100 shown in FIG. 1 are associated with a quantum processor that includes a group 106 of trapped ions (i.e., five shown as approximately equally spaced circles) extending along the Z axis. Each ion in group 106 of trapped ions is an ion, e.g., a positive ytterbium ion, having a nuclear spin I and an electron spin S such that the difference between the nuclear spin I and the electron spin S is zero. 171 Yb + , positive barium ions 133 Ba + , positive cadmium ions 111 CD + or 113 CD + and all of these have nuclear spin I=1 / 2 and 2 S 1 / 2 In some embodiments, all ions in the group of trapped ions 106 are of the same species and isotope (e.g., 171 Yb + In some other embodiments, the group of trapped ions 106 includes one or more species or isotopes (e.g., some ions are 171 Yb + and some other ions 133 Ba +(where, .times. ...

[0014] An imaging objective 108, such as a 0.37 numerical aperture (NA) objective, collects fluorescence from the ions along the Y-axis and maps each ion to a multichannel photomultiplier tube (PMT) 110 (or some other imaging device) for measurement of individual ions. A Raman laser beam from a laser 112, provided along the X-axis, performs operations on the ions. A diffractive beam splitter 114 creates an array of Raman laser beams 116 that are individually switched using a multichannel acousto-optic modulator (AOM) 118. The AOM 118 is configured to selectively affect individual ions by individually controlling the illumination of the Raman laser beams 116. A global Raman laser beam 120, which is non-copropagating with the Raman laser beam 116, illuminates all ions at once from a different direction. In some embodiments, individual Raman laser beams (not shown) can be used, each to illuminate an individual ion, rather than a single global Raman laser beam 120. A system controller (also called an "RF controller") 104 controls the AOM 118, and thus the intensity, timing, and phase of laser pulses applied to the trapped ions in the group 106 of trapped ions. The CPU 122 is the processor of the system controller 104. The ROM 124 stores various programs, and the RAM 126 is a working memory for various programs and data. The storage unit 128 includes a non-volatile memory, such as a hard disk drive (HDD) or flash memory, and stores various programs even when the power is turned off. The CPU 122, the ROM 124, the RAM 126, and the storage unit 128 are interconnected via a bus 130. The system controller 104 executes control programs stored in the ROM 124 or the storage unit 128 and using the RAM 126 as a working area.The control programs include software applications containing program code that can be executed by CPU 122 to perform various functions related to receiving and analyzing data and controlling any and all aspects of the methods and hardware used to implement and operate the ion trap quantum computing system 100 described herein.

[0015] 2 shows a schematic diagram of an ion trap 200 (also called a "Paul trap") that confines ions in groups 106, according to one embodiment. The confinement potential is applied by both a static (DC) voltage and a radio frequency (RF) voltage. The static (DC) voltage V S is applied to end cap electrodes 210 and 212 to confine ions along the Z axis (also called the "axial" or "longitudinal" direction). The ions within group 106 are approximately evenly distributed in the axial direction due to Coulomb interactions between the ions. In some embodiments, ion trap 200 includes four hyperbolic-shaped electrodes 202, 204, 206, and 208 that extend along the Z axis.

[0016] During operation, (amplitude V RF A sinusoidal voltage V1 having a phase shift of 180° (and amplitude V RF / 2) is a sinusoidal voltage V2 having a driving frequency ω RF The quadrupole potential is applied to the other pair of opposing electrodes 206, 208 at a frequency of 100 kHz to generate a quadrupole potential. In some embodiments, a sinusoidal voltage is applied only to the other pair of opposing electrodes 202, 204, and the other pair of opposing electrodes 206, 208 is grounded. The quadrupole potential generates an effective confinement force for each trapped ion in the XY plane perpendicular to the Z axis (also called the "radial" or "transverse" direction), which is proportional to the distance from the saddle point (i.e., the location in the axial (Z) direction) where the RF field vanishes. The radial (i.e., XY plane) motion of each ion is approximated as a harmonic oscillation (called the "secular motion") with a restoring force toward the radial saddle point, each with a spring constant k x and ky In some embodiments, the radial spring constants are modeled as equal when the quadrupole potential is radially symmetric. However, if undesired, the radial ion motion may be distorted due to some asymmetry in the physical trap configuration, small DC patch potentials due to non-uniformities on the electrode surfaces, etc. These and other external distortion sources may cause ions to de-center from the saddle point.

[0017] A different type of trap, not shown, is a microfabricated trapping tip, where a similar approach to that described above is used to hold or confine ions or atoms in place on the surface of the microfabricated trapping tip. A laser beam, such as the Raman laser beam described above, can be applied to the ions or atoms as they lie just above the surface.

[0018] 3 shows a schematic energy diagram 300 of each ion in the group of trapped ions 106, according to one embodiment. Each ion in the group of trapped ions 106 has a nuclear spin I and an electron spin S such that the difference between the nuclear spin I and the electron spin S is zero. In one example, each ion is a positive ytterbium ion. 171 Yb + and ω 01 Nuclear spins I=1 / 2 and I=2π with energy division corresponding to a frequency difference (called the "carrier frequency") of 12.642812 GHz. 2 S 1 / 2 In another example, each ion has a hyperfine state (i.e., two electronic states). 133 Ba + , positive cadmium ions 111 CD + or 113 CD + all of which have nuclear spin I=1 / 2 and 2 S 1 / 2 The qubit is formed in two hyperfine states, denoted |0> and |1>, and has a hyperfine ground state (i.e., 2 S1 / 2 A low-energy state among the hyperfine states is chosen to represent |0>. Hereinafter, the terms "hyperfine state", "internal hyperfine state", and "qubit" may be used interchangeably to represent |0> and |1>. Each ion can be cooled without phonon excitation (i.e., n ph = 0), the ground state of motion of any motion mode m is |0> m (i.e., the kinetic energy of the ions can be reduced), and then the qubit state can be prepared in the hyperfine ground state |0> by optical pumping, where |0> denotes the individual qubit state of the trapped ion, and |0> with the subscript m. m represents the motional ground state of motional mode m of the group 106 of trapped ions.

[0019] The individual qubit states of each trapped ion can be, for example, excited 2 P 1 / 2 The laser beam from the laser can be operated by a mode-locked laser at 355 nanometers (nm) through a level (represented by |e>). As shown in Figure 3, the laser beam from the laser is split into a pair of non-copropagating laser beams (the first laser beam with frequency ω1 and the second laser beam with frequency ω2) in a Raman configuration, with a transition frequency ω between |0> and |e> as illustrated in Figure 3. 0e With respect to the one-photon transition detuning frequency Δ=ω1-ω 0e The two-photon transition detuning frequency δ involves adjusting the amount of energy provided to the trapped ion by the first and second laser beams, which, when used in combination, move the trapped ion between the hyperfine states |0> and |1>. The one-photon transition detuning frequency Δ can be adjusted to the two-photon transition detuning frequency (also simply called the "detuning frequency") δ=ω1-ω2-ω 01 (hereafter, denoted as ±μ, where μ is a positive value), the single-photon Rabi frequency Ω at which Rabi flops occur between states |0> and |e>, and between states |1> and |e>, respectively. 0e (t) and Ω1e (t) (which is time dependent and determined by the amplitudes and phases of the first and second laser beams), as well as the spontaneous emission rate from the excited state |e>, the Rabi flop (called "carrier transition") between the two hyperfine states |0> and |1> is induced at the two-photon Rabi frequency Ω(t). The two-photon Rabi frequency Ω(t) is given by Ω 0e Ω 1e / 2Δ, where Ω 0e and Omega 1e are the single-photon Rabi frequencies of the first and second laser beams, respectively. Hereinafter, this set of non-copropagating laser beams in a Raman configuration for manipulating the internal hyperfine state of a qubit (qubit state) may be referred to as a "composite pulse" or simply a "pulse," and the resulting time-dependent pattern of the two-photon Rabi frequency Ω(t) may be referred to as the "amplitude" of the pulse or simply a "pulse," which are illustrated and further explained below. The detuning frequency δ=ω1-ω2-ω 01 is sometimes called the detuning frequency of the composite pulse or the detuning frequency of the pulse. The amplitude of the two-photon Rabi frequency Ω(t), which is determined by the amplitudes of the first and second laser beams, is sometimes called the "amplitude" of the composite pulse.

[0020] It should be noted that the specific atomic species used in the description provided herein are merely examples of atomic species that, when ionized, have a stable and well-defined two-level energy structure and optically accessible excited states, and are not intended to limit the possible configurations, specifications, etc. of ion trap quantum processors according to the present disclosure. For example, other ion species include alkaline earth metal ions (Be + , Ca + , Sr + , Mg + , and Ba + ) or transition metal ions (Zn + , Hg + , Cd + ) is included.

[0021] (tangle formation) 4A, 4B, and 4C show, for example, some schematic collective transverse motional mode structures (also simply referred to as "motional mode structures") for a group 106 of five trapped ions, where a static voltage V applied to end cap electrodes 210 and 212 S The confining potential due to the ion trap 200 is weak compared to the radial confining potential. The collective transverse motion mode of a group of trapped ions 106 is determined by a combination of the confining potential created by the ion trap 200 and the Coulomb interactions between the trapped ions. The trapped ions undergo collective transverse motion (referred to as "collective transverse motion mode," "collective motion mode," or simply "motion mode"), each mode having a different energy (or equivalently, frequency) associated with it. In the following, the m-th lowest energy motion mode will be referred to as |n ph > m where n ph where m represents the number of motion quanta (units of energy excitation, called "phonons") of a motion mode, and the number M of a given transverse motion mode is equal to the number of trapped ions in group 106. Figures 4A-4C show schematic examples of different types of collective transverse motion modes that may be experienced by five trapped ions arranged in group 106. Figure 4A shows a typical motion mode |n ph > M Schematic diagram of the general motion mode |n>, where M is the number of motion modes. M In this case, all ions oscillate transversely in phase. Figure 4B shows the second highest energy tilting mode |n ph > M-1 In the tilt motion mode, the ions at both ends move laterally out of phase (i.e., in opposite directions). Figure 4C shows the tilt motion mode |n ph > M-1 Higher order motion modes |n, which have lower energy than ph > M-3 FIG.

[0022] It should be noted that the above specific configuration is merely one of several possible examples of a trap for confining ions according to the present disclosure and does not limit possible configurations, specifications, etc. according to the present disclosure. For example, the shape of the electrodes is not limited to the hyperbolic electrodes described above. In other examples, the trap that generates an effective electric field that causes ions to move radially as a harmonic oscillation may be a multilayer trap in which multiple electrode layers are stacked and RF voltage is applied to two diagonal electrodes, or a surface trap in which all electrodes are arranged in a single plane on the chip. Furthermore, the trap may be divided into multiple segments, adjacent pairs of which may be linked to shuttle one or more ions, or may be connected by a photonic interconnect. The trap may also be an array of individual trapping regions arranged closely to each other on a microfabricated ion trap chip, such as those described above. In some embodiments, the quadrupole potential has a spatially varying DC component in addition to the RF component described above.

[0023] In an ion trap quantum computer, the motional mode can act as a data bus mediating the entanglement between two qubits, which is used to implement a two-qubit entanglement gate (called an "XX gate"). That is, each of the two qubits is entangled with a motional mode, and, as described below, the entanglement is transferred to the entanglement between the two qubits by using motional sideband excitations. Figures 5A and 5B show, in accordance with one embodiment, a signal at frequency ω m Mode of motion with │n ph > M 5B shows a schematic diagram of the motional sideband spectrum of ions in group 106 at δ = ω − ω . As shown in Figure 5B, when the detuning frequency of the composite pulse is zero (i.e., the frequency difference between the first and second laser beams is the carrier frequency δ = ω − ω ). 01= 0), a simple Rabi flop (carrier transition) occurs between the qubit states |0> and |1>. If the detuning frequency of the composite pulse is positive (i.e., the frequency difference between the first and second laser beams is tuned higher than the carrier frequency), then δ = ω1 - ω2 - ω 01 = μ>0, called the "blue sideband"), and the combined qubit motional state │0>│n ph > m and |1>|n ph +1> m (i.e., when the qubit state |0> flips to |1>, |n ph > m n represented by ph From the mth motion mode with phonon excitation │n ph +1> m (n ph +1) a transition to the mth motional mode occurs with phonon excitation). If the detuning frequency of the composite pulse is negative (i.e., the frequency difference between the first and second laser beams is greater than the frequency of the motional mode |n ph > m The frequency ω m If the frequency is tuned lower than the carrier frequency by 01 =-μ<0, called the "red sideband"), and the combined qubit motional state │0>│n ph > m and |1>|n ph -1> m (i.e., when the qubit state flips from |0> to |1>, the motional mode |n ph > m From the above, the motion mode with one less phonon excitation │n ph -1> m (A transition to occurs.)

[0024] amplitude Ω (i) and Omega (j) and detuning frequency μ, and by applying a sideband pulse of duration τ (called the “gate duration”), we can perform an entanglement gate operation (XX gate) between the ith and jth pair of qubits, XX ij (θij )

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[0025] This entanglement gate operation has amplitude Ω (i) can be performed simultaneously for any pair of qubits by appropriately adjusting , and such a gate is hereinafter referred to as an efficient arbitrary simultaneous entanglement (EASE) gate,

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[0026] The EASE gate combined with appropriate single-qubit gates can be used to implement various two-qubit gate operations, such as ZZ gates, controlled Z (CZ) gates, controlled not (CNOT) gates, and SWAP gates, for any pair of qubits, either individually or simultaneously. ij (θ ij ) is the exclusive OR (XOR) of the ith and jth qubits up to the global phase,

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[0027] (Building quantum circuits using EASE gates) In quantum computing, a quantum algorithm is selected and decomposed into a series of quantum circuits containing single-qubit, two-qubit, and multi-qubit gate operations to be implemented on a quantum processor. In some embodiments, a quantum algorithm is decomposed using commonly used quantum circuits (i.e., specific sequences of quantum gate operations). Such quantum circuits include Clifford circuits (also known as "stabilized circuits"), multiple-controlled-NOT gates, qubit-permutation gates, controlled-SWAP gates, and controlled-permutation gates. For example, Clifford circuits are well-known as circuits that can be efficiently simulated by classical computers. Quantum algorithms are often decomposed in terms of Clifford and non-Clifford circuits. Multiple-controlled-NOT gates are used to implement quantum algorithms including Grover's algorithm and quantum approximate optimization algorithms, implement reversible logic such as Reed-Muller, and simulate strongly interacting materials. Quantum-permutation gates are used to implement quantum algorithms including string matching algorithms and simulate interacting materials using the quantum-enhanced Ewald method. Controlled-SWAP gates are used to implement quantum algorithms including the discrete logarithm algorithm and Shor's algorithm. Controlled permutation gates are used to implement quantum algorithms, including quantum string matching algorithms.

[0028] A Clifford circuit operating on n qubits is a quantum circuit that can be constructed only from CZ gate layers (i.e., combinations of CZ gates across one or more pairs of qubits among the n qubits), CNOT gate layers (i.e., combinations of CNOT gates across one or more pairs of qubits among the n qubits), Hadamard gate layers (i.e., combinations of Hadamard H gates on one or more qubits among the n qubits), and phase gate layers (i.e., combinations of topological S gates on one or more qubits among the n qubits). Any Clifford circuit has been shown to decompose into the standard form HS-CZ-CNOT-H-CZ-SH, where H, S, CZ, and CNOT represent the Hadamard gate layer, phase gate layer, CZ gate layer, and CNOT gate layer, respectively. Because the Hadamard gate H and the phase gate S are single-qubit gate operations that can be implemented simultaneously and efficiently, the CZ and CNOT gate layers used to decompose Clifford circuits, along with the multiplexed controlled-NOT gates and qubit permutation gates, are efficiently constructed with EASE gates in the embodiments described herein.

[0029] In the following description, "constructing" a circuit that implements a gate operation or layer of gate operations refers to decomposing, by a classical computer (e.g., a digital computer), a given gate operation or layer of gate operations into one or more EASE gates and single-qubit gates, and computing, by the classical computer, a sequence of one or more EASE gates and single-qubit gates that are implemented on a quantum processor as part of executing a selected quantum algorithm to complete the computational operation. By using gate operations and layers of gate operations that are efficiently constructed by the methods described herein, an entire quantum computation can be performed efficiently.

[0030] (CZ gate layer) As described above, a CZ gate layer operating on n qubits is a combination of one or more CZ gates, each spanning a pair of qubits among the n qubits. In the following description, each qubit pair for which a CZ gate is included in the CZ gate layer is referred to as a "participating pair," and the qubits of the participating pair are referred to as "participating qubits." For example, in a CZ gate layer including CZ gates spanning qubit pairs (1,2), (1,4), (3,6), and (3,8), the qubits are numbered 0, 1, ..., n-1, the participating pairs are (1,2), (1,4), (3,6), and (3,8), and the participating qubits are 1, 2, 3, 4, 6, and 8.

[0031] 6 shows a flowchart illustrating a method 600 for constructing a circuit that implements a CZ gate layer operating on n qubits, according to one embodiment. The method 600 begins at block 602, where each of one or more CZ gates included in the CZ gate layer is synchronized by a classical computer with a ZZ gate in antiphase S to a global phase. -1 In block 602, a CZ gate is decomposed across the ith and jth qubit pair.

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[0032] In block 604, ZZ gates across all of the participating pairs (i.e., ZZ gates and antiphase S) are connected together so that all of the ZZ gates are connected together. -1The operation of block 604 is performed by a ZZ gate and an antiphase S -1 The gates can be interchanged (i.e., ZZ gate and antiphase S -1 This is possible because the order of gates can be permuted without affecting the result of the gate operations). Therefore, the CZ layer is now a set of all participating pairs (i,j) and antiphase S -1 A single block of ZZ gates for a layer of gates

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[0033] In block 606, a single block of ZZ gates

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[0034] Thus, the entire circuit implementing the CZ gate layer, including CZ gates across the involved pair (i,j) of qubits, consists of Hadamard gates on all involved qubits, a single EASE gate for the involved pair (i,j),

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[0035] (CNOT gate layer) A CNOT gate layer operating on n qubits is a combination of one or more CNOT gates, each spanning a pair of qubits among the n qubits. Similar to the above description of the CZ gate layer, each pair of qubits that a CNOT gate layer includes is called a "participating pair," and the qubits of the participating pair are called "participating qubits." In general, a CNOT gate layer is a layer of n × n transformation matrices M CNOT Boolean variable by

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[0036] 7 shows a flowchart illustrating a method 700 for constructing a circuit that implements a CNOT gate layer operating on n qubits without ancillary qubits, according to one embodiment. The method 700 begins at block 702 by calculating a transformation matrix M that represents the CNOT gate layer. CNOT is an n×n lower triangular matrix

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[0037] In block 704, a circuit is constructed by a classical computer that performs the linear transformation represented by each row of the upper triangular matrix U.

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[0038] In block 706, a circuit is constructed by a classical computer that implements the linear transformation represented by each row of the lower triangular matrix L.

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[0039] Thus, without an ancillary qubit, the overall circuit implementing a CNOT gate layer operating on n qubits includes 2n EASE gates and a single-qubit gate. Thus, method 700 can be implemented using Ω(n 2 This provides improved efficiency over previous methods using a universal gate set including single-qubit gates and two-qubit gates, requiring (log(n)) two-qubit gates.

[0040] 8 shows a flowchart illustrating a method 800 for constructing a circuit that implements a CNOT gate layer operating on n qubits with n / 2 ancillary qubits, according to one embodiment. In the example described here, n is 2 m where m is a natural number for simplicity. However, one skilled in the art will readily appreciate that method 800 is applicable when n is any number. Method 800 begins at block 802 by generating a transformation matrix M representing a CNOT gate layer. CNOT is an n×n lower triangular matrix

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[0041] In block 804, the 2×2 block diagonal elements of the upper triangular matrix U using one ancillary qubit are

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[0042] In block 806, each 4×4 block diagonal element of the upper triangular matrix U using two ancillary qubits is

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[0043] In block 808, 2 l-1 Each 2 of the upper triangular matrix U uses ancillary qubits l ×2 l 2 of the block diagonal elements (l=3,4,…,m=logn) l-1 ×2 l-1 Circuits that implement the linear transformations represented by the off-diagonal elements are constructed by a classical computer. The circuits each have a Boolean variable

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[0044] In block 810, a circuit is constructed by a classical computer that implements the linear transformation represented by the lower triangular matrix L using n / 2 ancillary qubits. Construction of the circuit in block 810 follows steps in blocks 804 through 808. The circuit constructed in block 810 includes 3logn (=3m) EASE gates and a single-qubit gate.

[0045] Thus, the entire circuit implementing a CNOT gate layer operating on n qubits with n / 2 ancillary qubits includes 6 log n (= 6 m) EASE gates and single-qubit gates. 2 This provides improved efficiency over previous methods using a universal gate set including single-qubit gates and two-qubit gates, requiring (log(n)) two-qubit gates.

[0046] (Multiple Controlled NOT Gates) Multiple controlled-NOT gates (C n-1 A NOT gate (also called a Toffoli-n gate) flips the value of a target bit when all of the (n-1) qubits are in state |0>. For example, a C 2 A NOT gate (called a "Toffoli-3 gate" or simply a "Toffoli gate") flips the target bit only if both control bits are in state |1>, leaving all three qubits unchanged otherwise, thereby converting the three-qubit state |x>|y>|z>(x,y,z={0,1}) into a three-qubit state

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[0047] In general, C n-1 The Z gate generates an n-qubit state |b0b1…b n-1 >

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[0048] FIG. 9 illustrates a C n-1 9 shows a flowchart illustrating a method 900 for constructing a circuit that implements a Z-gate. The method 900 begins at block 902, where the C n-1 Selected XOR pattern T of Z gate l A circuit is constructed using a classical computer to temporarily copy the set of C to an auxiliary qubit. 4 For the Z gate (n=5), the set of selected XOR patterns is: XOR patterns of length 2,

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[0049] In block 904, C in the expansion n-1 Term T in the expansion of the Z-gate l A circuit is constructed on a classical computer that implements all of the terms. All of the terms are rotated by an appropriately chosen rotation angle θ ij and ZZ gate ZZ with θ ij (θ ij ) and a rotation gate Z(θ). All of these ZZ gates can be implemented with a single EASE gate with an appropriate single-qubit gate. Thus, the circuit constructed in block 904 includes a single EASE gate and a single-qubit gate.

[0050] In block 906, a circuit is constructed that includes the same set of CNOT gates as in block 902. This circuit converts all of the ancillary qubits back to the state |0> so that they can be reused in the next step. As mentioned above, this set of CNOT gates can be simultaneously implemented with a single EASE gate with appropriate single-qubit gates. Thus, the circuit constructed in block 906 includes a single EASE gate and a single-qubit gate.

[0051] Therefore, C acting on n qubits (n=5, 6) n-1 The complete circuit implementing the Z-gate includes three EASE gates and a single-qubit gate. The Toffoli-n gate is n-1 Circuits implementing Toffoli-5 and Toffoli-6 gates also include three EASE gates and a single-qubit gate, since they can be easily obtained by combining a Z gate with a Hadamard gate applied to the target qubit.

[0052] Using the Toffoli-6 gate constructed as above, C n-1 Note that the Z-gate (n ≥ 6) can be implemented efficiently. n-1 It is known in the art that the Z gate can be decomposed using n / 2 Toffoli-6 gates. n-1 The Z gate can be implemented using 3n / 2 EASE gates and single-qubit gates. Thus, method 800 offers improved efficiency over conventional methods using universal gate sets including single-qubit and two-qubit gates, which require at least 2n two-qubit gates.

[0053] FIG. 10 illustrates a O(2 n ) ancillary qubits to act on n qubits, C n-110 shows a flowchart illustrating a method 1000 for constructing a circuit that implements a Z-gate. The method 1000 begins at block 1002, where the C n-1 A circuit is constructed that implements the linear term T1 of the Z-gate. The circuit constructed in block 1002 is the same as that constructed in block 902 of method 900 and includes a Z-gate on qubit j (j=0, 1, ..., n-1).

[0054] In block 1004, C n-1 XOR pattern T in the unfolding of the Z gate l This is a circuit that temporarily copies all of (l=2,...,n) to an auxiliary qubit.

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[0055] In block 1006, the XOR pattern T l For each of (l=2,…,n) the phase shift

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[0056] In block 1008, a circuit is constructed by a classical computer that converts all ancillary qubits back to the state |0>. The circuit constructed in block 1008 is the same as that constructed in block 1004 and includes a single EASE gate and a single-qubit gate.

[0057] Therefore, 2 n C, which acts on n qubits using n ancillary qubits n-1 The entire circuit implementing the Z-gate includes two EASE gates and a single-qubit gate. Thus, method 1000 provides improved efficiency over conventional methods using universal gate sets including single-qubit and two-qubit gates, which require at least 2n two-qubit gates.

[0058] (Quantum substitution gate) 11 shows a flowchart illustrating a method 1100 of constructing a circuit that implements a qubit permutation gate that operates on n qubits, according to one embodiment. Method 1100 begins at block 1102, where a qubit permutation operation is decomposed into a SWAP gate. It is known in the art that qubit permutation operations can be implemented as a four-layer SWAP gate that uses n ancillary qubits, or a six-layer SWAP gate that does not use ancillary qubits.

[0059] Each SWAP gate is decomposed into CNOT gates in block 1104. It is known in the art that a SWAP gate can be implemented as three CNOT gates.

[0060] In block 1106, a circuit implementing the CNOT gates is constructed by a classical computer. Because each of the CNOT gates can be implemented by a single EASE gate along with an appropriate single-qubit gate, the circuit constructed in block 1106 includes three EASE gates and a single-qubit gate.

[0061] Thus, the entire circuit implementing the qubit permutation includes 12 EASE gates and single-qubit gates using n ancillary qubits, or 18 EASE gates and single-qubit gates without ancillary qubits. Method 1100 therefore provides improved efficiency over conventional methods using universal gate sets including single-qubit and two-qubit gates, which require O(n) two-qubit gates.

[0062] (controlled substitution gate) 12 shows a flowchart illustrating a method 1200 of constructing a circuit implementing a controlled permutation gate operating on n qubits, according to one embodiment. Method 1200 begins at block 1202, where the controlled permutation gate is decomposed into controlled SWAP gates with shared control. It is known in the art that each of the controlled SWAP gates can be implemented as seven CNOT gates.

[0063] A circuit implementing the CNOT gates is constructed by a classical computer in block 1204. Because each of the seven CNOT layers can be simultaneously implemented in a single EASE gate along with an appropriate single-qubit gate, the circuit constructed in block 1204 includes seven EASE gates and a single-qubit gate.

[0064] Thus, the entire circuit implementing the controlled permutation gate includes O(l) EASE gates and single-qubit gates. Thus, method 1200 provides improved efficiency over conventional methods using universal gate sets including single-qubit and two-qubit gates, which require O(n) two-qubit gates.

[0065] Using the methods described herein to implement controlled permutation gates can reduce the complexity of quantum algorithms that use controlled permutations. For example, the circuit depth of a string matching algorithm that matches a pattern of length M in a text of length N can be reduced to:

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[0066] Various quantum circuits, including one or more EASE gates and single-qubit gates formed by use of a classical computer using the methods described herein, can be implemented on a quantum computer in combination with other quantum circuits to perform quantum computations. Each EASE gate can be implemented on a quantum computer by methods described in detail in U.S. patent application Ser. No. 16 / 578,137 (entitled "Simultaneously Entangling Gates For Trapped-Ion Quantum Computers") and U.S. patent application Ser. No. 16 / 854,043 (entitled "Amplitude, Frequency, And Phase Modulated Simultaneous Entangling Gates For Trapped-Ion Quantum Computers"), which are incorporated herein by reference. An EASE gate, which simultaneously performs entanglement gate operations on any pair of qubits in a quantum processor, can be implemented by applying a laser pulse to each of the qubits involved, with the amplitude and phase of each pulse being appropriately adjusted by a software program in the classical computer. Pulses determined by a software program are applied to participating qubits (a chain of N trapped ions) in the quantum processor to perform EASE gate operations on selected pairs of qubits, controlled by a system controller.

[0067] At the end of the quantum computation, the population of qubit states (trapped ions) within the quantum processor (including the group of trapped ions 106) is determined (read) by measurements taken by the imaging objective 108 and mapped to the PMT 110, thereby determining the result of the quantum computation and providing it as input to a classical computer (e.g., a digital computer). The result of the quantum computation can then be processed by the classical computer 102 and output to a user interface, such as a graphics processing unit (GPU) of the classical computer 102, printed on paper, and / or stored in the memory of the classical computer 102. The result of the quantum computation can be used by the classical computer to perform a desired activity or to obtain a solution to a problem that cannot typically be ascertained, or cannot be ascertained within a reasonable time, by a classical computer alone. Problems known to be unsolvable or unascertainable by today's conventional computers (i.e., classical computers) and that are known to be solvable using the results obtained from a performed quantum computation can include, but are not limited to, simulation of the internal chemical structure of complex molecules and materials, and factorization of large integers.

[0068] The method of constructing quantum circuits using EASE gates described herein offers an improvement in computational complexity over other existing methods of constructing quantum circuits known in the art. A CZ gate layer operating on n qubits can be implemented by a single EASE gate and a single-qubit gate according to method 600 described above, whereas conventional methods using a universal gate set including single-qubit and two-qubit gates require O(n 2 ) two-qubit gates. A CNOT gate layer operating on n qubits can be implemented with 2n EASE gates and single-qubit gates by the method 700 described above, without an ancillary qubit, whereas conventional methods require O(n 2) two-qubit gates. A CNOT gate layer operating on n qubits can be implemented with 6logn EASE gates and single-qubit gates with n / 2 ancillary qubits by the method 800 described above, whereas conventional methods require O(n 2 ) two-qubit gates. Toffoli-5 and Toffoli-6 gates can be implemented by the above method 900 with 3 EASE gates and a single qubit gate, whereas conventional methods require at least 10 and 12 two-qubit gates. A Toffoli-n gate operating on n qubits can be implemented by the above method 900 with 3n / 2 EASE gates and a single qubit gate, whereas conventional methods require at least 2n two-qubit gates. A Toffoli-n gate operating on n qubits can be implemented by the above method 1000 with O(2 n ) ancillary qubits, can be implemented by two EASE gates, whereas conventional methods require at least 2n two-qubit gates. A qubit permutation operation and a controlled permutation gate acting on n qubits can each be implemented by O(1) EASE gates (i.e., the number of EASE gates required remains constant as the number of qubits, n, increases) and a single qubit, whereas conventional methods require O(n) two-qubit gates.

[0069] While the forgoing is directed to particular embodiments, other and further embodiments may be devised without departing from the basic scope thereof, which scope is determined by the claims that follow.

Claims

1. 1. A method of performing a computation using an ion trap quantum computing system comprising a classical computer, a system controller, and a quantum processor, comprising: computing with the classical computer a circuit that implements a selected set of gate operations using one or more Efficient Arbitrary Simultaneous Entanglement (EASE) gates; implementing, by the system controller, the circuit computed on the quantum processor; measuring, by the system controller, a population of qubit states in the quantum processor; outputting by the classical computer the population of qubit states measured in the quantum processor; Including, The set of selected gating operations satisfies at least one of the following (a) to (f): (a) the set of selected gate operations includes one or more layers of controlled Z gates, each of which is applied to a pair of qubits among n qubits in the quantum processor; the calculated circuit includes a single EASE gate and a single qubit gate; (b) the set of selected gate operations includes one or more layers of controlled-NOT gates, each of which is applied to a pair of qubits among the n qubits in the quantum processor; The calculated circuit includes 2n EASE gates and a single qubit gate. (c) the set of selected gate operations includes one or more layers of controlled-NOT gates, each of which is applied to a pair of qubits among the n qubits in the quantum processor; The calculated circuit includes 6 log n EASE gates and single-qubit gates using n / 2 ancillary qubits. (d) the set of selected gate operations includes a multiplexed controlled-NOT gate operating on n qubits in the quantum processor; The calculated circuit includes 3n / 2 EASE gates and a single qubit gate. (e) the set of selected gate operations includes qubit permutation gates operating on n qubits in the quantum processor; The calculated circuit includes 12 EASE gates and single-qubit gates using n ancillary qubits, or 18 EASE gates and single-qubit gates without n ancillary qubits. (f) the set of selected gate operations includes controlled permutation gates operating on n qubits in the quantum processor; The computed circuit includes O(1) EASE gates and a single-qubit gate. method.

2. a quantum processor including n qubits, each qubit including a trapped ion having two hyperfine states; one or more lasers configured to illuminate a laser beam provided to trapped ions within the quantum processor; A classical computer, Computing a circuit that implements the selected set of gate operations using one or more efficient arbitrary simultaneous entanglement (EASE) gates. a classical computer configured to perform operations including: executing on said quantum processor a control program for controlling said one or more lasers; implementing the computed circuit on the quantum processor; measuring a population of qubit states within the quantum processor; a system controller configured to perform operations including Equipped with the classical computer is further configured to output the population of qubit states measured in the quantum processor; The set of selected gating operations satisfies at least one of the following (a) to (f): (a) the set of selected gate operations includes one or more layers of controlled Z gates, each of which is applied to a pair of qubits among n qubits in the quantum processor; the calculated circuit includes a single EASE gate and a single qubit gate; (b) the set of selected gate operations includes one or more layers of controlled-NOT gates, each of which is applied to a pair of qubits among the n qubits in the quantum processor; The calculated circuit includes 2n EASE gates and a single qubit gate. (c) the set of selected gate operations includes one or more layers of controlled-NOT gates, each of which is applied to a pair of qubits among the n qubits in the quantum processor; The calculated circuit includes 6 log n EASE gates and single-qubit gates using n / 2 ancillary qubits. (d) the set of selected gate operations includes a multiplexed controlled-NOT gate operating on n qubits in the quantum processor; The calculated circuit includes 3n / 2 EASE gates and a single qubit gate. (e) the set of selected gate operations includes qubit permutation gates operating on n qubits in the quantum processor; The calculated circuit includes 12 EASE gates and single-qubit gates using n ancillary qubits, or 18 EASE gates and single-qubit gates without n ancillary qubits. (f) the set of selected gate operations includes controlled permutation gates operating on n qubits in the quantum processor; The computed circuit includes O(1) EASE gates and a single-qubit gate. Ion trap quantum computing system.

3. Classical computers and a quantum processor including n qubits, each qubit including a trapped ion having two hyperfine states; a system controller configured to execute a control program to control one or more lasers to perform operations on the quantum processor; a non-volatile memory having some instructions stored therein; 1. An ion trap quantum computing system comprising: computing with the classical computer a circuit that implements a selected set of gate operations using one or more Efficient Arbitrary Simultaneous Entanglement (EASE) gates; implementing, by the system controller, the circuit computed on the quantum processor; measuring, by the system controller, a population of qubit states in the quantum processor; outputting by the classical computer the population of qubit states measured in the quantum processor; Let the operation, including The set of selected gating operations satisfies at least one of the following (a) to (e): (a) the set of selected gate operations includes one or more layers of controlled Z gates, each of which is applied to a pair of qubits among n qubits in the quantum processor; the calculated circuit includes a single EASE gate and a single qubit gate; (b) the set of selected gate operations includes one or more layers of controlled-NOT gates, each of which is applied to a pair of qubits among the n qubits in the quantum processor; The calculated circuit includes 2n EASE gates and a single qubit gate. (c) the set of selected gate operations includes one or more layers of controlled-NOT gates, each of which is applied to a pair of qubits among the n qubits in the quantum processor; The calculated circuit includes 6 log n EASE gates and single-qubit gates using n / 2 ancillary qubits. (d) the set of selected gate operations includes a multiplexed controlled-NOT gate operating on n qubits in the quantum processor; The calculated circuit includes 3n / 2 EASE gates and a single qubit gate. (e) the set of selected gate operations includes qubit permutation gates operating on n qubits in the quantum processor; The calculated circuit includes 12 EASE gates and single-qubit gates using n ancillary qubits, or 18 EASE gates and single-qubit gates without n ancillary qubits. Ion trap quantum computing system.

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