Semiconductor Devices

Abstract

To provide a semiconductor device having high heat dissipation.SOLUTION: A semiconductor device includes: a substrate 10; an active region provided in the substrate; a plurality of gate fingers 16 provided on the active region, extending in an extension direction, and arranged in an arrangement direction orthogonal to the extension direction; and gate connection wiring 20 commonly connected to the plurality of gate fingers and provided between the plurality of gate fingers and a first side surface 13a of the substrate. When viewed from the arrangement direction, a first position P1a where a first end of a first gate finger 16a as a part of the plurality of gate fingers is connected to the gate connection wiring is closer to the first side surface than a second position P1b where a first end of a second gate finger 16b as another part of the plurality of gate fingers is connected to the gate connection wiring.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, for example, a semiconductor device having a field effect transistor. [Background technology]

[0002] Radio frequency power amplifiers for base stations use field effect transistors (FETs) such as gallium nitride high electron mobility transistors (GaN HEMTs). It is known that FETs are laid out in a multi-finger configuration (see, for example, Patent Documents 1 and 2). A method for calculating the thermal resistance of a GaN HEMT is known (see, for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2020 / 0127627 [Patent Document 2] U.S. Patent No. 10,381,984 [Patent Document 3] Japanese Patent Application Laid-Open No. 2014-179541 [Patent Document 4] Japanese Patent Application Laid-Open No. 2007-141971 [Patent Document 5] Japanese Patent Application Laid-Open No. 2009-277877 [Patent Document 6] Japanese Patent Application Publication No. 2019-92009 [Non-patent literature]

[0004] [Non-Patent Document 1] K. Ohgami etal. “Transient Thermal Response Impact of 3.5GHz GaN HEMT Amplifier on TDD LTE Spectrum and its Improvement Based on a Thermal Equivalent Circuit Approach” IEEE Symposium on Compound Semiconductor Integrated Circuit (2016). Summary of the Invention [Problem to be solved by the invention]

[0005] In a multi-finger type FET, increasing the heat dissipation capacity increases the chip size, while decreasing the chip size decreases the heat dissipation capacity.

[0006] The present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a semiconductor device with high heat dissipation properties. [Means for solving the problem]

[0007] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; an active region provided within the substrate; a plurality of gate fingers provided on the active region, extending in an extension direction, and arranged in an arrangement direction perpendicular to the extension direction; and a gate connection wiring to which the plurality of gate fingers are commonly connected and provided between the plurality of gate fingers and a first side surface of the substrate, wherein, when viewed from the arrangement direction, a first position at which first ends of some first gate fingers of the plurality of gate fingers are connected to the gate connection wiring is closer to the first side surface than a second position at which first ends of some second gate fingers of the plurality of gate fingers are connected to the gate connection wiring. [Effects of the Invention]

[0008] According to the present disclosure, a semiconductor device with high heat dissipation properties can be provided. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram of an amplifier according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the amplifier according to the first embodiment. [Figure 3] FIG. 3 is a plan view of the semiconductor chip in the first embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA in FIG. [Figure 5] FIG. 5 is a plan view of a semiconductor chip in Comparative Example 1. FIG. [Figure 6] FIG. 6 is a cross-sectional view taken along line AA in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along the line BB in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along CC in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line DD in FIG. [Figure 10] FIG. 10 is a plan view of a semiconductor chip according to the second embodiment. [Figure 11] FIG. 11 is a cross-sectional view taken along line AA in FIG. [Figure 12] FIG. 12 is a plan view of a semiconductor chip according to the third embodiment. [Figure 13] FIG. 13 is a plan view of a semiconductor chip according to the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described.

[0011] [Details of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a semiconductor device including: a substrate; an active region provided in the substrate; a plurality of gate fingers provided on the active region, extending in an extension direction and arranged in an arrangement direction perpendicular to the extension direction; and a gate connection wiring to which the plurality of gate fingers are commonly connected and provided between the plurality of gate fingers and a first side surface of the substrate, wherein, when viewed from the arrangement direction, a first position where first ends of some first gate fingers of the plurality of gate fingers are connected to the gate connection wiring is closer to the first side surface than a second position where first ends of some second gate fingers of the plurality of gate fingers are connected to the gate connection wiring, thereby improving heat dissipation. (2) It is preferable that at least a part of the first region in which the first bonding wire is connected to the gate connection wiring overlaps between the first position and the second position when viewed from the arrangement direction. (3) The semiconductor device comprises a plurality of source fingers provided on the active region, extending in the extension direction and arranged in the arrangement direction; a plurality of drain fingers provided on the active region, extending in the extension direction and arranged alternately with the plurality of source fingers in the arrangement direction; and drain connection wiring to which first ends of the plurality of drain fingers are commonly connected and which is provided between the plurality of gate fingers and a second side of the substrate opposite to the first side, and it is preferable that each of the plurality of gate fingers is sandwiched between one of the plurality of source fingers and one of the plurality of drain fingers in the arrangement direction. (4) When viewed from the arrangement direction, it is preferable that the third position where the second end of the first gate finger on the drain connection wiring side is located and the fourth position where the second end of the second gate finger on the drain connection wiring side is located are different, and that at least a portion of the second region where the second bonding wire is connected to the drain connection wiring overlaps between the third position and the fourth position when viewed from the arrangement direction. (5) When viewed from the arrangement direction, it is preferable that a third position where the second end of the first gate finger on the drain connection wiring side is located is the same as a fourth position where the second end of the second gate finger on the drain connection wiring side is located, and the number of first bonding wires connected to the gate connection wiring is smaller than the number of second bonding wires connected to the drain connection wiring. (6) The thickness of the substrate is preferably at least half the shortest distance in the arrangement direction between adjacent gate fingers among the plurality of gate fingers. (7) The device preferably comprises a base substrate and a bonding material that bonds the base substrate to the underside of the substrate, wherein the distance between the first position and the first side surface is smaller than the thickness of the substrate, and the bonding material covers the area between the lower end and a position on the side surface that is separated by the distance from the upper end to the lower end of the substrate by the above-mentioned distance. (8) It is preferable that the plurality of gate fingers, including a third region in which one or more of the first gate fingers are provided without any other gate fingers therebetween, and a fourth region in which one or more of the second gate fingers are provided without any other gate fingers therebetween, are arranged alternately in the arrangement direction. (9) The substrate preferably includes a SiC substrate.

[0012] Specific examples of semiconductor devices according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0013] [Example 1] FIG. 1 is a block diagram of an amplifier according to a first embodiment. As shown in FIG. 1, the amplifier 100 includes an FET 55, an input matching circuit 52, and an output matching circuit 54. The source S of the FET 55 is connected to ground. A high-frequency signal input from an input terminal Tin is input to a gate G of the FET 55 via the input matching circuit 52. The high-frequency signal amplified by the FET 55 is output from an output terminal Tout via the output matching circuit 54. The input matching circuit 52 matches the input impedance of the input terminal Tin with the impedance of the gate G of the FET 55. The output matching circuit 54 matches the output impedance of the output terminal Tout with the impedance of the drain D of the FET 55. The amplifier 100 is a power amplifier for wireless communications, for example, for frequencies between 0.5 GHz and 10 GHz (e.g., 3.9 GHz). The output power of the amplifier 100 is, for example, 30 dBm to 40 dBm, and the drain efficiency is, for example, 50% to 70%. When the drain efficiency is 50%, the power consumption is almost the same as the output power, which is 1 W to 10 W. Most of the power consumption in amplifier 100 is the power consumption of FET 55.

[0014] FIG. 2 is a plan view of the amplifier in the first embodiment. A semiconductor chip 50 and matching components 40 and 45 are mounted on a base substrate 30. The base substrate 30 is a conductive substrate. The semiconductor chip 50 includes a substrate 10 and, provided on the substrate 10, source fingers 12, drain fingers 14, gate fingers 16, drain connection wiring 18, and gate connection wiring 20. The matching components 40 and 45 are, for example, capacitive components. The matching component 40 includes a dielectric substrate 41 and an electrode 42 provided on the dielectric substrate 41. The matching component 45 includes a dielectric substrate 46 and an electrode 47 provided on the dielectric substrate 46.

[0015] The input terminal Tin and the output terminal Tout are provided, for example, on an insulating frame provided on the base substrate 30, and are electrically isolated from the base substrate 30. The input terminal Tin and the electrode 42 are connected by a bonding wire 43, and the electrode 42 and the gate connecting wiring 20 are connected by a bonding wire 44. The drain connecting wiring 18 and the electrode 47 are connected by a bonding wire 48. The electrode 47 and the output terminal Tout are connected by a bonding wire 49. The bonding wires 43 and 44 and the matching component 40 form an input matching circuit 52. The bonding wires 48 and 49 and the matching component 45 form an output matching circuit 54.

[0016] FIG. 3 is a plan view of the semiconductor chip in Example 1. FIG. 4 is a cross-sectional view taken along the line AA in FIG. 3. The arrangement direction of the gate fingers 16 is the X direction, the extension direction is the Y direction, and the normal direction of the substrate 10 is the Z direction. The X direction, Y direction, and Z direction are perpendicular to each other. As shown in FIGS. 3 and 4, the semiconductor chip 50 is bonded to a base substrate 30 by a bonding material 32. The substrate 10 includes a substrate 10a and a semiconductor layer 10b. The base substrate 30 is, for example, a copper substrate, and has a thickness T2 of, for example, 100 μm to 500 μm. The bonding material 32 is a conductive layer formed by sintering a metal paste such as silver paste, for example, a conductive layer formed by sintering a nanosilver paste containing nanosilver particles with a particle diameter of 10 nm to 100 nm. When the FET 55 is a GaN HEMT, the substrate 10a is, for example, a SiC substrate or a diamond substrate. The semiconductor layer 10b is a nitride semiconductor layer, and includes, from the substrate 10a side, a GaN channel layer and an AlGaN barrier layer. The thickness T1 of the substrate 10 is, for example, 50 μm to 200 μm. The thickness of the semiconductor layer 10b is much thinner than the thickness of the substrate 10a, for example, several μm or less. Therefore, the thickness T1 of the substrate 10 is almost the same as the thickness of the substrate 10a.

[0017] Source fingers 12 and drain fingers 14 are arranged alternately in the X direction on the substrate 10. Gate fingers 16 are provided between the source fingers 12 and the drain fingers 14. The source fingers 12 are electrically connected to and short-circuited with the base substrate 30 by through electrodes 24 that penetrate the substrate 10. teeth The source fingers 12, drain fingers 14, and gate fingers 16 are commonly connected to a drain connection wiring 18 at the +Y end. The multiple gate fingers 16 are commonly connected to a gate connection wiring 20 at the -Y end. The drain connection wiring 18 is provided between the gate fingers 16 and a second side surface 13b of the substrate 10 (the side surface opposite to the first side surface 13a). The gate connection wiring 20 is provided between the gate fingers 16 and the first side surface 13a of the substrate 10. The source fingers 12, drain fingers 14, and gate fingers 16 are provided on an active region 22. The active region 22 is a region in which the semiconductor layer 10b is activated. The area outside the active region 22 is an inactive region. The drain connection wiring 18 and gate connection wiring 20 are provided on the inactive region.

[0018] Regions 35a and 35b are alternately provided in the X direction on the upper surface 13 of the substrate 10. The source fingers 12, drain fingers 14, gate fingers 16, and active region 22 are shifted in the -Y direction in region 35a and in the +Y direction in region 35b. The gate fingers 16 provided in regions 35a and 35b are referred to as gate fingers 16a and 16b, respectively. The drain connection wiring 18 has a protrusion 18a protruding in the -Y direction in region 35a and a recess 18b recessed in the +Y direction in region 35b. The gate connection wiring 20 has a recess 20a recessed in the -Y direction in region 35a and a protrusion 20b protruding in the +Y direction in region 35b. A ball 48a of a bonding wire 48 is bonded to the protrusion 18a, and a ball 44a of a bonding wire 44 is bonded to the protrusion 20b. At least a portion of region 38a where ball 48a joins protrusion 18a is located between positions P1a and P1b, and at least a portion of region 38b where ball 44a joins protrusion 20b is located between positions P2a and P2b.

[0019] The pitches in the X direction of the source fingers 12 and the drain fingers 14 are defined as Lss and Ldd, respectively. The pitch between two gate fingers 16 is defined as Lgg. Lss, Ldd, and Lgg are uniform in the X and Y directions, for example. When adjacent gate fingers 16 are gate fingers 16a, the intervals between adjacent gate fingers 16a are the same in multiple regions 35a. When adjacent gate fingers 16 are gate fingers 16b, the intervals between adjacent gate fingers 16b are the same in multiple regions 35a. 35b The distances are the same in the region 35a. When adjacent gate fingers 16 are gate fingers 16a and 16b, the distance between adjacent gate fingers 16a and 16b may be the same as or different from the distance between adjacent gate fingers 16a and 16b. Lss, Ldd, and Lgg are, for example, 50 μm to 300 μm. The lengths of the substrate 10 in the X and Y directions are Lx and Ly. Lx is, for example, 300 μm to 10,000 μm, and Ly is, for example, 300 μm to 2,000 μm. The length of the gate finger 16a in the region 35a is L1a. The position where the gate finger 16a connects to the gate connection wiring 20 is P2a. The position of the +Y end of the gate finger 16a is P1a. The length in the Y direction between the side surface 13a on the -Y side of the substrate 10 and position P2a is L2a. The length in the Y direction between the side surface 13b on the +Y side of the substrate 10 and the position P1a is defined as L3a. The length of the gate finger 16b in the region 35b is defined as L1b. The position where the gate finger 16b connects to the gate connection wiring 20 is defined as P2b. The position of the +Y end of the gate finger 16b is defined as P1b. The length in the Y direction between the side surface 13a on the -Y side of the substrate 10 and the position P2b is defined as L2b. The length in the Y direction between the side surface 13b on the +Y side of the substrate 10 and the position P1b is defined as L3b. The distance between the positions P2a and P1b is L5. L1a and L1b are, for example, 100 μm to 1800 μm.

[0020] The source fingers 12 and the drain fingers 14 are metal layers, such as aluminum wiring, copper wiring, or gold wiring. The gate fingers 16a and 16b are metal layers, such as gold layers. The drain connection wiring 18 and the gate connection wiring 20 are metal layers, such as gold layers. The bonding wires 44 and 48 are metal wires, such as gold wires. The diameter W1 of the bonding wires 44 and 48 is, for example, 20 μm to 50 μm, and the number of bonding wires 44 and 48 is appropriately set depending on the value of the current flowing through the bonding wires 44 and 48. The width W2 (diameter) of the balls 44a and 48a is, for example, 80 μm to 100 μm.

[0021] [Comparative Example 1] FIG. 5 is a plan view of a semiconductor chip in Comparative Example 1. FIG. 6 is a cross-sectional view taken along the line AA in FIG. 5. As shown in FIGS. 5 and 6, in Comparative Example 1, the source fingers 12, drain fingers 14, and gate fingers 16 are positioned in the same Y direction as in Example 1. The drain connection wiring 18 and the gate connection wiring 20 do not have protrusions 18a, 20b and recesses 18b, 20a. The widths W5 and W4 of the drain connection wiring 18 and the gate connection wiring 20 in the Y direction are greater than the width W2 of the balls 44a and 48a in the Y direction. For example, when W2 is 100 μm, W4 and W5 are greater than 100 μm. Considering margins between the side surfaces 13a and 13b of the substrate 10 and the gate connection wiring 20 and the drain connection wiring 18, the distance L2 between the side surface 13a and the position P2 where the gate finger 16 is connected to the gate connection wiring 20 is, for example, 150 μm, and the length L3 between the +Y end of the gate finger 16 and the side surface 13b is, for example, 150 μm. If the length L1 of the gate finger 16 is, for example, 400 μm, the length Ly of the substrate 10 in the Y direction is, for example, 700 μm. In Comparative Example 1, the regions 38a and 38b where the balls 44a and 48a are bonded to the gate connection wiring 20 and the drain connection wiring 18, respectively, are not located between positions P1 and P2.

[0022] The region where heat is generated in the semiconductor chip 50 is the vicinity of the maximum electric field in the channel layer in the semiconductor layer 10b. In the cross section of FIG. 6, the heat generation region is near the upper surface 13 of the substrate 10, and in the plan view of FIG. 5, it is approximately the same as the region where the gate finger 16 and the active region 22 overlap. The position where the gate finger 16 is connected to the gate connection wiring 20 P2 The distance between the -Y end of the region where the gate finger 16 and the active region 22 overlap is sufficiently short compared to the length L1 of the gate finger 16. P1 and the +Y end of the region where the gate finger 16 and the active region 22 overlap is sufficiently short compared with the length L1 of the gate finger 16. Therefore, the heat generation region can be regarded as the gate finger 16 (i.e., between positions P1 and P2).

[0023] When a SiC substrate is used as the substrate 10a and a copper substrate is used as the base substrate 30, the thermal conductivities of SiC and copper are approximately equal, at 400 to 450 W / (K·m) and 390 W / (K·m), respectively. As described in Non-Patent Document 1, the heat flow path 36 from the gate finger 16 to the base substrate 30 via the substrate 10 widens in the -Z direction from the gate finger 16. The heat flow path 36 widens at an angle of 45° with respect to the -Z direction. The lower surface 31 of the base substrate 30 is a heat dissipation surface from which heat is dissipated. The lower surface 31 is thermally connected to a heat source such as a housing or a heat sink. The length of the heat flow path 36 on the lower surface 31 is Lb = L1 + 2 × (T1 + T2). When T1 = 100 μm and T2 = 300 μm, Lb is 1200 μm. The z coordinate of the upper surface 13 of the substrate 10 is set to 0, the -Z direction is set to z, and the z of the lower surface 31 of the base substrate 30 is set to zt. If the area of ​​the XY plane of the heat flow path 36 at z is set to S(z) and the thermal conductivity of the substrate 10 and the base substrate 30 is set to λm, the thermal resistance Rth from the gate finger 16 provided on the upper surface 13 of the substrate 10 to the lower surface 31 is given by Equation 1.

number

[0024] If the thermal resistance Rth is high, heat generated near the gate fingers 16 cannot be dissipated, and the temperature in the active region 22 near the gate fingers 16 rises. This leads to a deterioration in the FET characteristics and shortened FET life. To suppress the rise in temperature near the gate fingers 16, the density of the gate fingers 16 must be reduced, which increases the chip area of ​​the semiconductor chip 50.

[0025] [Heat flow path in Example 1] 7 to 9 are cross-sectional views taken along lines BB, CC, and DD in FIG. 3, respectively. As shown in FIG. 7, in the cross-sectional view BB of Example 1, the arrangement pitch of the gate fingers 16a and 16b is Lgg / 2. The heat flow paths 36 expand as they move in the -Z direction from the gate fingers 16a and 16b. The expansion angle of the heat flow paths 36 with respect to the -Z direction is 45°. When the position z from the top surface 13 of the substrate 10 is approximately Lgg / 4 or more, the heat flow paths 36 expanding from adjacent gate fingers 16a and 16b overlap, and the area S(z) increases.

[0026] 8, in the CC cross section, no gate finger 16a is provided in region 35a, and instead a protruding portion 18a of the drain connection wiring 18 is provided. Heat flow paths 36 spreading from adjacent gate fingers 16b via the protruding portion 18a spread below the protruding portion 18a. This increases the area S(z) at the same position z compared to Comparative Example 1. In particular, when position z is approximately 3Lgg / 4 or greater, the heat flow paths 36 spreading from adjacent gate fingers 16b via the protruding portion 18a overlap, further increasing the area S(z).

[0027] 9, in the DD cross section, no gate finger 16b is provided in region 35b, and instead a protruding portion 20b of the gate connection wiring 20 is provided. Heat flow paths 36 spreading from adjacent gate fingers 16a via the protruding portion 20b spread below the protruding portion 20b. As a result, the area S(z) at the same position z becomes larger compared to Comparative Example 1. In particular, when position z is approximately 3Lgg / 4 or more, the heat flow paths 36 spreading from adjacent gate fingers 16a via the protruding portion 20b overlap, further increasing the area S(z).

[0028] As described above, in Example 1, the area S(z) at the same position z is larger than in Comparative Example 1, thereby reducing the thermal resistance Rth. If 3Lgg / 4 is sufficiently smaller than T1 + T2, the heat flow path 36 can be considered to extend from position P2a of the -Y end of gate finger 16a and position P1b of the +Y end of gate finger 16b toward the -Y and +Y sides at angles of 45° in the -Z direction, as shown in FIG. 4 . When the distance L5 between positions P2a and P1b is 500 μm, the length Lb of the heat flow path 36 on the lower surface 31 is 1300 μm. Compared to Comparative Example 1, the length Lb of the heat flow path 36 on the upper surface 13 of the substrate 10 is 1.25 times longer (L5 / L1 = 500 / 400), and the length Lb of the heat flow path 36 on the lower surface 31 is 1.08 times longer (1300 / 1200). Thus, in Example 1, the area S(z) at each position z is larger and the thermal resistance Rth is lower than in Comparative Example 1. This makes it possible to suppress the temperature rise of the gate fingers 16a and 16b.

[0029] If the lengths L2a and L3b in FIG. 3 are 100 μm and the lengths L2b and L3a are 200 μm, the length Ly in the X direction of the substrate 10 is 700 μm, which is the same as that of Comparative Example 1. The bonding wire 48 is bonded to the protrusion 18a in region 35a, and the bonding wire 44 is bonded to the protrusion 20b in region 35b. That is, at least a portion of region 38a is located between positions P1a and P1b, and at least a portion of region 38b is located between positions P2a and P2b. This ensures that L3a and L2b of 200 μm are secured as the regions for bonding the balls 48a and 44a. Thus, Example 1 can achieve the same size of semiconductor chip 50 as Comparative Example 1 while enhancing heat dissipation from the FET. In Example 1, the size of the semiconductor chip 50 can be reduced while maintaining the same heat dissipation as Comparative Example 1. Thus, Example 1 enables enhanced heat dissipation and miniaturization.

[0030] [Example 2] FIG. 10 is a plan view of a semiconductor chip in Example 2. FIG. 11 is a cross-sectional view taken along the line AA in FIG. 10. As shown in FIGS. 10 and 11, in Example 2, lengths L2a and L3b are, for example, 70 μm, and lengths L2b and L3a are 170 μm. Lengths L1b and L1a are 400 μm. If balls 44a and 48a are 100 μm, lengths L1b and L2a of 170 μm are sufficient. This allows the length Ly of substrate 10 in the Y direction to be 640 μm. However, if L2a and L3b are too short, heat flow path 36 will extend beyond side surfaces 13a and 13b of substrate 10. Therefore, bonding material 32a is provided below side surfaces 13a and 13b of substrate 10. When nano silver paste is used as the bonding material 32a, the thermal conductivity of the bonding material 32a made by sintering the nano silver paste is 200 to 300 W / (K·m), which is as high as that of SiC and copper. As a result, the heat flow passes through the bonding material 32a, and the same thermal resistance as in Example 1 can be obtained. In addition, the chip area can be reduced.

[0031] When the length L2a is shorter than the thickness T1 of the substrate 10, the heat flow path 36 extends beyond the side surface 13a of the substrate 10. The position where the heat flow path 36 extends beyond the side surface 13a is position P3a, which is L2a in the -Z direction from the top surface 13 of the substrate 10. Therefore, it is preferable that the range where the bonding material 32a contacts the side surface 13a of the substrate 10 includes position P3a. When L3b is shorter than the thickness T1, it is preferable that the range where the bonding material 32a contacts the side surface 13b of the substrate 10 includes position P3b, which is L3b in the -Z direction from the top surface 13 of the substrate 10.

[0032] [Example 3] 12 is a plan view of a semiconductor chip in Example 3. As shown in FIG. 12, the gate connection wiring 20 has a protrusion 20b and a recess 20a, but the drain connection wiring 18 has no protrusion or recess. Position P2a is located on the -Y side of position P2b. Positions P1a and P1b are approximately at the same position in the Y direction. There are approximately twice as many bonding wires 48 as there are bonding wires 44.

[0033] The lengths L1a and L1b of the gate fingers 16a and 16b are, for example, 440 μm and 360 μm, respectively. The lengths L2a and L2b are, for example, 70 μm and 150 μm, respectively. The length L3 is, for example, 150 μm. The length Ly of the substrate 10 in the Y direction is 660 μm. The distance L5 between P2a and P1b is 440 μm, and the length Lb of the heat flow path on the lower surface 31 of the base substrate 30 is 1240 μm. The other configurations are the same as those in Example 2, so a description thereof will be omitted.

[0034] In Example 3, the thermal resistance is larger than in Examples 1 and 2. The output current of amplifier 55 is two to five times the input current. The number of bonding wires 44 and 48 is set so that the current value flowing through each bonding wire 44 and 48 is equal to or less than the allowable current value. In this case, the number of bonding wires 44 can be set to 1 / 2 to 1 / 5 of the number of bonding wires 48. In Example 3, the ratio of the number of bonding wires 44 and 48 can be made close to the ratio of the input current to the output current.

[0035] [Example 4] FIG. 13 is a plan view of a semiconductor chip in Example 4. As shown in FIG. 13, recesses 18b and 20a are provided in region 35a, and protrusions 18a and 20b are provided in region 35b. Position P2a is located on the -Y side of position P2b, and position P1a is located on the +Y side of position P1b. As a result, length L1a of gate finger 16a is longer than length L1b of gate finger 16b. Lengths L1a and L1b are, for example, 500 μm and 300 μm, respectively. The other configurations are the same as in Example 2, and a description thereof will be omitted. In Example 4 as well, thermal resistance can be reduced, as in Example 2.

[0036] According to Examples 1 to 4, when viewed from the X direction, a first position P2a at which first ends of some first gate fingers 16a of the plurality of gate fingers 16 are connected to the gate connection wiring 20 is located closer to the first side surface 13a of the substrate 10 than a second position P2b at which first ends of some second gate fingers 16b of the plurality of gate fingers 16 are connected to the gate connection wiring 20. As a result, as shown in FIG. 9 , the heat flow path 36 is widened between positions P2a and P2b, thereby reducing the thermal resistance from the gate fingers 16 to the lower surface 31 of the base substrate 30. This improves heat dissipation. To further improve heat dissipation, the distance between positions P2a and P2b is preferably 0.05 times or more, more preferably 0.1 times or more, the length of the shortest gate finger 16 in the Y direction.

[0037] At least a portion of the first region 38b, where the bonding wire 44 (first bonding wire) is connected to the gate connection wiring 20, overlaps between positions P2a and P2b when viewed from the X direction. This allows L2a to be shortened, thereby reducing the size of the semiconductor chip 50. When viewed from the X direction, it is preferable that the first region 38b overlaps between positions P2a and P2b by 50% or more.

[0038] The source fingers 12 and the drain fingers 14 are arranged alternately, and the gate fingers 16 are each sandwiched between one of the source fingers 12 and one of the drain fingers 14 in the X direction, thereby realizing a multi-finger type FET.

[0039] When viewed from the X direction, the third position P1a, where the second end of the gate finger 16a on the drain connection wiring 18 side is located, is different from the fourth position P1b, where the second end of the gate finger 16b on the drain connection wiring 18 side is located. At least a portion of the second region 38a, where the bonding wire 48 (second bonding wire) is connected to the drain connection wiring 18, overlaps between the third position P1a and the fourth position P1b, when viewed from the X direction. This allows L3a to be shortened, and the semiconductor chip 50 to be miniaturized. When viewed from the X direction, it is preferable that the second region 38a overlaps between positions P1a and P1b by 50% or more.

[0040] As in the third embodiment, when viewed from the X direction, the third position P1a of the gate finger 16a and the fourth position P1b of the gate finger 16b are the same. This allows the number of bonding wires 48 connected to the drain connecting wiring 18 to be greater than the number of bonding wires 44 connected to the gate connecting wiring 20. This allows the number of bonding wires 48 through which an output current greater than an input current flows to be increased. The number of bonding wires 48 is preferably 1.5 times or more the number of bonding wires 44, and more preferably 2 times or more.

[0041] As shown in FIG. 7, the thickness T1 of the substrate 10 is at least half the shortest distance Lgg / 2 in the X direction between adjacent gate fingers 16 among the multiple gate fingers 16. This allows the heat flow paths 36 from adjacent gate fingers 16 to overlap within the substrate 10, thereby further improving heat dissipation. Also, as shown in FIG. 9, the thickness T1 of the substrate 10 is preferably at least three-half the shortest distance Lgg / 2 in the X direction between adjacent gate fingers 16a. This allows the heat flow paths 36 from gate fingers 16b that sandwich the protrusion 20b within the substrate 10 to overlap, thereby further improving heat dissipation. The thickness T1 of the substrate 10 is preferably at least one time Lgg / 2, and more preferably at least two times Lgg / 2.

[0042] The device includes a base substrate 30 and a bonding material 32 that bonds the base substrate 30 to the underside of the substrate 10. This allows the heat flow paths 36 to spread within the base substrate 30. Therefore, even if the thickness T1 of the substrate 10 is thinner than Lgg / 4, the heat flow paths 36 from adjacent gate fingers 16 overlap within the base substrate 30. This improves heat dissipation.

[0043] 11 of Example 2, the distance L2a between the first position P2a and the first side surface 13a is smaller than the thickness T1 of the substrate 10. In this case, the bonding material 32a covers the area between the lower end of the side surface 13a and a position P3a that is separated by the distance L2a from the upper end to the lower end of the substrate 10. This allows the heat flow path 36 to expand within the bonding material 32a, thereby improving heat dissipation.

[0044] In the case of a GaN HEMT, a sapphire substrate, a silicon substrate, a GaN substrate, a diamond substrate, or the like can be used as the substrate 10a. To reduce the thermal resistance of the heat flow path 36, the substrate 10 preferably includes a single-crystal SiC substrate with high thermal conductivity. The thickness of the SiC substrate 10a is preferably 0.9 times or more, and more preferably 0.95 times or more, the thickness T1 of the substrate 10. Although a nitride semiconductor layer such as a GaN-based semiconductor layer has been described as an example of the semiconductor layer 10b, the semiconductor layer 10b may also be a GaAs-based semiconductor layer.

[0045] In the first to fourth embodiments, an example has been described in which two gate fingers 16a are provided in one region 35a, and two gate fingers 16b are provided in one region 35b. The number of gate fingers 16a provided in one region 35a may be one or three or more. The number of gate fingers 16b provided in one region 35b may be one or three or more. That is, in the region 35a (first 3 In the region 35b (the first region), one or more gate fingers 16a are provided without any other gate fingers 16 therebetween. 4 In each of the regions 35a and 35b, one or more gate fingers 16b are provided without any other gate fingers 16 sandwiched therebetween. The regions 35a and 35b are alternately provided in the X direction. This improves heat dissipation in a multi-finger FET with high output power. From the viewpoint of increasing output power, the number of regions 35a and 35b is preferably two or more, and more preferably three or more.

[0046] When the number of gate fingers 16a per region 35a is large, the distance between regions 35b in FIG. 8 becomes longer. Therefore, the position z where the heat flow paths 36 from adjacent regions 35b overlap becomes larger. As a result, S(z) in Equation 1 does not become large, resulting in high thermal resistance. The same applies when the number of gate fingers 16b per region 35b is large. Therefore, the number of gate fingers 16a provided in one region 35a is preferably four or less, more preferably three or less, and even more preferably two or less. The number of gate fingers 16b provided in one region 35b is preferably four or less, more preferably three or less, and even more preferably two or less.

[0047] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0048] 10, 10a board 10b Semiconductor layer 12 Sauce Fingers 13 Top side 13a, 13b Sides (1st side, 2nd side) 14 Drain Finger 16 Gate Finger 16a, 16b: gate fingers (first gate finger, second gate finger) 18 Drain connection wiring 18a, 20b convex parts 18b, 20a recess 20 Gate connection wiring 22 Active area 24 Through electrode 30 Base board 31 Bottom side 32, 32a Bonding material 35a, 35b, 38a, 38b area 36 Heat flow path 40, 45 Matching parts 41, 46 Dielectric substrate 42, 47 electrode 43, 44, 48, 49 Bonding wire 44a, 48a balls 50 semiconductor chips 52 Input matching circuit 54 Output matching circuit 55 Amplifier P1a, P1b position (3rd position, 4th position) P2a, P2b position (1st position, 2nd position)

Claims

1. A substrate; an active region disposed within the substrate; a plurality of gate fingers provided on the active region, extending in an extension direction and arranged in an arrangement direction perpendicular to the extension direction; a gate connection wiring, the gate fingers being commonly connected, the gate connection wiring being provided between the gate fingers and a first side surface of the substrate; a plurality of source fingers provided on the active region, extending in the extension direction and arranged in the arrangement direction; a plurality of drain fingers provided on the active region, extending in the extension direction and alternately arranged with the plurality of source fingers in the arrangement direction; a drain connection wiring, to which first ends of the drain fingers are commonly connected, and provided between the gate fingers and a second side surface of the substrate opposite to the first side surface; Equipped with each of the plurality of gate fingers is sandwiched between one of the plurality of source fingers and one of the plurality of drain fingers in the arrangement direction; when viewed from the arrangement direction, a first position where first ends of some first gate fingers of the plurality of gate fingers are connected to the gate connection wiring is closer to the first side surface than a second position where first ends of some second gate fingers of the plurality of gate fingers are connected to the gate connection wiring; When viewed from the arrangement direction, a third position where a second end of the first gate finger on the drain connection wiring side is located is closer to the second side surface than a fourth position where a second end of the second gate finger on the drain connection wiring side is located.

2. 2 . The semiconductor device according to claim 1 , wherein at least a portion of a first region in which a first bonding wire is connected to the gate connection wiring overlaps between the first position and the second position when viewed from the arrangement direction.

3. 3. The semiconductor device according to claim 2, wherein at least a portion of the second region in which the second bonding wire is connected to the drain connecting wiring overlaps between the third position and the fourth position when viewed from the arrangement direction.

4. when viewed from the arrangement direction, a third position where a second end of the first gate finger on the drain connection wiring side is located is the same as a fourth position where a second end of the second gate finger on the drain connection wiring side is located; 3. The semiconductor device according to claim 2, wherein the number of first bonding wires connected to the gate connecting wiring is smaller than the number of second bonding wires connected to the drain connecting wiring.

5. 5. The semiconductor device according to claim 1, wherein the thickness of the substrate is equal to or greater than half the shortest distance in the arrangement direction between adjacent gate fingers among the plurality of gate fingers.

6. A base substrate; a bonding material that bonds the base substrate and the lower surface of the substrate; Equipped with a distance between the first position and the first side surface is smaller than a thickness of the substrate; The semiconductor device according to claim 5 , wherein the bonding material covers a portion of the first side surface that is spaced apart from the upper end toward the lower end of the substrate by the distance and a lower end of the first side surface.

7. 7. The semiconductor device according to claim 1, wherein a third region in which one or more first gate fingers are provided without any other gate fingers therebetween and a fourth region in which one or more second gate fingers are provided without any other gate fingers therebetween are alternately arranged in the arrangement direction.

8. The semiconductor device according to claim 1 , wherein the substrate includes a SiC substrate.

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