Masked Shift-Add Operation

Abstract

The computer-implemented method includes receiving, by a processing unit, an instruction to perform a masked shift-and-add operation with a set of operands. A logical AND operation is performed on a first pair of operands in the set of operands to obtain a first intermediate result. The first intermediate result is shifted by a first shift amount based on a first operand of the first pair of operands. A logical AND operation is performed on a second pair of operands in the set of operands to obtain a second intermediate result. The second intermediate result is shifted by a second shift amount based on the first operand of the second pair of operands. The shifted first intermediate result is added to the shifted second intermediate result. The method further includes outputting an output of the addition as a result of the masked shift-and-add operation.

Description

[Technical Field]

[0001] The present invention relates generally to computer technology, and more particularly to performing arithmetic operations by implementing masked shift-and-add operations. [Background technology]

[0002] Computers are typically used to perform arithmetic operations. Some applications, such as cryptography, blockchain, machine learning, image processing, computer games, e-commerce, etc., require that such operations be performed efficiently (e.g., fast). Therefore, integer arithmetic performance has become a focus of both academic and industrial research.

[0003] Several existing techniques are used to improve the performance of computers, particularly processors and / or arithmetic logic units, by implementing arithmetic instructions to exploit the hardware architecture or to adapt the computational process to the hardware architecture. Examples of such techniques include dividing an instruction into multiple operations where each operation is performed in parallel, combining two or more operations to reduce memory accesses, ordering operations to reduce memory access time, and storing operands in a specific order to reduce access time. Applications such as cryptography and machine learning may require different types of arithmetic operations. Operations frequently used in such applications need to be adapted to hardware to improve the performance of such operations and, therefore, the application. Summary of the Invention

[0004] According to one or more embodiments of the present invention, a computer-implemented method includes receiving, by a processing unit, an instruction to perform a masked shift-and-add operation with a set of operands. The method further includes performing a logical AND operation on a first pair of operands in the set of operands to obtain a first intermediate result. The method further includes shifting the first intermediate result by a first shift amount based on the first operand of the first pair of operands. The method further includes performing a logical AND operation on a second pair of operands in the set of operands to obtain a second intermediate result. The method further includes shifting the second intermediate result by a second shift amount based on the first operand of the second pair of operands. The method further includes adding the shifted first intermediate result and the shifted second intermediate result. The method further includes outputting an output of the addition as a result of the masked shift-and-add operation.

[0005] In one or more embodiments of the present invention, the first shift amount is the index of the first non-zero bit in the first operand of the first pair of operands.

[0006] In one or more embodiments of the present invention, shifting the first intermediate result by the first shift amount includes zero-padding the first intermediate result by the first shift amount.

[0007] In one or more embodiments of the present invention, shifting the second intermediate result by the second shift amount includes zero-padding the second intermediate result by the second shift amount.

[0008] In one or more embodiments of the invention, the method further includes updating a carry flag of the processing unit based on a carry resulting from adding the shifted first intermediate result and the shifted second intermediate result.

[0009] In one or more embodiments of the present invention, a carry flag is updated based on a received instruction that performs a masked shift-and-add operation.

[0010] In one or more embodiments of the present invention, a processing unit shifts the first intermediate result and the second intermediate result and adds the shifted first intermediate result and the second intermediate result in parallel for two or more input values, and an output of the parallelized operations is a result of the masked shift-and-add operation for the two or more input values.

[0011] According to one or more embodiments of the present invention, a system includes a set of registers and one or more processing units coupled to the set of registers, the one or more processing units configured to perform a method for performing a masked shift-and-add operation on a set of operands. Performing the masked shift-and-add operation includes performing a logical AND operation on a first pair of operands in the set of operands to obtain a first intermediate result. Performing the masked shift-and-add operation further includes shifting the first intermediate result by a first shift amount based on the first operand of the first pair of operands. Performing the masked shift-and-add operation further includes performing a logical AND operation on a second pair of operands in the set of operands to obtain a second intermediate result. Performing the masked shift-and-add operation further includes shifting the second intermediate result by a second shift amount based on the first operand of the second pair of operands. Performing the masked shift-and-add operation further includes adding the shifted first intermediate result and the shifted second intermediate result. Performing the masked shift-and-add operation further includes outputting an output of the addition as a result of the masked shift-and-add operation.

[0012] In one or more embodiments of the present invention, the first shift amount is the index of the first non-zero bit in the first operand of the first pair of operands.

[0013] In one or more embodiments of the present invention, shifting the first intermediate result by the first shift amount includes zero-padding the first intermediate result by the first shift amount.

[0014] In one or more embodiments of the present invention, shifting the second intermediate result by the second shift amount includes zero-padding the second intermediate result by the second shift amount.

[0015] In one or more embodiments of the invention, the method further includes updating a carry flag based on a carry resulting from adding the shifted first intermediate result and the shifted second intermediate result.

[0016] In one or more embodiments of the present invention, a carry flag is updated based on a received instruction that performs a masked shift-and-add operation.

[0017] In one or more embodiments of the present invention, the set of operands is provided in a set of registers.

[0018] According to one or more embodiments of the present invention, a computer program product includes a computer-readable memory having computer-executable instructions stored thereon, which, when executed by a processor, cause the processor to perform a method for performing arithmetic operations using masked shift-and-add operations in parallel. Performing each masked shift-and-add operation on a set of operands includes receiving an instruction to perform a masked shift-and-add operation with the set of operands. Performing each masked shift-and-add operation further includes performing a logical AND operation on a first pair of operands in the set of operands to obtain a first intermediate result. Performing each masked shift-and-add operation further includes shifting the first intermediate result by a first shift amount based on the first operand of the first pair of operands. Performing each masked shift-and-add operation further includes performing a logical AND operation on a second pair of operands in the set of operands to obtain a second intermediate result. Performing each masked shift-and-add operation further includes shifting the second intermediate result by a second shift amount based on the first operand of the second pair of operands. Performing each masked shift and add operation further includes adding the shifted first intermediate result and the shifted second intermediate result, and performing each masked shift and add operation further includes outputting an output of the addition as a result of the masked shift and add operation.

[0019] According to one or more embodiments of the present invention, the first shift amount is the index of the first non-zero bit in the first operand of the first pair of operands.

[0020] According to one or more embodiments of the present invention, shifting the first intermediate result by the first shift amount includes zero-padding the first intermediate result by the first shift amount.

[0021] According to one or more embodiments of the present invention, shifting the second intermediate result by the second shift amount includes zero-padding the second intermediate result by the second shift amount.

[0022] According to one or more embodiments of the present invention, performing the operation further includes updating a carry flag based on a carry resulting from adding the shifted first intermediate result and the shifted second intermediate result.

[0023] In accordance with one or more embodiments of the present invention, the operands are provided in registers.

[0024] According to one or more embodiments of the present invention, a computer processor includes a set of registers and an instruction execution unit configured to execute a masked shift-and-add instruction on a set of operands. The execution includes performing a logical AND operation on a first pair of operands to obtain a first intermediate result. The execution further includes shifting the first intermediate result by a first shift amount based on a first operand of the first pair of operands. The execution further includes performing a logical AND operation on a second pair of operands to obtain a second intermediate result. The execution further includes shifting the second intermediate result by a second shift amount based on the first operand of the second pair of operands. The execution further includes adding the shifted first intermediate result and the shifted second intermediate result. The execution further includes outputting an output of the addition as a result of the masked shift-and-add operation.

[0025] In one or more embodiments of the present invention, the first pair of operands and the second pair of operands are processed in parallel.

[0026] In one or more embodiments of the present invention, the operands are provided in a set of registers.

[0027] According to one or more embodiments of the present invention, a computer-implemented method for arithmetic operations includes, by a processing unit, dividing two input values ​​of an arithmetic operation into several separate portions and performing masked shift-and-add operations in parallel using two corresponding portions of the two input values ​​as part of a set of operands for the masked shift-and-add operations. Performing each masked shift-and-add operation includes performing a logical AND operation on a first pair of operands to obtain a first intermediate result. Performing each masked shift-and-add operation further includes shifting the first intermediate result by a first shift amount based on the first operand of the first pair of operands. Performing each masked shift-and-add operation further includes performing a logical AND operation on a second pair of operands to obtain a second intermediate result. Performing each masked shift-and-add operation further includes shifting the second intermediate result by a second shift amount based on the first operand of the second pair of operands. Performing each masked shift-and-add operation further includes adding the shifted first intermediate result and the shifted second intermediate result. Performing each masked shift and add operation further includes outputting the output of the addition as a result of the masked shift and add operation.

[0028] In one or more embodiments of the present invention, the first pair of operands and the second pair of operands are processed in parallel.

[0029] The above features may be provided by at least one system, a computer program product, and a machine, among other types of implementations.

[0030] Embodiments of the present invention provide a technical solution that facilitates processors that can implement masked shift-add instructions (e.g., add_ms, add_msc) in reduced time compared to existing techniques. Embodiments of the present invention improve time requirements by facilitating execution of masked shift-add instructions with reduced cross-iteration dependencies. The dependencies are reduced in one or more embodiments of the present invention by encoding the shift amount in a mask, where the shift is the index of a non-zero bit in the mask. Furthermore, embodiments of the present invention facilitate utilizing this instruction to perform carry ripple operations and reduce the number of carry bits in a reduced-base representation to a single bit (Table 2).

[0031] Additional technical features and advantages are realized through the techniques of the present invention. Embodiments and aspects of the present invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, reference is made to the detailed description and drawings.

[0032] The particulars of the exclusive rights set forth herein are particularly pointed out and distinctly claimed in the claims at the end of the specification. The foregoing and other features and advantages of embodiments of the present invention will become apparent from the following detailed description read in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a visual representation of a technical problem addressed by one or more embodiments of the present invention. [Figure 2] 1 is a flowchart of a method for performing a masked shift-and-add operation in accordance with one or more embodiments of the present invention. [Figure 3] FIG. 1 illustrates a method for determining a shift amount in accordance with one or more embodiments of the present invention. [Figure 4] FIG. 2 illustrates operations being performed on values ​​in registers of a processor in accordance with one or more embodiments of the present invention. [Figure 5]1 is a block diagram comparing an addition operation performed using existing technology and an addition operation performed in accordance with one or more embodiments of the present invention. [Figure 6] FIG. 1 is a block diagram of a processor in accordance with one or more embodiments of the present invention. [Figure 7] FIG. 1 is a diagram of a computing system in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0034] The diagrams depicted herein are for illustrative purposes. There may be many variations to the diagrams or the operations described therein without departing from the spirit of the invention. For example, operations may be performed in a different order, or operations may be added, deleted, or modified. Also, the term "coupled" and variations thereof mean having a communication path between two elements and do not imply a direct connection between those elements without an intervening element / connection therebetween. All such variations are considered part of this specification.

[0035] In the accompanying drawings and the following detailed description of the disclosed embodiments, various elements shown in the figures are given two- or three-digit reference numbers. With minor exceptions, the left-most digit(s) of each reference number corresponds to the figure in which the element is first shown.

[0036]

[0006] A technical solution is described herein that improves the efficiency of computer processors by facilitating the implementation of masked shift-add operations. Addition and multiplication arithmetic operations are frequently used in computer systems.

[0037] Computer systems typically use binary representation when performing arithmetic operations. Furthermore, computer systems, particularly processors and the arithmetic logic units (ALUs) of processors, have a predetermined "width" or "word size" (w), such as 32 bits, 64 bits, 128 bits, etc. The width represents the maximum number of bits that a processor can process at one time. The width of a processor can be determined by the size of the registers, the size of the ALU processing width, or other such processing limits of components associated with the processor.

[0038] Technical challenges exist when a processor performs addition and multiplication operations using a reduced-radix representation. FIG. 1 provides a visual representation of the technical challenges addressed by one or more embodiments of the present invention. Let p be a number of n bits, w be the word size of processor 10, and assume that an arithmetic operation is performed on p. At this time, processor 10 determines a radix

Number

Number

Number

Number

[0039] For example, consider a multiplication operation performed on p. After the multiplication, each word stored in each register 12 has an accumulation of carry bits 14. The carry bits 14 must be added to subsequent words, with each "rim" returning to the ρ bit. In existing processors, a "ripple-carry" operation is performed, starting with the least significant word and progressing to the most significant word, to propagate the carry bits 14. This operation must be performed sequentially, but data dependencies between words mean that an operation on a word can only begin after the carry bits 14 of the previous word have been added and the result of that addition is available.

[0040] Embodiments of the present invention provide technical solutions that address such technical challenges. Embodiments of the present invention reduce data dependencies between words, making it easier to perform operations that propagate carry bit 14 sequentially. As a result, in one or more embodiments of the present invention, carry propagation operations can be issued one after the other without having to wait for the result of a ripple operation on a previous word. Embodiments of the present invention thereby improve processor operation and, therefore, provide improvements in computing technology.

[0041] 2 illustrates a flowchart of a method for performing a masked shift-and-add operation in accordance with one or more embodiments of the present invention. The method includes, at block 100, receiving an instruction to perform a masked shift-and-add operation. For example, the instruction may be expressed as "add_ms,a,b,c,d,e," where operands a, b, c, d, and e are registers 12 within processor 10. Another variation of the instruction may be "add_msc,a,b,c,d,e," in which carry bits are added and the carry resulting from the addition is stored in a carry bit / flag (not shown) of processor 10.

[0042] The result of this instruction is e=[(a&c)>>c_first_one]+[(b&d)>>d_first_one], where c_first_one is the index of the first non-zero bit in c, counting from the least significant bit, and d_first_one is the index of the first non-zero bit in d, counting from the least significant bit. Figure 4 illustrates operations being performed on values ​​in registers 12 of processor 10, in accordance with one or more embodiments of the present invention.

[0043] It is understood that the names of the instructions, the operands used, and the format of the instructions may vary in other embodiments of the invention. Additionally, it is understood that in other embodiments of the invention, the operands may be provided in different forms, such as memory locations, immediate values, address pointers, etc. Additionally, although embodiments of the invention are described herein as having operands in a particular order, in other embodiments of the invention, the order of the operands may differ.

[0044] In block 101, processor 10 reads registers a and c12, which are the first and third operands. In block 102, processor 10 performs a logical AND operation (&) on the first and third operands, which are stored as an intermediate result. In block 103, processor 10 determines the shift amount using register c12, which is the third operand.

[0045] FIG. 3 illustrates a method for determining a shift amount according to one or more embodiments of the present invention. In block 201, processor 10 bit-wise scans an operand, starting from the least significant bit (LSB) to the most significant bit (MSB). Note that in some embodiments, the LSB may be assigned index 0, and in some embodiments, the MSB may be assigned index 0. The operand may be a register 12, a memory location, an immediate value, or any other type of input that specifies an input value on which the shift amount is based. For each bit encountered in the operand from the LSB to the most significant bit (MSB), in block 202, processor 10 checks whether the bit is non-zero (i.e., 1). Checking for non-zero bits (block 202) continues until a non-zero bit is encountered (in block 203) or until all bits in the input value have been checked. In block 203, the index of the first non-zero bit is determined. If the operand is zero, a zero value is output.

[0046] Referring again to the method flowchart of FIG. 2, once the shift amount is determined using the third operand c (block 103), in block 104 processor 10 performs a shift operation on the intermediate result by that shift amount and zero-pads the result to obtain a new (second) intermediate result.

[0047] In block 105, processor 10 reads second and fourth operands b and d. In block 106, processor 10 performs a logical AND operation (&) on the second and fourth operands, which are stored as the intermediate (third) result. In block 107, processor 10 determines a (second) shift amount using the fourth operand d. The shift amount is determined using the same technique as described in FIG. 3. Furthermore, in block 108, processor 10 shifts the (third) intermediate result by the (second) shift amount and zero-pads the result to obtain a new (fourth) intermediate result.

[0048] In block 109, processor 10 adds together the second intermediate result and the fourth intermediate result (from blocks 104 and 108). The result of the addition is stored in a fifth operand, e, in block 110.

[0049] In block 111, if the carry bit is to be recorded, processor 10 updates carry flag 401 in response to the carry from the addition operation (in block 109) of the second intermediate result and the fourth intermediate result.

[0050] Performing the addition in this manner reduces the time required to obtain a result compared to existing techniques. Figure 5 shows a block diagram comparing an addition operation performed using existing techniques and an addition operation performed in accordance with one or more embodiments of the present invention. For comparison, consider the current state of the art, which uses a word size w=64 and a radix ρ=56. The addition is performed using the pseudocode / algorithm shown in Table 1. In summary, the current state of the art performs the addition by: 1) generating partial products that overflow the 56 bits of the radix but fit into an entire word; 2) starting with the least significant word, selecting a carry bit as the bit in the word that overflows the radix; 3) adding the carry bit to the subsequent word; and 4) repeating steps 2 and 3 above for all partial products.

[0051] [Table 1]

[0052] As can be seen, there are dependencies between instructions within and across iterations (e.g., lines 4 and 5 in a subsequent iteration depend on the result of line 16 in the previous iteration). Steps 3 and 4 in one iteration (see previous paragraph) must be completed before the next iteration can begin.

[0053] As will be further explained, one or more embodiments of the present invention reduce and possibly eliminate this latency component within an iteration and across iterations.

[0054] Consider a masked shift-and-add operation according to one or more embodiments of the present invention using a word size w=64 and a radix ρ=54. The execution of the instruction can be represented as the pseudocode / algorithm shown in Table 2.

[0055] [Table 2]

[0056] As described herein, partial products are generated that overflow the 54-bit base but fit into an entire word. Starting with the most significant word, the processor performs add_ms pp[i], pp[i-1], MASK_54_107, MASK_108_127, res[i], where MASK_54_127 = zeros in bits 0:53, ones in bits 54:107, zeros in bits 108:127, and MASK_108_127 = zeros in bits 0:107, ones in bits 108:127. This step is repeated for all partial products.

[0057] An embodiment of the present invention combines steps 3 and 4 from the state of the art above into one instruction. Furthermore, once step 3 issues an instruction for one iteration, the instruction for the next iteration can be issued immediately on the next clock without waiting for the completion of the previous iteration. In summary, with masked shift-and-add operations according to one or more embodiments of the present invention, dependencies are limited to instructions within a single iteration. Because there are no cross-iteration dependencies, loops can be unrolled to reduce the time required to obtain a result.

[0058] For example, embodiments of the present invention provide a 40% improvement over existing techniques for 256-bit multiplications and a 25% improvement for 2048-bit multiplications. Further improvements are obtained by keeping processor 10 in redundant reduced radix form when subsequent operations are also multiplications.

[0059] Therefore, embodiments of the present invention provide a technical solution that facilitates processors that can implement masked shift-add instructions (e.g., add_ms, add_msc) in reduced time compared to existing techniques. Embodiments of the present invention improve time requirements by facilitating execution of masked shift-add instructions with reduced cross-iteration dependencies. Dependencies are reduced in one or more embodiments of the present invention by encoding the shift amount in a mask, where the shift is the index of a non-zero bit in the mask. Furthermore, embodiments of the present invention facilitate utilizing this instruction to perform a carry ripple operation and reduce the number of carry bits in a reduced-base representation to a single bit (Table 2).

[0060] 6 illustrates a block diagram of a processor in accordance with one or more embodiments of the present invention. The processor 10 may include, among other components, an instruction fetch unit 601, an instruction decode and operand fetch unit 602, an instruction execution unit 603, a memory access unit 604, a writeback unit 605, a set of registers 12, and a masked shift-and-add executor 606. In one or more embodiments of the present invention, the masked shift-and-add executor 606 may be part of an arithmetic logic unit (ALU) (not shown).

[0061] In one or more embodiments of the present invention, processor 10 may be one of several computer processors in a processing unit, such as a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), or any other processing unit of a computer system. Alternatively or additionally, processor 10 may be a computing core that is part of one or more processing units.

[0062] The instruction fetch unit 601 is responsible for organizing program instructions to be retrieved from memory and executed into the appropriate sequence and transferring them to the instruction execution unit 603. The instruction decode and operand fetch unit 602 facilitates instruction and operand parsing, e.g., address resolution and prefetching, before transferring the instructions to the instruction execution unit 603. The instruction execution unit 603 performs operations and calculations according to the instructions. The memory access unit 604 facilitates accessing specific locations within a memory device coupled to the processor 10. The memory device may be a cache memory, a volatile memory, a non-volatile memory, etc. The write-back unit 605 facilitates recording the contents of the register 12 to one or more locations within the memory device. The masked shift-add executor 606 facilitates executing masked shift-add instructions as described herein.

[0063] It should be noted that the components of the processor may differ in various ways in one or more embodiments of the present invention without affecting the features of the technical solution described herein. In some embodiments of the present invention, the components of the processor 10 may be combined, separated, or different from those described herein.

[0064] Turning now to FIG. 7 , a computer system 1500 according to one embodiment is generally illustrated. Computer system 1500 may be a target computing system used to perform one or more functions that require a masked shift-and-add operation to be performed. Computer system 1500 may be an electronic computer framework that includes and / or uses any number and combination of computing devices and networks utilizing various communication technologies as described herein. Computer system 1500 may be readily scalable, extensible, and modular, with the ability to adapt to different services or reconfigure some functions independently of each other. Computer system 1500 may be, for example, a server, desktop computer, laptop computer, tablet computer, or smartphone. In some examples, computer system 1500 may be a cloud computing node. Computer system 1500 may be described in the general context of computer system-executable instructions, such as program modules, executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer system 1500 may be practiced in a distributed cloud computing environment where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media, including memory storage devices.

[0065] As shown in FIG. 7, computer system 1500 includes one or more central processing units (CPUs) 1501a, 1501b, 1501c, etc. (collectively or generically referred to as processors 1501). Processor 1501 may be a single-core processor, a multi-core processor, a computing cluster, or any number of other configurations. Processor 1501, also referred to as a processing circuit, is coupled to system memory 1503 and various other components via a system bus 1502. System memory 1503 may include read-only memory (ROM) 1504 and random access memory (RAM) 1505. ROM 1504 is coupled to system bus 1502 and may include a basic input / output system (BIOS) that controls certain basic functions of computer system 1500. RAM is read / write memory coupled to system bus 1502 for use by processor 1501. System memory 1503 provides temporary memory space for the execution of instructions during operation. System memory 1503 may include random access memory (RAM), read-only memory, flash memory, or any other suitable memory system.

[0066] Computer system 1500 includes an input / output (I / O) adapter 1506 and a communications adapter 1507 coupled to a system bus 1502. I / O adapter 1506 may be a small computer system interface (SCSI) adapter that communicates with a hard disk 1508 and / or any other similar component. I / O adapter 1506 and hard disk 1508 are collectively referred to herein as mass storage 1510.

[0067] Software 1511 for execution by computer system 1500 may be stored in mass storage 1510. Mass storage 1510 is an example of a tangible storage medium readable by processor 1501, and software 1511 is stored as instructions executed by processor 1501 to cause computer system 1500 to operate as described hereinbelow with respect to various figures. Examples of computer program products and the execution of such instructions are described in more detail below. Communications adapter 1507 interconnects system bus 1502 with network 1512, which may be an external network, enabling computer system 1500 to communicate with other similar systems. In one embodiment, a portion of system memory 1503 and mass storage 1510 cooperate to store an operating system, which may be any suitable operating system, such as IBM Corporation's z / OS® or AIX® operating systems, that coordinates the functions of the various components shown in FIG. 7.

[0068] Additional input / output devices are shown connected to the system bus 1502 via a display adapter 1515 and an interface adapter 1516. In one embodiment, adapters 1506, 1507, 1515, and 1516 may be connected to one or more I / O buses that are connected to the system bus 1502 through an intermediate bus bridge (not shown). A display 1519 (e.g., a screen or display monitor) is connected to the system bus 1502 by the display adapter 1515, which may include a graphics controller and a video controller to improve performance of graphics-intensive applications. A keyboard 1521, a mouse 1522, speakers 1523, etc. may be interconnected to the system bus 1502 via the interface adapter 1516, which may include, for example, a Super I / O chip that combines multiple device adapters into a single integrated circuit. Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include common protocols such as Peripheral Component Interconnect (PCI). Thus, when configured as shown in Figure 7, computer system 1500 includes processing capability in the form of processor 1501, storage capability including system memory 1503 and mass storage 1510, input means such as keyboard 1521 and mouse 1522, and output capability including speakers 1523 and display 1519.

[0069] In some embodiments, communications adapter 1507 can transmit data using any suitable interface or protocol, such as an Internet Small Computer System Interface, among others. Network 1512 can be a cellular network, a wireless network, a wide area network (WAN), a local area network (LAN), or the Internet, among others. External computing devices can connect to computer system 1500 through network 1512. In some examples, the external computing device can be an external web server or a cloud computing node.

[0070] It should be understood that the block diagram of Figure 7 is not intended to imply that computer system 1500 includes all of the components shown in Figure 7. Rather, computer system 1500 may include fewer suitable components or additional components not shown in Figure 7 (e.g., additional memory components, embedded controllers, modules, additional network interfaces, etc.). Furthermore, the embodiments described herein with respect to computer system 1500 may be implemented using any suitable logic, and logic as referred to herein may, in various embodiments, include suitable hardware (e.g., a processor, embedded controller, or application specific integrated circuit, among others), software (e.g., an application, among others), firmware, or any suitable combination of hardware, software, and firmware.

[0071] The present invention may be a system, method, or computer program product, or a combination thereof, at any possible level of integration of technical detail. The computer program product may include one or more computer-readable storage media having computer-readable program instructions for causing a processor to implement aspects of the present invention.

[0072] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the above. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or ridge structures in grooves in which instructions are recorded, or any suitable combination of the above. The computer-readable storage medium used in this invention should not be construed as a transitory signal itself, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse through a fiber optic cable), or an electrical signal transmitted over an electrical wire.

[0073] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage within the computer-readable storage medium within the respective computing / processing device.

[0074] Computer-readable program instructions for carrying out operations of the present invention may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk®, C++, and the like, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server, as a standalone software package. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to implement aspects of the present invention.

[0075] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or blocks, can be implemented by computer-readable program instructions.

[0076] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine whose instructions, executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium capable of directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored constitutes an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0077] The computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause a series of operational steps on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0078] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of an instruction set, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by special-purpose hardware-based systems that perform the specified functions or that operate or implement a combination of special-purpose hardware and computer instructions.

[0079] The description of various embodiments of the present invention has been presented for purposes of illustration and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles, practical applications, or technical improvements over commercially available technologies of the embodiments, or to enable those skilled in the art to understand the embodiments described herein.

Claims

1. 1. A computer-implemented method comprising: receiving, by a processing unit, an instruction to perform a masked shift-and-add operation with a set of operands; performing a logical AND operation on a first pair of operands in the set of operands to obtain a first intermediate result; shifting the first intermediate result by a first shift amount based on a first operand of the first pair of operands, including scanning the first operand of the first pair of operands from least significant bit to most significant bit, and the first shift amount being an index of a first non-zero bit determined by the scanning; performing a logical AND operation on a second pair of operands in the set of operands to obtain a second intermediate result; shifting the second intermediate result by a second shift amount based on a first operand of the second pair of operands; adding the shifted first intermediate result and the shifted second intermediate result; outputting the output of said addition as a result of said masked shift-and-add operation; 10. A computer-implemented method comprising:

2. 2. The computer-implemented method of claim 1, wherein the first shift amount is a zero value if the first operand is zero.

3. 2. The computer-implemented method of claim 1, wherein shifting the first intermediate result by the first shift amount comprises zero-padding the first intermediate result by the first shift amount.

4. 2. The computer-implemented method of claim 1, wherein shifting the second intermediate result by the second shift amount comprises zero-padding the second intermediate result by the second shift amount.

5. 2. The computer-implemented method of claim 1, further comprising: updating a carry flag of the processing unit based on a carry resulting from adding the shifted first intermediate result and the shifted second intermediate result.

6. 6. The computer-implemented method of claim 5, wherein the carry flag is updated based on the received instruction that performs the masked shift-and-add operation.

7. the processing unit performs the shifting of the first intermediate result and the second intermediate result and the addition of the shifted first intermediate result and the second intermediate result in parallel for two or more input values; 2. The computer-implemented method of claim 1, wherein an output of the parallelized operation is a result of the masked shift-and-add operation on the two or more input values.

8. 1. A system comprising: A set of registers, one or more processing units coupled to said set of registers; wherein the one or more processing units are configured to perform a method for performing a masked shift-and-add operation on a set of operands, wherein performing the masked shift-and-add operation comprises: performing a logical AND operation on a first pair of operands in the set of operands to obtain a first intermediate result; shifting the first intermediate result by a first shift amount based on a first operand of the first pair of operands, including scanning the first operand of the first pair of operands from least significant bit to most significant bit, and the first shift amount being an index of a first non-zero bit determined by the scanning; performing a logical AND operation on a second pair of operands in the set of operands to obtain a second intermediate result; shifting the second intermediate result by a second shift amount based on a first operand of the second pair of operands; adding the shifted first intermediate result and the shifted second intermediate result; and outputting the output of the addition as a result of the masked shift-and-add operation. system.

9. 9. The system of claim 8, wherein the first shift amount is a zero value if the first operand is zero.

10. 9. The system of claim 8, wherein shifting the first intermediate result by the first shift amount comprises zero-padding the first intermediate result by the first shift amount.

11. 9. The system of claim 8, wherein shifting the second intermediate result by the second shift amount comprises zero-padding the second intermediate result by the second shift amount.

12. 9. The system of claim 8, wherein performing the masked shift-and-add operation further comprises updating a carry flag based on a carry resulting from adding the shifted first intermediate result and the shifted second intermediate result.

13. 13. The system of claim 12, wherein the carry flag is updated based on a received instruction that performs the masked shift-and-add operation.

14. 9. The system of claim 8, wherein the set of operands is provided in the set of registers.

15. A computer program product for causing a computer processor to carry out the steps of the method according to any one of claims 1 to 7.

16. 1. A computer processor comprising: A set of registers, an instruction execution unit configured to execute a masked shift and add instruction on a set of operands, said execution comprising: performing a logical AND operation on a first pair of operands to obtain a first intermediate result; shifting the first intermediate result by a first shift amount based on a first operand of the first pair of operands, including scanning the first operand of the first pair of operands from least significant bit to most significant bit, and the first shift amount being an index of a first non-zero bit determined by the scanning; performing a logical AND operation on a second pair of operands to obtain a second intermediate result; shifting the second intermediate result by a second shift amount based on a first operand of the second pair of operands; adding the shifted first intermediate result and the shifted second intermediate result; and outputting an output of the addition as a result of the masked shift-and-add operation.

17. 17. The computer processor of claim 16, wherein the first pair of operands and the second pair of operands are processed in parallel.

18. 17. The computer processor of claim 16, wherein the operands are provided in the set of registers.

19. 1. A computer-implemented method for arithmetic operations, comprising: dividing, by a processing unit, two input values ​​of the arithmetic operation into several separate portions, and performing the masked shift-and-add operations in parallel using two corresponding portions of the two input values ​​as part of a set of operands for the masked shift-and-add operations, wherein performing each masked shift-and-add operation comprises: performing a logical AND operation on a first pair of operands to obtain a first intermediate result; shifting the first intermediate result by a first shift amount based on a first operand of the first pair of operands, including scanning the first operand of the first pair of operands from least significant bit to most significant bit, and the first shift amount being an index of a first non-zero bit determined by the scanning; performing a logical AND operation on a second pair of operands to obtain a second intermediate result; shifting the second intermediate result by a second shift amount based on a first operand of the second pair of operands; adding the shifted first intermediate result and the shifted second intermediate result; and outputting the output of the addition as a result of the masked shift-and-add operation.

20. 20. The computer-implemented method of claim 19, wherein the first pair of operands and the second pair of operands are processed in parallel.

Images