Multi-layered non-volatile memory with fault and error mitigation.

Abstract

The present invention provides an apparatus, method, and storage system that offer proactive measures against the risk of potential defects in memory cells of word lines located at or near the boundaries of a hierarchy. [Solution] The device includes one or more control circuits configured to connect to a plurality of non-volatile memory cells in a NAND string coupled to a word line. A method by which the control circuit applies different programming schemes to different sets of word lines includes applying a first number of program pulses to a first set of word lines according to a first programming scheme and applying a second number of program pulses to a second set of word lines according to a second programming scheme. The second set of word lines includes one or more edge word lines or junction word lines, and the second number of program pulses is greater than the first number of program pulses.

Description

Technical Field

[0001] The technology relates to a non-volatile memory and a programming operation for programming non-volatile memory cells.

[0002] Semiconductor memories are widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. A semiconductor memory may include a non-volatile memory or a volatile memory. A non-volatile memory enables information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0003] The memory structure within a memory system typically includes many memory cells and various control lines. The memory structure may be three-dimensional. One type of three-dimensional structure has non-volatile memory cells arranged in vertical NAND strings. A NAND string includes memory cell transistors connected in series, a drain-side select gate at one end, and a source-side select gate at the other end. In some cases, a NAND memory is formed in two or more levels where the NAND strings extend through the levels. A block typically has many word lines within each level that supply voltage to the control gates of the memory cell transistors.

[0004] Non-volatile memory cells can be programmed with several data states to store data. Using more data states allows for the storage of more bits per memory cell. Some memory cells can be programmed with data states by accumulating electric charge in the memory cell. For example, the threshold voltage (Vt) of a NAND memory cell can be set to a target Vt by programming charge into a charge storage area, such as a charge trap layer. The amount of charge accumulated in the charge trap layer establishes the Vt of the memory cell. The cell can then be read by detecting the Vt.

[0005] Defects can occur within memory structures and affect memory operation. Some defects can be detected during testing. Potential defects may not be detected during testing and may appear later (e.g., when the memory system is in use). For example, a block or part of a block may become inaccessible (e.g., program and / or read failures). In some cases, a potential defect may result in a high error rate in data read from the word lines of a block. Mitigating failures and / or errors in non-volatile memory can be difficult. [Brief explanation of the drawing]

[0006] Elements with similar numbering refer to common components in different drawings. [Figure 1] A block diagram showing one embodiment of a storage system. [Figure 2A] This is a block diagram of one embodiment of a memory die. [Figure 2B] This is a block diagram of one embodiment of an integrated memory assembly. [Figure 3] An example of a part of the memory structure is shown. [Figure 4A] An example of a memory structure is shown. [Figure 4B] An example of a memory structure is shown. [Figure 4C]An example of a memory structure is shown. [Figure 4D] An example of a memory structure is shown. [Figure 4E] An example of a memory structure is shown. [Figure 4F] An example of a memory structure is shown. [Figure 5A] This shows the threshold voltage distribution. [Figure 5B] This shows the threshold voltage distribution. [Figure 6] This shows an example of applying a read voltage to a read memory cell. [Figure 7] This shows a portion of the 3D memory structure, including memory holes. [Figure 8] An example of a memory structure with two layers is shown. [Figure 9] An example of a two-tiered memory structure with misalignment is shown. [Figure 10A] Examples of two-layer and three-layer NAND strings are shown. [Figure 10B] Examples of two-layer and three-layer NAND strings are shown. [Figure 11A] Examples of programming using the first and second programming methods are shown below. [Figure 11B] Examples of programming using the first and second programming methods are shown below. [Figure 12A] Examples of programming using the first and second programming methods are shown below. [Figure 12B] Examples of programming using the first and second programming methods are shown below. [Figure 13] This example shows a method that involves programming word lines using different programming methods. [Figure 14] This example shows a method that involves applying different programming schemes to different sets of word lines. [Modes for carrying out the invention]

[0007] This specification discloses techniques for mitigating failures and errors that may occur due to potential defects in multilayer NAND memory structures. In some cases, certain word lines may be more susceptible to potential defects that may appear after some use. For example, as the number of program erase cycles increases and wear occurs, potential defects may appear. For example, the voltage applied during program, read, and / or erase operations may contribute to the manifestation of potential defects. Identifying word lines at risk may enable mitigation actions to be taken. For example, one or more word lines near junctions or interfaces between layers of a multilayer structure may be at high risk of being affected by potential defects, including failures (e.g., failures in reading and / or programming of a block or part of a block) and errors (e.g., a high error rate in data from some word lines of a block). In some cases, program operations targeting such high-risk word lines may be adapted to mitigate problems associated with potential defects. For example, word lines at certain locations within the layers of a multilayer structure may be at higher risk than other word lines, and the program scheme may be adapted to reduce the risk of such defects manifesting (e.g., as failures and / or errors). Word lines in the middle or near the middle of a hierarchy may be programmed using a first programming scheme, while boundary word lines may be programmed using a second programming scheme that uses more program pulses, which may have lower voltage and / or shorter duration than the first programming scheme. Boundary word lines may include junction word lines (e.g., one or more word lines on either side of a junction between hierarchies) and / or edge word lines (e.g., one or more word lines at the lower edge of a block).

[0008] Aspects of the technology address technical problems related to potential defects, including read failures, write failures, and / or high error rates. Aspects of the technology provide technical solutions that include using different program schemes adapted to different word lines according to the word line location within each hierarchy (e.g., using different program schemes for junction / edge word lines and non-junction / edge word lines).

[0009] Figure 1 is a block diagram of one embodiment of a storage system 100 capable of carrying out the technology described herein. In one embodiment, the storage system 100 is a solid-state drive ("SSD"). The storage system 100 may be a memory card, a USB drive, or another type of storage system. The proposed technology is not limited to any one type of storage system. The storage system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smartphone, tablet, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100 but is connected to the storage system 100. In other embodiments, the storage system 100 is incorporated into the host 102.

[0010] The components of the storage system 100 shown in Figure 1 are electrical circuits. The storage system 100 includes a memory controller 120 (or storage controller) connected to non-volatile storage 130 and local high-speed memory 140 (e.g., DRAM, SRAM, MRAM). The local memory 140 is non-temporary memory that may include volatile memory or non-volatile memory. The local high-speed memory 140 is used by the memory controller 120 to perform specific operations. For example, the local high-speed memory 140 may store a logic-to-physical address translation table ("L2P table").

[0011] Memory controller 120 is connected to host 102 and includes a host interface 152 for communication. In one embodiment, host interface 152 implements Non-Volatile Memory Express (NVMe) over Peripheral Component Interconnect Express (PCIe). Other interfaces such as Small Computer System Interface (SCSI) and Serial ATA (SATA) can also be used. Host interface 152 is also connected to a Network-on-Chip (NOC) 154. NOC is a communication subsystem on an integrated circuit. NOC can use synchronous and asynchronous clock domains or asynchronous logic that is not clocked. NOC technology applies networking theory and methods to on-chip communication, resulting in significant improvements over conventional bus and crossbar interconnects. NOC improves the scalability of a System-on-Chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wiring and links of NOC are shared by many signals. Since all links within NOC can operate simultaneously on different data packets, a high level of parallelism is achieved. Therefore, as the complexity of the integrated subsystem continues to increase, NOC provides improved performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wiring, shared buses, or segmented buses with bridges). In other embodiments, NOC 154 can be replaced by a bus.

[0012] Processor 156, ECC engine 158, memory interface

[160] , and local memory controller 164 are connected to and communicate with NOC 154. Local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., DRAM, SRAM, MRAM).

[0013] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding. In one embodiment, the ECC engine 158 is a software-programmed electrical circuit. For example, the ECC engine 158 may be a programmable processor. In another embodiment, the ECC engine 158 is a custom, dedicated hardware circuit without any software. In yet another embodiment, the functions of the ECC engine 158 are implemented by a processor 156.

[0014] Processor 156 performs various controller memory operations such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom dedicated hardware circuit without any software. Processor 156 also implements the conversion module as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is internally addressed to the storage system using physical addresses associated with one or more memory dies. However, the host system addresses various memory locations using logical addresses. This allows the host to assign data to contiguous logical addresses, while the storage system can freely store data as desired among the locations of one or more memory dies. To implement this system, memory controller 120 (e.g., the conversion module) performs address translation between the logical addresses used by the host and the physical addresses used by the memory die. One exemplary implementation is to maintain a table (i.e., the L2P table described above) that identifies the current translation between logical and physical addresses. Entries in the L2P table can include identification of the logical address and the corresponding physical address. Tables from logical addresses to physical addresses (or L2P tables) include the word "table", but they do not necessarily have to be literal tables. Rather, tables from logical addresses to physical addresses (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all of the L2P table. In such cases, the entire set of L2P tables is stored in storage 130, and a subset of the L2P tables is cached in local high-speed memory 140 (L2P cache).

[0015] The memory interface 160 communicates with the non-volatile storage 130. In one embodiment, the memory interface provides a toggle-mode interface. Other interfaces may also be used. In some exemplary implementations, the memory interface 160 (or another part of the memory controller 120) implements a scheduler and buffers for sending data to and receiving data from one or more memory dies.

[0016] In one embodiment, the non-volatile storage 130 includes one or more memory dies. Figure 2A is a functional block diagram of one embodiment of a memory die 200 comprising non-volatile storage. Each of the one or more memory dies of the non-volatile storage 130 may be implemented as the memory die 200 in Figure 2A. The components shown in Figure 2A are electrical circuits. The memory die 200 includes a memory structure 202 (e.g., a memory array) which may include non-volatile memory cells (also called non-volatile storage cells), as will be described in more detail below. The array terminal lines of the memory structure 202 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations may also be implemented. The memory die 200 includes a row control circuit 220, the output of which is connected to each word line of the memory structure 202. The row control circuit 220 receives a group of M row address signals and one or more different control signals from the system control logic 260 and may typically include circuits such as a row decoder 222, an array driver 224, and a block selection circuit 226 for both read and write (programming) operations. The row control circuit 220 may also include a read / write circuit. The memory die 200 also includes a column control circuit 210 which includes a read / write circuit 225. The read / write circuit 225 may include a sense amplifier and a data latch. The input and output of the sense amplifier are connected to the respective bit lines of the memory structure 202. Although only a single block is shown for the memory structure 202, the memory die may include multiple arrays that can be accessed individually. The column control circuit 210 receives a group of N column address signals and one or more different control signals from the system control logic 260 and may typically include circuits such as a column decoder 212, an array terminal receiver or driver circuit 214, a block selection circuit 216, and a read / write circuit, and an I / O multiplexer.

[0017] The system control logic 260 receives data and commands from the memory controller 120 and provides output data and status to the host. In some embodiments, the system control logic 260 (including one or more electrical circuits) includes a state machine 262 that provides die-level control of memory operation. In one embodiment, the state machine 262 is programmable by software. In other embodiments, the state machine 262 does not use software and is fully implemented in hardware (e.g., electrical circuits). In yet another embodiment, the state machine 262 is replaced by a microcontroller or microprocessor, which is either on or off the memory chip. The system control logic 260 may also include a power control module 264 that controls the power and voltage supplied to the rows and columns of the memory structure 202 during memory operation. The system control logic 260 includes storage 266 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating the memory structure 202.

[0018] Commands and data are transferred between the memory controller 120 and the memory die 200 via the memory controller interface 268 (also called the "communication interface"). The memory controller interface 268 is an electrical interface for communicating with the memory controller 120. Examples of the memory controller interface 268 include a toggle-mode interface and an open NAND flash interface (ONFI). Other I / O interfaces can also be used.

[0019] In some embodiments, all elements of the memory die 200, including the system control logic 260, may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on a die different from the die containing the memory structure 202.

[0020] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, where multiple memory levels are formed on a single substrate such as a wafer. The memory structure may include any type of non-volatile memory monolithically formed on one or more physical levels of memory cells having active areas located on a silicon (or other type) substrate. In one example, the non-volatile memory cells include a vertical NAND string with a charge trap layer.

[0021] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are floating-gate NAND flash memory cells. Other types of memory cells (e.g., NOR flash memory) can also be used.

[0022] The exact type of memory array architecture or memory cell included in the memory structure 202 is not limited to the examples given above. Many different types of memory array architectures or memory technologies can be used to form the memory structure 202. No specific non-volatile memory technology is required for the purposes of the newly claimed embodiments proposed herein. Other examples of technologies suitable for the memory cells of the memory structure 202 include ReRAM memory (resistive random-access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), etc. Examples of technologies suitable for the memory cell architecture of the memory structure 202 include two-dimensional arrays, three-dimensional arrays, crosspoint arrays, stacked two-dimensional arrays, vertical bit-line arrays, etc.

[0023] An example of a ReRAM crosspoint memory includes a reversible resistive switching element arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. Conductive bridge memory elements are sometimes called programmable metallization cells. Conductive bridge memory elements can be used as state change elements based on the physical rearrangement of ions in a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one of which is relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature rises, the mobility of ions also increases, reducing the programming threshold of the conductive bridge memory cell. Thus, conductive bridge memory elements can have a wide programming threshold with respect to temperature.

[0024] Another example is magnetoresistive random-access memory (MRAM), which stores data using magnetic storage elements. The element is formed from two ferromagnetic layers, each capable of holding a magnetization separated by a thin insulating layer. One of the two layers is a permanent magnet set to a specific polarity, and the magnetization of the other layer can be changed to match the magnetization of an external magnetic field in order to store the memory. The memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is positioned perpendicular to each other and parallel to the cell, one above the cell and one below the cell, between a pair of write lines. When current passes through them, an induced magnetic field is generated. Embodiments of MRAM-based memory are described in more detail below.

[0025] Phase-change memory (PCM) utilizes the inherent behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of germanium atoms using a laser pulse (or a light pulse from another source). Thus, the programming input is a laser pulse. The memory cell can be suppressed by preventing the memory cell from receiving light. In other embodiments of PCM, the memory cell is programmed by a current pulse. Note that the use of “pulse” as herein does not require a square wave and includes (continuous or discontinuous) oscillations or bursts of sound, current, voltage, light, or other waves. Individual selectable memory cells or these memory elements within a bit may include further series elements, such as an obonic threshold switch or a metal-insulating substrate, which is a selector.

[0026] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory configuration, or material composition, but rather cover many related memory structures within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0027] The elements in Figure 2A can be grouped into two parts: (1) the memory structure 202 and (2) the peripheral circuitry, which includes all the other components shown in Figure 2A. A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die of the storage system 100 allocated to the memory structure 202. However, this reduces the area of ​​the memory die available for the peripheral circuitry. This can impose very strict limitations on the elements of these peripheral circuits. For example, the need to fit the sensing amplifier circuitry within the available area can be a significant constraint on the sensing amplifier design architecture. With respect to the system control logic 260, the reduction in area availability can limit the available functions that can be implemented on-chip. Therefore, the fundamental trade-off in the design of the memory die for the storage system 100 is the amount of area allocated to the memory structure 202 versus the amount of area allocated to the peripheral circuitry.

[0028] Another area where the memory structure 202 and peripheral circuits often conflict lies in the processing involved in forming these areas, as these areas often involve different processing techniques and involve trade-offs in having different techniques on a single die. For example, if the memory structure 202 is NAND flash, it is an NMOS structure, but the peripheral circuits are often CMOS-based. For example, elements such as sensing amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in system control logic 260 often use PMOS devices. The processing operations for manufacturing CMOS dies differ in many ways from the processing operations optimized for NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures (see, for example, Figure 4) can particularly benefit from special processing operations.

[0029] To overcome these limitations, the embodiments described below allow the elements of Figure 2A to be separated onto separately formed dies, which are then joined together. More specifically, the memory structure 202 can be formed on a single die (called a memory die), and some or all of the peripheral circuit elements, including one or more control circuits, can be formed on a separate die (called a control die). For example, the memory die may be formed solely from memory elements such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or an array of memory cells of other memory types. Some or all of the peripheral circuits, even if they include elements such as decoders and sense amplifiers, can be moved to a separate control die. This allows each memory die to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without having to worry about CMOS elements moved onto a control die that can be optimized for CMOS processing. This allows for more space for peripheral elements and can incorporate additional capabilities that could not be easily incorporated when limited to the margins of the same die holding the memory cell array. Subsequently, the two dies can be joined to each other in a joined multi-die memory circuit, with the array on one die connected to the peripheral elements on the other die. The following focuses on a joined memory circuit with one memory die and one control die, but other embodiments can use more dies, such as two memory dies and one control die.

[0030] Figure 2B shows an alternative arrangement to the arrangement in Figure 2A, which may be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B shows a functional block diagram of one embodiment of an integrated memory assembly 207. One or more integrated memory assemblies 207 may be used to implement non-volatile storage 130 of a storage system 100. The integrated memory assembly 207 includes two types of semiconductor dies (or more simply, “dies”). The memory structure die 201 includes a memory structure 202. The memory structure 202 includes non-volatile memory cells. The control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, the control die 211 is configured to connect to the memory structure 202 within the memory structure die 201. In some embodiments, the memory structure die 201 and the control die 211 are bonded together.

[0031] Figure 2B shows an example of peripheral circuits, including control circuits, that are coupled to a memory structure 202 formed within a memory structure die 201 or formed within a control die 211. Common components are labeled as in Figure 2A. The system control logic 260, row control circuit 220, and column control circuit 210 are located within the control die 211. In some embodiments, all or part of the column control circuit 210 and all or part of the row control circuit 220 are located on the memory structure die 201. In some embodiments, some of the circuits within the system control logic 260 are located on the memory structure die 201.

[0032] The system control logic 260, row control circuit 220, and column control circuit 210 may be formed by a common process (e.g., a CMOS process), and as a result, additional elements and functions, such as ECC, which are more typically found on the memory controller 120, may require little or no additional process steps (i.e., the same process steps used to manufacture the memory controller 120 may also be used to manufacture the system control logic 260, row control circuit 220, and column control circuit 210). Therefore, moving such circuitry from a die such as the memory structure die 201 may reduce the number of steps required to manufacture such a die, while adding such circuitry to a die such as the control die 211 may not require many additional process steps. The control die 211 is sometimes called a CMOS die because it uses CMOS technology to implement some or all of the control circuits 260, 210, and 220.

[0033] Figure 2B shows a column control circuit 210, which includes a read / write circuit 225 on a control die 211 coupled to a memory structure 202 on a memory structure die 201 via an electrical path 206. For example, the electrical path 206 can provide electrical connections between a column decoder 212, a driver circuit 214, a block selection circuit 216, and the bit lines of the memory structure 202. The electrical path can extend from the column control circuit 210 in the control die 211 through pads on the control die 211 bonded to corresponding pads on the memory structure die 201 connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path in the electrical path 206, which includes a pair of bond pads connected to the column control circuit 210. Similarly, a row control circuit 220, which includes a row decoder 222, an array driver 224, and a block selection circuit 226, is coupled to the memory structure 202 via an electrical path 208. Each electrical path 208 may correspond to a word line, a dummy word line, or a selection gate line. An additional electrical path may be provided between the control die 211 and the memory structure die 201.

[0034] For the purposes of this specification, the terms “control circuit” or “one or more control circuits” may include any one or any combination of the following: the memory controller 120, the state machine 262, the power control module 264, the system control logic 260, all or part of the row control circuit 220, all or part of the column control circuit 210, the read / write circuit 225, the sense amplifier, the microcontroller, the microprocessor, and / or other similar functional circuits. A control circuit may include hardware only, or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FPGA, ASIC, integrated circuit, or other type of circuit.

[0035] For the purposes of this specification, the term “apparatus” may include, but is not limited to, one or more of the storage system 100, memory controller 120, storage 130, memory die 200, integrated memory assembly 207, and / or control die 211.

[0036] Figure 3 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array / structure that may comprise a memory structure 202 including multiple non-volatile memory cells arranged as a vertical NAND string. For example, Figure 3 shows a portion of one block 400 of the memory. The illustrated structure includes a set of bit lines BL positioned above a stack 401 of alternating dielectric and conductive layers. For illustrative purposes, one of the dielectric layers is marked as D, and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric and conductive layers may vary based on specific implementation requirements. In one embodiment, the alternating dielectric and conductive layers are divided into four (or a different number) regions (e.g., subblocks) by isolation regions IR. Figure 3 shows one isolation region IR separating two subblocks. Below the alternating dielectric and word line layers are source line layers SL. Memory holes are formed within the stack of alternating dielectric and conductive layers. For example, one of the memory holes is marked as MH. Note that in Figure 3, the dielectric layers are shown as see-through so that the reader can see the memory holes arranged in a stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material containing charge trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. Further details of the three-dimensional monolithic memory array including the memory structure 202 are provided below.

[0037] Figure 4A is a block diagram illustrating one exemplary organization of a memory structure 202 divided into two planes 302 and 304. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, a block of memory cells is a unit of erasure; that is, all memory cells in a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize the memory structure 202 to enable signaling and selection circuits. In some embodiments, a block represents a group of connected memory cells such that the memory cells in the block share a common set of word lines.

[0038] Figures 4B to 4F show exemplary three-dimensional ("3D") NAND structures that correspond to the structure in Figure 3 and can be used to implement the memory structure 202 in Figure 2A or Figure 2B. Figure 4B is a block diagram showing a top view of a portion of one block of the memory structure 202. The portion of the block shown in Figure 4B corresponds to portion 306 of block 2 in Figure 4A. In one embodiment, the memory array has many layers. However, Figure 4B shows only the top layer.

[0039] Figure 4B shows several circles representing vertical columns. Each vertical column contains multiple selection transistors (also called select gates or selection gates) and multiple memory cells. In one embodiment, each vertical column implements a NAND string. For example, Figure 4B shows vertical columns 422, 432, 442, and 452. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. Further details of the vertical columns are provided below. The block shown in Figure 4B extends beyond the shown portion, so the block contains more vertical columns than shown in Figure 4B.

[0040] Figure 4B also shows a set of bit lines 415, including bit lines 411, 412, 413, 414, ... 419. Since only a portion of the block is shown in Figure 4B, 24 bit lines are shown. It is conceivable that more than 24 bit lines are connected to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate its connection to a single bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, and 452.

[0041] The block shown in Figure 4B includes a set of local interconnects 402, 404, 406, 408, and 410 that connect various layers to source lines below the vertical columns. Local interconnects 402, 404, 406, 408, and 410 also work to divide each layer of the block into four regions. For example, the upper layer shown in Figure 4B is divided into regions 420, 430, 440, and 450 called fingers. In the layers of the block that implement the memory cells, the four regions are called word line fingers, separated by local interconnects. In one embodiment, the word line fingers on the common level of the block are connected to each other to form a single word line. In another embodiment, the word line fingers on the same level are not connected to each other. In one exemplary implementation, bit lines are connected to only one vertical column each of regions 420, 430, 440, and 450. In this implementation, each block has 16 active columns, and each bit line connects to 4 rows within each block. In one embodiment, all 4 rows connected to a common bit line are connected to the same word line (via different word line fingers on the same level that are connected together). Thus, the system uses source-side selection lines and drain-side selection lines to select one (or another subset) of the 4 memory items to be used for memory operations (programming, verifying, reading, and / or erasing).

[0042] Figure 4B shows that each region has 4 rows of vertical columns, 4 regions, and 16 rows of vertical columns within a block, although the exact numbers are illustrative for an exemplary implementation. Other embodiments may include more or fewer regions per block, more or fewer rows of vertical columns per region, and more or fewer rows of vertical columns per block.

[0043] Figure 4B also shows vertical columns arranged in a staggered pattern. In other embodiments, different patterns of staggered arrangements can be used. In some embodiments, the vertical columns are not arranged in a staggered pattern.

[0044] Figure 4C shows one embodiment of stack 435, illustrating a cross-sectional view along line AA in Figure 4B. In addition to data word line layers WLL0 to WLL95, there are two SGD layers (SGD0, SDG1), two SGS layers (SGS0, SGS1), and six dummy word line layers DWLD0, DWLD1, DWLM1, DWLM0, DWLS0, and DWLS1. Each NAND string has a drain-side selection transistor in the SGD0 layer and a drain-side selection transistor in the SGD1 layer. During operation, the same voltage may be applied to each layer (SGD0, SGD1), resulting in each transistor's control terminal receiving the same voltage. Each NAND string has a source-side selection transistor in the SGS0 layer and a drain-side selection transistor in the SGS1 layer. During operation, the same voltage may be applied to each layer (SGS0, SGS1), resulting in each transistor's control terminal receiving the same voltage. Dielectric layers DL0 to DL106 are also shown. You can use more or less SGD, SGS, and DWL.

[0045] Cell memory cells 432 and 434 are shown within a multilayer stack. The stack includes a substrate 303, an insulating film 250 on the substrate, and a portion of the source line SL. A portion of the bit line 414 is also shown. Note that the NAND string 484 is connected to the bit line 414. The NAND string 484 has a source end 439 at the bottom of the stack and a drain end 438 at the top of the stack. The source end 439 is connected to the source line SL. A conductive via 441 connects the drain end 438 of the NAND string 484 to the bit line 414. Local interconnects 404 and 406 from Figure 4B are also shown.

[0046] Stack 435 is divided into three vertical subblocks (VSB0, VSB1, VSB2). Vertical subblock VSB0 includes WLL0 to WLL31. The following layers can also be considered part of vertical subblock VSB0 (SGS0, SGS1, DWLS0, DWLS1). Vertical subblock VSB1 includes WLL32 to WLL63. Vertical subblock VSB2 includes WLL64 to WLL95. The following layers can also be considered part of vertical subblock VSB2 (SGD0, SGD1, DWLD0, DWLD1). Each NAND string has a set of data memory cells in each of the vertical subblocks. The dummy word line layer DMLM0 is located between vertical subblock VSB0 and vertical subblock VSB1. The dummy word line layer DMLM1 is located between vertical subblock VSB1 and vertical subblock VSB2. The dummy word line layer has dummy memory cell transistors that can be used to electrically isolate a first set of memory cell transistors in the memory string (e.g., corresponding to vertical subblock VSB0 word lines WLL0 to WLL31) from a second set of memory cell transistors in the memory string (e.g., corresponding to vertical subblock VSB1 word lines WLL32 to WLL63) during memory operations (e.g., erase operations or programming operations).

[0047] Figure 4D shows an alternative diagram of the SG layer and word line layer of stack 435 in Figure 4C. The SGD layer SGD0 and SGD0 (drain-side SG layer) each contain parallel rows of SG lines associated with the drain side of the set of NAND strings. For example, SGD0 includes drain-side SG regions 420, 430, 440, and 450, which are consistent with Figure 4B.

[0048] Below the SGD layer is a drain-side dummy word line layer. Each dummy word line layer, in one approach, represents a word line and is connected to a set of dummy memory cells at a given height in the stack. For example, DWLD0 includes word line layer regions 451, 453, 455, and 457. Dummy memory cells, also called non-data memory cells, do not store data and are unsuitable for storing data, while data memory cells are suitable for storing data. Furthermore, the Vth of dummy memory cells is generally fixed at the time of manufacture or can be periodically adjusted, while the Vth of data memory cells changes more frequently, for example, during erasure and programming operations of data memory cells.

[0049] Below the dummy word line layer are the data word line layers. For example, WLL95 includes word line layer regions 471, 472, 473, and 474.

[0050] Below the data word line layer is the source-side dummy word line layer.

[0051] Below the source-side dummy word line layer is the SGS layer. The SGS layers SGS0 and SGS1 (source-side SG layers) each contain parallel rows of SG lines associated with the source side of the set of NAND strings. For example, SGS0 contains source-side SG lines 475, 476, 477, and 478. Each SG line can be controlled independently in one approach, or they can be connected and controlled in common.

[0052] Figure 4E shows a diagram of region 445 in Figure 4C. Data memory cell transistors 520 and 521 are located above dummy memory cell transistor 522. Below dummy memory cell transistor 522 are data memory cell transistors 523 and 524. For example, atomic layer deposition can be used to deposit several layers along the sidewall (SW) of the memory hole 444 and / or within each word line layer. For example, each row (e.g., pillars formed by the material within the memory hole) may include a blocking oxide / blocking high-k material 470, a charge trap layer or film 463 such as SiN or other nitride, a tunnel layer 464, a polysilicon body or channel 465, and a dielectric core 466. The word line layers may include a conductive metal 462 such as tungsten as a control gate. Alternatively, other metals can also be used as control gates. For example, control gates 490, 491, 492, 493, and 494 are provided. In this example, all layers except the metals are located within the memory hole. In other approaches, a portion of the layer may be within the control gate layer. Additional pillars are similarly formed within different memory holes. The pillars can form columnar active areas (AAs) of the NAND string.

[0053] When a data memory cell transistor is programmed, electrons accumulate in a portion of the charge trap layer associated with the data memory cell transistor. These electrons are drawn from the channel through the tunnel layer into the charge trap layer. The Vth of the data memory cell transistor increases proportionally to the amount of accumulated charge. During the erase operation, the electrons return to the channel.

[0054] Non-data transistors (e.g., selection transistors, dummy memory cell transistors) may also include a charge trap layer 463. In Figure 4E, the dummy memory cell transistor 522 includes a charge trap layer 463. Therefore, the threshold voltage of at least some non-data transistors may be adjusted by accumulating electrons in or removing electrons from the charge trap layer 463. Not all non-data transistors need to have an adjustable Vth. For example, the charge trap layer 463 does not need to be present in all selection transistors.

[0055] Each memory hole may be filled with multiple annular layers, including a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. The core region of each memory hole is filled with a body material, and the multiple annular layers are located between the core region and the WLL in each memory hole.

[0056] In some cases, the tunnel layer 464 may include multiple layers, such as an oxide-nitride-oxide configuration.

[0057] Figure 4F is a schematic diagram of a portion of the memory shown in Figures 3 to 4E. Figure 4F shows the physical word lines WLL0 to WLL95 running across the entire block. The structure of Figure 4F corresponds to portion 306 within block 2 in Figures 4A to 4E, including bit lines 411, 412, 413, 414, ... 419. Within the block, each bit line is connected to four NAND strings. Drain-side selection lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings connects to the relevant bit line. Source-side selection lines SGS0, SGS1, SGS2, and SGS3 are used to determine which of the four NAND strings connects to the common source line. The block can also be thought of as being divided into four horizontal subblocks HSB0, HSB1, HSB2, and HSB3. Horizontal subblock HSB0 corresponds to the vertical NAND string controlled by SGD0 and SGS0, horizontal subblock HSB1 corresponds to the vertical NAND string controlled by SGD1 and SGS1, horizontal subblock HSB2 corresponds to the vertical NAND string controlled by SGD2 and SGS2, and horizontal subblock HSB3 corresponds to the vertical NAND string controlled by SGD3 and SGS3.

[0058] Memory cells in a memory system can be erased, programmed, and read. After a successful programming process, the threshold voltage of a memory cell should, as necessary, fall within one or more distributions of threshold voltages for programmed memory cells, or within the distribution of threshold voltages for erased memory cells. Figure 5A is a graph of threshold voltage versus number of memory cells, showing an example of the threshold voltage distribution of a memory array when each memory cell stores one bit of data per memory cell. Memory cells that store one bit of data per memory cell are called single-level cells ("SLC"). Data stored in an SLC memory cell is called SLC data. Therefore, SLC data contains one bit per memory cell. Data stored as one bit per memory cell is SLC data. Figure 5A shows two threshold voltage distributions E and P. Threshold voltage distribution E corresponds to the erased data state. Threshold voltage distribution P corresponds to the programmed data state. Therefore, a memory cell with a threshold voltage in threshold voltage distribution E is in the erased data state (e.g., erased). Therefore, a memory cell with a threshold voltage in threshold voltage distribution P is in the programmed data state (e.g., programmed). In one embodiment, an erased memory cell stores the data "1", and a programmed memory cell stores the data "0". Figure 5A shows the read reference voltage Vr. By testing whether the threshold voltage of a given memory cell is higher or lower than Vr (e.g., by performing one or more sense operations), the system can determine whether a memory cell is erased (state E) or programmed (state P). Figure 5A also shows the verification reference voltage Vv. In some embodiments, when programming memory cells to data state P, the system tests in a program verification (or "verification") operation whether those memory cells have a threshold voltage greater than or equal to Vv. In some embodiments, verification is not performed during SLC programming.

[0059] A memory cell configured to store multiple bits per memory cell is called a multilevel cell ("MLC"). Data stored in an MLC memory cell is called MLC data. Therefore, MLC data contains multiple bits per memory cell. Data stored as multiple bits per memory cell is MLC data. In the exemplary embodiment of Figure 5B, each memory cell stores 3 bits of data. Other embodiments may use other data capacities per memory cell (e.g., 2, 4, or 5 bits of data per memory cell). Memory cells may be configured for SLC or MLC storage of data. In some cases, a block of non-volatile memory cells may be configured for SLC data storage at one time and for MLC data storage at another time.

[0060] Figure 5B shows eight threshold voltage distributions corresponding to eight data states, each storing three bits per cell. The first threshold voltage distribution (data state) Er represents an erased memory cell. The other seven threshold voltage distributions (data states) A-G represent programmed memory cells and are therefore also called programmed states. Each threshold voltage distribution (data state) corresponds to a predetermined value of a set of data bits. The specific relationship between the data programmed into a memory cell and the threshold voltage level of the cell depends on the data encoding scheme employed in the cell. In one embodiment, data values ​​are assigned to threshold voltage ranges using Gray code assignment such that only one bit is affected if the memory threshold voltage is incorrectly shifted to its adjacent physical state. In one embodiment, the number of memory cells in each state is approximately the same.

[0061] Figure 5B shows seven read reference voltages VrA, VrB, VrC, VrD, VrE, VrF, and VrG for reading data from memory cells. By testing whether the threshold voltage of a given memory cell is higher or lower than the seven read reference voltages (e.g., performing a sense operation), the system can determine which data state (i.e., A, B, C, D, ...) the memory cell is in. Figure 5B also shows several verification reference voltages. The verification voltages are VvA, VvB, VvC, VvD, VvE, VvF, and VvG. In some embodiments, when programming memory cells to data state A, the system tests whether those memory cells have a threshold voltage greater than or equal to VvA. If a memory cell has a threshold voltage greater than or equal to VvA, the memory cell is prohibited from further programming (locked out). Similar reasoning applies to other data states. In some embodiments, no verification is performed during MLC programming.

[0062] Each memory cell programmed according to the scheme shown in Figure 5B can store 3 bits of data, each bit associated with a logical page, using eight data states. A read operation can be directed to one or more logical pages of data. Read operations directed to different logical pages may perform reads at different read voltages (for example, it may not be necessary to perform the read step at all read voltages indicated in response to a read request directed to only one or two of the stored logical pages).

[0063] Figure 6 shows exemplary voltage signals for performing a read operation (plots 1400-1404). Voltage 1400 represents the voltage Vcgr applied to the control gate of a selected memory cell via the selected word line WLn to perform a read at three different read voltages (e.g., to retrieve data from one logical page). The control gate read voltage Vcgr (also called the “read voltage”) is set to VrF, VrD, and VrB. Sensing is performed between each value of Vcgr to determine the data for the logical page. Voltage 1401 represents the read path voltage (Vpass) applied to the unselected word lines (e.g., WL0-WLn-1 and WLn+1-WL95). Vsgd represents the SGD voltage 1402, set to a high level provided to the SGD transistor selected in the conductive state (e.g., SGD0). Vbl 1403 represents the bit line voltage applied to bit lines such as bit lines 411-419, set to a level such as 0.5V as part of the sensing process. Vsl 1404 indicates the source line voltage applied to the SL, which can be set to a small positive voltage in one approach.

[0064] At time t0, the unselected word line voltages 1401, Vsgd 1402, Vbl 1403, and Vsl 1404 are ramped up to their respective target voltages. Then, at time t1, the selected word line voltage Vcgr 1400 is ramped up to the first read voltage VrF, and the first read step is performed to identify which memory cells are on / off at the VrF applied to their control gates. Then, at time t2, the selected word line voltage Vcgr 1400 is ramped down to the second read voltage VrD, and the second read step is performed to identify which memory cells are on / off at the VrD applied to their control gates. Then, at time t3, the selected word line voltage Vcgr 1400 is ramped down to the third read voltage VrB, and the third read step is performed to identify which memory cells are on / off at the VrB applied to their control gates. Subsequently, at time t4, the selected word line voltage Vcgr 1400 is ramped down to the post-read voltage (e.g., 0 volts). While the example in Figure 6 shows a sequence of three different read voltages for reading a single logic page, other examples may use other sequences with a different number of read voltages. Read operations, such as the one shown in Figure 6, can be affected by potential defects, resulting in read failures or data being read with a higher error rate than desired (e.g., requiring significant resources for decoding).

[0065] Figures 4A to 4F show simplified examples of 3D NAND memory structures, but some memory structures may differ from the examples shown in ways that can affect memory operation (for example, operations including read operations as shown in Figure 6 and / or program operations as shown in Figures 5A to 5B). For example, Figure 4E shows memory holes 444 with uniform diameter, but in some cases the diameter of the memory holes may contain some degree of non-uniformity, which can give different characteristics to non-volatile memory cells at different levels (e.g., along different word lines). In some cases, non-volatile memory cells in a particular word line may be more susceptible to certain failure modes than non-volatile memory cells in other word lines.

[0066] Figure 7 shows a portion of a memory hole 444 (as previously shown in Figure 4E) containing three memory cells 910a to 910c, each coupled to three word lines WLx-1 to WLx+1, respectively. Figure 9 shows that the diameter of the memory hole 444 is not uniform. For example, the memory hole has a first diameter d1 at the lowermost point shown (bottom of WLx-1) while having a second diameter d2 at the highest point shown (top of WLx+1). Such non-uniform shapes can result from the etching process used to form the memory holes. Non-uniform memory hole diameters can result in non-uniform memory cell characteristics. The diameter of the memory holes may vary according to a pattern (e.g., increasing from bottom to top) which can allow measures to be taken to address the resulting different memory cell characteristics (e.g., different characteristics at different levels). Other physical dimensions or material properties may differ from layer to layer within the 3D memory structure, which can cause non-uniformity between memory cells in different layers.

[0067] In some memory structures, memory holes are formed in multiple layers such that the taper of the memory holes with increasing depth is not continuous (for example, the diameter of the memory holes may be discontinuously tapered at each layer at the junctions between layers). Figure 8 shows an example of a 3D NAND memory structure including memory holes 1120 formed in two layers, namely the lower layer 1122 and the upper layer 1124, which are physically connected at a junction 1126 (interface). In each layer, the memory holes 1120 are tapered such that at the highest level shown (highest word line level WLm), the diameter d2 of the memory hole 1120 is greater than the diameter d1 at the lowest level shown (lowest word line WL0). This taper is non-uniform with discontinuities between WLn and WLn+1 where the layer interfaces along the junction 1126 are located. For example, the diameter of the memory hole 1120 at WLn may be d2, and the diameter at WLn+1 may be d1. In some cases, memory cells near the bottom of a memory hole may be more susceptible to program and / or read failures. For example, memory cells near the bottom of the lower layer 1122 (e.g., memory cells of one or more word lines including WL0) and memory cells near the bottom of the upper layer 1124 (e.g., one or more word lines including WLn+1) may have an increased risk of program and / or read failures due to potential defects or other reasons.

[0068] In some cases, a certain degree of misalignment may occur between layers. For example, the memory hole portions of each layer may be formed by separate patterning and etching processes, with the memory hole pattern of one layer aligned with the pattern of the previous layer to enable continuity of memory holes. However, the alignment may be imperfect, which can affect the memory hole structure and lead to defects, including potential flaws.

[0069] Figure 9 shows an example of a memory hole 1120, which includes an upper memory hole portion 1120a formed in the upper layer 1124 and a lower memory hole portion 1120b formed in the lower layer 1122. Figure 9 shows a misalignment between the upper memory hole portion 1120a and the lower memory hole portion 1120b that may affect the characteristics of the memory structure. For example, word lines in one or more layers near the junction 1126 between the upper layer 1124 and the lower layer 1122 may be affected by such misalignment (e.g., short circuits or high leakage between word lines and / or between memory holes and word lines). Such word lines may be prone to program and / or read failures. For example, memory cells in one or more junction word lines on both sides of the interface between layers (e.g., memory cells in word lines including WLn and WLn+1) may have an increased risk of program and / or read failures.

[0070] In some cases, defects may be detected during testing, and the memory die (or a portion thereof) may be designated as unacceptable and discarded (e.g., not to be used to store user data). In some cases, defects may be latent for a memory cell to pass testing and be usable to store user data. Subsequently, such defects may manifest, resulting in data being unreadable or readable with a high error rate. Correction of high-error-rate data may be possible (e.g., error correction codes (ECC), exclusive OR (XOR), and / or other redundancies may enable recovery of unreadable or high-error-rate-readable data). However, such recovery may require considerable time and / or resources, and it may be preferable to maintain user data under lower error-rate conditions (e.g., conditions that do not require considerable time and resources to read and transmit to a host).

[0071] Aspects of the technology address technical problems related to read failures, program failures, high error rates, and / or other problems that may arise along specific word lines of 3D NAND memory (e.g., due to potential defects). Aspects of the technology provide technical solutions to such problems, including selectively applying proactive measures to mitigate or eliminate problems associated with specific word lines.

[0072] Memory cells in word lines located at or near hierarchical boundaries may be at risk of potential defects. Boundary word lines may include word lines close to inter-hierarchical junctions ("junction word lines"), such as WLn and WLn+1 adjacent to junction 1126. For example, WLn may be the topmost word line of hierarchical 1122, and WLn+1 may be the bottommost word line of hierarchical 1124. In some cases, two or more word lines on either side of a junction may be considered junction word lines. Boundary word lines may also include word lines at the edge of a hierarchy, such as WL0 in Figure 9, that are not close to a junction ("edge word lines"). Memory cells in junction word lines and edge word lines are examples of memory cells that may be subject to proactive measures, while memory cells in other word lines (e.g., non-junction / edge or intermediate word lines) may not be subject to proactive measures (for example, proactive measures are selectively applied to specific word lines identified as high-risk because they are close to hierarchical boundaries, such as inter-hierarchical junctions or hierarchical edges).

[0073] Figure 10A shows an example of a NAND string 1010 in a two-tier memory structure. The NAND string 1010 is connected to a common source (CelSrc) at the bottom via source selection gates SGS, SGSB, and source-side dummy word line WLDS. The lower tier, tier 1, includes word lines including edge word line 1012 and junction word line 1014. Edge word line 1012 may be the lowest data word line of tier 1 (e.g., WLDS may be a dummy word line that does not store data). Junction word line 1014 may be the highest data word line of tier 1 (e.g., DL1 may be a dummy word line that does not store data). The upper tier, tier 2, includes word lines including junction word line 1016 (e.g., the lowest data word line of tier 2). When accessing the memory cells of edge word line 1012 and junction word lines 1014 and 1016, preemptive measures may be used to reduce risk (e.g., the risk of potential defects appearing).

[0074] Figure 10B shows an example of a NAND string 1020 in a three-tier memory structure. The NAND string 1020 includes edge word lines 1012 and junction word lines 1014 and 1016, as shown in Figure 10A. In addition, the NAND string 1020 includes junction word lines 1022 and 1024 on both sides of the interface between tier 2 (the intermediate tier in this example) and tier 3 (the upper tier). Preemptive measures may be used to reduce the risk of errors when accessing memory cells of the edge word line 1012 and junction word lines 1014, 1016, 1022, and 1024. While the examples in Figures 10A and 10B show examples with two and three tiers, respectively, the embodiments of the technique are not limited to the examples shown and can be extended to any number of tiers.

[0075] Preemptive measures may be taken to reduce the risk of memory cell failure in certain word lines identified as high-risk word lines (e.g., boundary word lines including junction and / or edge word lines). Such measures may include one or more read, write, and / or erase methods that can reduce the risk (compared to methods used for other word lines not identified as high-risk, such as intermediate word lines).

[0076] In some cases, a program pulse can expose a memory cell to significant stress, potentially revealing a potential defect. Reducing such stress can reduce or delay the manifestation of potential defects and associated consequences (failures or high error rates). Figures 11A–12D show examples of schemes that include risk-reducing write schemes that may be used when programming memory cells in word lines identified as high risk. Figure 11A shows an example of applying a single programming pulse 710 to program a memory cell that uses two data states to store one bit of data per cell (as previously shown, for example, in Figure 5A). In this example, verification may not be necessary, and as a result, one pulse step and zero verification steps (1P0V) are sufficient to program the cell. Such a write scheme may be used to program SLC memory cells in NAND strings of a memory array.

[0077] The horizontal axis in Figure 11A represents time, and each trace is labeled according to the component to which the corresponding voltage is applied (voltage increases vertically). At time t0, the voltages ramp up from 0 volts to various target voltages. For example, the bit line ("BL") voltage ramps up from 0 volts to VDDSA (e.g., 2V). The selected gate drain ("SGD") voltage ramps up from 0 volts to VSGD (e.g., 2.5V) to turn on (conduct) the SGD transistor. The unselected word line ("WL") voltage ramps up from 0 volts to the pass voltage Vpass (e.g., 9V) to make the corresponding channel conductive. The selected WL voltage ramps up from 0 volts to the program voltage VPGM for a single pulse 710 to trigger programming. The selected gate source ("SGS") voltage is maintained at 0 volts to keep the SGS transistor off (non-conductive). The source voltage ("CELSRC") ramps up from 0 volts to VDDSA (e.g., 2.5 volts).

[0078] Subsequently, at time t1, the selected WL voltage ramps down from VPGM at the end of program pulse 710, while the other voltages remain at their previous levels. Then, at time t2, the BL, SGD, unselected WL, and other voltages, including the CELSRC voltage, ramp down.

[0079] The pulse 710 shown in Figure 11A can cause significant stress on memory cells, including high-risk memory cells. In some cases, the risk can be reduced by avoiding the programming scheme shown in Figure 11A when programming high-risk memory cells and using an alternative programming scheme.

[0080] Figure 11B shows an example of a risk reduction scheme that may be applied when programming memory cells on high-risk word lines (e.g., edge and / or junction word lines). For example, if a high-risk word line is selected, the selected word line may receive the voltage signal shown in Figure 11B (other components may receive the same voltage as shown in Figure 11A). In contrast, a non-high-risk word line may receive the selected word line signal (pulse 710) shown in Figure 11A.

[0081] Figure 11B shows n program pulses numbered p1 to pn that may be used to program a memory cell along a selected word line. In the illustrated example, all pulses have the same pulse height or program voltage Vmax, which may be the same as or different from the single pulse voltage in Figure 11A (e.g., lower than VPGM as shown in Figure 12B). In other examples, the pulses may have different pulse heights (e.g., non-uniform from pulse to pulse). At time t0, the first pulse p1 is started and ends at time t1'. The pulse width (from t0 to t1') may be significantly smaller than the pulse width (from t0 to t1) in Figure 11A. Then, at time t3, the second pulse p2 is started. The second pulse p2 and subsequent pulses may be identical to or different from the first pulse p1. The sequence of n pulses continues until the end of the final pulse pn at time tn. The number n may be any number greater than 1, for example, 2, 3, 4, 5, or more. Each individual pulse p1~pn may be narrower than the voltage pulse 710, but the combined width of all pulses p1~pn (time t0~tn) may be longer than that of pulse 710 (longer than the time t0~t1). By selectively applying the scheme in Figure 11B (for example, only to high-risk word lines), the increased time can be maintained at an acceptable level.

[0082] Figures 12A to 12B illustrate embodiments of the technique implemented in MLC memory (for example, as shown in Figure 5B, which stores more than one bit per memory cell using more than two data states).

[0083] Figure 12A shows a voltage signal containing multiple pulses applied to the control gate of a nonvolatile memory cell (e.g., applied to a selected word line) during an exemplary programmed operation. The horizontal axis represents the number of pulses in the range of 1 to m, and the vertical axis represents the programmed voltage. Voltages applied to other memory structure components (e.g., bit lines, selection lines, unselected word lines) may be similar to those shown in Figure 11A. During programmed operation, a programmed loop is executed for the selected word lines within the selection blocks in each plane. The programmed loop includes a programmed portion in which programmed pulses of the corresponding programmed voltage are applied to the selected word line, followed by a verification portion in which a verification signal is applied to the selected word line while one or more verification tests are performed on the associated memory cell. Each state other than the erased state is assigned a verification voltage used for state verification tests during programmed operation.

[0084] The voltage signal 1200 includes a series of program pulses at different program voltages, including an initial program pulse 1202 applied to the word line selected for programming. In this example, the voltage signal includes program pulses having corresponding program voltages whose amplitude increases stepwise up to the final program voltage Vfin applied in pulse m. This may be called incremental step pulse programming, where the program voltage starts at the initial program pulse 1202 at the initial level and increases stepwise in each successive program loop, for example, until the program operation is completed. A successful completion occurs when the threshold voltage of the selected memory cell reaches the verification voltage of the assigned data state.

[0085] The program operation can include a single programming pass (e.g., as shown in Figure 11A) or multiple programming passes (e.g., as shown in Figure 12A), each pass using, for example, incremental step pulse programming. In SLC memory where two data states are used, verification may not be necessary.

[0086] The verification signals in each program loop of the multi-pulse scheme, including the exemplary verification signal 1204, may include one or more verification voltages based on the assigned data states being verified for the program loop. The verification test may include lower assigned data states, then intermediate assigned data states, and then higher assigned data states as the program operation progresses. The exemplary verification signal shows three verification voltages for simplification.

[0087] The data that is programmed or read can be placed on a page. For example, with four data states, i.e., 2 bits per cell, the data of two logical pages can be stored together on one page. Exemplary encodings of the bits for states Er, A, B, and C are 11, 10, 00, and 01 in upper page (UP) bit / lower page (LP) bit format, respectively. Lower page reads may use VrA and VrC, and upper page reads may use VrB. With eight data states, i.e., 3 bits per cell, the data of three pages can be stored. Exemplary encodings of the bits for states Er, A, B, C, D, E, F, and G are 111, 110, 100, 000, 010, 011, 001, and 101, respectively.

[0088] In some cases, a method such as the one shown in Figure 12A may be used to program memory cells of a first set of word lines in a memory structure (e.g., intermediate word lines not near hierarchical boundaries), while a different method may be used to program memory cells of a second set of word lines in the same memory structure (e.g., high-risk word lines that may include edge word lines and / or junction word lines).

[0089] Figure 12B shows an example of a voltage signal 1220 that includes a series of voltage pulses used to program the memory cells of a second set of word lines (e.g., a set of word lines identified as high risk, such as edge and / or junction word lines). Pulses 1~m-1 may be identical to those in Figure 12A. However, in contrast to Figure 12A, pulse m-1 is followed by a series of pulses (numbered m~m+x) having a voltage Vmax (lower pulse height) lower than the voltage Vfin of pulse m. This can reduce the stress on the memory cells. Pulses m~m+x may also have a shorter duration than pulses 1~m-1 (and pulse m in Figure 12A). Figure 12B shows Vmax as being equal to the voltage of pulse m-1, but in other examples this is not the case (e.g., Vmax may be greater than or less than the voltage of pulse m-1). The total time for programming can increase (e.g., pulses m~m+x in Figure 12B may take longer than pulse m in Figure 12A). However, since this programming method is applied selectively, the overall programming time may not be significantly affected.

[0090] Figure 12B corresponds to replacing pulse m in Figure 12A with a series of x pulses having smaller pulse heights and widths, but in other examples, more than one pulse may be replaced by such smaller pulses. For example, two or more pulses in Figure 12A (e.g., pulses m and m-1, or pulse m~my, where y can be any number less than m) may be replaced by smaller pulses.

[0091] Embodiments of the technology may include applying different programming schemes to different word lines according to their respective positions within a hierarchy (e.g., applying different numbers of programming pulses, and / or pulses of different pulse heights and / or pulse widths). For example, a first number of programming pulses (e.g., one as in Figure 11A, or m as in Figure 12A) are applied to program the non-volatile memory cells of a first set of word lines to a target data state, and a second number of programming pulses (e.g., n as in Figure 11B, or a number greater than the first number, such as m+x as in Figure 12B) are applied to program the non-volatile memory cells of a second set of word lines. The second set of word lines may be selected according to their positions within their respective hierarchies. For example, the second set of word lines may include edge word lines (word lines at or near the bottom of the lowest hierarchy) and / or junction word lines (e.g., word lines at or near junctions between hierarchies, at or near the top or bottom of each hierarchy).

[0092] In the examples in Figures 11A to 12B, two different programming schemes are used depending on the word line position within each hierarchy (e.g., a first programming scheme for intermediate word lines and a second programming scheme for edge and junction word lines). In other examples, more than two programming schemes may be used. For example, junction word lines may be programmed using one programming scheme, while edge word lines may be programmed using a different programming scheme (e.g., in addition to the programming scheme used for non-edge / junction or intermediate word lines). Other position-dependent schemes may also be applied.

[0093] Figure 13 shows an example of a method for programming memory cells of multiple word lines (e.g., word lines in two or more layers of a NAND flash memory structure). The method includes making a determination 1330 of whether the current word line is a junction word line (e.g., located at or near a junction or interface between layers), and if so, configuring for the use of a junction word line programming scheme 1332 (e.g., using a lower voltage and / or an increased number of pulses of duration). If the current word line is not a junction word line, a determination 1334 is made of whether the current word line is an edge word line (e.g., at or near the bottom of the lowest layer), and if so, configuring for the use of an edge word line programming scheme 1336. If the word line is neither a junction word line nor an edge word line, the method includes configuring for an edge / junction word line (intermediate word line) programming scheme (e.g., the first programming scheme in Figure 11A or Figure 12A). The configuration of steps 1332, 1334, and 1338 may include loading appropriate parameters into appropriate registers (e.g., set feature registers). This method includes programming 1340 using a configured programming scheme (e.g., junction word line programming scheme, edge word line programming scheme, or non-edge / junction word line scheme) and determining 1342 whether a programming path has occurred. If programming does not result in a program path, the program failure routine 1344 is applied. If programming results in a program path, a determination 1346 is made as to whether the current word line is the last word line (e.g., the last word line to be written by the current write command). If it is the last word line, the operation terminates. If the current word line is not the last word line, the next word line becomes the current word line 1348, and the steps are repeated for the next word line (the new current word line). This may continue until the last word line is reached.

[0094] Figure 14 shows an example of a method for programming non-volatile memory cells in a multi-layer NAND memory structure (e.g., a structure including a NAND string extending through two or more layers having word lines of two or more layers coupled to memory cells). The method includes applying a first number of program pulses to a first set of word lines 1460 to program the memory cells of a first set of word lines to a target data state, according to a first programming scheme (e.g., using a programming scheme as shown in Figure 11A or Figure 12A to program non-edge / junction word lines). The method further includes identifying a second set of word lines according to their location in two or more layers 1462 (e.g., identifying edge and / or junction word lines), and applying a second number greater than the first number of program pulses to program the memory cells of a second set of word lines to a target data state, according to a second programming scheme 1464. For example, applying n program pulses instead of one pulse as shown in Figure 11B, or applying m+x pulses instead of m pulses as shown in Figure 12B. The program pulses of the second programming method may have a lower voltage and / or pulse width compared to the program pulses of the first programming method.

[0095] The methods shown in Figures 13 and 14 can be implemented using any suitable circuit. For example, a control circuit such as the row control circuit 220 configured as described above (e.g., in combination with the system control logic 260 and / or other circuits) can be used to selectively apply different programming schemes according to the word line locations within each hierarchy. Such a control circuit (e.g., the row control circuit 220 alone, and / or the row control circuit 220 in combination with the system control logic 260 and / or other circuits) can be considered an example of a means for selecting a word line programming scheme according to the word line locations within each hierarchy, applying a first number of program pulses to program a first set of word line non-volatile memory cells located in the middle of each hierarchy to a target data state according to a first programming scheme, and applying a second number of program pulses greater than the first number to program a second set of word line non-volatile memory cells located at the edges of each hierarchy to a target data state according to a second programming scheme.

[0096] According to an example of the technology, the apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells in a NAND string coupled to a word line. The control circuits are configured to apply a first number of program pulses to a first set of word lines according to a first programming scheme, and to apply a second number of program pulses to a second set of word lines according to a second programming scheme. The second set of word lines includes one or more edge word lines or junction word lines, and the second number of program pulses is greater than the first number of program pulses.

[0097] In one or more embodiments, the first number is 1, and the second number is 2 or more.

[0098] In one or more embodiments, the first number is greater than 1, and the second number is at least 2 greater than the first number.

[0099] In one or more embodiments, the NAND string is formed in lower and upper layers joined along an interface, and the second set of word lines consists of a bottom edge word line of the lower layer, a first joint word line at the top of the lower layer, and a second joint word line at the bottom of the upper layer.

[0100] In one or more embodiments, the first set of word lines consists of all word lines joined to the NAND string, excluding the edge word lines, the first junction word lines, and the second junction word lines.

[0101] In one or more embodiments, the NAND string is formed in a lower hierarchy, an intermediate hierarchy, and an upper hierarchy, the lower hierarchy being joined to the intermediate hierarchy along a first interface, the upper hierarchy being joined to the intermediate hierarchy along a second interface, and the second set of word lines consisting of a bottom edge word line of the lower hierarchy, a first joint word line at the top of the lower hierarchy, a second joint word line at the bottom of the intermediate hierarchy, a third joint word line at the top of the intermediate hierarchy, and a fourth joint word line at the bottom of the upper hierarchy.

[0102] In one or more embodiments, the first set of word lines consists of edge word lines and all word lines coupled to the NAND string, excluding the first junction word lines, the second junction word lines, the third junction word lines, and the fourth junction word lines.

[0103] In one or more embodiments, a program pulse in a first programming scheme has a first voltage, and a program pulse in a second programming scheme has a second voltage, the second voltage being smaller than the first voltage.

[0104] In one or more embodiments, a first programming scheme includes applying a first number of program pulses over a first period, and a second programming scheme includes applying a second number of program pulses over a second period longer than the first period.

[0105] An exemplary method for programming multiple non-volatile memory cells in a memory structure comprising NAND strings extending through two or more layers, wherein the word lines of the two or more layers are coupled to the multiple non-volatile memory cells, the method comprising: applying a first number of program pulses to the memory cells of a first set of word lines in order to program them to a target data state according to a first programming scheme; identifying a second set of word lines according to their positions in the two or more layers; and applying a second number of program pulses greater than the first number to program the memory cells of a second set of word lines in order to program them to a target data state according to a second programming scheme.

[0106] In one or more embodiments, applying a first number of program pulses consists of applying a single pulse, and applying a second number of program pulses consists of applying two or more pulses.

[0107] In one or more embodiments, applying a first number of pulses consists of applying two or more pulses, and applying a second number of pulses consists of applying more pulses than the first number of pulses.

[0108] In one or more embodiments, identifying a second set of word lines includes identifying at least one edge word line at the bottom of the lowest level of two or more levels.

[0109] In one or more embodiments, identifying a second set of word lines further includes identifying at least one junction word line located at the top of the lowest level of two or more hierarchies.

[0110] In one or more embodiments, identifying a second set of word lines further includes identifying at least one junction word line at the bottom of the hierarchy above the lowest hierarchy of two or more hierarchies.

[0111] In one or more embodiments, a program pulse in a first programming scheme has a first voltage, and a program pulse in a second programming scheme has a second voltage, the second voltage being smaller than the first voltage.

[0112] In one or more embodiments, the program pulse of the first program scheme has a first pulse width, and the program pulse of the second program scheme has a second pulse width, the second pulse width being smaller than the first pulse width.

[0113] An exemplary storage system includes a plurality of non-volatile memory cells arranged in NAND strings extending through two or more layers and connected to word lines in each layer, and means for selecting a word line programming scheme according to the word line locations within each of the two or more layers, applying a first number of program pulses to program a first set of word line non-volatile memory cells located midway through each layer to a target data state according to a first programming scheme, and applying a second number greater than the first number of program pulses to program a second set of word line non-volatile memory cells located at or near the boundaries of each layer to a target data state according to a second programming scheme.

[0114] In one or more embodiments, a plurality of non-volatile memory cells are arranged on a memory die, and the means for selection is located on a control die coupled to the memory die.

[0115] In one or more embodiments, two or more layers include at least a first layer and a second layer that are physically connected along a joint, and the second set of word lines includes at least a word line in the first layer closest to the joint and a word line in the second layer closest to the joint.

[0116] For the purposes of this specification, references to “embodiments,” “one embodiment,” “several embodiments,” or “another embodiment” herein may be used to describe different embodiments or the same embodiment.

[0117] For the purposes of this specification, a connection may be a direct connection or an indirect connection (for example, through one or more other parts). In some cases, when an element is said to be connected or coupled to another element, that element may be directly connected to the other element or indirectly connected to the other element through one or more intervening elements. When an element is said to be directly connected to another element, there are no intervening elements between that element and the other element. Two devices are “communicating” if they are connected directly or indirectly so that electronic signals can be communicated between them.

[0118] For the purposes of this specification, the term "based on" may be read as "based at least in part on."

[0119] For the purposes of this specification, the use of numerical terms such as “first” object, “second” object, and “third” object, without additional context, may not imply an ordering of objects, but rather may be used for identifying purposes to distinguish different objects.

[0120] For the purposes of this specification, the term “set” of objects may refer to one or more “sets” of objects.

[0121] The detailed description above is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the disclosed form to the exact form. Many modifications and variations are possible in light of the above teachings. The embodiments described have been selected to best illustrate the principles of the proposed art and its practical application, thereby enabling other persons skilled in the art to best utilize it in various embodiments and with various modifications suitable for the specific use to be intended. The scope is intended to be defined by the claims appended herein.

Claims

1. It is a device, The system comprises one or more control circuits configured to connect to multiple non-volatile memory cells in a NAND string coupled to a word line, and the one or more control circuits are An apparatus configured to program a first set of word line non-volatile memory cells to a target data state by applying a first number of program pulses according to a first programming scheme, and to program a second set of word line non-volatile memory cells to a target data state by applying a second number of program pulses according to a second programming scheme, wherein the second set of word lines includes one or more edge word lines or junction word lines, and the second number of program pulses is greater than the first number of program pulses.

2. The apparatus according to claim 1, wherein the first number is 1 and the second number is 2 or more.

3. The apparatus according to claim 1, wherein the first number is greater than 1, and the second number is greater than the first number by at least 2.

4. The apparatus according to claim 1, wherein the NAND string is formed in lower and upper layers joined along an interface, and the second set of word lines consists of an edge word line at the bottom of the lower layer, a first joint word line at the top of the lower layer, and a second joint word line at the bottom of the upper layer.

5. The apparatus according to claim 4, wherein the word lines of the first set consist of all word lines coupled to the NAND string, excluding the edge word lines, the first joint word lines, and the second joint word lines.

6. The apparatus according to claim 1, wherein the NAND string is formed in a lower hierarchy, an intermediate hierarchy, and an upper hierarchy, the lower hierarchy is joined to the intermediate hierarchy along a first interface, the upper hierarchy is joined to the intermediate hierarchy along a second interface, and the second set of word lines consists of an edge word line at the bottom of the lower hierarchy, a first joint word line at the top of the lower hierarchy, a second joint word line at the bottom of the intermediate hierarchy, a third joint word line at the top of the intermediate hierarchy, and a fourth joint word line at the bottom of the upper hierarchy.

7. The apparatus according to claim 6, wherein the word lines of the first set consist of all word lines coupled to the NAND string, excluding the edge word lines and the first joint word lines, the second joint word lines, the third joint word lines, and the fourth joint word lines.

8. The apparatus according to claim 1, wherein the program pulse in the first programming method has a first voltage, and the program pulse in the second programming method has a second voltage, the second voltage being smaller than the first voltage.

9. The apparatus according to claim 1, wherein the first programming method comprises applying a first number of program pulses over a first period, and the second programming method comprises applying a second number of program pulses over a second period longer than the first period.

10. A method for programming multiple non-volatile memory cells in a memory structure including a NAND string extending through two or more layers, wherein the word lines of the two or more layers are coupled to the multiple non-volatile memory cells, and the method In order to program the memory cells of a first set of word lines to a target data state according to a first programming method, a first number of program pulses are applied to the first set of word lines, Identifying a second set of word lines according to their positions within the two or more hierarchy levels, A method comprising applying a second number of program pulses, greater than the first number, to program the memory cells of the second set of word lines to the target data state, according to a second programming scheme.

11. The method according to claim 10, wherein applying a first number of program pulses consists of applying a single pulse, and applying a second number of program pulses consists of applying two or more pulses.

12. The method according to claim 10, wherein applying the first number of pulses consists of applying two or more pulses, and applying the second number of pulses consists of applying more pulses than the first number of pulses.

13. The method according to claim 10, wherein identifying the second set of word lines includes identifying at least one edge word line at the bottom of the lowest level of the two or more levels.

14. The method according to claim 13, wherein identifying the second set of word lines further comprises identifying at least one junction word line located at the top of the lowest level of the two or more levels.

15. The method according to claim 14, wherein identifying the second set of word lines further comprises identifying at least one junction word line at the bottom of the hierarchy above the lowest hierarchy of the two or more hierarchies.

16. The method according to claim 10, wherein the program pulse in the first program method has a first voltage, and the program pulse in the second program method has a second voltage, the second voltage being smaller than the first voltage.

17. The method according to claim 16, wherein the program pulse in the first program method has a first pulse width, and the program pulse in the second program method has a second pulse width, the second pulse width being smaller than the first pulse width.

18. It is a storage system, Multiple non-volatile memory cells are arranged in a NAND string that extends through two or more layers and connects to the word lines of each layer, A storage system comprising: means for selecting a word line programming scheme according to the word line positions within each of the two or more layers; applying a first number of program pulses to program a first set of word line non-volatile memory cells located in the middle of each layer to a target data state according to a first programming scheme; and applying a second number of program pulses greater than the first number to program a second set of word line non-volatile memory cells located at or near the boundaries of each layer to a target data state according to a second programming scheme.

19. The storage system according to claim 18, wherein the plurality of nonvolatile memory cells are arranged on a memory die, and the selection means is arranged on a control die coupled to the memory die.

20. The storage system according to claim 18, wherein the two or more layers include at least a first layer and a second layer that are physically connected along a joint, and the word lines of the second set include at least a word line in the first layer closest to the joint and a word line in the second layer closest to the joint.

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