Doherty amplifier

Abstract

This Doherty amplifier is configured comprising: a first output circuit (6) having a first transmission line for transmitting a first signal output from a carrier amplifier (4), and outputting the first signal after transmission by the first transmission line to a load (9); and a second output circuit (7) having a second transmission line for transmitting a second signal output from a peak amplifier (5), and outputting the second signal after transmission by the second transmission line to the load (9). The first transmission line is provided with: a first T-type circuit (11) having one end connected to the output side of the carrier amplifier (4) and having the load (9) and the other end connected thereto; and a first capacitor (12) having one end connected to the other end of the first T-type circuit (11) and the other end grounded. The second transmission line is provided with: a second T-type circuit (21) having one end connected to the output side of the peak amplifier (5); a second capacitor (22) having one end connected to the other end of the second T-type circuit (21) and having a load (9) and the other end connected thereto; and a third capacitor (23) having one end connected to the other end of the second T-type circuit (21) and the other end grounded.

Description

[Technical Field]

[0001] This disclosure relates to a Doherty amplifier. [Background technology]

[0002] There is a Doherty amplifier which has a carrier amplifier and a peak amplifier. As an example of such a Doherty amplifier, Patent Document 1 discloses a Doherty amplifier comprising a first output circuit for transmitting a first signal output from a carrier amplifier and a second output circuit for transmitting a second signal output from a peak amplifier. The second output circuit includes a high-pass circuit to cancel out the effects of parasitic capacitance of the peak amplifier. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2022-118445 [Overview of the project] [Problems that the invention aims to solve]

[0004] In the Doherty amplifier disclosed in Patent Document 1, the frequency characteristics during backoff operation are improved by including a high-pass circuit in the second output circuit. However, there is a problem that the effect of widening the bandwidth is limited if the second output circuit is only a high-pass circuit.

[0005] This disclosure was made to solve the above-mentioned problems, and aims to provide a Doherty amplifier that can achieve wider bandwidth characteristics than the Doherty amplifier disclosed in Patent Document 1. [Means for solving the problem]

[0006] The Doherty amplifier according to the present disclosure has a first transmission line for transmitting a first signal output from a carrier amplifier, and a first output circuit that outputs the first signal after transmission by the first transmission line to a load. It also has a second transmission line for transmitting a second signal output from a peak amplifier, and a second output circuit that outputs the second signal after transmission by the second transmission line to the load. The first transmission line includes a first T-shaped circuit with one end connected to the output side of the carrier amplifier and the other end connected to the load, and a first capacitor with one end connected to the other end of the first T-shaped circuit and the other end grounded. The second transmission line includes a second T-shaped circuit with one end connected to the output side of the peak amplifier, a second capacitor with one end connected to the other end of the second T-shaped circuit and the other end connected to the load, and a third capacitor with one end connected to the other end of the second T-shaped circuit and the other end grounded.

Advantages of the Invention

[0007] According to the present disclosure, broadband characteristics can be realized compared to the Doherty amplifier disclosed in Patent Document 1.

Brief Description of the Drawings

[0008] [Figure 1] It is a configuration diagram showing the Doherty amplifier according to Embodiment 1. [Figure 2] It is a configuration diagram showing the interiors of the first output circuit 6 and the second output circuit 7 respectively. [Figure 3] It is a circuit diagram showing the first output circuit 6 and the second output circuit 7 respectively. [Figure 4] It is a circuit diagram showing the first output circuit 6 and the second output circuit 7 respectively with parasitic capacitances Cs1, Cs2, etc. added. [Figure 5] It is a circuit diagram showing a circuit in which characteristic impedances Z1, Z2, Z3 are replaced by a lumped constant circuit network. [Figure 6] It is a circuit diagram showing that the first output circuit 6 and the second output circuit 7 are realized by two T-shaped matching circuits and a lumped constant circuit network Cm, C3, Ca. [Figure 7] It is an explanatory diagram showing the simulation result of the mismatch on the first transmission line side at saturation. [Figure 8] It is an explanatory diagram showing the simulation result of the mismatch on the second transmission line side at saturation. [Figure 9] It is an explanatory diagram showing the simulation result of the mismatch on the first transmission line side at back-off. [Figure 10] It is an explanatory diagram showing the simulation result of the saturation output power of the Doherty amplifier. [Figure 11] It is an explanatory diagram showing the simulation result of the saturation efficiency of the Doherty amplifier. [Figure 12] It is an explanatory diagram showing the simulation result of the back-off efficiency of the Doherty amplifier. [Figure 13] It is a circuit diagram when Z1 = 77Ω, Z2 = 77Ω, RL = 50Ω, and Ropt = 60Ω in the first output circuit 6 and the second output circuit 7. [Figure 14] It is an explanatory diagram showing the correspondence relationship between the capacitance C3, the characteristic impedance Z3, and the phase θ3 of the second capacitor 22. [Figure 15] It is an explanatory diagram showing the simulation result of the mismatch on the first transmission line side at saturation. [Figure 16] It is an explanatory diagram showing the simulation result of the mismatch on the second transmission line side at saturation. [Figure 17] It is an explanatory diagram showing the simulation result of the loss of the Doherty amplifier at saturation. [Figure 18] It is an explanatory diagram showing the simulation result of the mismatch on the first transmission line side at back-off. [Figure 19] It is an explanatory diagram showing the simulation result of the loss of the Doherty amplifier at back-off. [Figure 20] It is an explanatory diagram showing the simulation result of the saturation output power of the Doherty amplifier. [Figure 21] It is an explanatory diagram showing the simulation result of the saturation efficiency of the Doherty amplifier. [Figure 22] This is an explanatory diagram showing the simulation results of the backoff efficiency of a Doherty amplifier. [Modes for carrying out the invention]

[0009] To provide a more detailed explanation of this disclosure, the forms for implementing this disclosure will be described below with reference to the attached drawings.

[0010] Embodiment 1. Figure 1 is a diagram showing the configuration of a Doherty amplifier according to Embodiment 1. The Doherty amplifier shown in Figure 1 comprises a distributor 1, a first input circuit 2, a second input circuit 3, a carrier amplifier 4, a peak amplifier 5, a first output circuit 6, a second output circuit 7, and a combining point 8.

[0011] Distributor 1 distributes the power of the input signal, which is the signal to be amplified. Hereinafter, the signal distributed to the carrier amplifier 4 will be referred to as the first signal. The signal distributed to the peak amplifier 5 will be referred to as the second signal. The distributor 1 outputs the first signal to the first input circuit 2 and the second signal to the second input circuit 3.

[0012] The first input circuit 2 delays the first signal output from the distributor 1 and outputs the delayed first signal to the carrier amplifier 4. The second input circuit 3 delays the second signal output from the distributor 1 and outputs the delayed second signal to the peak amplifier 5.

[0013] The carrier amplifier 4 includes an input matching circuit 4a and a first transistor 4b. The carrier amplifier 4 is supplied with the first signal, which has been delayed by the first input circuit 2, as the signal to be amplified. The carrier amplifier 4 operates, for example, with Class A bias or Class AB bias, amplifies the first signal after the delay from the first input circuit 2, and outputs the amplified first signal to the first output circuit 6. The input matching circuit 4a matches the impedance of the input side of the first transistor 4b. The first transistor 4b is implemented, for example, by a FET (Field Effect Transistor). The first transistor 4b amplifies the first signal after the delay caused by the first input circuit 2.

[0014] The peak amplifier 5 includes an input matching circuit 5a and a second transistor 5b. The peak amplifier 5 is supplied with the second signal, which has been delayed by the second input circuit 3, as the signal to be amplified. The peak amplifier 5 operates, for example, with a Class C bias, amplifies the second signal after the delay from the second input circuit 3, and outputs the amplified second signal to the second output circuit 7. The input matching circuit 5a matches the impedance of the input side of the second transistor 5b. The second transistor 5b is implemented, for example, by a FET. The second transistor 5b amplifies the second signal after the delay caused by the second input circuit 3.

[0015] The first output circuit 6 has a first transmission line for transmitting the first signal output from the carrier amplifier 4. The first output circuit 6 outputs the first signal, after transmission via the first transmission line, to the synthesis point 8. The second output circuit 7 has a second transmission line for transmitting the second signal output from the peak amplifier 5. The second output circuit 7 outputs the second signal, after transmission via the second transmission line, to the synthesis point 8.

[0016] The combination point 8 is connected to the output side of the first output circuit 6, the output side of the second output circuit 7, and the input side of the load 9. Load 9 is driven by the signal amplified by the Doherty amplifier.

[0017] Figure 2 is a diagram showing the internal configuration of the first output circuit 6 and the second output circuit 7, respectively. The first output circuit 6 includes a first T-type circuit 11 and a first capacitor 12 as the first transmission line. The first T-type circuit 11 is, for example, a high-pass type circuit and includes transmission lines 11a, 11b, and 11c. One end of the first T-type circuit 11 is connected to the output side of the carrier amplifier 4. The other end of the first T-type circuit 11 is connected to one end of the first capacitor 12 and to the combination point 8, respectively. The first T-type circuit 11 blocks the passage of low-frequency signals contained in the first signal output from the carrier amplifier 4, while allowing high-frequency signals contained in the first signal to pass through.

[0018] One end of the transmission line 11a is connected to the output side of the carrier amplifier 4. The other end of transmission line 11a is connected to one end of transmission line 11b and one end of transmission line 11c. The characteristic impedance of transmission line 11a is Z A Therefore, the phase of the transmission line 11a is θ A That is the case.

[0019] One end of transmission line 11b is connected to the other end of transmission line 11a and one end of transmission line 11c. The other end of the transmission line 11b is connected to one end of the first capacitor 12 and to the combination point 8. The characteristic impedance of transmission line 11b is Z B Therefore, the phase of the transmission line 11b is θ B That is the case.

[0020] One end of transmission line 11c is connected to the other end of transmission line 11a and one end of transmission line 11b. The other end of transmission line 11c is grounded. The characteristic impedance of transmission line 11c is Z C Therefore, the phase of the transmission line 11c is θ CIt is.

[0021] One end of the first capacitor 12 is connected to each of the other end of the transmission line 11b and the combining point 8. The other end of the first capacitor 12 is grounded. The capacitance of the first capacitor 12 is C m It is.

[0022] The second output circuit 7 includes, as a second transmission line, a second T-type circuit 21, a second capacitor 22, and a third capacitor 23. The second T-type circuit 21 is, for example, a high-pass type circuit and includes a transmission line 21a, a transmission line 21b, and a transmission line 21c. One end of the second T-type circuit 21 is connected to the output side of the peak amplifier 5. The other end of the second T-type circuit 21 is connected to each of one end of the second capacitor 22 and one end of the third capacitor 23. The second T-type circuit 21 blocks the passage of the low-frequency signals included in the second signal output from the peak amplifier 5 and allows the high-frequency signals included in the second signal to pass through.

[0023] One end of the transmission line 21a is connected to the output side of the peak amplifier 5. The other end of the transmission line 21a is connected to each of one end of the transmission line 21b and one end of the transmission line 21c. The characteristic impedance of the transmission line 21a is Z D and the phase of the transmission line 21a is θ D It is.

[0024] One end of the transmission line 21b is connected to each of the other end of the transmission line 21a and one end of the transmission line 21c. The other end of the transmission line 21b is connected to each of one end of the second capacitor 22 and one end of the third capacitor 23. The characteristic impedance of the transmission line 21b is Z E and the phase of the transmission line 21b is θ E It is.

[0025] One end of transmission line 21c is connected to the other end of transmission line 21a and one end of transmission line 21b. The other end of transmission line 21c is grounded. The characteristic impedance of transmission line 21c is Z F Therefore, the phase of the transmission line 21c is θ F That is the case.

[0026] One end of the second capacitor 22 is connected to the other end of the transmission line 21b and to one end of the third capacitor 23. The other end of the second capacitor 22 is connected to the composite point 8. The capacitance of the second capacitor 22 is C3.

[0027] One end of the third capacitor 23 is connected to the other end of the transmission line 21b and to one end of the second capacitor 22. The other end of the third capacitor 23 is grounded. The capacitance of the third capacitor 23 is C a That is the case.

[0028] Next, we will explain the operation of the Doherty amplifier shown in Figure 1. In the Doherty amplifier shown in Figure 1, for example, the equivalent electrical length of the second transmission line is -20 degrees, and the difference between the phase of the signal to be amplified by the carrier amplifier 4 and the phase of the signal to be amplified by the peak amplifier 5 is 90 degrees + 20 degrees.

[0029] When the distributor 1 receives an input signal, which is the signal to be amplified, it distributes the power of the input signal. The distributor 1 outputs the first signal, which is one of the signals after distribution, to the carrier amplifier 4, and outputs the second signal, which is the other of the signals after distribution, to the peak amplifier 5.

[0030] When the first input circuit 2 receives the first signal from the distributor 1, it delays the first signal and outputs the delayed first signal to the carrier amplifier 4. When the second signal is supplied from the distributor 1, the second input circuit 3 delays the second signal and outputs the delayed second signal to the peak amplifier 5.

[0031] The carrier amplifier 4 amplifies the first signal after the delay from the first input circuit 2, and outputs the amplified first signal to the first output circuit 6. The peak amplifier 5 amplifies the second signal, which has been delayed by the second input circuit 3, and outputs the amplified second signal to the second output circuit 7.

[0032] When the first output circuit 6 receives the amplified first signal from the carrier amplifier 4, it transmits the amplified first signal to the synthesis point 8. When the second output circuit 7 receives the amplified second signal from the peak amplifier 5, it transmits the amplified second signal to the synthesis point 8. At the synthesis point 8, the amplified first signal and the amplified second signal are combined, and the combined signal of the first and second signals is supplied to the load 9.

[0033] Here, the first transistor 4b of the carrier amplifier 4 has a parasitic capacitance C. s1 There is a parasitic capacitance C in the second transistor 5b of the peak amplifier 5. s2 It exists. These parasitic capacities C s1 ,C s2 This can affect the operation of the Doherty amplifier, and as a result, the frequency characteristics of the efficiency during back-off operation, or the frequency characteristics of the saturation efficiency, may become narrower. In the Doherty amplifier shown in Figure 1, these parasitic capacitances C s1 ,C s2 To mitigate the effects of the above, the first output circuit 6 comprises a first T-type circuit 11 and a first capacitor 12, and the second output circuit 7 comprises a second T-type circuit 21, a second capacitor 22 and a third capacitor 23.

[0034] The following describes the implementation of the first output circuit 6 and the second output circuit 7. First, as shown in Figure 3, the first output circuit 6 is represented by a circuit with characteristic impedance Z1 and phase θ1, and the second output circuit 7 is represented by a circuit with characteristic impedance Z2 and phase θ2, and a circuit with characteristic impedance Z3 and phase θ3. Figure 3 is a circuit diagram showing the first output circuit 6 and the second output circuit 7, respectively. In the example in Figure 3, θ1 = 90 degrees, θ2 = 90 degrees, and θ3 = -90 degrees. In this case, the characteristic impedance Z1 satisfies the following equation (1), and the ratio of the characteristic impedance Z2 to the characteristic impedance Z3 is expressed as shown in the following equation (2).

[0035] In formulas (1) and (2) of TIFF0007858954000001.tif46166, R L The load is 9, and the resistance is R opt This is the optimal load for the first transistor 4b. α is the optimal load ratio between the first transistor 4b and the second transistor 5b.

[0036] Next, as shown in Figure 4, the parasitic capacitance C of the first transistor 4b. s1 And the parasitic capacitance C of the second transistor 5b. s2 This is added to the circuit shown in Figure 3. Also, parasitic capacity C s1 Coil L to compensate s1 And, parasitic capacity C s2 Coil L to compensate s2 This is added to the circuit shown in Figure 3. Figure 4 shows the parasitic capacity C. s1 ,C s2 These are circuit diagrams showing the first output circuit 6 and the second output circuit 7, respectively, with the addition of the above.

[0037] Next, as shown in Figure 5, the characteristic impedances Z1, Z2, and Z3 are replaced by a lumped-element network. Figure 5 is a circuit diagram showing a circuit in which characteristic impedances Z1, Z2, and Z3 are replaced by a lumped-element circuit network.

[0038] Next, as shown in Figure 6, a portion of the first output circuit 6 is represented by a T-type matching circuit using a distributed constant circuit, and a portion of the second output circuit 7 is represented by a T-type matching circuit using a distributed constant circuit. As a result, the first output circuit 6 and the second output circuit 7 are connected by two T-type matching circuits and a lumped-parameter network C, as shown in Figure 6. m ,C3,C a This is achieved by [the following]. Figure 6 shows that the first output circuit 6 and the second output circuit 7 consist of two T-type matching circuits and a lumped-parameter network C m ,C3,C a This is a circuit diagram showing how it is realized.

[0039] Figure 7 is an explanatory diagram showing the simulation results of the mismatch on the first transmission line side when saturated. Figure 8 is an explanatory diagram showing the simulation results of the mismatch on the second transmission line side when saturated. In Figures 7 and 8, the horizontal axis represents frequency, and the vertical axis represents mismatch. As is clear from Figures 7 and 8, the Doherty amplifier shown in Figure 1 has improved mismatch bandwidth characteristics at saturation compared to the Doherty amplifier of Patent Document 1, as the first output circuit 6 comprises a first T-type circuit 11 and a first capacitor 12, and the second output circuit 7 comprises a second T-type circuit 21, a second capacitor 22 and a third capacitor 23.

[0040] Figure 9 is an explanatory diagram showing the simulation results of the mismatch on the first transmission line side during backoff. In Figure 9, the horizontal axis represents frequency, and the vertical axis represents mismatch. As is clear from Figure 9, the Doherty amplifier shown in Figure 1 has improved mismatch bandwidth characteristics during backoff compared to the Doherty amplifier of Patent Document 1, as the first output circuit 6 comprises a first T-type circuit 11 and a first capacitor 12, and the second output circuit 7 comprises a second T-type circuit 21, a second capacitor 22 and a third capacitor 23.

[0041] Figure 10 is an explanatory diagram showing the simulation results of the saturation output power of a Doherty amplifier. Figure 11 is an explanatory diagram showing the simulation results of the saturation efficiency of the Doherty amplifier. Figure 12 is an explanatory diagram showing the simulation results of the backoff efficiency of the Doherty amplifier. In Figures 10, 11, and 12, the horizontal axis represents frequency. In Figure 10, the vertical axis represents the saturated output power; in Figure 11, the vertical axis represents the saturated efficiency; and in Figure 12, the vertical axis represents the back-off efficiency. As is clear from Figures 10, 11, and 12, the Doherty amplifier shown in Figure 1 achieves broader bandwidth of saturation output power, broader bandwidth of saturation efficiency, and broader bandwidth of backoff efficiency compared to the Doherty amplifier of Patent Document 1.

[0042] In the above embodiment 1, the Doherty amplifier is configured to include a first output circuit 6 that has a first transmission line for transmitting a first signal output from a carrier amplifier 4 and outputs the first signal after transmission by the first transmission line to a load 9, and a second output circuit 7 that has a second transmission line for transmitting a second signal output from a peak amplifier 5 and outputs the second signal after transmission by the second transmission line to a load 9. The first transmission line includes a first T-type circuit 11 with one end connected to the output side of the carrier amplifier 4 and the other end connected to the load 9, and a first capacitor 12 with one end connected to the other end of the first T-type circuit 11 and the other end grounded. The second transmission line includes a second T-type circuit 21, one end of which is connected to the output side of the peak amplifier 5; a second capacitor 22, one end of which is connected to the other end of the second T-type circuit 21 and the other end of which is connected to the load 9; and a third capacitor 23, one end of which is connected to the other end of the second T-type circuit 21 and the other end of which is grounded. Therefore, the Doherty amplifier can achieve wider bandwidth characteristics than the Doherty amplifier disclosed in Patent Document 1.

[0043] Embodiment 2. Embodiment 2 describes specific circuit conditions for achieving broadband characteristics of the Doherty amplifier. In Embodiment 2, as shown in Figure 13, Z1 = 77Ω, Z2 = 77Ω, R L = 50Ω, R opt Assuming that the impedance is 60Ω, the characteristic impedance Z3 and phase θ3 are determined by selecting one of the capacitances shown in Figure 14 for the capacitance C3 of the second capacitor 22. If we select a capacitance C3 of the second capacitor 22, for example, 81fF, then the characteristic impedance Z3 will be 100Ω and the phase θ3 will be -90 degrees. If we select a capacitance C3 of the second capacitor 22, for example, 59 fF, the characteristic impedance Z3 will be 145 Ω and the phase θ3 will be -110 degrees. In this case, the ratio of the characteristic impedance Z3 to the characteristic impedance Z2 is 1.88 ≈ 2. Figure 13 shows the first output circuit 6 and the second output circuit 7, where Z1=77Ω, Z2=77Ω, RL = 50Ω, R opt This is the circuit diagram when the resistance is 60Ω. Figure 14 is an explanatory diagram showing the correspondence between the capacitance C3 of the second capacitor 22, its characteristic impedance Z3, and its phase θ3. If the parameters (C3, Z3, θ3) of the Doherty amplifier shown in Figure 13 are determined according to the correspondence shown in Figure 14, the circuit will be a modified version of the Doherty amplifier shown in Figures 4 to 6.

[0044] Figure 15 is an explanatory diagram showing the simulation results of the mismatch on the first transmission line side when saturated. Figure 16 is an explanatory diagram showing the simulation results of the mismatch on the second transmission line side when saturated. Figure 17 is an explanatory diagram showing the simulation results of the Doherty amplifier loss at saturation. In Figures 15 and 16, the horizontal axis represents frequency, and the vertical axis represents mismatch. In Figure 17, the horizontal axis represents frequency, and the vertical axis represents loss. As is clear from Figures 15 and 16, the bandwidth characteristics of the mismatch at saturation change when the capacitance C3 of the second capacitor 22 is adjusted. As is clear from Figure 17, the loss at saturation changes when the capacitance C3 of the second capacitor 22 is adjusted.

[0045] Figure 18 is an explanatory diagram showing the simulation results of the mismatch on the first transmission line side during backoff. Figure 19 is an explanatory diagram showing the simulation results of the Doherty amplifier loss during backoff. In Figure 18, the horizontal axis represents frequency, and the vertical axis represents mismatch. In Figure 19, the horizontal axis represents frequency, and the vertical axis represents loss. As is clear from Figure 18, adjusting the capacitance C3 of the second capacitor 22 changes the bandwidth characteristics of the mismatch during back-off. As is clear from Figure 19, the loss during backoff changes when the capacitance C3 of the second capacitor 22 is adjusted.

[0046] Figure 20 is an explanatory diagram showing the simulation results of the saturation output power of a Doherty amplifier. Figure 21 is an explanatory diagram showing the simulation results of the saturation efficiency of the Doherty amplifier. Figure 22 is an explanatory diagram showing the simulation results of the backoff efficiency of the Doherty amplifier. In Figures 20, 21, and 22, the horizontal axis represents frequency. In Figure 20, the vertical axis represents the saturated output power; in Figure 21, the vertical axis represents the saturated efficiency; and in Figure 22, the vertical axis represents the back-off efficiency. As is clear from Figures 20, 21, and 22, adjusting the capacitance C3 of the second capacitor 22 changes the bandwidth characteristics of the saturated output power, the saturated efficiency, and the backoff efficiency, respectively. In particular, when 59fF is selected as the capacitance C3 of the second capacitor 22, the effect of broadband characteristics becomes remarkably apparent. As shown in Figure 21, the efficiency at high frequencies is best improved when capacitance C3 is 59 fF. When C3 < 59 fF (θ3 < -110°), the efficiency improvement at high frequencies is not achieved, indicating that the bandwidth is not widened.

[0047] Embodiment 2 describes a Doherty amplifier in which the capacitance C3 of the second capacitor 22 is adjusted. When, for example, 59fF is selected as the capacitance C3 of the second capacitor 22, that is, as the capacitance value of the second capacitor 22, the same 59fF may be used for the capacitance value of the first capacitor 12 and the capacitance value of the third capacitor 23. In other words, C m =C a The capacitance values ​​of the first capacitor 12, the second capacitor 22, and the third capacitor 23 may be set to the same value so that the result is C3.

[0048] Furthermore, this disclosure allows for free combination of each embodiment, modification of any component in each embodiment, or omission of any component in each embodiment. [Industrial applicability]

[0049] This disclosure is suitable for Doherty amplifiers. [Explanation of Symbols]

[0050] 1 Distributor, 2 First input circuit, 3 Second input circuit, 4 Carrier amplifier, 4a Input matching circuit, 4b First transistor, 5 Peak amplifier, 5a Input matching circuit, 5b First transistor, 6 First output circuit, 7 Second output circuit, 8 Combination point, 9 Load, 11 First T-type circuit, 11a Transmission line, 11b Transmission line, 11c Transmission line, 12 First capacitor, 21 Second T-type circuit, 21a Transmission line, 21b Transmission line, 21c Transmission line, 22 Second capacitor, 23 Third capacitor.

Claims

1. A first output circuit having a first transmission line for transmitting a first signal output from a carrier amplifier, and outputting the first signal after transmission by the first transmission line to a load, The device includes a second transmission line for transmitting a second signal output from a peak amplifier, and a second output circuit for outputting the second signal after transmission via the second transmission line to the load. The first transmission line is, A first T-shaped circuit, one end of which is connected to the output side of the carrier amplifier and the other end of which is connected to the load, The first T-shaped circuit comprises a first capacitor, one end of which is connected to the other end and the other end of which is grounded. The second transmission line is, A second T-shaped circuit, one end of which is connected to the output side of the peak amplifier, The other end of the second T-shaped circuit is connected to one end of a second capacitor, and the other end of the capacitor is connected to the load. A Doherty amplifier characterized by comprising a third capacitor, one end of which is connected to the other end of the second T-shaped circuit and the other end of which is grounded.

2. The Doherty amplifier according to claim 1, characterized in that the equivalent electrical length of the second transmission line is -20 degrees, and the difference between the phase of the signal to be amplified by the carrier amplifier and the phase of the signal to be amplified by the peak amplifier is 90 degrees + 20 degrees.

3. The Doherty amplifier according to claim 1, characterized in that the capacitance value of the first capacitor, the capacitance value of the second capacitor, and the capacitance value of the third capacitor are the same.

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