High-efficiency dual-drive power amplifier for high-reliability applications

Abstract

A dual-drive power amplifier (PA), in which the PA core includes a differential pair of transistors M1 and M2 driven by a coupling network having two transmission line couplers, a first transmission line section of the coupler configured to carry an input signal Vin to drive the gate of the opposite transistor, and a second transmission line section grounded at one end, with a coupled portion αVin of the input signal Vin coupled to the first transmission line section to drive the source terminal of the corresponding transistor. The coupling network arrangement allows the source terminal to be driven at a voltage lower than ground potential. The embodiments disclosed herein further provide an input matching network, a driver, an interstage matching network, and an output network for practical implementation of the PA core.

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 136264, filed on 12 January 2021, which is incorporated herein by reference as if it were described in its entirety.

[0002] (Field of Invention) Various embodiments of this disclosure relate generally to amplifiers, and more particularly to configurations of dual-drive power amplifiers for wireless communications applications. [Background technology]

[0003] (background) Conventional power amplifiers (PAs) implemented in CMOS can suffer from low efficiency, low output power, low gain, and limited maximum operating frequency due to factors such as low breakdown voltage, low quality coefficient of on-chip passive elements, and large signal loss of intrinsic devices at higher frequencies. Complex design techniques have been implemented to address some of these problems. For example, techniques such as load modulation, harmonic tuned loads, stacked PA cores, nonlinearity cancellation, neutralization techniques using passive networks, and mixed-signal reconfigurable architectures have been used to improve certain performance metrics of PAs, but the core units are still primarily based on common source / common emitter (CS / CE) topology. While transistors in most commercial semiconductor processes have at least three terminals (gate, source, and drain), conventional PA design techniques only utilize transistors as two-terminal devices.

[0004] (New spectral availability enables many new 5G New Opportunities for radio (NR) applications are available. However, stringent efficiency and linearity requirements present significant challenges for designers. Conventional PA designs and the design techniques described above have primarily focused on increasing peak / power backoff (PBO), power added efficiency (PAE), and output power (Pout). However, in highly scaled silicon processes with low supply voltages, such techniques yield reduced returns on PAE and output power, as the transistor knee voltage (Vknee) constitutes a significant portion of the supply voltage. Furthermore, in practical use, the supply voltage is often reduced to ensure device reliability. This is particularly relevant to array operation, where array element coupling results in substantial antenna impedance mismatch and undesirable large PA voltage swings. While previous techniques have improved PA efficiency overall, they fundamentally cannot surpass the theoretical PA core efficiency at the same conduction angle (e.g., a Class B common source (CS) PA) without relying on device switching or harmonic shaping. Performance challenges remain regarding improvements in PA efficiency, output power, linearity, data rate, and reliability. [Overview of the Initiative]

[0005] The disclosed technology relates to a new power amplifier (PA) topology employing a novel dual-drive PA configuration, in which transistors within the PA core are driven with phase shift at the gate and source terminals using a dual-drive coupling network, while providing correct DC bias to the gate and source terminals.

[0006] According to an exemplary implementation of the disclosed technology, the PA core includes a differential pair of transistors M1 and M2 driven by a coupling network having two transmission line-based couplers, the first transmission line section of the pair being configured to transmit an input signal Vin to drive the gate of the opposite transistor, the second transmission line section being grounded at one end, and the coupled portion αVin of the input signal Vin being coupled to the first transmission line section to drive the source terminal of the corresponding transistor. This coupling network arrangement allows the source terminal to be driven at a voltage lower than ground potential. In embodiments disclosed herein, input matching networks, drivers, interstage matching networks, and output networks are further provided for practical implementations of the PA core.

[0007] According to an exemplary implementation of the disclosed technology, a dual-drive power amplifier core is provided, comprising a first transistor M1 having at least three terminals: an M1 gate / base terminal, an M1 drain / collector terminal, and an M1 source / emitter terminal. The dual-drive power amplifier core also comprises a second transistor M2 having at least three terminals: an M2 gate / base terminal, an M2 drain / collector terminal, and an M2 source / emitter terminal. The dual-drive power amplifier core also includes a first transmission line coupler comprising: a first transmission line section T1 having a first end and a second end, the first end being grounded and the second end connected to the M1 source / emitter terminal; and a second transmission line section T2 having a first end and a second end, the first end being configured to receive a core first input signal Vin+ and a first bias voltage, the second end being connected to the M2 gate / base terminal and coupled to the M1 drain / collector terminal, and electromagnetically coupled to the first transmission line section T1. The dual-drive power amplifier core also includes a second transmission line coupler comprising a third transmission line section T3 having a first end and a second end, the first end being grounded and the second end connected to the M2 source / emitter terminal, and a fourth transmission line section T4 having a first end and a second end, the first end being configured to receive the core's second input signal Vin- and a first bias voltage, the second end being connected to the M1 gate / base terminal and coupled to the M2 drain / collector terminal, and electromagnetically coupled to the third transmission line section T3. The dual-drive power amplifier core also includes a core first output terminal Vout+ connected to the M1 drain / collector terminal and configured to receive a second bias voltage, and a core second output terminal Vout- connected to the M2 drain / collector terminal and configured to receive a second bias voltage, wherein the core first and core second output terminals are configured to output an amplified differential signal corresponding to the difference between the core first input signal Vin+ and the core second input signal Vin-.

[0008] According to another exemplary implementation of the disclosed technology, a pair of transmission line-based couplers is provided. The above-described transmission line-based coupler is configured to receive differential input voltage signals at two input terminals and to passively couple scaled differential input voltage signals at four output terminals. The above-described pair of transmission line-based couplers is a first transmission line coupler having a first end and a second end, the first end being grounded and the second end being V S1 A first transmission line section T1 configured to output a signal, having a first end and a second end, the first end configured to receive a core first input signal Vin+ and a first bias voltage, and the second end having V G2 It is configured to output a signal and is electromagnetically coupled to the first transmission line section T1, and in response to receiving an input signal Vin+ at the first end, V S1 The first transmission line coupler includes a second transmission line section T2 that generates a signal. The pair of transmission line-based couplers is a second transmission line coupler having a first end and a second end, the first end being grounded and the second end being V S2 A third transmission line section T3 configured to output a signal, having a first end and a second end, the first end configured to receive a core second input signal Vin- and a first bias voltage, and the second end receiving V G1 It is configured to output a signal and is electromagnetically coupled to the third transmission line section T3, and in response to receiving the input signal Vin- at the first end, V G1 It includes a second transmission line coupler which comprises a fourth transmission line section T4 that generates a signal.

[0009] These and other aspects of the Disclosure are described below in the "Detailed Description" and accompanying drawings. Other aspects and features of the embodiments will become apparent to those skilled in the art when considering the following descriptions of specific exemplary embodiments in conjunction with the drawings. Features of the Disclosure may be discussed in relation to specific embodiments and drawings, but all embodiments of the Disclosure may include one or more of the features discussed herein. Furthermore, one or more embodiments may be described as having certain advantageous features, and one or more such features may also be used in conjunction with the various embodiments described herein. Similarly, exemplary embodiments may be described below as embodiments of devices, systems, or methods, but it should be understood that such exemplary embodiments may be implemented in the various devices, systems, and methods of the Disclosure. [Brief explanation of the drawing]

[0010] The following detailed descriptions of specific embodiments in this disclosure will be better understood in conjunction with the accompanying drawings. Specific embodiments are shown in the drawings for illustrative purposes. However, it should be understood that this disclosure is not limited to the exact arrangements and means of the embodiments shown in the drawings. [Figure 1A] Figure 1A is an exemplary diagram of a MOSFET transistor according to an exemplary embodiment of the disclosed technology, having a gate terminal driven by a first drive signal Vin, a source terminal driven by a second drive signal αVin, and a resulting output signal Vout. [Figure 1B] Figure 1B is a graph of a first drive signal Vin, a second drive signal αVin, and the resulting output signal Vout (as shown in Figure 1A) with respect to ground and knee voltage Vknee, according to an exemplary embodiment of the disclosed technology. [Figure 2] Figure 2 is a schematic diagram of a dual-drive power amplifier (PA) core according to an exemplary embodiment of the disclosed technology. [Figure 3A]FIG. 3A is a diagram of a coupled transmission line pair that enables passive generation of signals αVin+ from Vin+ and αVin- from Vin- according to an exemplary embodiment of the disclosed technology. [Figure 3B] FIG. 3B is a three-dimensional view of an exemplary physical layout of a coupled transmission line pair as illustrated in FIG. 3A according to an exemplary embodiment of the disclosed technology. [Figure 4A] FIG. 4A is a block diagram of an exemplary power amplifier that utilizes a dual drive core according to an exemplary embodiment of the disclosed technology. [Figure 4B] FIG. 4B is a detailed schematic diagram of a power amplifier that utilizes a dual drive core (corresponding to the block diagram of FIG. 4A) according to an exemplary embodiment of the disclosed technology.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] (Detailed Description) The disclosed technology includes a new power amplifier (PA) architecture that can overcome some of the above-described problems associated with conventional approaches. The disclosed PA topology employs a new dual drive configuration in which the PA core transistors are driven with a phase shift at the gate and source terminals. The term "transistor" as used herein may refer to any three-terminal signal amplification device, including but not limited to MOSFET, CMOS, NMOS, PMOS, BJT, NPN, PNP, etc. (e.g., having corresponding terminals such as the base, collector, and emitter of a BJT).

[0012] The disclosed PA topology allows the source and drain of the transistor to swing in phase, thus artificially reducing the transistor knee voltage and thereby increasing the output voltage swing. This dual-drive PA topology significantly increases the output power, linearity, and efficiency of the PA while enabling a reduction in the supply voltage. Furthermore, since the disclosed dual-drive topology can be configured as a combination of a common gate and a common source, the input impedance of the PA stage can be significantly reduced, enabling a matched network between wideband and low-loss stages. The PA topology disclosed herein can provide excellent performance for highly reliable commercial applications while enabling the use of lower supply voltages.

[0013] To facilitate understanding of the principles and features of this disclosure, various exemplary embodiments are described below. The components, steps, and materials described below as constituting various elements of the embodiments disclosed herein are intended to be illustrative and not limiting. Many suitable components, steps, and materials that perform the same or similar functions as those described herein are intended to be included within the scope of this disclosure. Such other components, steps, and materials not described herein may include, but are not limited to, similar components or steps developed after the development of the embodiments disclosed herein.

[0014] Figure 1A is an exemplary diagram of a dual-drive MOSFET transistor according to an exemplary embodiment of the disclosed technology, having a gate terminal driven by a first drive signal Vin, a source terminal driven by a second drive signal αVin, and a resulting output signal Vout. In this implementation, α can be negative as it provides a source drive signal that is out of phase with the gate drive signal Vin.

[0015] FIG. 1B is a graph of the first drive signal Vin, the second drive signal αVin, and the resulting output signal Vout (as shown in FIG. 1A) with respect to the ground and knee voltages, according to an exemplary embodiment of the disclosed technology.

[0016] The power efficiency of the dual drive transistor can be expressed as follows.

Equation

Equation

[0017] The bias current is expressed as follows.

Equation

[0018] The power efficiency of the dual feed transistor for a typical class B amplifier can be expressed as follows.

Equation

[0020] When a transistor is driven only at the gate, the maximum efficiency of the device depends on the device's conduction angle and the technology-specific V knee This is determined by, and this results in particularly lower V DD With respect to the value, the peak output voltage swing is reduced and the drain efficiency is limited. The disclosed technology utilizes a transistor, which is a device with three or more terminals, and further provides a coupling network for driving both the gate and source terminals with phase-shifted inputs Vin and αVin, respectively. The source voltage can swing below ground while being in phase with the drain voltage, increasing the maximum drain output voltage swing by αVin without the need to increase the supply voltage.

[0021] The advantages of the dual-drive PA topology disclosed herein may include: (1) Increased PA core drain efficiency exceeding that of a typical common-source topology at the same conduction angle due to increased source coupling coefficient; (2) Lower V DD V below knee The reduced V can be mitigated by reducing the effects of DD (3) Higher drain efficiency that can be maintained even with voltage. Power saturation Psat can be increased while reducing device AM-PM and AM-AM distortion by the active device spending more time in its saturation region and less time spent in the triode. (4) The parallel input resistance of the transistor is reduced by the device gate impedance being coupled in parallel with the low source impedance, which means that the parallel input resistance of the transistor can also be designed with source-coupled αVin to facilitate the design of wideband and low-loss interstage matching networks. (5) The reliability problem of voltage peaking in complex harmonic shaping PAs can be mitigated (Class J or continuous-mode Class F PAs).

[0022] The dual-drive PA topologies disclosed herein are particularly well-suited for high-reliability commercial and defense applications requiring lower supply voltages. Certain exemplary implementations of the disclosed technology may also be suitable for power amplifiers with higher supply voltages, such as satellite communications applications where the supply voltage may be 20 volts or more. It should also be emphasized that the dual-drive PA topologies disclosed herein differ from conventional multilayer PAs. In such conventional multilayer PA devices, the source terminals of the MOSFET transistors in the bottom layer of the multilayer device are coupled to ground, thereby determining the amplitude of the device's total output voltage. In contrast, the source terminals of the disclosed technology are connected to coupled transmission lines that allow the source voltage to be stepped down below ground, as described below.

[0023] Figure 2 is a schematic diagram of a dual-drive power amplifier (PA) core according to an exemplary embodiment of the disclosed technology, which may utilize a transistor differential pair including a first transistor M1 202 and a second transistor M2 204 together with a dual-drive coupling network 206. The dual-drive coupling network 206 may include transmission line segments T1 208, T2 210, T3 212, and T4 214, where T1 208 and T2 210 are electromagnetically coupled, and T4 214 and T1 208 are electromagnetically coupled. In the dual-drive coupling network 206, a first portion Vin- of the balanced input signal can be applied through T4 214 to drive the gate of M1 202, while a version of Vin- is coupled via T3 212 to drive the source terminal of M2 204. Simultaneously, a second portion of the balanced input signal Vin+ can be applied through T2 210 to drive the gate of M2 204, while a version of Vin+ is coupled via T1 208 to drive the source terminal of M1 202. The implementation configuration disclosed herein further enables the provision of correct DC bias points, such as a non-zero DC voltage for the gate and DC ground for the source. Using this new PA topology, the sources of transistors 202 and 204 can swing in phase with the drain, thus enabling voltage knee / output swing extensions that allow for a linear increase in output power and power added efficiency while using low supply voltages.

[0024] Figure 3A is a diagram of a coupled network 300 including pairs of transmission line-based couplers T1 208 and T2 210, T3 212 and T4 214 as shown in Figure 2, where T1 208 is coupled with T2 210 (S 302) and T3 212 is coupled with T4 214 (S 304). Although each of T1 208, T2 210, T3 212 and T4 214 can be considered an independent transmission line (on their own), T1 208 is in close proximity to T2 210, allowing T1 208 and T2 210 to be electromagnetically coupled to form a first transmission line-based coupler. Similarly, T3 212 and T4 214 may form a second transmission line-based coupler. Couplers 302 and 304 can passively generate signals αVin+ and αVin- from Vin+ and Vin-, respectively. In some exemplary implementations, the coupled network 300 can introduce degradation of an inductive reactance source, which can reduce the overall device power gain. In some implementations, the inductive reactance can maintain the desired coupling coefficient α while the even-mode impedance Z 0e and odd-mode impedance Z 0o This can be reduced by selecting a transmission line geometry that gives a moderately low value to it. According to a particular implementation of the disclosed technology, the coupling coefficient α can be set by the transmission line geometry.

[0025] In one example implementation of the disclosed technology, the coupling coefficient α may be set in the range of about 0.1 to about 0.9. In other exemplary implementations, the coupling coefficient α may be set in the range of about 0.2 to about 0.8. In other exemplary implementations, the coupling coefficient α may be set in the range of about 0.3 to about 0.7. In other exemplary implementations, the coupling coefficient α may be set in the range of about 0.4 to about 0.6. In other exemplary implementations, the coupling coefficient α may be set in the range of about 0.3 to about 0.4.

[0026] Figure 3B is a three-dimensional diagram of an exemplary physical layout of a coupled network 300 having coupled transmission line pairs T1 208 and T2 210, T3 212 and T4 214 corresponding to the elements shown in Figures 3A and 2. This unique layout configuration allows the signal Vin+ (Vin-) to be input at one end of transmission line T2 210 (T4 214) and electromagnetically coupled to T1 208 (T3 212) over a length L. According to some exemplary implementations of the disclosed technology, the resulting signal V (as further described below) S1 , V G1 , V G2 , V S2 A unique crossover region 306 may be used to route the signal to the rest of the circuit in a convenient manner.

[0027] In some exemplary implementations, the transmission lines 208, 210, 212, and 214 of the coupling network 300 may be designed and manufactured using several different variables to control impedance, coupling coefficient, etc. Such variables may include transmission line length L, width W1, thickness t2 and t1, gap tg, and / or ground surface opening width w2. In one exemplary implementation of the disclosed technology, the length L may be about 50 microns, the width W1 may be about 10 microns, the thickness t1 and t2 may be about 3 microns, the gap tg may be about 1.6 microns, and the ground surface opening width W2 may be about 14 microns. As shown, one end of the bottom traces T1 208 and T3 212 may be connected to the ground surface 314. In these geometries, the even-mode impedance Z 0e and odd-mode impedance Z 0o These can be set to approximately 15 ohms and approximately 40 ohms, respectively, at 30 GHz. In some exemplary implementations, the conduction angle may be adjusted to approximately 8.5 degrees, and the k coefficient may be approximately 0.47 at 30 GHz.

[0028] Figure 4A is an exemplary block diagram of a power amplifier 400 that can utilize the dual-drive PA core 200 (as described above) according to an exemplary embodiment of the disclosed technology. Various configurations can be configured to utilize the dual-drive core 200 without departing from the scope of the disclosed technology. Figure 4A shows one example of how other stages (such as the input matching network 402, the driver 404, the interstage matching network 406, and / or the output network 408) can be utilized with the dual-drive PA core 200. Next, with reference to Figure 4B, specific exemplary components of each stage in the exemplary power amplifier 400 will be described.

[0029] Figure 4B is a detailed schematic diagram of an example power amplifier circuit 401 utilizing a dual-drive PA core 200 according to an exemplary embodiment of the disclosed technology. While other stages, components, and arrangements may be used without departing from the scope of the disclosed technology, the arrangement shown in Figure 4B illustrates a practical use of the dual-drive PA core 200 having stages 402, 404, 406, and 408, which may correspond to similar stages shown in Figure 4A.

[0030] As described above with reference to Figures 2, 3A, and 3B, the dual-drive power amplifier core 200 may include a first transistor M1 202 having at least three terminals: an M1 gate terminal, an M1 drain terminal, and an M1 source terminal. The dual-drive power amplifier core 200 may also include a second transistor M2 204 having at least three terminals: an M2 gate terminal, an M2 drain terminal, and an M2 source terminal.

[0031] The dual-drive power amplifier core 200 may include a first transmission line coupler comprising a first transmission line section T1 208 having a first end and a second end, the first end being grounded and the second end being connected to the M1 source terminal.

[0032] The dual-drive power amplifier core 200 may include a first transmission line coupler comprising a second transmission line section T2 210 having a first end and a second end, where the first end may be configured to receive one or more of the core first input signals and / or a first bias voltage. The second end of the second transmission line section T2 210 may be connected to the M2 gate terminal or capacitively coupled to the M1 drain terminal. As described above, the first transmission line section T1 208 may be electromagnetically coupled to the second transmission line section T2 210.

[0033] The dual-drive power amplifier core 200 may include a second transmission line coupler comprising a third transmission line section T3 212 having a first end and a second end, the first end being grounded and the second end being connected to the M2 source terminal.

[0034] The dual-drive power amplifier core 200 may include a fourth transmission line section T4 214 having a first end and a second end, where the first end may be configured to receive one or more of the core second input signal and / or a first bias voltage. The second end of the fourth transmission line section T4 214 may be connected to the M1 gate terminal and, in some implementations, capacitively coupled to the M2 drain terminal. As described above, the third transmission line section T3 212 may be electromagnetically coupled to the fourth transmission line section T4 214.

[0035] In some exemplary implementations, as shown in Figure 4B, the drain terminals M1 202 and M2 204 may be configured as outputs, and VDD may be connected via the output network 408. PA It may also be subject to this. In some exemplary implementations, the drain terminals of M1 202 and M2 204 may be considered as the first and second core output terminals, respectively, and may be configured to output amplified differential signals corresponding to the difference between the first and second core input signals at the gates of M1 202 and M2 204.

[0036] In some exemplary implementations, circuit 401 is configured to control the voltage applied to the M1 202 drain terminal and the M2 204 drain terminal, and the cascode bias control terminal V CAS A cascode current buffer may be included. In some exemplary implementations, the cascode current buffer may increase the supply voltage and output power. In some exemplary implementations, the cascode current buffer may be biased for 1.3V operation. The cascode current buffer may include a third transistor M3 414 having at least three terminals: an M3 gate terminal, an M3 drain terminal, and an M3 source terminal. The cascode current buffer may include a fourth transistor M4 416 having at least three terminals: an M4 gate terminal, an M4 drain terminal, and an M4 source terminal. In some exemplary implementations, the M3 source terminal may be connected to the core first output terminal, and the M4 source terminal may be connected to the core second output terminal. In some exemplary implementations, the M3 gate terminal may be connected to the M4 gate terminal and the cascode bias control terminal V CAS It can be connected to.

[0037] In some exemplary implementations, circuit 401 may include an output network 408 having an output transformer 414 with a single-grip terminal 1 and a single-grip terminal 2. In some exemplary implementations, the output transformer 414 may include a primary center tap terminal. In some exemplary implementations, single-grip terminal 1 may be connected to the M3 drain terminal, and single-grip terminal 2 may be connected to the M4 drain terminal. In some exemplary implementations, the primary center tap terminal may be connected to the supply voltage VDD. PA It can be configured to receive a cascode bias control terminal V CAS This can be configured to control a second bias voltage applied to the M1 and M2 drain terminals. In some exemplary implementations, the second bias voltage is the supply voltage VDD PA It can be derived from this.

[0038] As shown in Figure 4B, the circuit 401 may include a transformer 420 having a single terminal 1, a single terminal 2, and a primary center tap terminal, and an interstage matching network 406 which may include a secondary first terminal, a secondary second terminal, and a secondary center tap terminal. In some exemplary implementations, the secondary first terminal may be connected to the first end of a second transmission line section T2 210, and the secondary second terminal may be connected to the first end of a fourth transmission line section T4 214. In some exemplary implementations, the secondary center tap terminal may be connected to the VGS PA It can be configured to receive a bias voltage.

[0039] A common source driver 404 may communicate with the interstage matching network 406 and may include a fifth transistor M5 422 having at least three terminals: an M5 gate terminal, an M5 drain terminal, and an M5 source terminal.

[0040] In some exemplary implementations, the common source driver 404 may include a sixth transistor M6 424 having at least three terminals: an M6 gate terminal, an M6 drain terminal, and an M6 source terminal. In some exemplary implementations, the common source driver 404 may include a gate resistor 414 having a first end and a second end. In some exemplary implementations, the M5 source terminal and the M6 ​​source terminal may be grounded, and the M5 drain terminal may be connected to a single-ply terminal 1 of the interstage matching network 406 and capacitively coupled to the M6 ​​gate terminal. In some exemplary implementations, the M6 ​​drain terminal may be connected to a single-ply terminal 2 of the interstage matching network 406 and capacitively coupled to the M5 gate terminal. In some exemplary implementations, the M5 gate terminal may be connected to the first end of the gate resistor 414, and the M6 ​​gate terminal may be connected to the second end of the gate resistor 414. In some exemplary implementations, the gate resistor 414 may be selected to optimize the input impedance of the driver stage 404, for example, by minimizing the S11 (input reflection) parameter.

[0041] A specific exemplary implementation of the disclosed technology is a VDD connected to the primary center tap terminal of the interstage matched network converter 420. DR It may include terminals and be configured to receive the supply voltage to the common source driver 404 circuit.

[0042] In some exemplary implementations, the input side of the power amplifier circuit 401 (shown on the left in Figure 4B) may include an input matching network 402 which may include an input transformer 414 having a primary terminal 1, a primary terminal 2, a secondary terminal 1, and a secondary terminal 2. In one exemplary implementation of the disclosed technology, one or more of the RF input terminals may be capacitively coupled to the primary terminals of the input transformer 414. In some exemplary implementations, the transformer 414 may be a VGS for biasing the gate-source of M5 422 and M6 242 in the driver section 404. DR It may include a secondary center-tapped terminal that can be connected to the bias input terminal. In some exemplary implementations, the secondary first terminal of the transformer 414 may be connected to the first end of the gate resistor 414, and the secondary second terminal may be connected to the second end of the gate resistor 414. In one exemplary implementation, the gate resistor 414 may be approximately 550 ohms. A gate resistor 414 with a different resistance value may be used as needed.

[0043] In some exemplary implementations, the input matching network 402 may be configured as a single-ended RF input (referenced to ground), as shown in the illustration. Alternatively, the input ground connection may be open, and the secondary first input of the input transformer 414 may be connected to another RF input connection 410 to accept a balanced input (or an input signal not referenced to ground). Similarly, on the output side (right end), the output network 408 may be configured as a single-ended RF output referenced to ground (as shown in the illustration), or the output ground connection may be open, and the corresponding output transformer terminal may be connected to a second RF output connection 412 to provide an output that is not referenced to ground, for example, balanced, floating, and / or otherwise.

[0044] Compared to conventional capacitive coupling networks, the coupled transmission lines (T1 208 coupled to T2 210, and T3 212 coupled to T4 214) can be configured to account for all routing parasiticities and can be optimized for desired amplitude / phase coupling with flexibility. Furthermore, this input coupling network 206 naturally provides appropriate DC bias to each transistor M1 202 and M2 204 device terminal (assuming the interstage matching transformer 420 provides DC gate bias via the center tap) without requiring additional passive elements.

[0045] According to some exemplary implementations of the disclosed technology, neutralizing capacitors may be used in one or more of the driver 404 and / or dual-drive PA core 200 stages to enhance stability and gain. In some exemplary implementations, the input matching network 402 may include additional capacitors and gate resistor terminations for broadband S11 matching. According to some exemplary implementations of the disclosed technology, the interstage matching network 406 may use a single transformer 420 without gate reverse Qing resistors, due to the lower real impedance at the dual-drive PA core inputs (748Ω for CS and 36Ω for dual-drive PA).

[0046] Based on large-signal CW simulations, the drain efficiency, OP1dB, and Psat of a dual-drive PA core may increase as the coupling coefficient α increases. Conversely, as α increases, the power gain may decrease due to the reduction in PA core input impedance and source inductance degeneracy. Therefore, there may be an optimal dual-drive operating region where the gain is sufficient to maintain the overall PA PAE. According to some exemplary implementations of the disclosed technology, α may be chosen to be 0.35.

[0047] Using a 45nm SOI CMOS process, 1.3 × 1.2 mm 2A prototype of the disclosed dual-drive PA with a total area of ​​[specified area] was manufactured. A maximum OP1dB of 19.1dBm was achieved at 31GHz, with less than 1dB variation from 23GHz to 34GHz.

[0048] The dual-drive PA prototype disclosed herein is capable of achieving a maximum PAE of 50% (PAEmax) and a maximum DE of 59.7% (DEmax) at 29 GHz, which are the highest PAE and DE reported for a two-stage PA in silicon. From 24 GHz to 35 GHz, the PA also maintains a PAEmax of ≥ 40%. OP1dB and Psat are within 1 dB across the entire bandwidth, and the maximum PAE at OP1dB (PAEOP1dB) is 47.4%.

[0049] Tests of single-carrier signals and 5G NR FR2 modulation without DPD from 24GHz to 36GHz for 1.7 / 1.9V VDD showed that the disclosed technology provided the highest measured performance for average Pout / PAE (Pavg / PAEavg), which was 15.05dBm / 30.13% for a 1.5GSym / s 64-QAM signal with -25dB rms EVM at 30GHz for a 1.9V supply voltage. The best measured performance for Pavg / PAEavg was 11.39dBm / 16.98% for a 5G NR FR2 200MHz 1-CC 64-QAM signal with -25dB rms EVM at 30GHz for a 1.9V supply voltage.

[0050] Tables 1A, 1B, and 1C in the Appendix summarize the performance results of the dual-drive PA technology disclosed herein against previous studies. Specific exemplary implementations of the disclosed technology support highly efficient, linear, broadband modulation, demonstrating superior performance compared to conventional PAs and highlighting the suitability of the disclosed dual-drive PA for high-reliability applications.

[0051] It should be understood that the embodiments and claims disclosed herein are not limited in their application to the structural and arrangement details of the components described in the description and shown in the drawings. Rather, the description and drawings provide examples of conceivable embodiments. The embodiments and claims disclosed herein are further possible in other embodiments and can be practiced and executed in various ways. It should also be understood that the expressions and terms used herein are for illustrative purposes only and should not be considered to limit the scope of the claims.

[0052] Therefore, those skilled in the art will understand that the concepts on which this application and claims are based can be readily used as the basis for the design of other structures, methods, and systems to accomplish some of the embodiments and objectives of the claims presented herein. It is therefore important that the claims be considered to include such equivalent configurations.

[0053] (appendix) [Table 1A] [1] T. Li et al., "A Continuous-Mode Harmonically Tuned 19-to-29.5GHz Ultra-Linear PA Supporting 18Gb / s at 18.4% Modulation PAE and 43.5% Peak PAE", ISSCC, pp. 410-412, February 2018. [2] K. Ning and JF Buckwalter, "A 28-GHz, 18-dBm, 48% PAE Stacked-FET Power Amplifier with Coupled-Inductor Neutralization in 45-nm SOI CMOS", 2018 IEEE Symposium on Integrated Circuits and Technologies for BiCMOS and Compound Semiconductors (BCICTS), 2018, pp. 85-88, DOI: 10.1109 / BCICTS.2018.8550832 [Table 1B] [3] F. Wang et al., "A Highly Linear Super-Resolution Mixed-Signal Doherty Power Amplifier for High-Efficiency mm-Wave 5G Multi-Gb / s Communications", ISSCC, pp. 88-99, February 2019. [4] S. Ali et al., "A 28GHz 41%-PAE Linear CMOS Power Amplifier Using a Transformer-Based AM-PM Distortion-Correction Technique for 5G Phased Arrays," ISSCC, pp. 406-408, February 2018. [5] M. Vigilante and P. Reynaert, "A Wideband Class-AB Power Amplifier With 29-57-GHz AM-PM Compensation in 0.9-V 28-nm Bulk CMOS," IEEE JSSC, Vol. 53, No. 5, pp. 1288-1301, May 2018. [Table 1C] [6] S. Shakib, M. Elkhholy, J. Dunmorth, V. Aparin, and K. Entesari, "2.7 a wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS", 2017 IEEE International Solid State Circuits Conference (ISSCC), 2017, pp. 44-45, DOI code: 10.1109 / ISSCC.2017, 7870252 [7] F. Wang and H. Wang, "An Instantaneously Broadband Ultra-Compact Highly Linear PA with Compensated Distributed-Balun Output Network Achieving >17.8dBm P1dB and >36.6% PAEP1dB over 24 to 40GHz and Continuously Supporting 64- / 256-QAM 5G NR Signals over 24 to 42GHz", ISSCC, pp. 372-374, February 2020.

Claims

1. Dual-drive power amplifier core, The first transistor M1 is, M1 gate terminal, M1 drain terminal, and A first transistor M1 having an M1 source terminal, The core first output terminal Vout+ is configured to be connected to the M1 drain terminal, The second transistor M2 is, M2 gate terminal, M2 drain terminal, and A second transistor M2 having an M2 source terminal, The core's second output terminal Vout- is configured to be connected to the M2 drain terminal, It is a transmission line coupler, A first transmission line coupler, A first transmission line section T1 having a first grounded end and a second end connected to the M1 source terminal, A first transmission line coupler having a first end configured to receive a core first input signal Vin+, and a second end connected to the M2 gate terminal and coupled to the M1 drain terminal, A second transmission line coupler, A third transmission line section T3 having a first grounded end and a second end connected to the M2 source terminal, A second transmission line coupler having a fourth transmission line section T4 having a first end configured to receive a core second input signal Vin- and a second end connected to the M1 gate terminal and coupled to the M2 drain terminal, Equipped with, The first core output terminal Vout+ and the second core output terminal Vout- are configured to output an amplified differential signal corresponding to the difference between the first core input signal Vin+ and the second core input signal Vin-. The first transmission line section T1 is electromagnetically coupled to the second transmission line section T2. A dual-drive power amplifier core, wherein the third transmission line section T3 is electromagnetically coupled to the fourth transmission line section T4.

2. A cascode current buffer, A cascode bias control terminal is configured to control the bias voltage applied to the M1 drain terminal and the M2 drain terminal, The third transistor M3, M3 gate terminal, M3 drain terminal, and A third transistor M3 having an M3 source terminal, The fourth transistor is M4, M4 gate terminal, M4 drain terminal, and A fourth transistor M4 having an M4 source terminal, It further includes a cascode current buffer equipped with, The M3 source terminal is connected to the core first output terminal Vout+. The M4 source terminal is connected to the core second output terminal Vout-, The dual-drive power amplifier core according to claim 1, wherein the M3 gate terminal is connected to the M4 gate terminal and the cascode bias control terminal.

3. The output transformer further comprises a single-stage 1-terminal, a single-stage 2-terminal, and a primary center-tapped terminal. The aforementioned terminal 1 is connected to the M3 drain terminal, The aforementioned single-ended terminal 2 is connected to the M4 drain terminal, The primary center tap terminal is supplied with voltage V ＤＤ It is configured to receive, The cascode bias control terminal is configured to control the bias voltage applied to the M1 drain terminal and the M2 drain terminal. The bias voltage is the supply voltage V ＤＤ A dual-drive power amplifier core according to claim 2, derived from the above.

4. The output transformer has a single-stage terminal 1, a single-stage terminal 2, and a primary center tap terminal, and the interstage matching network further comprises a secondary first terminal, a secondary second terminal, and a secondary center tap terminal. The secondary first terminal is connected to the first end of the second transmission line section T2. The secondary second terminal is connected to the first end of the fourth transmission line section T4. The dual drive power amplifier core according to claim 1, wherein the secondary center tap terminal is configured to receive a bias voltage.

5. It is a common source driver, The fifth transistor is M5, M5 gate terminal, M5 drain terminal, and A fifth transistor M5 having an M5 source terminal, The sixth transistor is M6, M6 gate terminal, M6 drain terminal, and A sixth transistor M6 having an M6 source terminal, A common source driver further comprises a gate resistor having a first end and a second end, The M5 source terminal and the M6 ​​source terminal are connected to ground. The M5 drain terminal is connected to the single-stage terminal 1 of the interstage matching network and is coupled to the M6 ​​gate terminal. The M6 ​​drain terminal is connected to the single-stage 2 terminal of the interstage matching network and is capacitively coupled to the M5 gate terminal. The M5 gate terminal is connected to the first end of the gate resistor, The dual-drive power amplifier core according to claim 4, wherein the M6 ​​gate terminal is connected to the second end of the gate resistor.

6. V is connected to the primary center tap terminal of the interstage matching network and is configured to receive the supply voltage to the common source driver. ＤＤ The dual drive power amplifier core according to claim 5, further comprising terminals.

7. The dual drive power amplifier core according to claim 5, further comprising an input balun network having a single-stage terminal 1, a single-stage terminal 2, a secondary first terminal, a secondary second terminal, and a secondary center tap terminal connected to a third bias input terminal, wherein the secondary first terminal is connected to the first end of the gate resistor, the secondary second terminal is connected to the second end of the gate resistor, and the single-stage terminal 1 is capacitively coupled to a first RF input terminal configured to receive a first RF input signal.

8. The dual-drive power amplifier core according to claim 7, wherein the two single-grip terminals of the input balun network are connected to ground and coupled to the one single-grip terminal, and the first RF input terminal is configured to receive an unbalanced RF input signal.

9. The dual-drive power amplifier core according to claim 7, wherein the two single-transition terminals of the input balun network are capacitively coupled to the second RF input terminal and the one single-transition terminal, and the first RF input terminal and the second RF input terminal are configured to receive a balanced RF signal.

10. The dual-drive power amplifier core according to claim 1, wherein the second end of the second transmission line section T2 is capacitively coupled to the M1 drain terminal, and the second end of the fourth transmission line section T4 is capacitively coupled to the M2 drain terminal.

11. The dual-drive power amplifier core according to claim 1, further comprising a signal crossover region configured to cross-route the second transmission line section T2 and the fourth transmission line section T4.

12. The dual-drive power amplifier core according to claim 1, wherein the second transmission line section T2 is stacked on the first transmission line section T1, and the fourth transmission line section T4 is stacked on the third transmission line section T3.

13. The dual-drive power amplifier core according to claim 1, wherein the first transistor M1 and the second transistor M2 are fabricated using one or more of the bulk CMOS, CMOS SOI, GaAs, and GaN processes.

14. The first end of the second transmission line section T2 is further configured to receive a first bias voltage, The first end of the fourth transmission line section T4 is further configured to receive the first bias voltage, The core's first output terminal Vout+, connected to the M1 drain terminal, is further configured to receive a second bias voltage. The dual-drive power amplifier core according to claim 1, wherein the core's second output terminal Vout- connected to the M2 drain terminal is further configured to receive the second bias voltage.

15. The dual-drive power amplifier core according to claim 1, wherein the first transistor and the second transistor constitute a transistor differential pair, and the transistor differential pair is configured to be driven with a phase difference at the gate terminal and source terminal.

16. The first transmission line coupler and the second transmission line coupler constitute a coupling network. The connected network is, In the gate and source terminals of the transistor differential pair, the core is driven with a phase shift. To enable the source and drain terminals of the transistor differential pair to swing in phase, A non-zero DC voltage is provided to each of the gate terminals, and a DC ground is provided to each of the source terminals. A dual drive power amplifier core according to claim 15, configured to perform one or more of the following.

17. The second end of the first transmission line section T1 is V Ｓ１ It is configured to output a signal, The second end of the second transmission line section T2 is V Ｇ２ It is configured to output a signal, The second end of the third transmission line section T3 is V Ｓ２ It is configured to output a signal, The second end of the fourth transmission line section T4 is V Ｇ１ It is configured to output a signal, The electromagnetic coupling between the first transmission line section T1 and the second transmission line section T2 is configured to generate the VS1 signal in response to the reception of the input signal Vin+ at the first end of the second transmission line section T2. The electromagnetic coupling between the third transmission line section T3 and the fourth transmission line section T4 occurs in response to the reception of the input signal Vin- at the first end of the fourth transmission line section T4, V Ｇ１ A dual-drive power amplifier core according to claim 1, configured to generate a signal.

18. The transmission line coupler further includes a signal crossover region configured to cross-route the V Ｇ１ signal and the V Ｇ２ signal to pair the V Ｇ１ signal and the V Ｇ２ signal with the V Ｓ１ signal and the V Ｓ２ signal, respectively. The dual-drive power amplifier core according to claim 17.

19. The dual-drive power amplifier core according to claim 17, wherein the second transmission line section T2 is stacked on the first transmission line section T1, and the fourth transmission line section T4 is stacked on the third transmission line section T3.

20. The dual-drive power amplifier core according to claim 19, wherein the second transmission line section T2 is configured to couple the Vin+ signal to the first transmission line section T1 with a coupling coefficient based on physical parameters including the length of the transmission lines, the width of the transmission lines, and the gap between the transmission lines.

21. The aforementioned coupling coefficient is, ０～１、 ０．２～０．６、 0.3 to 0.4, or A dual-drive power amplifier core according to claim 20, having one or more ranges from 0.5 to 0.

8.

22. The dual-drive power amplifier core according to claim 19, wherein the fourth transmission line section T4 is configured to couple the Vin- signal to the third transmission line section T3 with a coupling coefficient based on physical parameters including the length of the transmission lines, the width of the transmission lines, and the gap between the transmission lines.

23. The aforementioned coupling coefficient is, ０～１、 ０．２～０．６、 0.3 to 0.4, or A dual-drive power amplifier core according to claim 22, having one or more ranges from 0.5 to 0.8.

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