Measurement method and measuring device

Abstract

To provide a measurement method and a measurement device capable of suppressing deterioration in reliability of a display device.SOLUTION: A measurement method includes the steps of: forming a partition wall having a lower portion disposed on a base material and an upper portion protruding from a side surface of the lower portion; acquiring a first image for each element constituting the partition wall generated by irradiating the partition wall with electron beams; analyzing the acquired first image for each acquired element; and measuring an amount of protrusion of the upper portion from a side surface of the lower portion based on analysis results.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] Embodiments of the present invention relate to a measurement method and a measurement device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use.

[0003] By the way, the above-described display device is manufactured using each of the display panels cut from a mother substrate on which a plurality of display panels are formed.

[0004] In the process of manufacturing such a display device, a technique for suppressing a decrease in the reliability of the display device is required.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Summary of the Invention

Problems to be Solved by the Invention

[0006] The object of the present invention is to provide a measurement method and a measurement apparatus that can suppress the deterioration of the reliability of a display device. [Means for solving the problem]

[0007] The measurement method according to the embodiment comprises forming a partition wall having a lower part placed on a substrate and an upper part protruding from the side surface of the lower part; acquiring a first image of each element constituting the partition wall generated by irradiating the partition wall with an electron beam; analyzing the acquired first image of each element; and measuring the amount of protrusion of the upper part protruding from the side surface of the lower part based on the analysis results. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device in an embodiment. [Figure 2] Figure 2 shows an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the partition wall. [Figure 5] Figure 5 is a schematic cross-sectional view illustrating a display element formed using a partition wall. [Figure 6] Figure 6 is a schematic cross-sectional view illustrating a display element formed using a partition wall. [Figure 7] Figure 7 is a schematic cross-sectional view illustrating a display element formed using a partition wall. [Figure 8] Figure 8 is a diagram illustrating a motherboard inspection device used in the manufacturing process of a display device. [Figure 9] Figure 9 is a diagram illustrating the configuration of the EDX device. [Figure 10] Figure 10 shows an example of the hardware configuration of a measuring device. [Figure 11] FIG. 11 is a diagram showing an example of the functional configuration of the measuring device. [Figure 12] FIG. 12 is a flowchart showing an example of the processing procedure of the measuring device. [Figure 13] FIG. 13 is a diagram showing an example of an image of aluminum. [Figure 14] FIG. 14 is a diagram showing an example of an image of titanium. [Figure 15] FIG. 15 is a diagram showing a superposition of a part of an image of aluminum and a part of an image of titanium. [Figure 16] FIG. 16 is a diagram showing an example of an image of silicon.

MODE FOR CARRYING OUT THE INVENTION

[0009] One embodiment will be described with reference to the drawings. The disclosure is merely an example, and for those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the invention, they are naturally included in the scope of the present invention. Also, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but it is merely an example and does not limit the interpretation of the present invention. Also, in this specification and each drawing, components that exhibit the same or similar functions as those described above for the already shown drawings may be assigned the same reference numerals, and detailed descriptions that overlap may be omitted as appropriate.

[0010] In addition, in the drawings, for the purpose of facilitating understanding as necessary, the X-axis, Y-axis, and Z-axis that are perpendicular to each other are described. The direction along the X-axis is referred to as direction X, the direction along the Y-axis is referred to as direction Y, and the direction along the Z-axis is referred to as direction Z. Also, looking at various elements parallel to direction Z is referred to as a plan view.

[0011] The display device in this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, and mobile phone terminals.

[0012] Figure 1 shows an example of the configuration of a display device DSP in this embodiment. The display device DSP has a display area DA for displaying an image and a non-display area NDA surrounding the display area DA, on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the base material 10 in plan view is rectangular. However, the shape of the base material 10 in plan view is not limited to a rectangle; it may be a square, circle, ellipse, or other shape.

[0014] The display area DA comprises multiple pixels PX arranged in a matrix in directions X and Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Pixel PX may also include sub-pixels SP of other colors, such as white, along with sub-pixels SP1, SP2, and SP3. Furthermore, pixel PX may include sub-pixels SP of other colors in place of any of sub-pixels SP1, SP2, and SP3.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element 20 driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element 20.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown in Figure 1. The pixel circuit 1 may, for example, include more thin-film transistors and capacitors.

[0018] The display element 20 is an organic light-emitting diode (OLED) as a light-emitting element. For example, sub-pixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, sub-pixel SP2 is equipped with a display element 20 that emits light in the green wavelength range, and sub-pixel SP3 is equipped with a display element 20 that emits light in the blue wavelength range.

[0019] Figure 1 shows a display panel mainly used in the manufacture of a display device DSP. This display device DSP has a structure in which a circuit board or the like, which includes a driver (driver IC chip) for driving the display panel, is connected to the display panel.

[0020] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example shown in Figure 2, sub-pixels SP1 and SP2 are aligned in the Y direction. Furthermore, sub-pixels SP1 and SP2 are aligned with sub-pixel SP3 in the X direction.

[0021] When the sub-pixels SP1, SP2, and SP3 are arranged as shown in Figure 2, the display area DA forms columns in which sub-pixels SP1 and SP2 are arranged alternately in the Y direction, and columns in which multiple sub-pixels SP3 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction.

[0022] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example shown in Figure 2. As another example, the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the direction X.

[0023] The display area DA has ribs 5 and partition walls 6. Ribs 5 have apertures AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. In the example shown in Figure 2, aperture AP2 is larger than aperture AP1, and aperture AP3 is larger than aperture AP2. Partition walls 6 are positioned at the boundary between adjacent sub-pixels SP and overlap with ribs 5 in a plan view.

[0024] The partition wall 6 has a plurality of first partition walls 6x extending in direction X and a plurality of second partition walls 6y extending in direction Y. The plurality of first partition walls 6x are arranged between adjacent openings AP1 and AP2 in direction Y, and between two adjacent openings AP3 in direction Y. The second partition walls 6y are arranged between adjacent openings AP1 and AP3 in direction X, and between adjacent openings AP2 and AP3 in direction X.

[0025] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole is a grid that surrounds the openings AP1, AP2, and AP3. The partition wall 6 can also be said to have openings in the sub-pixels SP1, SP2, and SP3, similar to the rib 5.

[0026] In other words, in this embodiment, the rib 5 and the partition wall 6 are arranged to partition the sub-pixels SP1, SP2, and SP3.

[0027] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with aperture AP3. In the example shown in Figure 2, the outer shapes of upper electrode UE1 and organic layer OR1 are the same, the outer shapes of upper electrode UE2 and organic layer OR2 are the same, and the outer shapes of upper electrode UE3 and organic layer OR3 are the same.

[0028] The lower electrode LE1, upper electrode UE1, and organic layer OR1 constitute the display element 20 of the sub-pixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 constitute the display element 20 of the sub-pixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 constitute the display element 20 of the sub-pixel SP3.

[0029] The lower electrode LE1 is connected to the pixel circuit 1 that drives the sub-pixel SP1 (display element 20) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 that drives the sub-pixel SP2 (display element 20) through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 that drives the sub-pixel SP3 (display element 20) through the contact hole CH3.

[0030] In the example shown in Figure 2, contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent openings AP1 and AP2 in direction Y. Contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent openings AP3 in direction Y. In another example, at least a portion of contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0031] In the example shown in Figure 2, the lower electrodes LE1 and LE2 each have protrusions PR1 and PR2. Protrusion PR1 projects from the main body of the lower electrode LE1 (the part overlapping with the opening AP1) toward the contact hole CH1. Protrusion PR2 projects from the main body of the lower electrode LE2 (the part overlapping with the opening AP2) toward the contact hole CH2. Contact holes CH1 and CH2 overlap with protrusions PR1 and PR2, respectively.

[0032] Figure 3 is a schematic cross-sectional view of a display device DSP along the line III-III in Figure 2. In the display device DSP, an insulating layer 11 called an undercoat layer is placed on the substrate 10 (on the surface where the display elements 20 etc. are arranged).

[0033] The insulating layer 11 has a three-layer laminated structure, for example, consisting of a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxide film (SiO). However, the insulating layer 11 is not limited to a three-layer laminated structure; it may have a laminated structure with more than three layers, or it may have a single-layer structure or a two-layer laminated structure.

[0034] A circuit layer 12 is placed on top of the insulating layer 11. The circuit layer 12 has various circuits and wiring that drive the sub-pixels SP (SP1, SP2, and SP3), such as the pixel circuit 1 shown in Figure 1, scan line GL, signal line SL, and power line PL. The circuit layer 12 is covered by an insulating layer 13.

[0035] The insulating layer 13 functions as a planarizing film that flattens the irregularities caused by the circuit layer 12. Although not shown in Figure 3, the contact holes CH1, CH2, and CH3 described above are provided in the insulating layer 13.

[0036] The lower electrodes LE (LE1, LE2, and LE3) are positioned on the insulating layer 13. The ribs 5 are positioned on the insulating layer 13 and the lower electrodes LE. The ends (partially) of the lower electrodes LE are covered by the ribs 5.

[0037] The bulkhead 6 has a lower part 61 positioned on the rib 5 and an upper part 62 that covers the upper surface of the lower part 61. The upper part 62 has a greater width in directions X and Y than the lower part 61. As a result, the bulkhead 6 has a shape in which both ends of the upper part 62 protrude beyond the sides of the lower part 61. This shape of the bulkhead 6 can also be described as overhanging.

[0038] The organic layers OR (OR1, OR2, and OR3) and upper electrodes UE (UE1, UE2, and UE3), together with the lower electrodes LE (LE1, LE2, and LE3) described above, constitute the display element 20. As shown in Figure 3, the organic layer OR1 includes a first organic layer OR1a and a second organic layer OR1b that are spaced apart from each other. The upper electrode UE1 includes a first upper electrode UE1a and a second upper electrode UE1b that are spaced apart from each other. The first organic layer OR1a contacts the lower electrode LE1 through the opening AP1 and covers a part of the rib 5. The second organic layer OR1b is located above the upper part 62. The first upper electrode UE1a faces the lower electrode LE1 and covers the first organic layer OR1a. Furthermore, the first upper electrode UE1a is in contact with the side surface of the lower part 61. The second upper electrode UE1b is located above the partition wall 6 and covers the second organic layer OR1b.

[0039] Furthermore, as shown in Figure 3, the organic layer OR2 includes a first organic layer OR2a and a second organic layer OR2b that are spaced apart from each other. The upper electrode UE2 includes a first upper electrode UE2a and a second upper electrode UE2b that are spaced apart from each other. The first organic layer OR2a contacts the lower electrode LE2 through the opening AP2 and covers a portion of the rib 5. The second organic layer OR2b is located above the upper part 62. The first upper electrode UE2a faces the lower electrode LE2 and covers the first organic layer OR2a. In addition, the first upper electrode UE2a contacts the side surface of the lower part 61. The second upper electrode UE2b is located above the partition wall 6 and covers the second organic layer OR2b.

[0040] Furthermore, as shown in Figure 3, the organic layer OR3 includes a first organic layer OR3a and a second organic layer OR3b that are spaced apart from each other. The upper electrode UE3 includes a first upper electrode UE3a and a second upper electrode UE3b that are spaced apart from each other. The first organic layer OR3a contacts the lower electrode LE3 through the opening AP3 and covers a portion of the rib 5. The second organic layer OR3b is located above the upper part 62. The first upper electrode UE3a faces the lower electrode LE3 and covers the first organic layer OR3a. In addition, the first upper electrode UE3a contacts the side surface of the lower part 61. The second upper electrode UE3b is located above the partition wall 6 and covers the second organic layer OR3b.

[0041] In the example shown in Figure 3, the sub-pixels SP1, SP2, and SP3 include cap layers CP1, CP2, and CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, and OR3.

[0042] The cap layer CP1 includes a first cap layer CP1a and a second cap layer CP1b that are spaced apart from each other. The first cap layer CP1a is located at the opening AP1 and is positioned above the first upper electrode UE1a. The second cap layer CP1b is located above the partition wall 6 and is positioned above the second upper electrode UE1b.

[0043] The cap layer CP2 includes a first cap layer CP2a and a second cap layer CP2b that are spaced apart from each other. The first cap layer CP2a is located at the opening AP2 and is positioned above the first upper electrode UE2a. The second cap layer CP2b is located above the partition wall 6 and is positioned above the second upper electrode UE2b.

[0044] The cap layer CP3 includes a first cap layer CP3a and a second cap layer CP3b that are spaced apart from each other. The first cap layer CP3a is located at the opening AP3 and is positioned above the first upper electrode UE3a. The second cap layer CP3b is located above the partition wall 6 and is positioned above the second upper electrode UE3b.

[0045] Sub-pixels SP1, SP2, and SP3 are each provided with sealing layers SE1, SE2, and SE3, respectively. Sealing layer SE1 continuously covers each component of sub-pixel SP1, including the first cap layer CP1a, partition wall 6, and second cap layer CP1b. Sealing layer SE2 continuously covers each component of sub-pixel SP2, including the first cap layer CP2a, partition wall 6, and second cap layer CP2b. Sealing layer SE3 continuously covers each component of sub-pixel SP3, including the first cap layer CP3a, partition wall 6, and second cap layer CP3b.

[0046] In the example shown in Figure 3, the second organic layer OR1b, second upper electrode UE1b, second cap layer CP1b, and sealing layer SE1 on the partition wall 6 between sub-pixels SP1 and SP3 are separated from the second organic layer OR3b, second upper electrode UE3b, second cap layer CP3b, and sealing layer SE3 on the same partition wall 6. Similarly, the second organic layer OR2b, second upper electrode UE2b, second cap layer CP2b, and sealing layer SE2 on the partition wall 6 between sub-pixels SP2 and SP3 are separated from the second organic layer OR3b, second upper electrode UE3b, second cap layer CP3b, and sealing layer SE3 on the same partition wall 6.

[0047] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 14. The resin layer 14 is covered by a sealing layer 15. Furthermore, the sealing layer 15 is covered by a resin layer 16.

[0048] The insulating layer 13 and the resin layers 14 and 16 are made of organic material. The ribs 5, the sealing layer 15, and the SEs (SE1, SE2, and SE3) are made of inorganic material such as silicon nitride (SiNx).

[0049] The lower portion 61 of the partition wall 6 is conductive. The upper portion 62 of the partition wall 6 may also be conductive. The lower electrode LE may be formed of a transparent conductive oxide such as ITO (Indium Tin Oxide), or it may have a laminated structure of a metallic material such as silver (Ag) and a conductive oxide. The upper electrode UE is formed of a metallic material such as an alloy of magnesium and silver (MgAg). The upper electrode UE may also be formed of a conductive oxide such as ITO.

[0050] When the potential of the lower electrode LE is relatively higher than the potential of the upper electrode UE, the lower electrode LE corresponds to the anode and the upper electrode UE corresponds to the cathode. Conversely, when the potential of the upper electrode UE is relatively higher than the potential of the lower electrode LE, the upper electrode UE corresponds to the anode and the lower electrode LE corresponds to the cathode.

[0051] The organic layer OR includes a pair of functional layers and an emissive layer disposed between these functional layers. As an example, the organic layer OR has a structure in which a hole injection layer, a hole import layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in that order.

[0052] The cap layer CP (CP1, CP2, and CP3) is formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. Furthermore, these multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrode UE and also different from the materials of the sealing layer SE. Note that the cap layer CP may be omitted.

[0053] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE (first upper electrodes UE1a, UE2a, and UE3a) that are in contact with the side surface of the lower part 61. Pixel voltages are supplied to the lower electrodes LE (LE1, LE2, and LE3) through the pixel circuits 1 of the sub-pixels SP (SP1, SP2, and SP3).

[0054] When a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the first organic layer OR1a emits light in the red wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the first organic layer OR2a emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the first organic layer OR3a emits light in the blue wavelength range.

[0055] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0056] Figure 4 is a schematic enlarged cross-sectional view of the partition wall 6. In Figure 4, elements other than the rib 5, partition wall 6, insulating layer 13, and the pair of lower electrodes LE are omitted. The pair of lower electrodes LE correspond to any of the lower electrodes LE1, LE2, and LE3 described above. Furthermore, the first partition wall 6x and the second partition wall 6y described above have the same structure as partition wall 6 shown in Figure 4.

[0057] In the example shown in Figure 4, the lower part 61 of the partition wall 6 includes a barrier layer 611 placed on the rib 5 and a metal layer 612 placed on the barrier layer 611. The barrier layer 611 is made of a different material from the metal layer 612, and is made of a metallic material such as molybdenum. The metal layer 612 is made thicker than the barrier layer 611. The metal layer 612 may be a single layer or a laminated structure of different metallic materials. As an example, the metal layer 612 may be made of aluminum (Al).

[0058] The upper part 62 is thinner than the lower part 61. In the example shown in Figure 4, the upper part 62 includes a first layer 621 placed on top of the metal layer 612 and a second layer 622 placed on top of the first layer 621. For example, the first layer 621 is made of titanium (Ti), and the second layer 622 is made of ITO. Here, the upper part 62 has been described as having a two-layer laminated structure, but the upper part 62 may also be a single-layer structure made of a metallic material such as titanium. Furthermore, the upper part 62 may be made of a material other than a metallic material, such as an inorganic material such as silicon oxide (SiO). Moreover, the upper part 62 may be laminated by appropriately combining conductive oxides such as ITO, metallic materials such as titanium, and inorganic materials such as silicon oxide, or it may be a single layer made of any of the above materials.

[0059] In the example shown in Figure 4, the width of the lower part 61 decreases as it approaches the upper part 62. That is, the sides 61a and 61b of the lower part 61 are inclined with respect to direction Z. The upper part 62 has an end 62a that protrudes from the side 61a and an end 62b that protrudes from the side 61b.

[0060] The amount D by which the ends 62a and 62b protrude from the sides 61a and 61b (hereinafter referred to as the protrusion amount D of the partition wall 6) is, for example, 2.0 μm or less. In this embodiment, the protrusion amount D of the partition wall 6 corresponds to the length (distance) in the width direction (direction X or direction Y) perpendicular to the direction Z of the partition wall 6 between the lower ends (barrier layer 611) of the sides 61a and 61b and the ends 62a and 62b. Alternatively, the protrusion amount D of the partition wall 6 may be the length in the width direction perpendicular to the direction Z of the partition wall 6 between the upper ends of the sides 61a and 61b and the ends 62a and 62b.

[0061] The structure of the partition wall 6 and the materials of each part of the partition wall 6 may be appropriately selected, taking into consideration, for example, the method of forming the partition wall 6.

[0062] In this embodiment, the partition wall 6 is formed to partition the sub-pixels SP in a plan view. The organic layer OR described above is formed, for example, by an anisotropic or directional vacuum deposition method. However, when the organic material for forming the organic layer OR is deposited over the entire substrate 10 with the partition wall 6 in place, the partition wall 6 has the shape shown in Figures 3 and 4, so almost no organic layer OR is formed on the sides of the partition wall 6. This makes it possible to form an organic layer OR (display element 20) that is divided into sub-pixels SP by the partition wall 6.

[0063] Figures 5 to 7 are schematic cross-sectional views illustrating the display element 20 formed using the partition wall 6. The sub-pixels SPα, SPβ, and SPγ shown in Figures 5 to 7 correspond to any of the sub-pixels SP1, SP2, and SP3.

[0064] As described above, with the partition wall 6 in place, the organic layer OR, upper electrode UE, cap layer CP, and sealing layer SE are sequentially formed on the entire substrate 10 by vapor deposition, as shown in Figure 5. The organic layer OR includes a light-emitting layer that emits light of a color corresponding to the sub-pixel SPα. The overhanging partition wall 6 divides the organic layer OR into a first organic layer ORa covering the lower electrode LE and a second organic layer ORb on the partition wall 6, the upper electrode UE into a first upper electrode UEa covering the first organic layer ORa and a second upper electrode UEb covering the second organic layer ORb, and the cap layer CP into a first cap layer CPa covering the first upper electrode UEa and a second cap layer CPb covering the second upper electrode UEb. The first upper electrode UEa is in contact with the lower part 61 of the partition wall 6. The sealing layer SE continuously covers the first cap layer CPa, the second cap layer CPb, and the partition wall 6.

[0065] Next, as shown in Figure 6, a resist R is formed on the sealing layer SE. The resist R covers the subpixel SPα. That is, the resist R is positioned directly above the first organic layer ORa, the first upper electrode UEa, and the first cap layer CPa located on the subpixel SPα. The resist R is also positioned directly above the portion of the second organic layer ORb, the second upper electrode UEb, and the second cap layer CPb on the partition wall 6 between the subpixel SPα and the subpixel SPβ that is closer to the subpixel SPα. That is, at least a portion of the partition wall 6 is exposed from the resist R.

[0066] Furthermore, etching using the resist R as a mask removes the portions of the organic layer OR, upper power UE, cap layer CP, and sealing layer SE that are exposed from the resist R, as shown in Figure 7. As a result, a display element 20 including the lower electrode LE, first organic layer ORa, first upper electrode UEa, and first cap layer CPa is formed in the sub-pixel SPα. On the other hand, the lower electrode LE is exposed in the sub-pixels SPβ and SPγ. The etching described above includes, for example, dry etching of the sealing layer SE, wet etching and dry etching of the cap layer CP, wet etching of the upper electrode UE, and dry etching of the organic layer OR.

[0067] As described above, once the display element 20 of the sub-pixel SPα is formed, the resist R is removed, and the display elements 20 of the sub-pixels SPβ and SPγ are formed sequentially, similar to the sub-pixel SPα.

[0068] As illustrated above, the sub-pixels SPα, SPβ, and SPγ are used to form the display elements 20 of sub-pixels SP1, SP2, and SP3. By further forming the resin layer 14, the sealing layer 15, and the resin layer 16, the structure of the display device DSP shown in Figure 3 is realized.

[0069] As described above, the partition wall 6 has a lower part 61 and an upper part 62 that protrudes from the side of the lower part 61. However, if the amount of protrusion D (canopy width) of the partition wall 6 is not appropriate, the reliability of the display device DSP may decrease.

[0070] Specifically, in the DSP display device, the organic layer OR is divided for each sub-pixel SP by a partition wall 6. If the protrusion amount D of the partition wall 6 is not sufficiently larger than the design value, it may not be possible to properly divide the organic layer OR. Also, if the side surface of the lower part 61 of the partition wall 6 is covered by the organic layer OR, the electrical connection between the lower part 61 and the upper electrode UE will be hindered. On the other hand, in the DSP display device, the upper electrode UE is in contact with the side surface of the lower part 61 of the partition wall 6. However, if the protrusion amount D of the partition wall 6 exceeds the design value, it may not be possible for the upper electrode UE to be in contact with the side surface of the lower part 61.

[0071] In other words, if the amount of protrusion D of the partition wall 6 is not appropriate, it is not possible to manufacture a highly reliable display device DSP. Therefore, it is useful to measure the amount of protrusion D (i.e., the length between the side surface of the lower part 61 and the end of the upper part 62 of the partition wall 6) during the manufacturing process of the display device DSP.

[0072] Incidentally, in general, the manufacturing process for a display device DSP involves manufacturing a mother board on which multiple display panels are formed on a mother board containing multiple substrates 10, and then manufacturing a display device DSP using each of the display panels cut from the mother board.

[0073] In the manufacturing process of the DSP display device described above, as shown in Figure 8, the motherboard (array board) 100 is inserted into a motherboard inspection device 300, which maintains a vacuum state via a load lock chamber 200, and the quality of the motherboard 100 is inspected in the motherboard inspection device 300.

[0074] In this case, the motherboard inspection device 300 is equipped with, for example, a scanning electron microscope (SEM), and according to the motherboard inspection device 300, it is possible to perform elemental analysis of the motherboard 100 using an energy dispersive X-ray spectroscopy (EDX) device attached to the SEM.

[0075] In this embodiment, we consider using the EDX device described above to continuously measure (inspect) the amount D of the protrusion of the partition wall 6 during flow.

[0076] Here, with reference to Figure 9, the configuration of the EDX apparatus described above will be briefly explained. As shown in Figure 9, the EDX apparatus 400 comprises a sample stage 401, an irradiator 402, and a detector 403. The irradiator 402 also comprises an electron gun 402a, a focusing lens 402b, a scanning coil 402c, and an objective lens 402d.

[0077] The electron gun 402a generates an electron beam. The focusing lens 402b and objective lens 402d focus the electron beam onto an electron spot on the sample (in this case, the motherboard 100) placed on the sample stage 401. This allows the irradiator 402 to irradiate the sample with the electron beam 404. The scanning coil 402c scans (moves) the electron spot where the electron beam is focused (i.e., the irradiation point of the electron beam 404) on the sample.

[0078] Here, as described above, the electron beam 404 irradiated onto the sample from the irradiator 402 penetrates from the surface of the sample to a predetermined depth, generating characteristic X-rays corresponding to the elements that make up the sample. These characteristic X-rays are detected by the detector 403.

[0079] The EDX device 400 performs elemental analysis (analysis of elemental components) using characteristic X-rays generated from each irradiation point of the electron beam 404 scanned over the sample, thereby identifying the elements that make up the sample. The EDX device 400 can generate an image (hereinafter referred to as an EDX image) based on the elements that make up the sample thus identified. The EDX image is equivalent to an image in which images of each element that makes up the sample are superimposed.

[0080] In this embodiment, the amount of protrusion D of the partition wall 6 is measured using the EDX image generated by the EDX device 400 as described above.

[0081] In this embodiment, the protrusion amount D of the partition wall 6 is measured by a measuring device that is communicatively connected to the EDX device 400. The measuring device may be implemented as part of the motherboard inspection device 300, or it may be implemented as a separate device from the motherboard inspection device 300. Alternatively, the measuring device may be implemented as an integral part of the EDX device 400 described above.

[0082] The measuring device according to this embodiment will be described below. Figure 10 shows an example of the hardware configuration of the measuring device.

[0083] The measuring device 500 shown in Figure 10 is implemented by, for example, a personal computer and includes a CPU 500a, non-volatile memory 500b, main memory 500c, and communication device 500d.

[0084] The CPU 500a is a processor for controlling the operation of the measuring device 500 and executes various programs loaded from the non-volatile memory 500b into the main memory 500c. The communication device 500d performs communication between the measuring device 500 and external devices (for example, the EDX device 400).

[0085] Figure 11 shows an example of the functional configuration of the measuring device 500. As shown in Figure 11, the measuring device 500 includes an image acquisition unit 501, an image analysis unit 502, and a measurement unit 503.

[0086] Furthermore, each of the parts 501 to 503 included in the measuring device 500 is a functional unit realized by, for example, the CPU 500a (i.e., the computer of the measuring device 500) executing a predetermined program (i.e., software). However, some or all of these parts 501 to 503 may be realized by hardware such as an IC (Integrated Circuit), or by a combination of software and hardware.

[0087] In this embodiment, the measuring device 500 is connected to the EDX device 400 in a communicative manner, and the image acquisition unit 501 acquires the EDX image generated by the EDX device 400 from the EDX device 400 as described above. The image analysis unit 502 analyzes the EDX image acquired by the image acquisition unit 501. The measuring unit 503 measures the amount of protrusion D of the partition wall 6 formed on the motherboard 100 as described above (i.e., the length from the side surface of the lower part 61 to the end of the upper part 62 of the partition wall 6).

[0088] Below, an example of the processing procedure of the measuring device 500 according to this embodiment will be described with reference to the flowchart in Figure 12.

[0089] First, when a motherboard 100 is manufactured on a motherboard substrate including multiple substrates 10, an insulating layer 11, a circuit layer 12, an insulating layer 13, a lower electrode LE, ribs 5, and partition walls 6 are formed on it, the motherboard 100 is inserted into a motherboard inspection device 300 via a load lock chamber 200 shown in Figure 8. In the motherboard inspection device 300, an EDX device 400 generates an EDX image and outputs the EDX image to a measuring device 500.

[0090] The EDX image output from the EDX device 400 to the measuring device 500 corresponds to an image in which images of each element, generated based on the results of analyzing multiple elements constituting the motherboard 100 (such as the partition wall 6 formed on top of it) by irradiating the motherboard 100 with an electron beam 404, are superimposed. In this embodiment, since the EDX image is used to measure the protrusion amount D of the partition wall 6, the EDX device 400 irradiates the upper part 62 of the partition wall 6 on the side opposite to the base material 10 (lower part 61) with the electron beam 404 from a direction perpendicular to the base material 10. Furthermore, this electron beam 404 is irradiated with an intensity sufficient to penetrate at least the upper part 62 of the partition wall 6 and reach the lower part 61.

[0091] In this embodiment, the EDX image (image file) is assumed to be in a file format such as JPEG, but it may be in other file formats.

[0092] As described above, the EDX image output from the EDX device 400 is acquired by the image acquisition unit 501 included in the measuring device 500 (step S1).

[0093] Next, the image acquisition unit 501 extracts images of each element constituting the partition wall 6 from the EDX image acquired in step S1 (step S2).

[0094] Here, the lower part 61 (metal layer 612) of the partition wall 6 is formed of, for example, aluminum. The upper part 62 (first layer 621) of the partition wall is formed of, for example, titanium. In this case, the image acquisition unit 501 extracts images of aluminum and titanium from the EDX image acquired in step S1.

[0095] In this embodiment, the aluminum image extracted from the EDX image corresponds to an image generated by mapping characteristic X-rays (characteristic X-rays generated from the aluminum) detected by the detector 403 in the EDX device 400 to the pixels. Similarly, the titanium image extracted from the EDX image corresponds to an image generated by mapping characteristic X-rays (characteristic X-rays generated from the titanium) detected by the detector 403 in the EDX device 400 to the pixels.

[0096] When the process in step S2 is executed, the image analysis unit 502 obtains the number of pixels corresponding to the protrusion amount D of the partition wall 6 based on the image for each element extracted in step S2 (step S3).

[0097] Here, Figure 13 shows an example of an image of aluminum. In the image of aluminum shown in Figure 13, the lower part 61 of the partition wall 6 formed by the aluminum is visualized, and from this image of aluminum, for example, the width 601 (represented by the number of pixels) in direction X in a plan view of the lower part 61 can be recognized.

[0098] Figure 14 also shows an example of an image of titanium. In the titanium image shown in Figure 14, the upper part 62 of the partition wall 6 formed by the titanium is visualized, and from this image of titanium, for example, the width 602 (representing the number of pixels) in direction X in a plan view of the upper part 62 can be recognized.

[0099] In this case, the image analysis unit 502 can obtain the number of pixels corresponding to the protrusion amount D of the partition wall 6 based on the difference between the width 601 in the direction X of the lower part 61 recognized from the aluminum image and the width 602 in the direction X of the upper part 62 recognized from the titanium image.

[0100] Here, Figure 15 shows a superimposed image of aluminum shown in Figure 13 and a superimposed image of titanium shown in Figure 14. According to Figure 15, the width 602 of the upper part 62 of the partition wall 6 is wider than the width 601 of the lower part 61 of the partition wall 6, and the number of pixels corresponding to the protrusion amount D of the partition wall 6 can be obtained from the difference between the width 601 (represented by the number of pixels) of the lower part 61 and the width 602 (represented by the number of pixels) of the upper part 62. Specifically, the number of pixels corresponding to the protrusion amount D of the partition wall 6 can be calculated, for example, by "(number of pixels representing the width 602 of the upper part 62 - number of pixels representing the width 601 of the lower part 61) × 1 / 2".

[0101] Here, the number of pixels corresponding to the protrusion amount D of the partition wall 6 is obtained by calculation using the difference between the width 601 of the lower part 61 and the width 602 of the upper part 62. However, it is also possible to count the number of pixels corresponding to the protrusion amount D of the partition wall 6 on an image in which images of aluminum and titanium are superimposed, as shown in Figure 15 above.

[0102] Furthermore, although it has been explained here that the number of pixels corresponding to the protrusion amount D of the partition wall 6 is obtained based on the difference between the width 601 in direction X of the lower part 61 extending in direction Y and the width 602 in direction X of the upper part 62 extending in direction Y, the number of pixels corresponding to the protrusion amount D of the partition wall 6 may also be obtained based on the difference between the width in direction Y of the lower part 61 extending in direction X and the width in direction Y of the upper part 62 extending in direction X.

[0103] Furthermore, in this embodiment, it has been explained that images for each element (images of aluminum and titanium) are extracted from the EDX image, and the number of pixels corresponding to the protrusion amount D of the partition wall 6 is obtained based on the extracted images for each element. However, if, for example, the regions where aluminum is visible and the regions where titanium is visible can be identified based on the pixel values ​​(luminance values) of each of the multiple pixels constituting the EDX image, it is also possible to configure the system to obtain the number of pixels corresponding to the protrusion amount D of the partition wall 6 based on the regions where aluminum and titanium are visible identified in the EDX image.

[0104] In other words, in this embodiment, it is sufficient to have a configuration that obtains the number of pixels corresponding to the protrusion amount D of the partition wall 6 from the characteristics of the image that can be recognized by analyzing the EDX image (image for each element) (i.e., the analysis result of the EDX image).

[0105] Next, the measurement unit 503 measures the amount of protrusion D of the partition wall 6 based on the number of pixels acquired in step S3 (step S4).

[0106] In step S5, the measurement unit 503 performs a process to convert the number of pixels acquired in step S3 into the protrusion amount D of the partition wall 6 (the length between the side surface of the lower part 61 and the end of the upper part 62), for example, based on pre-prepared conversion information.

[0107] The conversion information is generated based on an image of at least one element constituting the sample (i.e., a standard sample EDX image including the sample) generated by irradiating a sample of known size (length) with the electron beam 404. Specifically, the number of pixels located between one end (corresponding to a pixel) and the other end (corresponding to a pixel) of the sample included in the standard sample EDX image is counted, and the known size of the sample is divided by this number of pixels to generate conversion information indicating the length corresponding to one pixel. With such conversion information, the number of pixels can be converted to the protrusion amount D (actual size) of the partition wall 6 by multiplying the length corresponding to one pixel shown by the conversion information by the number of pixels acquired in step S3. Note that the conversion information only needs to be information that can convert the number of pixels to length (i.e., information in which the correspondence between the number of pixels and length is defined).

[0108] Here, the protrusion amount D of the partition wall 6 is described as being measured based on conversion information indicating the length corresponding to a single pixel. However, the protrusion amount D of the partition wall 6 may also be measured (calculated) using a machine learning model generated by a machine learning algorithm such as a neural network. Such a machine learning model only needs to be constructed (generated) to output the protrusion amount D (actual size) of the partition wall 6 by taking the number of pixels corresponding to the protrusion amount D of the partition wall 6 obtained from the EDX image (image for each element) as input, after learning from a pre-prepared dataset (i.e., predicting the protrusion amount D of the partition wall 6 from the number of pixels). The dataset used to generate such a machine learning model should include, for example, the number of pixels corresponding to the known protrusion amount D of the partition wall 6 and the known protrusion amount D of the partition wall 6, which are obtained manually or automatically from images of each element constituting the partition wall 6 (e.g., images of aluminum and titanium) generated by irradiating the partition wall 6 with an electron beam 404, where the protrusion amount D is known.

[0109] If the amount of protrusion D of the partition wall 6 measured by the process shown in Figure 12 above is appropriate, then the display elements 20 of each sub-pixel SP can be formed on the motherboard 100 as described in Figures 5 to 7 above.

[0110] In addition, although Figure 12 above describes the case in which the amount of protrusion D of a part of the partition wall 6 formed on the motherboard 100 is measured, the process shown in Figure 12 may be performed multiple times to measure the amount of protrusion D at multiple parts of the partition wall 6.

[0111] Furthermore, although this embodiment describes measuring the protrusion amount D of the partition wall 6 using images of the elements (aluminum) constituting the lower part 61 and the elements (titanium) constituting the upper part 62 of the partition wall 6, the protrusion amount D of the partition wall 6 may also be measured using images of elements such as silicon (Si) constituting the insulating layer 13 (rib 5) shown in Figure 16. Note that the insulating layer 13 is formed over almost the entire surface of the motherboard 100, but in Figure 16, silicon formed beneath the metal materials (Al, Ti, and Ag, etc.) constituting the partition wall 6 (lower part 61 and upper part 62) and the lower electrode LE is not detected. In other words, Figure 16 shows an image in which the insulating layer 13 formed between the upper part 62 of the partition wall 6 and the lower electrode LE is visualized, for example, in a plan view.

[0112] For example, if the lower part 61 of the partition wall 6 is formed with relatively high precision, it may be possible to measure (predict) that the protrusion amount D of the partition wall 6 is appropriate when the width (number of pixels) in direction X or Y of the insulating layer 13 formed between the upper part 62 and the lower electrode LE in the image shown in Figure 16 is within a predetermined range.

[0113] In other words, in this embodiment, any configuration that measures the amount of protrusion D of the partition wall 6 based on EDX images (images for each element) is sufficient, and the elements (images) used to measure the amount of protrusion D of the partition wall 6 can be selected (changed) as appropriate.

[0114] As described above, in this embodiment, a partition wall 6 is formed on a substrate 10 (mother substrate) having a lower part 61 and an upper part 62 protruding from the side surface of the lower part 61. An image (first image) of each element constituting the partition wall 6 is obtained by irradiating the partition wall 6 with an electron beam 404, the obtained images of each element are analyzed, and the amount of protrusion D of the partition wall 6 (length from the side surface of the lower part 61 to the end of the upper part 62) is measured based on the analysis results.

[0115] Specifically, in this embodiment, images of the elements constituting the lower part 61 of the partition wall 6 (e.g., aluminum) and the elements constituting the upper part 62 (e.g., titanium) are acquired, the number of pixels corresponding to the protrusion amount D of the partition wall 6 is acquired based on the acquired images, and the protrusion amount of the partition wall 6 is measured based on the acquired number of pixels.

[0116] Furthermore, the number of pixels corresponding to the protrusion amount D of the partition wall 6 is obtained, for example, based on the difference between the number of pixels representing the width of the lower part 61, which is made of aluminum (first element), in a plan view, and the number of pixels representing the width of the upper part 62, which is made of titanium (second element), in a plan view.

[0117] Furthermore, when measuring the protrusion amount D of the partition wall 6 based on images of the elements constituting the lower part 61 and the elements constituting the upper part 62 as described above, the electron beam 404 for generating the image of each element (i.e., the EDX image) shall be irradiated from a direction perpendicular to the substrate 10 to the surface of the upper part 62 opposite to the substrate 10, with an intensity that penetrates at least the upper part 62 and reaches the lower part 61.

[0118] In this embodiment, the above-described configuration allows for the measurement of the protrusion amount D of the partition wall 6 (i.e., confirmation of whether the protrusion amount D of the partition wall 6 is appropriate) before manufacturing the display device DSP, thereby suppressing a decrease in the reliability of the display device DSP.

[0119] Furthermore, in this embodiment, the amount of protrusion D of the partition wall 6 is measured using an EDX device 400 attached to a SEM mounted on a motherboard inspection device 300 used to inspect the quality of the motherboard 100. Therefore, continuous measurement (inspection) using existing equipment can be achieved.

[0120] As described above, in this embodiment, it is sufficient to have a configuration in which the protrusion amount D of the partition wall 6 obtained from EDX images (images for each element) is measured. However, the protrusion amount D of the partition wall 6 can be measured, for example, using conversion information or a machine learning model. In this case, the conversion information can be prepared in advance based on, for example, images (second images) of each element constituting a sample whose size (length) is known, which are generated by irradiating the sample with an electron beam 404. The machine learning model can be generated by training a dataset that includes the number of pixels corresponding to the known protrusion amount D of the partition wall 6, obtained based on images (second images) of each element constituting the partition wall 6, which are generated by irradiating the partition wall 6 (sample) with an electron beam 404, and the known protrusion amount D of the partition wall 6.

[0121] Furthermore, although this embodiment describes the measurement of the protrusion amount D of the partition wall 6 based on the number of pixels corresponding to the protrusion amount D of the partition wall 6 obtained from the EDX image (image for each element), predetermined image processing may be performed to obtain an appropriate number of pixels for measuring the protrusion amount D of the partition wall 6, or a machine learning model constructed to obtain an appropriate number of pixels from the EDX image may be used.

[0122] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the measurement method and measuring device described above as embodiments of the present invention also fall within the scope of the present invention, insofar as they encompass the gist of the present invention.

[0123] Within the scope of the spirit of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications made by a person skilled in the art to the above-described embodiments, such as adding, deleting, or changing the design of components, or adding, omitting, or changing the conditions of processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0124] Furthermore, any other effects and benefits brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0125] DSP...Display device, DA...Display area, NDA...Non-display area, PX...Pixel, SP, SP1, SP2, SP3...Sub-pixel, LE, LE1, LE2, LE3...Lower electrode, UE, UE1, UE2, UE3...Upper electrode, OR, OR1, OR2, OR3...Organic layer, SE, SE1, SE2, SE3...Sealing layer, 1...Pixel circuit, 2...Pixel switch, 3...Drive transistor, 4...Capacitor, 5...Rib, 6...Partition, 10...Substrate, 11...Insulating layer, 12...Circuit layer, 13...Insulating layer, 14...Resin layer, 15...Sealing layer, 16...Resin Oil layer, 20...Display element, 61...Lower part, 62...Upper part, 100...Motherboard, 200...Load lock chamber, 300...Motherboard inspection device, 400...EDX device, 401...Sample stage, 402...Irradiator, 402a...Electron gun, 402b...Focusing lens, 402c...Scanning coil, 402d...Objective lens, 403...Detector, 500...Measurement device, 500a...CPU, 500b...Non-volatile memory, 500c...Main memory, 500d...Communication device, 501...Image acquisition unit, 502...Image analysis unit, 503...Measurement unit.

Claims

1. A partition wall is formed having a lower part placed on the base material and an upper part protruding from the side surface of the lower part, To obtain a first image of each element constituting the partition wall, generated by irradiating the partition wall with an electron beam, The first image obtained for each element is analyzed, Based on the analysis results, the amount of protrusion of the upper end protruding from the lower side surface is measured. A measurement method comprising the following:

2. The acquisition described above includes acquiring a first image of the first element constituting the lower part and a first image of the second element constituting the upper part. The analysis described above includes obtaining the number of pixels corresponding to the amount of protrusion based on the first image of the first element and the first image of the second element obtained, The measurement described above includes measuring the amount of protrusion based on the number of pixels acquired. The measurement method according to claim 1.

3. The measurement method according to claim 2, wherein the number of pixels corresponding to the amount of protrusion is obtained based on the difference between the number of pixels representing the width in a plan view of the lower part composed of the first element and the number of pixels representing the width in a plan view of the upper part composed of the second element.

4. The measurement described above includes converting the acquired number of pixels into the protrusion amount based on conversion information indicating the length corresponding to one pixel, The aforementioned conversion information is pre-prepared based on a second image of at least one element constituting a sample, which is generated by irradiating the sample, with an electron beam, with a known size. The measurement method according to claim 2.

5. The aforementioned measurement includes obtaining the amount of protrusion output from a machine learning model by inputting the acquired number of pixels into a machine learning model generated by training on a pre-prepared dataset. The dataset includes the number of pixels corresponding to the known protrusion amount, obtained based on a second image for each element constituting the partition wall, which is generated by irradiating the partition wall with a known protrusion amount using an electron beam, and the known protrusion amount. The measurement method according to claim 2.

6. The measurement method according to claim 1, wherein the electron beam is irradiated from a direction perpendicular to the substrate to the surface of the upper part opposite to the substrate with an intensity that penetrates at least the upper part and reaches the lower part.

7. An acquisition unit that acquires a first image of each element constituting a partition wall, which is generated by irradiating the partition wall, having a lower part placed on a substrate and an upper part protruding from the side surface of the lower part, with an electron beam, An analysis unit analyzes the first image for each element obtained, Based on the analysis results, a measuring unit measures the amount of protrusion of the upper end protruding from the lower side surface. A measuring device equipped with the following.

8. An irradiation unit that irradiates an electron beam onto a partition wall having a lower part placed on a substrate and an upper part protruding from the side surface of the lower part, A detection unit for detecting characteristic X-rays generated from the partition wall when the electron beam is irradiated. An acquisition unit that acquires a first image for each element constituting the partition wall, which is generated based on the detected characteristic X-rays, An analysis unit analyzes the first image for each element obtained, Based on the analysis results, a measuring unit measures the amount of protrusion of the upper end protruding from the lower side surface. A measuring device equipped with the following.

Images