Plasma processing equipment

Abstract

To provide a technique capable of increasing in-plane uniformity of a substrate after plasma processing.SOLUTION: A plasma processing apparatus comprises a plasma processing chamber, a first bias electrode that is arranged in an electrostatic chuck and has a first external diameter, a second bias electrode that is arranged in the electrostatic chuck and has a second external diameter, a third bias electrode that is arranged in the electrostatic chuck and has a third external diameter, a first DC power supply, a second DC power supply, a third DC power supply, a voltage adder, a first voltage pulse generator that is electrically connected to the first bias electrode, and generates a first voltage pulse signal, a second voltage pulse generator that is electrically connected to the second bias electrode and generates a second voltage pulse signal, and a third voltage pulse generator that is electrically connected to the third bias electrode and generates a third voltage pulse signal.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] Exemplary embodiments of this disclosure relate to plasma processing apparatus. [Background technology]

[0002] In plasma processing equipment, there is a technique for supplying high frequency and pulsed voltage to multiple electrodes, as described in Patent Document 1. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2022 / 0037119 [Overview of the project] [Problems that the invention aims to solve]

[0004] This disclosure provides a technology that can improve the in-plane uniformity of a substrate in plasma processing. [Means for solving the problem]

[0005] A plasma processing apparatus in one exemplary embodiment of the present disclosure includes a plasma processing chamber and a substrate support portion disposed within the plasma processing chamber, the substrate support portion including a base, an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface, and an edge ring disposed on the ring support surface so as to surround a substrate disposed on the substrate support surface; a substrate chuck electrode disposed below the substrate support surface within the electrostatic chuck; at least one ring chuck electrode disposed below the ring support surface within the electrostatic chuck; a first bias electrode disposed within the electrostatic chuck and having a first outer diameter; a second bias electrode disposed within the electrostatic chuck and having a second outer diameter larger than the first outer diameter; a third bias electrode disposed within the electrostatic chuck and having a third outer diameter larger than the second outer diameter; a first DC power supply configured to generate a first primary DC signal having a first primary voltage level; a second DC power supply configured to generate a second primary DC signal having a second primary voltage level; and a third primary DC signal having a third primary voltage level. A third DC power supply configured to generate a first secondary DC signal having a first secondary voltage level, a second secondary DC signal having a second secondary voltage level, and a third secondary DC signal having a third secondary voltage level, using the first to third primary DC signals, wherein the first secondary voltage level, the second secondary voltage level, and the third secondary voltage level are the first primary voltage level, the voltage level obtained by adding the first primary voltage level and the second primary voltage level, and the voltage level obtained by adding the first primary voltage level and the third primary voltage level A voltage adder that selects from among the voltage levels obtained by adding the first and second secondary DC signals in a manner that does not overlap with each other; a first voltage pulse generator that is electrically connected to the first bias electrode and configured to generate a first voltage pulse signal having a first secondary voltage level from a first secondary DC signal; a second voltage pulse generator that is electrically connected to the second bias electrode and configured to generate a second voltage pulse signal having a second secondary voltage level from a second secondary DC signal; and a third voltage pulse generator that is electrically connected to the third bias electrode and configured to generate a third voltage pulse signal from a third secondary DC signal.The system includes a third voltage pulse generator configured to generate a third voltage pulse signal having a third secondary voltage level. [Effects of the Invention]

[0006] According to one exemplary embodiment of the present disclosure, a technique can be provided that can improve the in-plane uniformity of a substrate in plasma processing. [Brief explanation of the drawing]

[0007] [Figure 1] This is a diagram illustrating an example configuration of a plasma processing system. [Figure 2] This is a diagram illustrating an example configuration of a capacitively coupled plasma processing apparatus. [Figure 3] This figure illustrates an example configuration of the substrate support and DC power supply in the first exemplary embodiment. [Figure 4] This is a diagram illustrating an example of a bias electrode configuration in plan view. [Figure 5] This figure shows an example of a voltage pulse. [Figure 6] This diagram illustrates the variation in plasma sheath on the substrate. [Figure 7] This diagram illustrates other possible arrangements of the bias electrode. [Figure 8] This diagram illustrates other possible arrangements of the bias electrode. [Figure 9] This diagram illustrates other possible arrangements of the bias electrode. [Figure 10] This diagram illustrates other possible arrangements of the bias electrode. [Figure 11] This figure illustrates an example configuration of the substrate support and DC power supply in a second exemplary embodiment. [Figure 12] This figure illustrates an example configuration of the substrate support and DC power supply in a third exemplary embodiment. [Modes for carrying out the invention]

[0008] The embodiments of this disclosure are described below.

[0009] In one exemplary embodiment, a plasma processing chamber and a substrate support portion disposed within the plasma processing chamber, the substrate support portion includes a base, an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface, and an edge ring disposed on the ring support surface so as to surround a substrate disposed on the substrate support surface, a substrate chuck electrode disposed below the substrate support surface within the electrostatic chuck, at least one ring chuck electrode disposed below the ring support surface within the electrostatic chuck, and a first outer diameter disposed within the electrostatic chuck A first bias electrode having a first outer diameter, a second bias electrode disposed in an electrostatic chuck and having a second outer diameter larger than the first outer diameter, a third bias electrode disposed in an electrostatic chuck and having a third outer diameter larger than the second outer diameter, a first DC power supply configured to generate a first primary DC signal having a first primary voltage level, a second DC power supply configured to generate a second primary DC signal having a second primary voltage level, a third DC power supply configured to generate a third primary DC signal having a third primary voltage level, and the first to third primary DC A voltage adder configured to generate a first secondary DC signal having a first secondary voltage level, a second secondary DC signal having a second secondary voltage level, and a third secondary DC signal having a third secondary voltage level using a signal, wherein the first secondary voltage level, the second secondary voltage level, and the third secondary voltage level are selected from a first primary voltage level, a voltage level obtained by adding the first primary voltage level and the second primary voltage level, and a voltage level obtained by adding the first primary voltage level and the third primary voltage level, so as not to overlap with each other. The system includes: a first voltage pulse generator electrically connected to a first bias electrode and configured to generate a first voltage pulse signal having a first secondary voltage level from a first secondary DC signal; a second voltage pulse generator electrically connected to a second bias electrode and configured to generate a second voltage pulse signal having a second secondary voltage level from a second secondary DC signal; and a third voltage pulse generator electrically connected to a third bias electrode and configured to generate a third voltage pulse signal having a third secondary voltage level from a third secondary DC signal.A plasma processing apparatus is provided.

[0010] In one exemplary embodiment, the first voltage pulse signal, the second voltage pulse signal, and the third voltage pulse signal each include a sequence of first voltage pulses, a sequence of second voltage pulses, and a sequence of third voltage pulses.

[0011] In one exemplary embodiment, the first primary voltage level, the second primary voltage level, and the third primary voltage level have a negative polarity.

[0012] In one exemplary embodiment, the absolute value of the first primary voltage level is greater than the absolute values of the second primary voltage level and the third primary voltage level.

[0013] In one exemplary embodiment, the first bias electrode is arranged to overlap the substrate support surface in the longitudinal direction, the second bias electrode is arranged to overlap the substrate support surface and the ring support surface in the longitudinal direction, and the third bias electrode is arranged to overlap the ring support surface in the longitudinal direction.

[0014] In one exemplary embodiment, the first bias electrode is arranged to overlap the substrate support surface in the longitudinal direction, the second bias electrode is arranged to overlap the substrate support surface in the longitudinal direction, and the third bias electrode is arranged to overlap the ring support surface in the longitudinal direction.

[0015] In one exemplary embodiment, the first bias electrode is arranged to overlap the substrate support surface in the longitudinal direction, the second bias electrode is arranged to overlap the substrate support surface in the longitudinal direction, and the third bias electrode is arranged to overlap the substrate support surface and the ring support surface in the longitudinal direction.

[0016] In one exemplary embodiment, the first bias electrode is arranged to overlap the substrate support surface in the longitudinal direction, the second bias electrode is arranged to overlap the substrate support surface in the longitudinal direction, and the third bias electrode is arranged to overlap the substrate support surface in the longitudinal direction.

[0017] In one exemplary embodiment, the first bias electrode, the second bias electrode, and the third bias electrode are arranged at the same height.

[0018] In one exemplary embodiment, the first bias electrode, the second bias electrode, and the third bias electrode are arranged at different heights from one another.

[0019] In one exemplary embodiment, the second bias electrode is positioned lower than the first bias electrode, and the third bias electrode is positioned lower than the second bias electrode.

[0020] In one exemplary embodiment, the outer edge region of the first bias electrode overlaps longitudinally with the inner edge region of the second bias electrode, and the outer edge region of the second bias electrode overlaps longitudinally with the inner edge region of the third bias electrode.

[0021] In one exemplary embodiment, the ring chuck electrode includes an inner ring chuck electrode to which a first ring chuck voltage having a first polarity is applied, and an outer ring chuck electrode to which a second ring chuck voltage having a second polarity is applied.

[0022] In one exemplary embodiment, a plasma processing chamber and a substrate support portion disposed within the plasma processing chamber, the substrate support portion including a base, an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface, and an edge ring disposed on the ring support surface so as to surround the substrate on the substrate support surface; a substrate chuck electrode disposed below the substrate support surface within the electrostatic chuck; at least one ring chuck electrode disposed below the ring support surface within the electrostatic chuck; a first bias electrode disposed within the electrostatic chuck and having a first outer diameter; and a component disposed within the electrostatic chuck with a diameter larger than the first outer diameter. A plasma processing apparatus is provided, comprising: a second bias electrode having a second outer diameter; a third bias electrode disposed within an electrostatic chuck and having a third outer diameter larger than the second outer diameter; a first voltage pulse generator electrically connected to the first bias electrode and configured to generate a first voltage pulse signal having a first voltage level; a second voltage pulse generator electrically connected to the second bias electrode and configured to generate a second voltage pulse signal having a second voltage level; and a third voltage pulse generator electrically connected to the third bias electrode and configured to generate a third voltage pulse signal having a third voltage level.

[0023] In one exemplary embodiment, the system further includes a first DC power supply configured to supply a first DC signal having a first voltage level to a first voltage pulse generator, a second DC power supply configured to supply a second DC signal having a second voltage level to a second voltage pulse generator, and a third DC power supply configured to supply a third DC signal having a third voltage level to a third voltage pulse generator.

[0024] In one exemplary embodiment, the first voltage level, the second voltage level, and the third voltage level have negative polarity.

[0025] In one exemplary embodiment, the first bias electrode is positioned to overlap longitudinally with the substrate support surface, the second bias electrode is positioned to overlap longitudinally with the substrate support surface, and the third bias electrode is positioned to overlap longitudinally with the ring support surface.

[0026] In one exemplary embodiment, the second bias electrode is positioned lower than the first bias electrode, and the third bias electrode is positioned lower than the second bias electrode.

[0027] In one exemplary embodiment, the outer edge region of the first bias electrode overlaps longitudinally with the inner edge region of the second bias electrode, and the outer edge region of the second bias electrode overlaps longitudinally with the inner edge region of the third bias electrode.

[0028] In one exemplary embodiment, a plasma processing chamber and a substrate support unit disposed within the plasma processing chamber, the substrate support unit includes a base, an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface, and an edge ring disposed on the ring support surface so as to surround a substrate disposed on the substrate support surface; a substrate chuck electrode disposed below the substrate support surface within the electrostatic chuck; at least one ring chuck electrode disposed below the ring support surface within the electrostatic chuck; a first bias electrode disposed within the electrostatic chuck and having a first outer diameter; a second bias electrode disposed within the electrostatic chuck and having a second outer diameter larger than the first outer diameter; a third bias electrode disposed within the electrostatic chuck and having a third outer diameter larger than the second outer diameter; and a first DC signal generating a first voltage level. A plasma processing apparatus is provided, comprising: a first DC power supply configured to generate a second DC signal having a second voltage level; a third DC power supply configured to generate a third DC signal having a third voltage level; a first voltage pulse generator electrically connected to a first bias electrode and configured to generate a first voltage pulse signal having a first voltage level; a second voltage pulse generator electrically connected to a second bias electrode and configured to generate a second voltage pulse signal having a fourth voltage level obtained by adding the first voltage level and the second voltage level; and a third voltage pulse generator electrically connected to a third bias electrode and configured to generate a third voltage pulse signal having a fifth voltage level obtained by adding the first voltage level, the second voltage level, and the third voltage level.

[0029] Hereinafter, each embodiment of this disclosure will be described in detail with reference to the drawings. In each drawing, the same or similar elements are denoted by the same reference numeral, and redundant explanations are omitted. Unless otherwise specified, positional relationships such as top, bottom, left, and right will be described based on the positional relationships shown in the drawings. The dimensional ratios in the drawings do not represent actual ratios, and actual ratios are not limited to those shown.

[0030] <An example of a plasma processing device> Figure 1 is a diagram illustrating an example configuration of a plasma processing system. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support unit 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas outlet for discharging gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20, which will be described later, and the gas outlet is connected to an exhaust system 40, which will be described later. The substrate support unit 11 is located in the plasma processing space and has a substrate support surface for supporting a substrate.

[0031] The plasma generation unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be a capacitively coupled plasma (CCP), an inductively coupled plasma (ICP), an electron-cyclotron-resonance plasma (ECR), a helicon wave plasma (HWP), or a surface wave plasma (SWP). Various types of plasma generation units, including an AC (Alternating Current) plasma generation unit and a DC (Direct Current) plasma generation unit, may also be used. In one embodiment, the AC signal (AC power) used in the AC plasma generation unit has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes an RF (Radio Frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0032] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include, for example, a computer 2a. The computer 2a may include, for example, a processing unit (CPU: Central Processing Unit) 2a1, a storage unit 2a2, and a communication interface 2a3. The processing unit 2a1 may be configured to perform various control operations by reading a program from the storage unit 2a2 and executing the read program. This program may be stored in the storage unit 2a2 in advance, or it may be retrieved via a medium when needed. The retrieved program is stored in the storage unit 2a2 and read from the storage unit 2a2 and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a, or it may be a communication line connected to the communication interface 2a3. The memory unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing device 1 via a communication line such as a LAN (Local Area Network).

[0033] The following describes an example configuration of a capacitively coupled plasma processing apparatus as an example of plasma processing apparatus 1. Figure 2 is a diagram illustrating an example configuration of a capacitively coupled plasma processing apparatus.

[0034] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a shower head 13. The substrate support unit 11 is located inside the plasma processing chamber 10. The shower head 13 is located above the substrate support unit 11. In one embodiment, the shower head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the shower head 13, the side walls 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded. The shower head 13 and the substrate support unit 11 are electrically insulated from the plasma processing chamber 10 housing.

[0035] The substrate support portion 11 includes a main body portion 111 and a ring assembly (edge ​​ring assembly) 112. The main body portion 111 has a central region 111a for supporting the substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a plan view. The substrate W is placed on the central region 111a of the main body portion 111, and the ring assembly 112 is placed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also called the substrate support surface for supporting the substrate W, and the annular region 111b is also called the ring support surface for supporting the ring assembly 112.

[0036] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is placed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b placed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may also have an annular region 111b. In this case, the ring assembly 112 may be placed on the annular electrostatic chuck or the annular insulating member, or on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, the RF or DC electrode may be placed within the ceramic member 1111a, in which case the RF or DC electrode functions as a lower electrode. When a bias RF signal or DC signal, described later, is connected to the RF or DC electrode, the RF or DC electrode is also called a bias electrode. Note that both the conductive member of the base 1110 and the RF or DC electrode may function as two lower electrodes.

[0037] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one covering ring. The edge rings are formed of a conductive or insulating material, and the covering rings are formed of an insulating material.

[0038] The substrate support section 11 may also include a temperature control module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature control module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid, such as brine or gas, flows through the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are arranged within the ceramic member 1111a of the electrostatic chuck 1111. The substrate support section 11 may also include a heat transfer gas supply section configured to supply a heat transfer gas between the back surface of the substrate W and the central region 111a.

[0039] The showerhead 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlet ports 13c. The processing gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s through the plurality of gas inlet ports 13c. The showerhead 13 also includes an upper electrode. In addition to the showerhead 13, the gas introduction unit may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the side wall 10a.

[0040] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas to the shower head 13 from a corresponding gas source 21 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of at least one processing gas.

[0041] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power), such as a source RF signal and a bias RF signal, to at least one lower electrode and / or at least one upper electrode. This causes plasma to be formed from at least one processing gas supplied to the plasma processing space 10s. Thus, the RF power supply 31 can function as at least part of the plasma generation unit 12. In addition, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, and ionic components in the formed plasma can be drawn into the substrate W.

[0042] In one embodiment, the RF power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generation unit 31a may be configured to generate a plurality of source RF signals having different frequencies. One or more generated source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0043] The second RF generation unit 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generation unit 31b may be configured to generate a plurality of bias RF signals having different frequencies. One or more generated bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0044] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generation unit 32a and a second DC generation unit 32b. In one embodiment, the first DC generation unit 32a is connected to at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to at least one lower electrode. In one embodiment, the second DC generation unit 32b is connected to at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to at least one upper electrode.

[0045] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of DC-based voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or a combination thereof pulse waveform. In one embodiment, a waveform generation unit for generating a sequence of voltage pulses from the DC signal is connected between the first DC generation unit 32a and at least one lower electrode. Thus, the first DC generation unit 32a and the waveform generation unit constitute a voltage pulse generation unit. When the second DC generation unit 32b and the waveform generation unit constitute a voltage pulse generation unit, the voltage pulse generation unit is connected to at least one upper electrode. The voltage pulses may have positive or negative polarity. The sequence of voltage pulses may also include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. The first and second DC generation units 32a and 32b may be provided in addition to the RF power supply 31, and the first DC generation unit 32a may be provided in place of the second RF generation unit 31b.

[0046] The exhaust system 40 may be connected to, for example, a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure regulating valve regulates the pressure in the plasma processing space 10s. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0047] <First Exemplary Embodiment> A first exemplary embodiment of the plasma processing apparatus 1 described above will now be explained. Figure 3 shows an example of the configuration of the substrate support unit 11 and the DC power supply 32 in the first exemplary embodiment. In one embodiment, the substrate support unit 11 has a substrate chuck electrode 200, a ring chuck electrode 201, a first bias electrode 202, a second bias electrode 203, and a third bias electrode 204 inside the electrostatic chuck 1111. The substrate chuck electrode 200 and the ring chuck electrode 201 may be examples of electrostatic electrodes 1111b.

[0048] In one embodiment, the DC power supply 32 includes a first DC power supply 250, a second DC power supply 251, a third DC power supply 252, a voltage adder 260, a first voltage pulse generator 270, a second voltage pulse generator 271, and a third voltage pulse generator 272.

[0049] The substrate chuck electrode 200 may be positioned below the substrate support surface within the electrostatic chuck 1111. In one embodiment, the substrate chuck electrode 200 has a circular shape. In one embodiment, the substrate chuck electrode 200 is connected to a DC power supply 301 via a switch 300. When a DC voltage from the DC power supply 301 is applied to the substrate chuck electrode 200, an electrostatic attraction (Coulomb force) is generated between the substrate chuck electrode 200 and the substrate W. The substrate W is attracted to the electrostatic chuck 1111 by this electrostatic attraction and is held by adsorption to the substrate support surface.

[0050] In one embodiment, the ring chuck electrode 201 may be positioned below the ring support surface within the electrostatic chuck 1111. In one embodiment, the ring chuck electrode 201 includes an inner ring chuck electrode 400 and an outer ring chuck electrode 401. In one embodiment, the inner ring chuck electrode 400 is connected to a DC power supply 411 via a switch 410. In one embodiment, the outer ring chuck electrode 401 is positioned outside the inner ring chuck electrode 400. In one embodiment, the outer ring chuck electrode 401 is connected to a DC power supply 421 via a switch 420. In one embodiment, a potential difference is generated between the inner ring chuck electrode 400 and the outer ring chuck electrode 401, and this potential difference causes the ring assembly 112 to be attracted and held on the ring support surface. In one embodiment, the polarity of the first ring chuck voltage applied to the inner ring chuck electrode 400 is different from the polarity of the second ring chuck voltage applied to the outer ring chuck electrode 401.

[0051] In one embodiment, the first bias electrode 202 and the second bias electrode 203 may be positioned below the substrate support surface within the electrostatic chuck 1111 so as to overlap longitudinally with the substrate support surface. The third bias electrode 204 may be positioned below the ring support surface within the electrostatic chuck 1111 so as to overlap longitudinally with the ring support surface. As shown in Figure 4, in one embodiment, the first bias electrode 202 has a circular shape. In one embodiment, the second bias electrode 203 and the third bias electrode 204 have an annular shape with a radial width. In one embodiment, the second bias electrode 203 has a larger diameter than the first bias electrode 202 and is positioned outside the first bias electrode 202. In one embodiment, the third bias electrode 204 has a larger diameter than the second bias electrode 203 and is positioned outside the second bias electrode 203.

[0052] As shown in Figure 3, the first bias electrode 202, the second bias electrode 203, and the third bias electrode 204 may be positioned at the same height. The first bias electrode 202 and the second bias electrode 203 may be separated by a distance D1 or more. The second bias electrode 203 and the third bias electrode 204 may be separated by a distance D2 or more.

[0053] The first DC power supply 250 can generate a first primary DC signal DC1 having a first primary voltage level V1. The first primary voltage level V1 may have negative polarity. The first DC power supply 250 is electrically connected to a voltage adder 260. The generated first primary DC signal DC1 can be supplied to the voltage adder 260.

[0054] The second DC power supply 251 can generate a second primary DC signal DC2 having a second primary voltage level V2. The second primary voltage level V2 may have negative polarity. The second DC power supply 251 is electrically connected to a voltage adder 260. The generated second primary DC signal DC2 can be supplied to the voltage adder 260.

[0055] A third DC power supply 252 can generate a third primary DC signal DC3 having a third primary voltage level V3. The third primary voltage level V3 may have negative polarity. The third DC power supply 252 is electrically connected to a voltage adder 260. The generated third primary DC signal DC3 can be supplied to the voltage adder 260. In one embodiment, the first primary voltage level V1 is greater than the second primary voltage level V2 and the third primary voltage level V3. In one embodiment, the absolute value of the first primary voltage level V1 is five times greater than the absolute values ​​of the second primary voltage level V2 and the third primary voltage level V3.

[0056] The voltage adder 260 can generate a first secondary DC signal DC4 having a first secondary voltage level V4, a second secondary DC signal DC5 having a second secondary voltage level V5, and a third secondary DC signal DC6 having a third secondary voltage level V6 from the voltage levels V1 to V3 of the first to third primary DC signals DC1 to DC3.

[0057] The first secondary voltage level V4 of the first secondary DC signal DC4, the second secondary voltage level V5 of the second secondary DC signal DC5, and the third secondary voltage level V6 of the third secondary DC signal DC6 are selected from (1) to (3) below in such a way that they do not overlap with each other. (1) The same voltage level (V1) as the first primary voltage level V1 (2) The voltage level obtained by adding the first primary voltage level V1 and the second primary voltage level V2 (V1+V2) (3) The voltage level obtained by adding the first primary voltage level V1 and the third primary voltage level V3 (V1 + V3) That is, if the first secondary voltage level V4 is (1) voltage level V1, then the second secondary voltage level V5 or the third secondary voltage level V6 becomes (2) voltage level (V1+V2), and the remaining second secondary voltage level V5 or third secondary voltage level V6 becomes (3) voltage level (V1+V3). If the second secondary voltage level V5 is (1) voltage level V1, then the first secondary voltage level V4 or the third secondary voltage level V6 becomes (2) voltage level (V1+V2), and the remaining first secondary voltage level V4 or third secondary voltage level V6 becomes (3) voltage level (V1+V3). If the third secondary voltage level V6 is (1) voltage level V1, then the first secondary voltage level V4 or the second secondary voltage level V5 becomes (2) voltage level (V1+V2), and the remaining first secondary voltage level V4 or second secondary voltage level V5 becomes (3) voltage level (V1+V3). Therefore, the first secondary voltage level V4, the second secondary voltage level V5, and the third secondary voltage level V6 exclusively possess one of the above (1) to (3).

[0058] The voltage adder 260 is electrically connected to the first voltage pulse generator 270, the second voltage pulse generator 271, and the third voltage pulse generator 272. The first secondary DC signal DC4 generated by the voltage adder 260 can be supplied to the first voltage pulse generator 270, the second secondary DC signal DC5 can be supplied to the second voltage pulse generator 271, and the third secondary DC signal DC6 can be supplied to the third voltage pulse generator 272.

[0059] The first voltage pulse generator 270 can generate a first voltage pulse signal DC7 having a first secondary voltage level V4 from a first secondary DC signal DC4 supplied from the voltage adder 260. The first voltage pulse signal DC7 may include a sequence of first voltage pulses. The first voltage pulse generator 270 is electrically connected to the first bias electrode 202. The generated first voltage pulse signal DC7 can be supplied to the first bias electrode 202. By supplying the first voltage pulse signal DC7 to the first bias electrode 202, a bias pulse signal based on a DC voltage is generated, which can draw ionic components in the plasma generated on the substrate W of the substrate support 11 towards the first bias electrode 202.

[0060] The second voltage pulse generator 271 can generate a second voltage pulse signal DC8 having a second secondary voltage level V5 from a second secondary DC signal DC5 supplied from the voltage adder 260. The second voltage pulse signal DC8 may include a sequence of second voltage pulses. The second voltage pulse generator 271 is electrically connected to the second bias electrode 203. The generated second voltage pulse signal DC8 can be supplied to the second bias electrode 203. By supplying the second voltage pulse signal DC8 to the second bias electrode 203, a bias pulse signal based on a DC voltage is generated, which can draw ionic components in the plasma generated on the substrate W of the substrate support 11 towards the second bias electrode 203.

[0061] The third voltage pulse generator 272 can generate a third voltage pulse signal DC9 having a third secondary voltage level V6 from a third secondary DC signal DC6 supplied from the voltage adder 260. The third voltage pulse signal DC9 may include a sequence of third voltage pulses. The third voltage pulse generator 272 is electrically connected to the third bias electrode 204. The generated third voltage pulse signal DC9 can be supplied to the third bias electrode 204. By supplying the third voltage pulse signal DC9 to the third bias electrode 204, a bias pulse signal based on a DC voltage is generated, which can draw ionic components in the plasma generated on the substrate W of the substrate support 11 towards the third bias electrode 204.

[0062] Figure 5 shows an example of the first to third voltage pulse signals DC7 to DC9. The first voltage pulse signal DC7 has a sequence of voltage pulses PS1 with a first secondary voltage level V4 during the first state S1 within the repetition period T, and a reference voltage level V4 during the second state S2 within the repetition period T. ref It can have a continuous state. That is, during the second state S2, the first voltage pulse signal DC7 is at the reference voltage level V ref It can be maintained at the reference voltage level V. ref The absolute value of is smaller than the absolute value of the first secondary voltage level V4. In one embodiment, the first secondary voltage level V4 has negative polarity. In one embodiment, the reference voltage level V ref It has a zero voltage level.

[0063] The second voltage pulse signal DC8 has a sequence of voltage pulses PS2 having a second secondary voltage level V5 during the first state S1 within the repetition period T, and a reference voltage level V5 during the second state S2 within the repetition period T. ref It can have a continuous state. That is, during the second state S2, the second voltage pulse signal DC8 is at the reference voltage level V ref It can be maintained at the reference voltage level V. ref The absolute value of is smaller than the absolute value of the second secondary voltage level V5. In one embodiment, the second secondary voltage level V5 has negative polarity and reference voltage level Vref has a zero voltage level.

[0064] The third voltage pulse signal DC9 has a sequence PS3 of voltage pulses having a third secondary voltage level V6 during a first state S1 within a repetition period T, and a reference voltage level V during a second state S2 within the repetition period T. ref and may have continuously. That is, during the second state S2, the third voltage pulse signal DC9 may be maintained at the reference voltage level V. ref The absolute value of the reference voltage level V ref is smaller than the absolute value of the third secondary voltage level V6. In one embodiment, the third secondary voltage level V6 has a negative polarity, and the reference voltage level V ref has a zero voltage level.

[0065] In one embodiment, the absolute value of the third secondary voltage level V6 may be larger than the absolute value of the second secondary voltage level V5, and the absolute value of the second secondary voltage level V5 may be larger than the absolute value of the first secondary voltage level V4. The absolute value of the second secondary voltage level V5 may be larger than the absolute values of the first secondary voltage level V4 and the third secondary voltage level V6. The absolute value of the first secondary voltage level V4 may be larger than the absolute values of the second secondary voltage level V5 and the third secondary voltage level V6. The magnitudes of the first to third secondary voltage levels V4 to V6 may be adjusted so that the plasma sheath generated on the substrate approaches the substrate in parallel.

[0066] <An example of a plasma processing method> The plasma processing method includes an etching process of etching a film on a substrate W using plasma. In one embodiment, the plasma processing method is executed by a control unit 2 in a plasma processing apparatus 1.

[0067] First, the substrate W is carried into the chamber 10 by a transfer arm, placed on the substrate support portion 11 by a lifter, and adsorbed and held on the substrate support portion 11 as shown in FIG. 2.

[0068] Next, the processing gas is supplied to the showerhead 13 by the gas supply unit 20, and then supplied from the showerhead 13 to the plasma processing space 10s. The processing gas supplied at this time includes a gas that generates the active species necessary for etching the substrate W.

[0069] One or more RF signals are supplied from the RF power supply 31 to the upper electrode and / or lower electrode. The atmosphere inside the plasma processing space 10s is exhausted from the gas outlet 10e, and the inside of the plasma processing space 10s may be depressurized. As a result, plasma is generated on the substrate support portion 11 of the plasma processing space 10s, and the substrate W is etched.

[0070] During plasma generation, a first voltage pulse signal DC7 is supplied to the first bias electrode 202 from the first voltage pulse generator 270 shown in Figure 3, a second voltage pulse signal DC8 is supplied to the second bias electrode 203 from the second voltage pulse generator 271, and a third voltage pulse signal DC9 is supplied to the third bias electrode 204 from the third voltage pulse generator 272. As a result, a bias potential based on the voltage pulse is generated on the substrate W and the ring assembly 112, and ionic components in the plasma on the substrate W are drawn towards the substrate W. At this time, the first to third secondary voltage levels V4 to V6 of the first to third voltage pulse signals DC7 to DC9 are adjusted, and a DC voltage is applied to each of the first to third bias electrodes 202 to 204, so that the plasma sheath PS generated above the substrate W and the ring assembly 112 is brought closer to being parallel (horizontal) to the substrate W, as shown in Figure 6. As a result, the angle at which the ionic components of the plasma enter the substrate W (ion incidence angle) approaches perpendicularity to the substrate W within the plane of the substrate W.

[0071] According to this exemplary embodiment, the plasma processing apparatus 1 includes a first bias electrode 202, a second bias electrode 203, a third bias electrode 204, a first DC power supply 250, a second DC power supply 251, a third DC power supply 252, a voltage adder 260, a first voltage pulse generator 270, a second voltage pulse generator 271, and a third voltage pulse generator 272. This allows, for example, control of the ion incidence angle in the plane of the substrate W during plasma processing. As a result, the in-plane uniformity of the substrate during plasma processing can be improved.

[0072] In the above embodiment, the first bias electrode 202 and the second bias electrode 203 were positioned below the substrate support surface, and the third bias electrode 204 was positioned below the ring support surface. However, as shown in Figure 7, the first bias electrode 202 may be positioned below the substrate support surface, the second bias electrode 203 may be positioned below both the substrate support surface and the ring support surface, and the third bias electrode 204 may be positioned below the ring support surface.

[0073] Furthermore, as shown in Figure 8, the first bias electrode 202 and the second bias electrode 203 may be positioned below the substrate support surface, and the third bias electrode 204 may be positioned below both the substrate support surface and the ring support surface. In addition, as shown in Figure 9, the first bias electrode 202, the second bias electrode 203, and the third bias electrode 204 may be positioned below the substrate support surface.

[0074] In the above embodiment, the plasma processing apparatus 1 may have bias electrodes in the electrostatic chuck 1111 in addition to the first to third bias electrodes 202 to 204. The number of bias electrodes may be four or more.

[0075] In the above embodiment, as shown in Figure 10, the first bias electrode 202, the second bias electrode 203, and the third bias electrode 204 may be positioned at different heights from each other. In one embodiment, the second bias electrode 203 may be positioned lower than the first bias electrode 202, and the third bias electrode 204 may be positioned lower than the second bias electrode 203. In one embodiment, the outer edge region 202a of the first bias electrode 202 may overlap vertically with the inner edge region 203a of the second bias electrode 203, and the outer edge region 203b of the second bias electrode 203 may overlap vertically with the inner edge region 204a of the third bias electrode 204. The radial width D3 of the overlapping portion of the first bias electrode 202 and the second bias electrode 203 may be 9 mm to 11 mm. The radial width D4 of the overlapping portion between the second bias electrode 203 and the third bias electrode 204 may be 9 mm to 11 mm.

[0076] Furthermore, the second bias electrode 203 may be positioned higher than the first bias electrode 202, and the third bias electrode 204 may be positioned higher than the second bias electrode 203.

[0077] The second bias electrode 203 may be positioned higher or lower than the first bias electrode 202 and the third bias electrode 204. In this case, the first bias electrode 202 may be positioned higher or lower than the third bias electrode 204, or at the same height.

[0078] <Second exemplary embodiment> A second exemplary embodiment of the plasma processing apparatus 1 will now be described. Figure 11 shows an example configuration of the substrate support 11 and DC power supply 32 in the second exemplary embodiment. In one embodiment, the substrate support 11 may be the same as in the first exemplary embodiment. In one embodiment, the first bias electrode 202, the second bias electrode 203 and the third bias electrode 204 may be arranged at different heights, with the second bias electrode 203 being positioned lower than the first bias electrode 202 and the third bias electrode 204 being positioned lower than the second bias electrode 203.

[0079] In one embodiment, the DC power supply 32 includes a first DC power supply 550, a second DC power supply 551, a third DC power supply 552, a first voltage pulse generator 570, a second voltage pulse generator 571, and a third voltage pulse generator 572.

[0080] The first DC power supply 550 can generate a first DC signal DC1 having a first voltage level V1. The first voltage level V1 may have negative polarity. The first DC power supply 550 may be electrically connected to a first voltage pulse generator 570. The generated first DC signal DC1 can be supplied to the first voltage pulse generator 570.

[0081] The second DC power supply 551 can generate a second DC signal DC2 having a second voltage level V2. The second voltage level V2 may have negative polarity. The second DC power supply 551 may be electrically connected to a second voltage pulse generator 571. The generated second DC signal DC2 can be supplied to the second voltage pulse generator 571.

[0082] The third DC power supply 552 can generate a third DC signal DC3 having a third voltage level V3. The third voltage level V3 may have negative polarity. The third DC power supply 552 may be electrically connected to a third voltage pulse generator 572. The generated second DC signal DC3 can be supplied to the third voltage pulse generator 572.

[0083] The first voltage pulse generator 570 can generate a first voltage pulse signal DC4 having a first voltage level V1 from a first DC signal DC1 supplied from a first DC power supply 550. The first voltage pulse signal DC4 may include a sequence of first voltage pulses having the first voltage level V1. In one embodiment, the sequence of first voltage pulses has a pulse pattern similar to the example shown in Figure 5. The first voltage pulse generator 570 may be electrically connected to the first bias electrode 202. The generated first voltage pulse signal DC4 can be supplied to the first bias electrode 202. By supplying the first voltage pulse signal DC4 to the first bias electrode 202, a bias pulse signal based on a DC voltage is generated, which can draw ionic components in the plasma generated on the substrate W of the substrate support 11 towards the first bias electrode 202.

[0084] The second voltage pulse generator 571 can generate a second voltage pulse signal DC5 having a second voltage level V2 from a second DC signal DC2 supplied from a second DC power supply 551. The second voltage pulse signal DC5 may include a sequence of second voltage pulses having a second voltage level V2. In one embodiment, the sequence of second voltage pulses has a pulse pattern similar to the example shown in Figure 5. The second voltage pulse generator 571 may be electrically connected to the second bias electrode 203. The generated second voltage pulse signal DC5 can be supplied to the second bias electrode 203. By supplying the second voltage pulse signal DC5 to the second bias electrode 203, a bias pulse signal based on a DC voltage is generated, which can draw ionic components in the plasma generated on the substrate W of the substrate support 11 towards the second bias electrode 203.

[0085] The third voltage pulse generator 572 can generate a third voltage pulse signal DC6 having a third voltage level V3 from a third DC signal DC3 supplied from a third DC power supply 552. The third voltage pulse signal DC6 may include a sequence of third voltage pulses having a third voltage level V3. In one embodiment, the sequence of third voltage pulses has a pulse pattern similar to the example shown in Figure 5. The third voltage pulse generator 572 may be electrically connected to a third bias electrode 204. The generated third voltage pulse signal DC6 can be supplied to the third bias electrode 204. By supplying the third voltage pulse signal DC6 to the third bias electrode 204, a bias pulse signal based on a DC voltage is generated, which can draw ionic components in the plasma generated on the substrate W of the substrate support 11 towards the third bias electrode 204. Other configurations of the plasma processing apparatus 1 may be the same as in the first exemplary embodiment described above.

[0086] During plasma generation, a first voltage pulse signal DC4 is supplied from the first voltage pulse generator 570 to the first bias electrode 202, a second voltage pulse signal DC5 is supplied from the second voltage pulse generator 571 to the second bias electrode 203, and a third voltage pulse signal DC6 is supplied from the third voltage pulse generator 572 to the third bias electrode 204. This generates a bias potential based on the voltage pulses on the substrate W and the ring assembly 112, drawing ionic components in the plasma on the substrate W towards the substrate W. At this time, the first to third voltage levels V1 to V3 of the first to third voltage pulse signals DC4 to DC6 are adjusted, and voltage pulses based on DC voltages are applied to each of the first to third bias electrodes 202 to 204, respectively, so that the plasma sheath PS generated above the substrate W and the ring assembly 112 is brought closer to being parallel (horizontal) to the substrate W, as shown in Figure 6. As a result, the angle at which the ionic components of the plasma enter the substrate W (ion incidence angle) approaches perpendicularity to the substrate W within the plane of the substrate W.

[0087] <Third exemplary embodiment> Figure 12 shows an example configuration of the substrate support 11 and DC power supply 32 in a third exemplary embodiment. In one embodiment, the DC power supply 32 may include a first DC power supply 550, a second DC power supply 551, a third DC power supply 552, a first voltage pulse generator 570, a second voltage pulse generator 571, and a third voltage pulse generator 572, similar to the second exemplary embodiment described above.

[0088] The first voltage pulse generator 570 can generate a first voltage pulse signal DC4 having a first voltage level V1. The first voltage pulse signal DC4 may include a sequence of first voltage pulses having the first voltage level V1. In one embodiment, the sequence of first voltage pulses has a pulse pattern similar to the example shown in Figure 5. The second voltage pulse generator 571 can generate a second voltage pulse signal DC5 having a fourth voltage level V4, which is the sum of the first voltage level V1 and the second voltage level V2. The second voltage pulse signal DC5 may include a sequence of second voltage pulses having the fourth voltage level V4. In one embodiment, the sequence of second voltage pulses has a pulse pattern similar to the example shown in Figure 5. The third voltage pulse generator 572 can generate a third voltage pulse signal DC6 having a fifth voltage level V5, which is the sum of the first voltage level V1, the second voltage level V2, and the third voltage level V3. The third voltage pulse signal DC6 may include a sequence of third voltage pulses having a fifth voltage level V5. In one embodiment, the sequence of third voltage pulses has a pulse pattern similar to the example shown in Figure 5. Other configurations of the plasma processing apparatus 1 may be the same as those in the second or first exemplary embodiment described above.

[0089] During plasma generation, a first voltage pulse signal DC4 having a first voltage level V1 is supplied from the first voltage pulse generator 570 to the first bias electrode 202, a second voltage pulse signal DC5 having a fourth voltage level V4 is supplied from the second voltage pulse generator 571 to the second bias electrode 203, and a third voltage pulse signal DC6 having a fifth voltage level V5 is supplied from the third voltage pulse generator 572 to the third bias electrode 204. This generates bias pulse signals based on DC voltages to the substrate W and the ring assembly 112, drawing ionic components in the plasma on the substrate W towards the substrate W. By applying voltage pulses based on DC voltages to each of the first to third bias electrodes 202 to 204, the plasma sheath PS generated above the substrate W and the ring assembly 112 is brought closer to being parallel (horizontal) to the substrate W, as shown in Figure 6. As a result, the angle at which the ionic components of the plasma enter the substrate W (ion incidence angle) approaches perpendicularity to the substrate W within the plane of the substrate W.

[0090] In the embodiments described above, the ring chuck electrode 201 shown in Figure 3 had two electrodes 400 and 401 having opposite polarities, but it may have a single electrode with unipolarity. The number of bias electrodes, DC power supplies, and voltage pulse generators was three each, but it may be four or more.

[0091] In the above embodiment, a capacitively coupled plasma apparatus was described as an example, but the invention is not limited to this and may be applied to other plasma apparatuses. For example, an inductively coupled plasma apparatus may be used instead of a capacitively coupled plasma apparatus. In this case, the inductively coupled plasma apparatus includes an antenna and a lower electrode. The lower electrode is located within the substrate support, and the antenna is located above or above the chamber. In one embodiment, the DC power supply 32 may be electrically connected to a bias electrode located within the substrate support, and a sequence of voltage pulses may be applied to the bias electrode. The RF power supply 31 may be electrically connected to the antenna and supply an RF signal to the antenna.

[0092] Embodiments of this disclosure further include the following aspects:

[0093] (Note 1) Plasma processing chamber and A substrate support unit disposed within the plasma processing chamber, the substrate support unit comprising: a base; an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface; and an edge ring disposed on the ring support surface so as to surround a substrate placed on the substrate support surface. Within the electrostatic chuck, a substrate chuck electrode is positioned below the substrate support surface, Within the electrostatic chuck, at least one ring chuck electrode is positioned below the ring support surface, A first bias electrode having a first outer diameter is disposed within the electrostatic chuck, A second bias electrode is disposed within the electrostatic chuck and has a second outer diameter larger than the first outer diameter, A third bias electrode is disposed within the electrostatic chuck and has a third outer diameter larger than the second outer diameter, A first DC power supply configured to generate a first primary DC signal having a first primary voltage level, A second DC power supply configured to generate a second primary DC signal having a second primary voltage level, A third DC power supply configured to generate a third primary DC signal having a third primary voltage level, A voltage adder configured to generate a first secondary DC signal having a first secondary voltage level, a second secondary DC signal having a second secondary voltage level, and a third secondary DC signal having a third secondary voltage level using the first to third primary DC signals, wherein the first secondary voltage level, the second secondary voltage level, and the third secondary voltage level are The first primary voltage level, The voltage level obtained by adding the first primary voltage level and the second primary voltage level, A voltage adder is selected from among the voltage levels obtained by adding the first primary voltage level and the third primary voltage level, such that they do not overlap. A first voltage pulse generator is electrically connected to the first bias electrode and configured to generate a first voltage pulse signal having the first secondary voltage level from the first secondary DC signal, A second voltage pulse generator is electrically connected to the second bias electrode and configured to generate a second voltage pulse signal having the second secondary voltage level from the second secondary DC signal, A third voltage pulse generator is electrically connected to the third bias electrode and configured to generate a third voltage pulse signal having the third secondary voltage level from the third secondary DC signal, A plasma processing apparatus, including a plasma treatment device.

[0094] (Note 2) The first voltage pulse signal, the second voltage pulse signal, and the third voltage pulse signal each include a sequence of first voltage pulses, a sequence of second voltage pulses, and a sequence of third voltage pulses, respectively. The plasma processing apparatus described in Appendix 1.

[0095] (Note 3) The first primary voltage level, the second primary voltage level, and the third primary voltage level have negative polarity. A plasma processing apparatus as described in Appendix 1 or 2.

[0096] (Note 4) The absolute value of the first primary voltage level is greater than the absolute values ​​of the second primary voltage level and the third primary voltage level. The plasma processing apparatus described in Appendix 3.

[0097] (Note 5) The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is arranged so as to overlap the substrate support surface and the ring support surface in the longitudinal direction. The third bias electrode is positioned so as to overlap the ring support surface in the longitudinal direction. A plasma processing apparatus as described in any one of the appendices 1 to 4.

[0098] (Note 6) The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is positioned so as to overlap the substrate support surface in the longitudinal direction. The third bias electrode is positioned so as to overlap the ring support surface in the longitudinal direction. A plasma processing apparatus as described in any one of the appendices 1 to 4.

[0099] (Note 7) The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is positioned so as to overlap the substrate support surface in the longitudinal direction. The third bias electrode is arranged so as to overlap the substrate support surface and the ring support surface in the longitudinal direction. A plasma processing apparatus as described in any one of the appendices 1 to 4.

[0100] (Note 8) The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is positioned so as to overlap the substrate support surface in the longitudinal direction. The third bias electrode is positioned so as to overlap the substrate support surface in the longitudinal direction. A plasma processing apparatus as described in any one of the appendices 1 to 4.

[0101] (Note 9) The first bias electrode, the second bias electrode, and the third bias electrode are arranged at the same height. A plasma processing apparatus as described in any one of the items 1 to 8 of the appendix.

[0102] (Note 10) The first bias electrode, the second bias electrode, and the third bias electrode are arranged at different heights from each other. A plasma processing apparatus as described in any one of the items 1 to 8 of the appendix.

[0103] (Note 11) The second bias electrode is positioned lower than the first bias electrode. The third bias electrode is positioned lower than the second bias electrode. The plasma processing apparatus described in Appendix 10.

[0104] (Note 12) The outer edge region of the first bias electrode overlaps longitudinally with the inner edge region of the second bias electrode. The outer edge region of the second bias electrode overlaps longitudinally with the inner edge region of the third bias electrode. The plasma processing apparatus described in Appendix 11.

[0105] (Note 13) The ring chuck electrode is, An inner ring chuck electrode to which a first ring chuck voltage having a first polarity is applied, Includes an outer ring chuck electrode to which a second ring chuck voltage having a second polarity is applied, A plasma processing apparatus as described in any one of the appendices 1 to 12.

[0106] (Note 14) Plasma processing chamber and A substrate support unit disposed within the plasma processing chamber, the substrate support unit comprising: a base; an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface; and an edge ring disposed on the ring support surface so as to surround the substrate on the substrate support surface. Within the electrostatic chuck, a substrate chuck electrode is positioned below the substrate support surface, Within the electrostatic chuck, at least one ring chuck electrode is positioned below the ring support surface, A first bias electrode having a first outer diameter is disposed within the electrostatic chuck, A second bias electrode is disposed within the electrostatic chuck and has a second outer diameter larger than the first outer diameter, A third bias electrode is disposed within the electrostatic chuck and has a third outer diameter larger than the second outer diameter, A first voltage pulse generator is electrically connected to the first bias electrode and configured to generate a first voltage pulse signal having a first voltage level, A second voltage pulse generator is electrically connected to the second bias electrode and configured to generate a second voltage pulse signal having a second voltage level, A third voltage pulse generator is electrically connected to the third bias electrode and configured to generate a third voltage pulse signal having a third voltage level, A plasma processing apparatus, including a plasma treatment device.

[0107] (Note 15) A first DC power supply configured to supply a first DC signal having the first voltage level to the first voltage pulse generator, A second DC power supply configured to supply a second DC signal having the second voltage level to the second voltage pulse generator, A third DC power supply configured to supply a third DC signal having the third voltage level to the third voltage pulse generator, The plasma processing apparatus described in Appendix 14, further including the plasma processing apparatus described in Appendix 14.

[0108] (Note 16) The first voltage level, the second voltage level, and the third voltage level have negative polarity. A plasma processing apparatus as described in Appendix 14 or 15.

[0109] (Note 17) The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is positioned so as to overlap the substrate support surface in the longitudinal direction. The third bias electrode is positioned so as to overlap the ring support surface in the longitudinal direction. A plasma processing apparatus as described in any one of the appendices 14 to 16.

[0110] (Note 18) The second bias electrode is positioned lower than the first bias electrode. The third bias electrode is positioned lower than the second bias electrode. The plasma processing apparatus described in Appendix 17.

[0111] (Note 19) The outer edge region of the first bias electrode overlaps longitudinally with the inner edge region of the second bias electrode. The outer edge region of the second bias electrode overlaps longitudinally with the inner edge region of the third bias electrode. The plasma processing apparatus described in Appendix 18.

[0112] (Note 20) Plasma processing chamber and A substrate support unit disposed within the plasma processing chamber, the substrate support unit comprising: a base; an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface; and an edge ring disposed on the ring support surface so as to surround a substrate placed on the substrate support surface. Within the electrostatic chuck, a substrate chuck electrode is positioned below the substrate support surface, Within the electrostatic chuck, at least one ring chuck electrode is positioned below the ring support surface, A first bias electrode having a first outer diameter is disposed within the electrostatic chuck, A second bias electrode is disposed within the electrostatic chuck and has a second outer diameter larger than the first outer diameter, A third bias electrode is disposed within the electrostatic chuck and has a third outer diameter larger than the second outer diameter, A first DC power supply configured to generate a first DC signal having a first voltage level, A second DC power supply configured to generate a second DC signal having a second voltage level, A third DC power supply configured to generate a third DC signal having a third voltage level, A first voltage pulse generator is electrically connected to the first bias electrode and configured to generate a first voltage pulse signal having the first voltage level, A second voltage pulse generator is electrically connected to the second bias electrode and configured to generate a second voltage pulse signal having a fourth voltage level obtained by adding the first voltage level and the second voltage level. A third voltage pulse generator is electrically connected to the third bias electrode and configured to generate a third voltage pulse signal having a fifth voltage level obtained by adding the first voltage level, the second voltage level, and the third voltage level. A plasma processing apparatus, including a plasma treatment device.

[0113] The embodiments described above are for illustrative purposes only and are not intended to limit the scope of this disclosure. The embodiments described above can be modified in various ways without departing from the scope and spirit of this disclosure. For example, some components of one embodiment can be added to other embodiments, or some components of one embodiment can be replaced with corresponding components of other embodiments. [Explanation of symbols]

[0114] 1... Plasma processing apparatus, 10... Chamber, 11... Substrate support, 112... Ring assembly, 1111... Electrostatic chuck, 200... Substrate chuck electrode, 201... Ring chuck electrode, 202... First bias electrode, 203... Second bias electrode, 204... Third bias electrode, 250... First DC power supply, 251... Second DC power supply, 252... Third DC power supply, 260... Voltage adder, 270... First voltage pulse generator, 271... Second voltage pulse generator, 272... Third voltage pulse generator, W... Substrate

Claims

1. Plasma processing chamber and A substrate support unit disposed within the plasma processing chamber, the substrate support unit comprising: a base; an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface; and an edge ring disposed on the ring support surface so as to surround a substrate placed on the substrate support surface. Within the electrostatic chuck, a substrate chuck electrode is positioned below the substrate support surface, Within the electrostatic chuck, at least one ring chuck electrode is positioned below the ring support surface, A first bias electrode having a first outer diameter is disposed within the electrostatic chuck, A second bias electrode is disposed within the electrostatic chuck and has a second outer diameter larger than the first outer diameter, A third bias electrode is disposed within the electrostatic chuck and has a third outer diameter larger than the second outer diameter, A first DC power supply configured to generate a first primary DC signal having a first primary voltage level, A second DC power supply configured to generate a second primary DC signal having a second primary voltage level, A third DC power supply configured to generate a third primary DC signal having a third primary voltage level, A voltage adder configured to generate a first secondary DC signal having a first secondary voltage level, a second secondary DC signal having a second secondary voltage level, and a third secondary DC signal having a third secondary voltage level using the first to third primary DC signals, wherein the first secondary voltage level, the second secondary voltage level, and the third secondary voltage level are The first primary voltage level, The voltage level obtained by adding the first primary voltage level and the second primary voltage level, A voltage adder is selected from among the voltage levels obtained by adding the first primary voltage level and the third primary voltage level, such that they do not overlap. A first voltage pulse generator is electrically connected to the first bias electrode and configured to generate a first voltage pulse signal having the first secondary voltage level from the first secondary DC signal, A second voltage pulse generator is electrically connected to the second bias electrode and configured to generate a second voltage pulse signal having the second secondary voltage level from the second secondary DC signal, A third voltage pulse generator is electrically connected to the third bias electrode and configured to generate a third voltage pulse signal having the third secondary voltage level from the third secondary DC signal, A plasma processing apparatus, including a plasma treatment device.

2. The first voltage pulse signal, the second voltage pulse signal, and the third voltage pulse signal each include a sequence of first voltage pulses, a sequence of second voltage pulses, and a sequence of third voltage pulses, respectively. The plasma processing apparatus according to claim 1.

3. The first primary voltage level, the second primary voltage level, and the third primary voltage level have negative polarity. The plasma processing apparatus according to claim 1.

4. The absolute value of the first primary voltage level is greater than the absolute values ​​of the second primary voltage level and the third primary voltage level. The plasma processing apparatus according to claim 3.

5. The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is arranged so as to overlap the substrate support surface and the ring support surface in the longitudinal direction. The third bias electrode is positioned so as to overlap the ring support surface in the longitudinal direction. The plasma processing apparatus according to claim 1.

6. The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The third bias electrode is positioned so as to overlap the ring support surface in the longitudinal direction. The plasma processing apparatus according to claim 1.

7. The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The third bias electrode is arranged so as to overlap the substrate support surface and the ring support surface in the longitudinal direction. The plasma processing apparatus according to claim 1.

8. The first bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The second bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The third bias electrode is arranged so as to overlap the substrate support surface in the longitudinal direction. The plasma processing apparatus according to claim 1.

9. The first bias electrode, the second bias electrode, and the third bias electrode are arranged at the same height. The plasma processing apparatus according to claim 1.

10. The first bias electrode, the second bias electrode, and the third bias electrode are arranged at different heights from each other. The plasma processing apparatus according to claim 1.

11. The second bias electrode is positioned lower than the first bias electrode. The third bias electrode is positioned lower than the second bias electrode. The plasma processing apparatus according to claim 10.

12. The outer edge region of the first bias electrode overlaps longitudinally with the inner edge region of the second bias electrode. The outer edge region of the second bias electrode overlaps longitudinally with the inner edge region of the third bias electrode. The plasma processing apparatus according to claim 11.

13. The ring chuck electrode is, An inner ring chuck electrode to which a first ring chuck voltage having a first polarity is applied, Includes an outer ring chuck electrode to which a second ring chuck voltage having a second polarity is applied, The plasma processing apparatus according to claim 1.

14. Plasma processing chamber and A substrate support unit disposed within the plasma processing chamber, the substrate support unit comprising: a base; an electrostatic chuck disposed on the base and having a substrate support surface and a ring support surface; and an edge ring disposed on the ring support surface so as to surround a substrate placed on the substrate support surface. Within the electrostatic chuck, a substrate chuck electrode is positioned below the substrate support surface, Within the electrostatic chuck, at least one ring chuck electrode is positioned below the ring support surface, A first bias electrode having a first outer diameter is disposed within the electrostatic chuck, A second bias electrode is disposed within the electrostatic chuck and has a second outer diameter larger than the first outer diameter, A third bias electrode is disposed within the electrostatic chuck and has a third outer diameter larger than the second outer diameter, A first DC power supply configured to generate a first DC signal having a first voltage level, A second DC power supply configured to generate a second DC signal having a second voltage level, A third DC power supply configured to generate a third DC signal having a third voltage level, A first voltage pulse generator is electrically connected to the first bias electrode and configured to generate a first voltage pulse signal having the first voltage level, A second voltage pulse generator is electrically connected to the second bias electrode and configured to generate a second voltage pulse signal having a fourth voltage level obtained by adding the first voltage level and the second voltage level. A third voltage pulse generator is electrically connected to the third bias electrode and configured to generate a third voltage pulse signal having a fifth voltage level obtained by adding the first voltage level, the second voltage level, and the third voltage level. A plasma processing apparatus, including a plasma treatment device.

Images