High-frequency semiconductor integrated circuits

Abstract

To suppress fluctuations of an impedance involved in switching control and improve a switching speed.SOLUTION: According to one embodiment, a high frequency semiconductor integrated circuit includes a first input terminal RFC, a second input terminal CTRL, a first output terminal RF1, a second output terminal RF2, a first switch circuit SW1a, a second switch circuit SW2a, a third switch circuit SW1b, and a fourth switch circuit SW2b. In a case where a coupling destination of the first input terminal is switched from the first output terminal to the second output terminal, a third switching operation changing the third switch circuit from an ON state to an OFF state and a fourth switching operation changing the fourth switch circuit from the OFF state to the ON state are finished, after a first switching operation changing the first switch circuit from the ON state to the OFF state and a second switching operation changing the second switch circuit from the OFF state to the ON state are finished.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to high-frequency semiconductor integrated circuits.

Background Art

[0002] As one type of high-frequency semiconductor integrated circuit, a semiconductor switch circuit corresponding to a high-frequency signal is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a high-frequency semiconductor integrated circuit that can suppress fluctuations in impedance associated with switching control and improve the switching speed.

Means for Solving the Problems

[0005] The high-frequency semiconductor integrated circuit according to the embodiment includes a first input terminal for receiving a high-frequency signal, a second input terminal for receiving a control signal, a first output terminal for outputting a high-frequency signal, a second output terminal for outputting a high-frequency signal, a first switch circuit for controlling the electrical connection between the first input terminal and the first output terminal, a second switch circuit for controlling the electrical connection between the first input terminal and the second output terminal, a third switch circuit for controlling the electrical connection between the first input terminal and the first output terminal and connected in parallel with the first switch circuit, and a fourth switch circuit for controlling the electrical connection between the first input terminal and the second output terminal and connected in parallel with the second switch circuit. When switching the connection destination of the first input terminal from the first output terminal to the second output terminal, a first switching operation to turn the first switch circuit from the ON state to the OFF state and a second switching operation to turn the second switch circuit from the OFF state to the ON state are completed, followed by a third switching operation to turn the third switch circuit from the ON state to the OFF state and a fourth switching operation to turn the fourth switch circuit from the OFF state to the ON state. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of the overall configuration of a high-frequency semiconductor integrated circuit according to the first embodiment. [Figure 2] Figure 2 shows an example of the circuit configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b provided in the high-frequency semiconductor integrated circuit according to the first embodiment. [Figure 3] Figure 3 is a graph showing the switching operation of the switch circuit provided in the high-frequency semiconductor integrated circuit according to the first embodiment. [Figure 4] Figure 4 shows the switching sequence in the switching operation of a high-frequency semiconductor integrated circuit according to the first embodiment, when the rise time and fall time are the same. [Figure 5] Figure 5 shows the switching sequence in the switching operation of a high-frequency semiconductor integrated circuit according to the first embodiment when the rise time is shorter than the fall time. [Figure 6]Figure 6 shows the switching sequence in the switching operation of a high-frequency semiconductor integrated circuit according to the first embodiment when the rise time is longer than the fall time. [Figure 7] Figure 7 shows an example of the relationship between the number of SPDT switches in parallel and the switching operation sequence. [Figure 8] Figure 8 is a schematic diagram showing the relationship between gate widths Wga and Wgb in a high-frequency semiconductor integrated circuit according to a modified example of the first embodiment. [Figure 9] Figure 9 is a graph showing the relationship between the gate width Wga and Wgb division ratio and the RFC impedance when switch circuits SW1a and SW2a are in the ON state in a high-frequency semiconductor integrated circuit according to a modified example of the first embodiment. [Figure 10] Figure 10 is a block diagram showing an example of the overall configuration of a high-frequency semiconductor integrated circuit according to the second embodiment. [Figure 11] Figure 11 shows an example of the circuit configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b provided in the high-frequency semiconductor integrated circuit according to the second embodiment. [Figure 12] Figure 12 is a block diagram showing an example of the overall configuration of a high-frequency semiconductor integrated circuit according to the third embodiment. [Figure 13] Figure 13 shows an example of the circuit configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b provided in the high-frequency semiconductor integrated circuit according to the third embodiment. [Figure 14] Figure 14 is a circuit diagram of a delay circuit included in the high-frequency semiconductor integrated circuit according to the third embodiment. [Figure 15] Figure 15 is a block diagram showing an example of the overall configuration of a high-frequency semiconductor integrated circuit according to the fourth embodiment. [Figure 16] Figure 16 is a block diagram showing an example of the overall configuration of a high-frequency semiconductor integrated circuit according to the fifth embodiment. [Figure 17] Figure 17 shows an example of the circuit configuration of the switch circuits SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c provided in the high-frequency semiconductor integrated circuit according to the fifth embodiment. [Figure 18] FIG. 18 is a diagram showing a switching sequence when the rise time length and the fall time length are the same in the switching operation of the high-frequency semiconductor integrated circuit according to the fifth embodiment. [Figure 19] FIG. 19 is a diagram showing a switching sequence when the rise time length is shorter than the fall time length in the switching operation of the high-frequency semiconductor integrated circuit according to the fifth embodiment. [Figure 20] FIG. 20 is a diagram showing a switching sequence when the rise time length is longer than the fall time length in the switching operation of the high-frequency semiconductor integrated circuit according to the fifth embodiment. [Figure 21] FIG. 21 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit according to the sixth embodiment. [Figure 22] FIG. 22 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit according to the seventh embodiment. [Figure 23] FIG. 23 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit according to the eighth embodiment.

Embodiments for Carrying Out the Invention

[0007] Embodiments will be described below with reference to the drawings. In the following description, components having substantially the same functions and configurations may be denoted by the same reference numerals, and repeated descriptions may be omitted. Also, the description of one embodiment applies to the description of another embodiment as well, unless explicitly or implicitly excluded.

[0008] In this specification and the claims, when a first element is “connected to” a second element, it includes that the first element is directly or always or selectively connected to the second element via an element having conductivity.

[0009] 1. First Embodiment A high-frequency semiconductor integrated circuit 1 according to the first embodiment will be described. In this embodiment, a single-pole double-throw (SPDT) switch will be described as an example of the high-frequency semiconductor integrated circuit 1. An SPDT switch is a high-frequency signal switching switch having one input terminal and two output terminals. For example, an SPDT switch is formed on a silicon on insulator (SOI) substrate. Note that the high-frequency semiconductor integrated circuit 1 is not limited to an SPDT switch. It can also be applied to an integrated circuit (IC) with three output terminals. For example, the high-frequency semiconductor integrated circuit 1 may be an SP3T switch.

[0010] 1.1 Configuration First, an example of the overall configuration of the high-frequency semiconductor integrated circuit 1 will be described with reference to Figure 1. Figure 1 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit 1.

[0011] As shown in Figure 1, the high-frequency semiconductor integrated circuit 1 has an input terminal (high-frequency signal input terminal) RFC for receiving high-frequency signals from the outside, an input terminal (control signal input terminal) CTRL for receiving control signals from the outside, and two output terminals (high-frequency signal output terminals) RF1 and RF2 for outputting high-frequency signals to the outside. Based on the control signal input from the input terminal CTRL, the high-frequency semiconductor integrated circuit 1 electrically connects the input terminal RFC with either the output terminal RF1 or RF2.

[0012] The high-frequency semiconductor integrated circuit 1 includes switching units 2a and 2b, and a buffer 3.

[0013] Switching units 2a and 2b can each function as a single SPDT switch. Switching units 2a and 2b are connected in parallel. That is, the high-frequency semiconductor integrated circuit 1 includes two parallel SPDT switches. In other words, the SPDT switch is divided into two stages. For example, the switching time of the connection in switching unit 2a is shorter than the switching time of the connection in switching unit 2b. That is, the switching speed of switching unit 2a is faster than the switching speed of switching unit 2b. Therefore, for example, when switching the connection destination of the input terminal RFC, the switching operation in switching unit 2b is completed after the switching operation in switching unit 2a is completed. That is, the connection switching operation is performed in two stages. Hereafter, unless we specify which of switching units 2a and 2b is being referred to, we will use the term "switching unit 2". Note that there may be three or more switching units 2. That is, there may be three or more SPDT switches in parallel.

[0014] The switching unit 2a includes two switch circuits SW1a and SW2a. Based on a control signal, one of the switch circuits SW1a and SW2a is turned ON and the other is turned OFF.

[0015] The switch circuit SW1a electrically connects the input terminal RFC and the output terminal RF1 based on the control signal input from the forward output terminal (+) of buffer 3. One end of the current path of the switch circuit SW1a is connected to the input terminal RFC, and the other end is connected to the output terminal RF1.

[0016] The switch circuit SW2a electrically connects the input terminal RFC and the output terminal RF2 based on the inverted signal of the control signal input from the inverting output terminal (-) of buffer 3. One end of the current path of the switch circuit SW2a is connected to the input terminal RFC, and the other end is connected to the output terminal RF2.

[0017] For example, when the control signal is at a "High" ("H") level, switch circuit SW1a is set to the ON state and switch circuit SW2a is set to the OFF state. Also, for example, when the control signal is at a "Low" ("L") level, switch circuit SW1a is set to the OFF state and switch circuit SW2a is set to the ON state.

[0018] The switching unit 2b includes two switch circuits SW1b and SW2b. Based on a control signal, one of the switch circuits SW1b or SW2b is turned ON and the other is turned OFF.

[0019] The switch circuit SW1b electrically connects the input terminal RFC and the output terminal RF1 based on the control signal input from the forward output terminal (+) of the buffer 3. One end of the current path of the switch circuit SW1b is connected to the input terminal RFC, and the other end is connected to the output terminal RF1. The switch circuit SW1a of switching unit 2a and the switch circuit SW1b of switching unit 2b are connected in parallel between the input terminal RFC and the output terminal RF1.

[0020] The switch circuit SW2b electrically connects the input terminal RFC and the output terminal RF2 based on the inverted signal of the control signal input from the inverting output terminal (-) of buffer 3. One end of the current path of the switch circuit SW2b is connected to the input terminal RFC, and the other end is connected to the output terminal RF2. The switch circuit SW2a of switching unit 2a and the switch circuit SW2b of switching unit 2b are connected in parallel between the input terminal RFC and the output terminal RF2.

[0021] For example, when the control signal is at a "High" ("H") level, switch circuit SW1b is set to the ON state and switch circuit SW2b is set to the OFF state. Also, for example, when the control signal is at a "Low" ("L") level, switch circuit SW1b is set to the OFF state and switch circuit SW2b is set to the ON state.

[0022] Buffer 3 includes an input terminal, a forward output terminal (+), and an inverting output terminal (-). The input terminal of buffer 3 is connected to the input terminal CTRL. The forward output terminal (+) of buffer 3 is connected to switch circuits SW1a and SW1b. The inverting output terminal (-) of buffer 3 is connected to switch circuits SW2a and SW2b. Buffer 3 outputs a control signal from the forward output terminal (+) and an inverted signal of the control signal from the inverting output terminal (-).

[0023] 1.2 Circuit configuration of a switch circuit Next, with reference to Figure 2, an example of the circuit configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b will be described. Figure 2 is a circuit diagram showing an example of the switch circuits SW1a, SW1b, SW2a, and SW2b. In the following description, unless the source and drain of a transistor are specified, one of the sources or drains of a transistor will be referred to as "one end of the transistor," and the other of the sources or drains of a transistor will be referred to as "the other end of the transistor."

[0024] First, let's explain the switch circuit SW1a.

[0025] As shown in Figure 2, the switch circuit SW1a includes multiple n-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 11a, multiple resistors 12a, and multiple resistors 13a. Transistor 11a functions as a switching element. The number of transistors 11a, resistors 12a, and resistors 13a included in the switch circuit SW1a is the same.

[0026] Multiple transistors 11a are connected in series between the input terminal RFC and the output terminal RF1. The gates of transistors 11a are connected to one terminal of the resistor element 13a. The number and size of transistors 11a are determined, for example, based on the amplitude level of the high-frequency signal to be transmitted. Also, for example, the gate width Wga of transistor 11a is determined based on the insertion loss (IL) when transmitting the high-frequency signal.

[0027] The resistor 12a is connected in parallel with the transistor 11a. More specifically, one terminal of the resistor 12a is connected to one end of the transistor 11a, and the other terminal is connected to the other end of the transistor 11a. Hereafter, the resistance value of the resistor 12a will be denoted as Rds.

[0028] The resistor element 13a is positioned, for example, to suppress leakage of current (high-frequency signal) to the gate side of transistor 11a. One terminal of the resistor element 13a is connected to the gate of transistor 11a, and the other terminal is connected to the positive output terminal (+) of buffer 3. Hereafter, the resistance value of the resistor element 13a will be denoted as Rgga.

[0029] Next, the switch circuit SW1b will be described. The switch circuit SW1b includes multiple n-type MOSFETs 11b, multiple resistors 12b, and multiple resistors 13b. The number of transistors 11b, resistors 12b, and resistors 13b included in the switch circuit SW1b is the same. For example, the switch circuit SW1b includes the same number of transistors 11b as the switch circuit SW1a.

[0030] Multiple transistors 11b are connected in series between the input terminal RFC and the output terminal RF1. The gates of transistors 11b are connected to one terminal of the resistor element 13b. Hereafter, the gate width of transistor 11b will be denoted as Wgb.

[0031] The resistor 12b is connected in parallel with the transistor 11b. More specifically, one terminal of the resistor 12b is connected to one end of the transistor 11b, and the other terminal is connected to the other end of the transistor 11b. The resistance value of the resistor 12b is the same as that of the resistor 12a, Rds.

[0032] One terminal of resistor element 13b is connected to the gate of transistor 11b, and the other terminal is connected to the positive output terminal (+) of buffer 3. Hereafter, the resistance value of resistor element 13b will be denoted as Rggb.

[0033] Next, the switch circuit SW2a will be described. The switch circuit SW2a includes multiple n-type MOSFETs 21a, multiple resistors 22a, and multiple resistors 23a. The number of transistors 21a, resistors 22a, and resistors 23a included in the switch circuit SW2a is the same. For example, the switch circuit SW2a includes the same number of transistors 21a as the transistors 11a in the switch circuit SW1a.

[0034] Multiple transistors 21a are connected in series between the input terminal RFC and the output terminal RF2. The gates of transistors 21a are connected to one terminal of the resistor element 23a. The gate width of transistors 21a is the same as that of transistor 11a, Wga.

[0035] The resistor 22a is connected in parallel with the transistor 21a. More specifically, one terminal of the resistor 22a is connected to one end of the transistor 21a, and the other terminal is connected to the other end of the transistor 21a. The resistance value of the resistor 22a is the same as that of the resistor 12a, Rds.

[0036] One terminal of resistor 23a is connected to the gate of transistor 21a, and the other terminal is connected to the inverting output terminal (-) of buffer 3. The resistance value of resistor 23a is the same as that of resistor 13a, Rgga.

[0037] Next, the switch circuit SW2b will be described. The switch circuit SW2b includes a plurality of n-type MOSFETs 21b, a plurality of resistor elements 22b, and a plurality of resistor elements 23b. The number of transistors 21b, resistor elements 22b, and resistor elements 23b included in the switch circuit SW2b is the same. For example, the switch circuit SW2b includes the same number of transistors 21b as the transistors 11a of the switch circuit SW1a.

[0038] The plurality of transistors 21b are connected in series between the input terminal RFC and the output terminal RF1. The gate of the transistor 21b is connected to one terminal of the resistor element 23b. The gate width of the transistor 21b is the same gate width Wgb as that of the transistor 11b.

[0039] The resistor element 22b is connected in parallel with the transistor 21b. More specifically, one terminal of the resistor element 22b is connected to one end of the transistor 21b, and the other terminal is connected to the other end of the transistor 21b. The resistance value of the resistor element 22b is the same resistance value Rds as that of the resistor element 12a.

[0040] One terminal of the resistor element 23b is connected to the gate of the transistor 21b, and the other terminal is connected to the inverting output terminal (-) of the buffer 3. Hereinafter, the resistance value of the resistor element 23b is the same resistance value Rggb as that of the resistor element 13b.

[0041] In this embodiment, for example, the gate widths Wga and Wgb and the resistance values Rgga and Rggb are in the relationship of Wga = Wgb and Rgga < Rggb, or the relationship of Wga < Wgb and Rgga = Rggb. Note that the gate widths Wga and Wgb and the resistance values Rgga and Rggb may also be in the relationship of Wga < Wgb and Rgga < Rggb.

[0042] Hereinafter, when not limiting any of the switch circuits SW1a, SW1b, SW2a, and SW2b, it is denoted as the switch circuit SW.

[0043] 1.3 Operating Characteristics of Switch Circuit Next, the operating characteristics of the switch circuit SW will be explained with reference to Figure 3. Figure 3 is a graph showing the switching operation of switch circuits SW1a, SW1b, SW2a, and SW2b. The vertical axis of the graph represents the gate voltage Vg (control signal voltage). The horizontal axis of the graph represents time. In Figure 3, the solid lines represent transistor 11a of switch circuit SW1a and transistor 21a of switch circuit SW2a. The dashed lines represent transistor 11b of switch circuit SW1b and transistor 21b of switch circuit SW2b.

[0044] In the switching operation of a switch circuit SW, when switching a transistor from the off state to the on state, or from the on state to the off state, the switching time is proportional to the CR time constant, which is determined by the gate capacitance and gate resistance of the transistor. For example, the gate capacitance is proportional to the gate width of the transistor. Also, the gate resistance increases as the resistance value of the resistive element connected to the gate of the transistor increases.

[0045] Below, Ton is defined as the rise time from when the gate voltage Vg of a transistor becomes above the threshold voltage, until the transistor (switch circuit SW) switches from the off state to the on state. Toff is defined as the fall time from when the gate voltage Vg of a transistor becomes below the threshold voltage, until the transistor (switch circuit SW) switches from the on state to the off state.

[0046] As shown in Figure 3, the CR time constants in switch circuits SW1b and SW2b are greater than those in switch circuits SW1a and SW2a. In this case, the rise time Ton and fall time Toff of switch circuits SW1b and SW2b are longer than those of switch circuits SW1a and SW2a.

[0047] More specifically, the gate widths Wga of transistors 11a and 21a, the gate widths Wgb of transistors 11b and 21b, the resistance values Rgga of resistor elements 13a and 23a, and the resistance values Rggb of resistor elements 13b and 23b are in a relationship where Wga = Wgb and Rgga < Rggb, or a relationship where Wga < Wgb and Rgga = Rggb. Therefore, the CR time constants in switch circuits SW1b and SW2b are larger than the CR time constants in switch circuits SW1a and SW2a.

[0048] Therefore, the switching operations (switching speeds) of switch circuits SW1b and SW2b are slower than the switching operations (switching speeds) of switch circuits SW1a and SW2a. That is, switch circuits SW1b and SW2b are delayed with respect to switch circuits SW1a and SW2a. In other words, the switching operation (switching speed) of switching unit 2b is delayed with respect to the switching operation (switching speed) of switching unit 2a.

[0049] Note that the rise time Ton and the fall time Toff vary due to manufacturing variations or fluctuations in the threshold voltage due to operating temperature or the like. Therefore, for example, even if the rise operation of switch circuit SW1a (transistor 11a) of switching unit 2a and the fall operation of switch circuit SW2a (transistor 21a) are started simultaneously, a deviation may occur in the timing when each operation is completed. The same applies to switching unit 2b.

[0050] 1.4 Specific Example of Switching Operation Next, referring to FIGS. 4 to 6, a specific example of the switching sequence when switching the connection of the input terminal RFC from the output terminal RF1 to the output terminal RF2 will be described. FIG. 4 shows the switching sequence when the rising time Ton and the falling time Toff in the switching operation are the same. That is, it shows the case where the on-operation and the off-operation of the transistor in the switching unit 2 are completed at the same timing. FIG. 5 shows the switching sequence when the length of the rising time Ton is shorter than the length of the falling time Toff in the switching operation. That is, it shows the case where the on-operation of the transistor in the switching unit 2 is completed earlier than the off-operation of the transistor. FIG. 6 shows the switching sequence when the length of the rising time Ton is longer than the length of the falling time Toff in the switching operation. That is, it shows the case where the off-operation of the transistor in the switching unit 2 is completed earlier than the on-operation of the transistor. In the examples of FIGS. 4 to 6, the on-resistance Ron of each of the switch circuits SW1a, SW1b, SW2a, and SW2b is 10 Ω. The characteristic impedance in the state where the input terminal RFC and either the output terminal RF1 or RF2 are connected is 50 Ω. Also, for example, the resistance value Rgga and the resistance value Rggb are in the relationship of Rgga < Rggb, and the gate width Wga and the gate width Wgb are in the relationship of Wga = Wgb.

[0051] First, the case where the on-operation and the off-operation of the transistor in the switching unit 2 are completed at the same timing will be described.

[0052] As shown in FIG. 4, in step 0, the input terminal RFC is connected to the output terminal RF1. Therefore, the switch circuits SW1a and SW1b are in the on-state, and the switch circuits SW2a and SW2b are in the off-state. For example, the port impedance (hereinafter referred to as "RFC impedance") at the input terminal RFC at this time is 55 Ω.

[0053] Step 1 is the step to bring the input terminal RFC into a state where it is connected to both output terminals RF1 and RF2 (hereinafter also referred to as the "simultaneous ON state"). In Step 1, the switching operation in the switching unit 2a is completed. More specifically, switch circuit SW1a is turned from the ON state to the OFF state. Then, switch circuit SW2a is turned from the OFF state to the ON state. As a result, switch circuits SW1b and SW2a are turned ON. This connects the input terminal RFC to output terminals RF1 and RF2. The RFC impedance is reduced to 30Ω.

[0054] In step 2, the switching operation in switching unit 2b is completed. More specifically, switch circuit SW1b is switched from the ON state to the OFF state. Then, switch circuit SW2b is switched from the OFF state to the ON state. As a result, switch circuits SW2a and SW2b are turned ON. This connects the input terminal RFC to the output terminal RF2. The RFC impedance is 55Ω.

[0055] Next, we will explain the case where the ON operation of the transistor in switching unit 2 is completed faster than the OFF operation of the transistor.

[0056] As shown in Figure 5, in switching units 2a and 2b, the timing of the transistor transitioning to the ON state and the timing of the transistor transitioning to the OFF state are different. Therefore, intermediate steps occur between step 0 and step 1, and between step 1 and step 2. Hereinafter, the step between step 0 and step 1 will be referred to as step 0.5, and the step between step 1 and step 2 will be referred to as step 1.5.

[0057] The state in Step 0 is the same as in Figure 4.

[0058] Next, in step 0.5, the transition of transistor 21a in switching unit 2a to the ON state is completed. More specifically, switch circuit SW1a remains in the ON state. Switch circuit SW2a is switched from the OFF state to the ON state. As a result, switch circuits SW1a, SW1b, and SW2a are all in the ON state. This connects the input terminal RFC to the output terminals RF1 and RF2. The RFC impedance is reduced to 29Ω.

[0059] In step 1, the transition of transistor 11a in switching unit 2a to the off state is completed. The states of each switch circuit SW1a, SW1b, SW2a, and SW2b are the same as in Figure 4.

[0060] Next, in step 1.5, the transition of transistor 21b in switching unit 2b to the ON state is completed. More specifically, switch circuit SW1b remains in the ON state. Switch circuit SW2b is switched from the OFF state to the ON state. As a result, switch circuits SW1b, SW2a, and SW2b are all in the ON state. This connects the input terminal RFC to the output terminals RF1 and RF2. The RFC impedance is reduced to 29Ω.

[0061] In step 2, the transition of transistor 11b in switching unit 2b to the off state is completed. The states of each switch circuit SW1a, SW1b, SW2a, and SW2b are the same as in Figure 4.

[0062] Next, we will explain the case where the off operation of the transistor in switching unit 2 is completed faster than the on operation of the transistor.

[0063] As shown in Figure 6, in switching units 2a and 2b, the timing of the transistor transitioning to the ON state and the timing of the transistor transitioning to the OFF state are different. Therefore, intermediate steps occur between step 0 and step 1, and between step 1 and step 2.

[0064] The state in Step 0 is the same as in Figure 4.

[0065] Next, in step 0.5, the transition of transistor 11a in switching unit 2a to the off state is completed. More specifically, switch circuit SW1a is switched from the on state to the off state. Switch circuit SW2a remains in the off state. As a result, switch circuit SW1b is turned on. This connects input terminal RFC to output terminal RF1. The RFC impedance increases to 60Ω.

[0066] In step 1, the transition of transistor 21a in switching unit 2a to the ON state is completed. The states of each switch circuit SW1a, SW1b, SW2a, and SW2b are the same as in Figure 4.

[0067] Next, in step 1.5, the transition of transistor 11b in switching unit 2b to the off state is completed. More specifically, switch circuit SW1b is switched from the on state to the off state. Switch circuit SW2b remains in the off state. As a result, switch circuit SW2a is turned on. This connects input terminal RFC to output terminal RF2. The RFC impedance increases to 60Ω.

[0068] In step 2, the transition of transistor 21b in switching unit 2b to the ON state is completed. The states of each switch circuit SW1a, SW1b, SW2a, and SW2b are the same as in Figure 4.

[0069] 1.5 Effects of this embodiment With the configuration according to this embodiment, it is possible to provide a high-frequency semiconductor integrated circuit that can suppress impedance fluctuations associated with switching control and improve switching speed. This effect will be explained with reference to Figure 7.

[0070] Figure 7 shows an example of the relationship between the number of parallel SPDT switches and the switching operation order. Figure 7(a) shows a comparative example where the number of parallel SPDT switches is 1 (one stage of SPDT switches). Figure 7(b) shows a case where the number of parallel SPDT switches is 2 (two stages of SPDT switches) as described in this embodiment. The configuration in Figure 7(b) is the same as in the first embodiment. Note that the example in Figure 7 shows the case where the connection of the input terminal RFC is switched from the output terminal RF1 to the output terminal RF2. In Figure 7(a), the on-resistance Ron of switch circuits SW1 and SW2 is set to 5Ω. In Figure 7(b), the on-resistance Ron of switch circuits SW1a, SW1b, SW2a, and SW2b is set to 10Ω. Also, for the sake of simplicity, the example in Figure 7 shows the case where the rise time Ton and fall time Toff of the transistor are the same length.

[0071] In high-frequency switch circuits such as SPDT switches, it is sometimes necessary to suppress impedance fluctuations during switching operations, depending on the application, such as when switching output terminals while the power input state remains active (also called a hot switch), or when it is desirable to suppress oscillation of the element preceding the input terminal. If the switching operation of the connection between the input terminal and each output terminal is not controlled, a state may occur where the input terminal is not connected to any output terminal (hereinafter referred to as the "simultaneous off state"). In the simultaneous off state, the impedance becomes very large (open state). Therefore, the switching order of the connection between the input terminal and each output terminal is controlled.

[0072] For example, in an SPDT switch, to avoid a simultaneous off state, the connection is switched after passing through a state where both output terminals are connected to the input terminals (simultaneous on state), as shown in step 1 of Figure 7(a) (step 2 of Figure 7(a)). For example, the RFC impedance in the simultaneous on state is half (e.g., 27.5Ω) of the state where the input terminal is connected to one of the output terminals (e.g., 55Ω). In this way, to control the system so that a simultaneous off state does not occur, a time difference is provided between the rise and fall times of the switching element (transistor). More specifically, the timing of the transistor's rise time is controlled to be earlier than the timing of its fall time. This makes the control of the switching operation complex. Furthermore, a delay circuit is required to delay the fall time. In this case, it is necessary to set a delay time with a margin that takes into account the variation in the length of the rise time and fall time due to fluctuations in the transistor's threshold voltage, which makes the time required for the switching operation relatively long.

[0073] In contrast, with the configuration according to this embodiment, as shown in Figure 7(b), the high-frequency semiconductor integrated circuit 1 can be provided with multiple switching units 2 in parallel, which switch the connections between the input terminals and each output terminal. Furthermore, the completion timing of the switching operation in each switching unit 2 can be set to be different. This prevents the occurrence of a simultaneous off state during the switching operation. More specifically, for example, the high-frequency semiconductor integrated circuit 1 includes switching units 2a and 2b. The timing of the completion of the switching operation of the switch circuits SW1b and SW2b of switching unit 2b is later than the timing of the completion of the switching operation of the switch circuits SW1a and SW2a of switching unit 2a. In the switching operation, the switching operation of switching unit 2a is completed first, resulting in a simultaneous on state (Step 1 in Figure 7(b)). After this, the switching operation of switching unit 2b is completed, and the switching operation is completed (Step 2 in Figure 7(b)). A delay in the timing of the switching operation can be introduced between switching units 2a and 2b. Therefore, even when the rise time and fall time of the transistors differ, simultaneous off states can be prevented. In other words, it becomes unnecessary to set a delay time that takes into account fluctuations in the transistor threshold voltage. Thus, the switching speed can be improved.

[0074] Furthermore, in the configuration according to this embodiment, for example, as shown in Figure 7, when two SPDT switches are in parallel, the on-resistance Ron of each transistor in each switch circuit can be doubled compared to when one SPDT switch is in parallel, in order to match the RFC impedance with when one SPDT switch is in parallel. As a result, the RFC impedance in the simultaneously on state can be higher than when one SPDT switch is in parallel. In other words, fluctuations in RFC impedance during switching operation can be suppressed.

[0075] Furthermore, in the configuration according to this embodiment, the gate widths Wga and Wgb can be reduced compared to the gate width Wg when the SPDT switches are in parallel, in order to double the on-resistance Ron. This reduces the gate capacitance (CR time constant) of the transistor. As a result, the switching speed (transition time) of the transistor can be reduced compared to when the SPDT switches are in parallel. Therefore, the switching speed of the high-frequency semiconductor integrated circuit 1 can be improved.

[0076] Furthermore, with the configuration according to this embodiment, the timing of the completion of the switching operation in each switching unit 2 can be delayed by optimizing the CR time constant in each switching unit 2. Therefore, a delay circuit can be omitted. Thus, an increase in the chip area of ​​the high-frequency semiconductor integrated circuit 1 can be suppressed.

[0077] 1.6 Modification of the First Embodiment Next, with reference to Figures 8 and 9, the relationship between the division ratio of gate width Wga and gate width Wgb and the RFC impedance will be explained. Figure 8 is a schematic diagram of a high-frequency semiconductor integrated circuit 1 showing the relationship between gate widths Wga and Wgb. Figure 9 is a graph showing the relationship between the division ratio of gate widths Wga and Wgb and the RFC impedance when switch circuits SW1a and SW2a are in the ON state.

[0078] As shown in Figure 8, for example, if the SPDT switch described in Figure 7(a) is in a single parallel configuration, the gate width Wg is set to "1", and the division ratio when the gate width Wg is divided into gate widths Wga and Wgb is X. In this case, the gate width Wga can be represented by WX, and the gate width Wgb can be represented by W(1-X). That is, the relationship is Wg = (WX + W(1-X)). Note that the relationship Wg = (WX + W(1-X)) is not necessarily true.

[0079] As shown in Figure 9, when the division ratio X is varied from 0.1 to 0.9, the RFC impedance when switch circuits SW1a and SW2a are in the ON state (simultaneously ON state) forms a graph symmetrical to the line around X=0.5. The RFC impedance at X=0.5 is 30Ω, which is the lowest compared to other division ratios X. As X decreases or increases, the RFC impedance tends to increase from 30Ω. The dashed line in Figure 9 shows the RFC impedance (27.5Ω) when one SPDT switch is in parallel. When two SPDT switches are in parallel, the RFC impedance is 30Ω or higher under all conditions, which is higher than the RFC impedance (27.5Ω) when one SPDT switch is in parallel. In other words, by arranging the SPDT switches in parallel, the RFC impedance when they are simultaneously ON becomes higher than when one SPDT switch is in parallel. That is, the impedance fluctuation due to switching operation is reduced.

[0080] 1.7 Effects of Modified Examples of the First Embodiment In a modified configuration of this embodiment, the RFC impedance when switch circuits SW1a and SW2a are in the ON state (simultaneously ON state) can be controlled by controlling the division ratio X of gate widths Wga and Wgb. This suppresses fluctuations in the RFC impedance when both are in the ON state.

[0081] 2. Second Embodiment Next, a second embodiment will be described. In the second embodiment, a configuration of the high-frequency semiconductor integrated circuit 1 that differs from that of the first embodiment will be described. The following description will focus on the differences from the first embodiment.

[0082] 2.1 Configuration First, an example of the overall configuration of the high-frequency semiconductor integrated circuit 1 will be described with reference to Figure 10. Figure 10 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit 1.

[0083] As shown in Figure 10, the high-frequency semiconductor integrated circuit 1 includes switching units 2a and 2b, a buffer 3, and resistor elements 4_1 and 4_2.

[0084] In this embodiment, a resistor 4 is provided between the buffer 3 and the switching unit 2b to cause a delay in the switching operation of the switching unit 2b relative to the switching unit 2a. More specifically, the positive output terminal (+) of the buffer 3 is connected to the switch circuit SW1b via resistor 4_1. The negative output terminal (-) of the buffer 3 is connected to the switch circuit SW2b via resistor 4_2. For example, resistors 4_1 and 4_2 have the same resistance value Rcn. Due to resistors 4_1 and 4_2, the switching unit 2b experiences a delay in its switching operation relative to the switching unit 2a.

[0085] The rest of the configuration is the same.

[0086] 2.2 Circuit configuration of a switch circuit Next, with reference to Figure 11, an example of the circuit configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b will be described. Figure 11 is a circuit diagram showing an example of the switch circuits SW1a, SW1b, SW2a, and SW2b.

[0087] As shown in Figure 11, the configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b is the same as in Figure 2 of the first embodiment.

[0088] One terminal of each of the multiple resistor elements 13b in the switch circuit SW1b is connected to the gates of each of the multiple transistors 11b. The other terminals of the multiple resistor elements 13b are commonly connected to one terminal of resistor element 4_1. The other terminal of resistor element 4_1 is connected to the positive output terminal (+) of buffer 3.

[0089] One terminal of each of the multiple resistor elements 23b in the switch circuit SW2b is connected to the gates of each of the multiple transistors 21b. The other terminals of the multiple resistor elements 23b are connected in common to one terminal of resistor element 4_2. The other terminal of resistor element 4_2 is connected to the inverting output terminal (-) of buffer 3.

[0090] In this embodiment, the resistors 4_1 and 4_2 cause a delay in the switching operation of the switch circuits SW1b and SW2b relative to the switch circuits SW1a and SW2a. For this reason, for example, the transistors 11a, 11b, 21a, and 21b and the resistors 13a, 13b, 23a, and 23b may have the relationship Wga=Wgb and Rgga=Rggb.

[0091] 2.3 Effects according to this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained.

[0092] 3. Third Embodiment Next, a third embodiment will be described. In the third embodiment, a configuration of the high-frequency semiconductor integrated circuit 1 that differs from the first and second embodiments will be described. The following description will focus on the differences from the first and second embodiments.

[0093] 3.1 Configuration First, an example of the overall configuration of the high-frequency semiconductor integrated circuit 1 will be described with reference to Figure 12. Figure 12 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit 1.

[0094] As shown in Figure 12, the high-frequency semiconductor integrated circuit 1 includes switching units 2a and 2b, buffers 3a and 3b, and a delay circuit 5.

[0095] Switching units 2a and 2b are the same as those shown in Figure 1 of the first embodiment.

[0096] Buffer 3a includes an input terminal, a forward output terminal (+), and an inverting output terminal (-). The input terminal of buffer 3a is connected to the input terminal CTRL. The forward output terminal (+) of buffer 3a is connected to switch circuit SW1a. The inverting output terminal (-) of buffer 3a is connected to switch circuit SW2a. Buffer 3a outputs a control signal from the forward output terminal (+) and an inverted signal of the control signal from the inverting output terminal (-).

[0097] Buffer 3b includes an input terminal, a forward output terminal (+), and an inverting output terminal (-). The input terminal of buffer 3b is connected to the output terminal of delay circuit 5. The forward output terminal (+) of buffer 3b is connected to switch circuit SW1b. The inverting output terminal (-) of buffer 3b is connected to switch circuit SW2b. Buffer 3b outputs a control signal from the forward output terminal (+) and an inverted signal of the control signal from the inverting output terminal (-).

[0098] The delay circuit 5 delays the control signal and sends it to the buffer 3b. The input terminal of the delay circuit 5 is connected to the input terminal CTRL. The output terminal of the delay circuit 5 is connected to the input terminal of the buffer 3b.

[0099] In this embodiment, the delay circuit 5 causes a delay in the switching operation of the switching unit 2b relative to the switching unit 2a.

[0100] 3.2 Circuit configuration of a switch circuit Next, with reference to Figure 13, an example of the circuit configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b will be described. Figure 13 is a circuit diagram showing an example of the switch circuits SW1a, SW1b, SW2a, and SW2b.

[0101] As shown in Figure 13, the configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b is the same as in Figure 2 of the first embodiment.

[0102] One terminal of each of the multiple resistor elements 13a in the switch circuit SW1a is connected to the gates of the multiple transistors 11a. The other terminals of the multiple resistor elements 13a are commonly connected to the positive (+) output terminal of the buffer 3a.

[0103] One terminal of each of the multiple resistor elements 13b in the switch circuit SW1b is connected to the gates of the multiple transistors 11b. The other terminals of the multiple resistor elements 13b are commonly connected to the positive output terminal (+) of the buffer 3b.

[0104] One terminal of each of the multiple resistor elements 23a in the switch circuit SW2a is connected to the gates of the multiple transistors 21a. The other terminals of the multiple resistor elements 23a are commonly connected to the inverting output terminal (-) of the buffer 3a.

[0105] One terminal of each of the multiple resistor elements 23b in the switch circuit SW2b is connected to the gates of the multiple transistors 21b. The other terminal of each of the multiple resistor elements 23b is connected to the inverting output terminal (-) of the buffer 3b.

[0106] In this embodiment, the delay circuit 5 causes a delay in the switching operation of switch circuits SW1b and SW2b relative to switch circuits SW1a and SW2a. For this reason, for example, transistors 11a, 11b, 21a, and 21b and resistor elements 13a, 13b, 23a, and 23b may have the relationship Wga=Wgb and Rgga=Rggb.

[0107] 3.3 Circuit configuration of the delay circuit Next, an example of the circuit configuration of the delay circuit 5 will be described with reference to Figure 14. Figure 14 is a circuit diagram of the delay circuit 5.

[0108] As shown in Figure 14, the delay circuit includes, for example, inverters 51 and 52, a resistor 53, and a capacitive element 54.

[0109] The input terminal of inverter 51 is connected to input terminal CTRL. The output terminal of inverter 51 is connected to one terminal of resistive element 53 and one electrode of capacitive element 54.

[0110] The input terminal of inverter 52 is connected to the other terminal of resistor element 53. The output terminal of inverter 52 is connected to the input terminal of buffer 3b.

[0111] The other electrode of the capacitive element 54 is grounded (connected to the ground voltage wiring).

[0112] The control signal is delayed by the CR time constant of the resistor 53 and capacitor 54 pair. The resistance value of the resistor 53 and the capacitance value of the capacitor 54 are arbitrarily set based on the set delay time. Multiple pairs of resistor 53 and capacitor 54 may be connected in series, or multiple delay circuits 5 may be provided in series, based on the set delay time.

[0113] 3.4 Effects of this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained.

[0114] 4. Fourth Embodiment Next, a fourth embodiment will be described. In the fourth embodiment, the configuration of the high-frequency semiconductor integrated circuit 1, which differs from that of the first to third embodiments, will be described. The following description will focus on the differences from the first to third embodiments.

[0115] 4.1 Configuration Referring to Figure 15, an example of the overall configuration of the high-frequency semiconductor integrated circuit 1 will be described. Figure 15 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit 1.

[0116] As shown in Figure 15, the high-frequency semiconductor integrated circuit 1 includes switching units 2a and 2b, a buffer 3, and delay circuits 5_1 and 5_2.

[0117] Switching units 2a and 2b are the same as those shown in Figure 1 of the first embodiment.

[0118] Buffer 3 includes an input terminal, a forward output terminal (+), and an inverting output terminal (-). The input terminal of buffer 3 is connected to the input terminal CTRL. In this embodiment, the forward output terminal (+) of buffer 3 is connected to the input terminals of switch circuit SW1a and delay circuit 5_1. The inverting output terminal (-) of buffer 3 is connected to the input terminals of switch circuit SW2a and delay circuit 5_2.

[0119] The delay circuit 5_1 delays the control signal received from buffer 3 and transmits it to switch circuit SW1b. The output terminal of the delay circuit 5_1 is connected to switch circuit SW1b.

[0120] The delay circuit 5_2 delays the inverted signal of the control signal received from buffer 3 and transmits it to the switch circuit SW2b. The output terminal of the delay circuit 5_2 is connected to the switch circuit SW2b.

[0121] The configurations of delay circuits 5_1 and 5_2 may be the same as those of the delay circuits 5_1 and 5_2. Furthermore, the configurations of delay circuits 5_1 and 5_2 may be the same as those shown in Figure 14 of the third embodiment.

[0122] In this embodiment, switch circuit SW1b experiences a delay in switching operation relative to switch circuit SW1a due to delay circuit 5_1. Similarly, switch circuit SW2b experiences a delay in switching operation relative to switch circuit SW2a due to delay circuit 5_2.

[0123] 4.2 Effects of this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained.

[0124] 5. Fifth Embodiment Next, a fifth embodiment will be described. In the fifth embodiment, a case will be described in which three switching units 2 are provided in three parallel configurations.

[0125] 5.1 Configuration First, an example of the overall configuration of the high-frequency semiconductor integrated circuit 1 will be described with reference to Figure 16. Figure 16 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit 1.

[0126] As shown in Figure 16, the high-frequency semiconductor integrated circuit 1 includes switching units 2a, 2b, and 2c, and a buffer 3.

[0127] Switching units 2a, 2b, and 2c can each function as a single SPDT switch. Switching units 2a, 2b, and 2c are connected in parallel. That is, the high-frequency semiconductor integrated circuit 1 includes three parallel SPDT switches. In other words, the SPDT switches are divided into three stages. For example, the switching time of the switch in switching unit 2a is shorter than the switching time of the switch in switching unit 2b. The switching time of the switch in switching unit 2b is shorter than the switching time of the switch in switching unit 2c. Therefore, for example, when switching the connection destination of the input terminal RFC, the switching operation in switching unit 2b is completed after the switching operation in switching unit 2a is completed. Then, after the switching operation in switching unit 2b is completed, the switching operation in switching unit 2c is completed. That is, the switching operation is performed in three stages. Hereafter, unless we specify which of switching units 2a, 2b, and 2c is being referred to, it will be written as "switching unit 2".

[0128] The configuration of switching units 2a and 2b is the same as in Figure 1 of the first embodiment.

[0129] The switching unit 2c includes two switch circuits SW1c and SW2c. Based on a control signal, one of the switch circuits SW1c and SW2c is turned ON and the other is turned OFF.

[0130] The switch circuit SW1c electrically connects the input terminal RFC and the output terminal RF1 based on the control signal input from the forward output terminal (+) of buffer 3. One end of the switch circuit SW1c is connected to the input terminal RFC, and the other end is connected to the output terminal RF1.

[0131] The switch circuit SW2c electrically connects the input terminal RFC and the output terminal RF2 based on the inverted signal of the control signal input from the inverting output terminal (-) of buffer 3. One end of the switch circuit SW2c is connected to the input terminal RFC, and the other end is connected to the output terminal RF2.

[0132] For example, when the control signal is at the "H" level, switch circuit SW1c is set to the ON state and switch circuit SW2c is set to the OFF state. Also, for example, when the control signal is at the "L" level, switch circuit SW1c is set to the OFF state and switch circuit SW2c is set to the ON state.

[0133] The positive (+) output terminal of buffer 3 is connected to switch circuits SW1a, SW1b, and SW1c. The negative (-) output terminal of buffer 3 is connected to switch circuits SW2a, SW2b, and SW2c.

[0134] 5.2 Circuit configuration of a switch circuit Next, with reference to Figure 17, an example of the circuit configuration of the switch circuits SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c will be described. Figure 17 is a circuit diagram showing an example of the switch circuits SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c. Note that the circuit configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b is the same as in Figure 2 of the first embodiment. For this reason, in the example in Figure 17, the circuit configuration of the switch circuits SW1a, SW1b, SW2a, and SW2b is omitted to simplify the explanation.

[0135] First, let's explain the switch circuit SW1c.

[0136] As shown in Figure 17, the switch circuit SW1c includes multiple n-type MOSFETs 11c, multiple resistors 12c, and multiple resistors 13c. The number of transistors 11c, resistors 12c, and resistors 13c included in the switch circuit SW1c is the same. For example, the switch circuit SW1c includes the same number of transistors 11c as the switch circuit SW1a.

[0137] Multiple transistors 11c are connected in series between the input terminal RFC and the output terminal RF1. The gates of transistors 11c are connected to one terminal of the resistor element 13c. Hereafter, the gate width of transistor 11c will be denoted as Wgc.

[0138] The resistor element 12c is connected in parallel with the transistor 11c. More specifically, one terminal of the resistor element 12c is connected to one end of the transistor 11c, and the other terminal is connected to the other end of the transistor 11c. The resistance value of the resistor element 12c is the same as that of the resistor element 12a, Rds.

[0139] One terminal of resistor element 13c is connected to the gate of transistor 11c, and the other terminal is connected to the positive output terminal (+) of buffer 3. Hereafter, the resistance value of resistor element 13c will be denoted as Rggc.

[0140] Next, the switch circuit SW2c will be described. The switch circuit SW2c includes multiple n-type MOSFETs 21c, multiple resistors 22c, and multiple resistors 23c. The number of transistors 21c, resistors 22c, and resistors 23c included in the switch circuit SW2c is the same. For example, the switch circuit SW2c includes the same number of transistors 21c as the transistors 11a in the switch circuit SW1a.

[0141] Multiple transistors 21c are connected in series between the input terminal RFC and the output terminal RF1. The gates of transistors 21c are connected to one terminal of the resistor element 23c. The gate width of transistor 21c is the same as that of transistor 11c, Wgc.

[0142] The resistor element 22c is connected in parallel with the transistor 21c. More specifically, one terminal of the resistor element 22c is connected to one end of the transistor 21c, and the other terminal is connected to the other end of the transistor 21c. The resistance value of the resistor element 22c is the same resistance value Rds as that of the resistor element 12a.

[0143] One terminal of the resistor element 23c is connected to the gate of the transistor 21c, and the other terminal is connected to the inverted output terminal (-) of the buffer 3. Hereinafter, the resistance value of the resistor element 23c is the same resistance value Rggc as that of the resistor element 13c.

[0144] In the present embodiment, for example, the gate widths Wga, Wgb, and Wgc and the resistance values Rgga, Rggb, and Rggc are in the relationship of Wga = Wgb = Wgc and Rgga < Rggb < Rggc, or in the relationship of Wga < Wgb < Wgc and Rgga = Rggb = Rggc. Note that the gate widths Wga, Wgb, and Wgc and the resistance values Rgga, Rggb, and Rggc may be in the relationship of Wga < Wgb < Wgc and Rgga < Rggb < Rggc. The CR time constant only needs to be in the relationship of (the CR time constant of the switch circuit SW1a (transistor 11a) and the switch circuit SW2a (transistor 21a)) < (the CR time constant of the switch circuit SW1b (transistor 11b) and the switch circuit SW2b (transistor 21b)) < (the CR time constant of the switch circuit SW1c (transistor 11c) and the switch circuit SW2c (transistor 21c)).

[0145] Hereinafter, when not limiting any of the switch circuits SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c, it is denoted as the switch circuit SW.

[0146] 5.3 Specific Example of Switching Operation Next, referring to FIGS. 18 to 20, a specific example of the switching sequence when switching the connection of the input terminal RFC from the output terminal RF1 to the output terminal RF2 will be described. FIG. 18 shows the switching sequence when the rise time Ton and the fall time Toff are the same in the switching operation. That is, it shows the case where the on operation and the off operation of the transistors in the switching unit 2 are completed at the same timing. FIG. 19 shows the switching sequence when the rise time Ton is shorter than the fall time Toff in the switching operation. That is, it shows the case where the on operation of the transistors in the switching unit 2 is completed earlier than the off operation of the transistors. FIG. 20 shows the switching sequence when the rise time Ton is longer than the fall time Toff in the switching operation. That is, it shows the case where the off operation of the transistors in the switching unit 2 is completed earlier than the on operation of the transistors. In the examples of FIGS. 18 to 20, the on-resistance Ron of each of the switch circuits SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c is 15Ω. The characteristic impedance in the state where the input terminal RFC and either the output terminal RF1 or RF2 are connected is 50Ω. Also, for example, the gate widths Wga, Wgb, and Wgc and the resistance values Rgga, Rggb, and Rggc are in the relationship of Wga < Wgb < Wgc and Rgga = Rggb = Rggc.

[0147] First, the case where the on operation and the off operation of the transistors in the switching unit 2 are completed at the same timing will be described.

[0148] As shown in FIG. 18, in step 0, the input terminal RFC is connected to the output terminal RF1. Therefore, the switch circuits SW1a, SW1b, and SW1c are in the on state, and the switch circuits SW2a, SW2b, and SW2c are in the off state. For example, the RFC impedance is 55Ω.

[0149] First, in step 1, the switching operation in switching unit 2a is completed. More specifically, switch circuit SW1a is switched from the ON state to the OFF state. Then, switch circuit SW2a is switched from the OFF state to the ON state. As a result, switch circuits SW1b, SW1c, and SW2a are turned ON. This connects the input terminal RFC to the output terminals RF1 and RF2. The RFC impedance is reduced to 30.5Ω.

[0150] In step 2, the switching operation in switching unit 2b is completed. More specifically, switch circuit SW1b is switched from the ON state to the OFF state. Then, switch circuit SW2b is switched from the OFF state to the ON state. As a result, switch circuits SW1c, SW2a, and SW2b are turned ON. This connects the input terminal RFC to the output terminals RF1 and RF2. The RFC impedance is 30.5Ω.

[0151] In step 3, the switching operation in switching unit 2c is completed. More specifically, switch circuit SW1c is switched from the ON state to the OFF state. Then, switch circuit SW2c is switched from the OFF state to the ON state. As a result, switch circuits SW2a, SW2b, and SW2c are turned ON. This connects the input terminal RFC to the output terminal RF2. The RFC impedance is 55Ω.

[0152] When three switching units 2 (SPDT switches) are connected in parallel, the on-resistance Ron can be set to, for example, three times that of a single SPDT switch in parallel. Therefore, the gate widths Wga, Wgb, and Wgc can be reduced compared to the gate width Wg of a single SPDT switch in parallel. As a result, the gate capacitance (CR time constant) of the transistor can be reduced to approximately 1 / 3. Consequently, the switching speed (transition time) of the transistor can be reduced to approximately 1 / 3 compared to a single SPDT switch in parallel.

[0153] Next, we will explain the case where the ON operation of the transistor in switching unit 2 is completed faster than the OFF operation of the transistor.

[0154] As shown in Figure 19, in switching units 2a, 2b, and 2c, the timing of the transistor transitioning to the ON state and the timing of the transistor transitioning to the OFF state are different. Therefore, intermediate steps occur between step 0 and step 1, between step 1 and step 2, and between step 2 and step 3. Hereinafter, the step between step 0 and step 1 will be referred to as step 0.5. The step between step 1 and step 2 will be referred to as step 1.5. The step between step 2 and step 3 will be referred to as step 2.5.

[0155] The state in Step 0 is the same as in Figure 18.

[0156] Next, in step 0.5, the transition of transistor 21a in switching unit 2a to the ON state is completed. More specifically, switch circuit SW1a remains in the ON state. Switch circuit SW2a is switched from the OFF state to the ON state. As a result, switch circuits SW1a, SW1b, SW1c, and SW2a are all in the ON state. This connects the input terminal RFC to the output terminals RF1 and RF2. The RFC impedance is reduced to 30Ω.

[0157] In step 1, the transition of transistor 11a in switching unit 2a to the off state is completed. The states of each switch circuit SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c are the same as in Figure 18.

[0158] Next, in step 1.5, the transition of transistor 21b in switching unit 2b to the ON state is completed. More specifically, switch circuit SW1b remains ON. Switch circuit SW2b is switched from the OFF state to the ON state. As a result, switch circuits SW1b, SW1c, SW2a, and SW2b are all ON. This connects the input terminal RFC to the output terminals RF1 and RF2. The RFC impedance is reduced to 29Ω.

[0159] In step 2, the transition of transistor 11b in switching unit 2b to the off state is completed. The states of each switch circuit SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c are the same as in Figure 18.

[0160] Next, in step 2.5, the transition of transistor 21c in switching unit 2c to the ON state is completed. More specifically, switch circuit SW1c remains in the ON state. Switch circuit SW2c is switched from the OFF state to the ON state. As a result, switch circuits SW1c, SW2a, SW2b, and SW2c are all in the ON state. This connects the input terminal RFC to the output terminals RF1 and RF2. The RFC impedance is 30Ω.

[0161] In step 3, the transition of transistor 11c in switching unit 2c to the off state is completed. The states of each switch circuit SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c are the same as in Figure 18.

[0162] Next, we will explain the case where the off operation of the transistor in switching unit 2 is completed faster than the on operation of the transistor.

[0163] As shown in Figure 20, in switching units 2a, 2b, and 2c, the timing of the transistor transitioning to the ON state and the timing of the transistor transitioning to the OFF state are different. Therefore, intermediate steps occur between step 0 and step 1, between step 1 and step 2, and between step 2 and step 3.

[0164] The state in Step 0 is the same as in Figure 18.

[0165] Next, in step 0.5, the transition of transistor 11a in switching unit 2a to the off state is completed. More specifically, switch circuit SW1a is switched from the on state to the off state. Switch circuit SW2a remains in the off state. As a result, switch circuits SW1b and SW1c are turned on. This connects the input terminal RFC to the output terminal RF1. The RFC impedance increases to 57.5Ω.

[0166] In step 1, the transition of transistor 21b in switching unit 2a to the ON state is completed. The states of each switch circuit SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c are the same as in Figure 18.

[0167] Next, in step 1.5, the transition of transistor 11b in switching unit 2b to the off state is completed. More specifically, switch circuit SW1b is switched from the on state to the off state. Switch circuit SW2b remains in the off state. As a result, switch circuits SW1c and SW2a are turned on. This connects the input terminal RFC to the output terminals RF1 and RF2. The RFC impedance is 32.5Ω.

[0168] In step 2, the transition of transistor 21b in switching unit 2b to the ON state is completed. The states of each switch circuit SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c are the same as in Figure 18.

[0169] Next, in step 2.5, the transition of transistor 11c in switching unit 2c to the off state is completed. More specifically, switch circuit SW1c is switched from the on state to the off state. Switch circuit SW2c remains in the off state. As a result, switch circuits SW2a and SW2b are turned on. This connects input terminal RFC to output terminal RF2. The RFC impedance increases to 57.5Ω.

[0170] In step 3, the transition of transistor 21c in switching unit 2c to the ON state is completed. The states of each switch circuit SW1a, SW1b, SW1c, SW2a, SW2b, and SW2c are the same as in Figure 18.

[0171] For example, comparing Figures 18 to 20 of a specific example of this embodiment with Figures 4 to 6 of a specific example of the first embodiment, it can be seen that as the number of switching units 2 (switch circuits SW) connected in parallel increases, fluctuations in RFC impedance during switching operations are suppressed and the transition time is shortened.

[0172] 5.4 Effects of this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained.

[0173] Furthermore, with the configuration according to this embodiment, the high-frequency semiconductor integrated circuit 1 can achieve further suppression of impedance fluctuations and improvement of switching speed by increasing the number of switching units 2 arranged in parallel.

[0174] 6. Sixth Embodiment Next, a sixth embodiment will be described. In the sixth embodiment, a configuration of the high-frequency semiconductor integrated circuit 1 that differs from that of the fifth embodiment will be described. The following description will focus on the differences from the fifth embodiment.

[0175] 6.1 Configuration Referring to Figure 21, an example of the overall configuration of the high-frequency semiconductor integrated circuit 1 will be described. Figure 21 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit 1.

[0176] As shown in Figure 21, the high-frequency semiconductor integrated circuit 1 includes switching units 2a, 2b, and 2c, a buffer 3, and delay circuits 6_1, 6_2, 7_1, and 7_2.

[0177] The switching units 2a, 2b, and 2c are the same as those shown in Figure 16 of the fifth embodiment.

[0178] Buffer 3 includes an input terminal, a forward output terminal (+), and an inverting output terminal (-). The input terminal of buffer 3 is connected to the input terminal CTRL. In this embodiment, the forward output terminal (+) of buffer 3 is connected to the input terminals of switch circuit SW1a and delay circuit 6_1. The inverting output terminal (-) of buffer 3 is connected to the input terminals of switch circuit SW2a and delay circuit 6_2.

[0179] The delay circuit 6_1 delays the control signal received from buffer 3 and transmits it to the input terminals of switch circuit SW1b and delay circuit 7_1. The output terminal of delay circuit 6_1 is connected to the input terminals of switch circuit SW1b and delay circuit 7_1.

[0180] The delay circuit 6_2 delays the inverted signal of the control signal received from buffer 3 and transmits it to the input terminals of switch circuit SW2b and delay circuit 7_2. The output terminal of delay circuit 6_2 is connected to the input terminals of switch circuit SW2b and delay circuit 7_2. The delay amount in delay circuit 6_2 is the same as that of delay circuit 6_1.

[0181] The delay circuit 7_1 further delays the delayed control signal received from the delay circuit 6_1 and transmits it to the switch circuit SW1c. In other words, the delay circuit 7_1 outputs the control signal that has been delayed by both the delay circuit 6_1 and the delay circuit 7_1. The output terminal of the delay circuit 7_1 is connected to the switch circuit SW1c.

[0182] The delay circuit 7_2 further delays the inverted signal of the delayed control signal received from the delay circuit 6_2 and transmits it to the switch circuit SW2c. That is, the delay circuit 7_2 outputs the inverted signal of the control signal delayed by the delay circuits 6_2 and 7_2. The output terminal of the delay circuit 7_2 is connected to the switch circuit SW2c. The amount of delay in the delay circuit 7_2 is the same as that of the delay circuit 7_1. The amount of delay in the delay circuits 7_1 and 7_2 may be the same as or different from that of the delay circuits 6_1 and 6_2. Also, the configuration of the delay circuits 6_1, 6_2, 7_1, and 7_2 may be the same as, for example, that shown in Figure 14 of the third embodiment. Furthermore, instead of the delay circuits 6_1, 6_2, 7_1, and 7_2, a resistor may be arranged as in the second embodiment.

[0183] In this embodiment, the delay circuit 6_1 causes a delay in the switching operation of switch circuit SW1b relative to switch circuit SW1a. Similarly, the delay circuit 7_1 causes a delay in the switching operation of switch circuit SW1c relative to switch circuit SW1b. Likewise, the delay circuit 6_2 causes a delay in the switching operation of switch circuit SW2b relative to switch circuit SW2a. And the delay circuit 7_2 causes a delay in the switching operation of switch circuit SW2c relative to switch circuit SW2b.

[0184] 6.2 Effects according to this embodiment With the configuration according to this embodiment, the same effects as those of the fifth embodiment can be obtained.

[0185] 7. Seventh Embodiment Next, a seventh embodiment will be described. In the seventh embodiment, the configuration of the high-frequency semiconductor integrated circuit 1, which differs from that of the fifth and sixth embodiments, will be described. The following description will focus on the differences from the fifth and sixth embodiments.

[0186] 7.1 Configuration Referring to Figure 22, an example of the overall configuration of the high-frequency semiconductor integrated circuit 1 will be described. Figure 22 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit 1.

[0187] As shown in Figure 22, the high-frequency semiconductor integrated circuit 1 includes switching units 2a, 2b, and 2c, buffers 3a, 3b, and 3c, and delay circuits 8 and 9.

[0188] The switching units 2a, 2b, and 2c are the same as those shown in Figure 16 of the fifth embodiment.

[0189] Buffer 3a includes an input terminal, a forward output terminal (+), and an inverting output terminal (-). The input terminal of buffer 3a is connected to the input terminal CTRL. In this embodiment, the forward output terminal (+) of buffer 3 is connected to the switch circuit SW1a. The inverting output terminal (-) of buffer 3a is connected to the switch circuit SW2a.

[0190] Buffer 3b includes an input terminal, a forward output terminal (+), and an inverting output terminal (-). The input terminal of buffer 3b is connected to the input terminal CTRL via a delay circuit 8. In this embodiment, the forward output terminal (+) of buffer 3 is connected to the switch circuit SW1b. The inverting output terminal (-) of buffer 3b is connected to the switch circuit SW2b.

[0191] Buffer 3c includes an input terminal, a forward output terminal (+), and an inverting output terminal (-). The input terminal of buffer 3c is connected to the input terminal CTRL via delay circuits 8 and 9. In this embodiment, the forward output terminal (+) of buffer 3 is connected to the switch circuit SW1c. The inverting output terminal (-) of buffer 3c is connected to the switch circuit SW2c.

[0192] The delay circuit 8 delays the control signal received from buffer 3 and transmits it to buffer 3b and the input terminals of delay circuit 9. The input terminal of delay circuit 8 is connected to the input terminal CTRL. The output terminal of delay circuit 8 is connected to the input terminal of buffer 3b and the input terminal of delay circuit 9.

[0193] The delay circuit 9 further delays the delayed control signal received from the delay circuit 8 and transmits it to the buffer 3c. That is, the delay circuit 9 outputs the control signal delayed by both the delay circuit 8 and the delay circuit 9. The output terminal of the delay circuit 9 is connected to the input terminal of the buffer 3c. The amount of delay in the delay circuit 8 may be the same as or different from the amount of delay in the delay circuit 9. Also, the configuration of the delay circuits 8 and 9 may be the same as, for example, that shown in Figure 14 of the third embodiment.

[0194] In this embodiment, the delay circuit 8 causes a delay in the switching operation of switch circuits SW1b and SW2b relative to switch circuits SW1a and SW2a. Furthermore, the delay circuit 9 causes a delay in the switching operation of switch circuits SW1c and SW2c relative to switch circuits SW1b and SW2b.

[0195] 7.2 Effects of this embodiment With the configuration according to this embodiment, the same effects as those of the fifth embodiment can be obtained.

[0196] 8. Eighth Embodiment Next, an eighth embodiment will be described. In the eighth embodiment, the case in which the high-frequency semiconductor integrated circuit 1 is an SP3T switch will be described. The SP3T switch is a high-frequency signal switching switch having one input terminal and three output terminals.

[0197] 8.1 Configuration Referring to Figure 23, an example of the overall configuration of the high-frequency semiconductor integrated circuit 1 will be described. Figure 23 is a block diagram showing an example of the overall configuration of the high-frequency semiconductor integrated circuit 1.

[0198] As shown in Figure 23, the high-frequency semiconductor integrated circuit 1 has a high-frequency signal input terminal RFC, a control signal input terminal CTRL, and three output terminals RF1, RF2, and RF3. Based on the control signal input from the input terminal CTRL, the high-frequency semiconductor integrated circuit 1 electrically connects the input terminal RFC to at least one of the output terminals RF1, RF2, and RF3.

[0199] The high-frequency semiconductor integrated circuit 1 includes two switching units 2a and 2b, a decoder 101, three delay circuits 111 to 113, and six buffers 121a, 121b, 122a, 122b, 123a, and 123b.

[0200] The switching unit 2a of this embodiment includes three switch circuits SW1a, SW2a, and SW3a.

[0201] The switch circuit SW1a electrically connects the input terminal RFC and the output terminal RF1 based on the control signal CS1 input from the forward output terminal (+) of the buffer 121a. One end of the switch circuit SW1a is connected to the input terminal RFC, and the other end is connected to the output terminal RF1.

[0202] The switch circuit SW2a electrically connects the input terminal RFC and the output terminal RF2 based on the control signal CS2 input from the forward output terminal (+) of the buffer 122a. One end of the switch circuit SW2a is connected to the input terminal RFC, and the other end is connected to the output terminal RF2.

[0203] The switch circuit SW3a electrically connects the input terminal RFC and the output terminal RF3 based on the control signal CS3 input from the forward output terminal (+) of buffer 123a. One end of the switch circuit SW3a is connected to the input terminal RFC, and the other end is connected to the output terminal RF3.

[0204] The switching unit 2b of this embodiment includes three switch circuits SW1b, SW2b, and SW3b.

[0205] The switch circuit SW1b electrically connects the input terminal RFC and the output terminal RF1 based on the control signal CS1 input from the forward output terminal (+) of the buffer 121b. One end of the switch circuit SW1b is connected to the input terminal RFC, and the other end is connected to the output terminal RF1.

[0206] The switch circuit SW2b electrically connects the input terminal RFC and the output terminal RF2 based on the control signal CS2 input from the forward output terminal (+) of buffer 122b. One end of the switch circuit SW2b is connected to the input terminal RFC, and the other end is connected to the output terminal RF2.

[0207] The switch circuit SW3b electrically connects the input terminal RFC and the output terminal RF3 based on the control signal CS3 input from the forward output terminal (+) of buffer 123b. One end of the switch circuit SW3b is connected to the input terminal RFC, and the other end is connected to the output terminal RF3.

[0208] Similar to the first embodiment, the timing of completion of the switching operation in switching unit 2a is earlier than the timing of completion of the switching operation in switching unit 2b. That is, the timing of completion of the switching operation in switch circuit SW1a is earlier than the timing of completion of the switching operation in switch circuit SW1b. The timing of completion of the switching operation in switch circuit SW2a is earlier than the timing of completion of the switching operation in switch circuit SW2b. The timing of completion of the switching operation in switch circuit SW3a is earlier than the timing of completion of the switching operation in switch circuit SW3b.

[0209] Decoder 101 decodes the signal received from the input terminal CTRL to generate control signals CS1, CS2, and CS3. Control signal CS1 is a signal that controls switch circuits SW1a and SW1b. Control signal CS2 is a signal that controls switch circuits SW2a and SW2b. Control signal CS3 is a signal that controls switch circuits SW3a and SW3b. For example, when decoder 101 turns on switch circuits SW1a and SW1b, it outputs a control signal CS1 at the "H" level. The same applies to control signals CS2 and CS3. Decoder 101 includes three output terminals T1, T2, and T3, which output control signals CS1, CS2, and CS3, respectively. Note that decoder 101 may be provided outside of the high-frequency semiconductor integrated circuit 1. In this case, the high-frequency semiconductor integrated circuit 1 has three signal input terminals to which control signals CS1 to CS3 are input.

[0210] The delay circuit 111 is a circuit that delays the control signal CS1. The input terminal of the delay circuit 111 is connected to the output terminal T1 of the decoder 101. The output terminal of the delay circuit 111 is connected to the input terminal of the buffer 121b. The delay circuit 111 transmits the delayed control signal CS1 to the buffer 121b.

[0211] The delay circuit 112 is a circuit that delays the control signal CS2. The input terminal of the delay circuit 112 is connected to the output terminal T2 of the decoder 101. The output terminal of the delay circuit 112 is connected to the input terminal of the buffer 122b. The delay circuit 112 transmits the delayed control signal CS2 to the buffer 122b.

[0212] The delay circuit 113 is a circuit that delays the control signal CS3. The input terminal of the delay circuit 113 is connected to the output terminal T3 of the decoder 101. The output terminal of the delay circuit 113 is connected to the input terminal of the buffer 123b. The delay circuit 113 transmits the delayed control signal CS3 to the buffer 123b.

[0213] Buffer 121a transmits the control signal CS1 to the switch circuit SW1a. The input terminal of buffer 121a is connected to the output terminal T1 of decoder 101. The forward output terminal (+) of buffer 121a is connected to the switch circuit SW1a.

[0214] Buffer 121b transmits the delayed control signal CS1 to the switch circuit SW1b. The input terminal of buffer 121b is connected to the delay circuit 111. The forward output terminal (+) of buffer 121b is connected to the switch circuit SW1b.

[0215] Buffer 122a transmits the control signal CS2 to the switch circuit SW2a. The input terminal of buffer 122a is connected to the output terminal T2 of decoder 101. The forward output terminal (+) of buffer 122a is connected to the switch circuit SW2a.

[0216] Buffer 122b transmits the delayed control signal CS2 to the switch circuit SW2b. The input terminal of buffer 122b is connected to the delay circuit 112. The forward output terminal (+) of buffer 122b is connected to the switch circuit SW2b.

[0217] Buffer 123a transmits the control signal CS3 to the switch circuit SW3a. The input terminal of buffer 123a is connected to the output terminal T3 of decoder 101. The forward output terminal (+) of buffer 123a is connected to the switch circuit SW3a.

[0218] Buffer 123b transmits the delayed control signal CS3 to the switch circuit SW3b. The input terminal of buffer 123b is connected to the delay circuit 113. The forward output terminal (+) of buffer 123b is connected to the switch circuit SW3b.

[0219] 8.2 Effects according to this embodiment With the configuration according to this embodiment, the same effects as in the first embodiment can be obtained.

[0220] 9. Variations, etc. The embodiments are not limited to the forms described above, and various modifications are possible.

[0221] In the above embodiment, if the resistance value or gate width is the same, it may include errors due to manufacturing variations.

[0222] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents.

[0223] <Note> Furthermore, some or all of the above embodiments may also be described as follows, but are not limited to these descriptions.

[0224] (Note 1) A first input terminal (RFC) that receives high-frequency signals, The second input terminal (CTRL) receives the control signal, The first output terminal (RF1) outputs the aforementioned high-frequency signal, A second output terminal (RF2) that outputs the aforementioned high-frequency signal, A first switch circuit (SW1a) controls the electrical connection between the first input terminal and the first output terminal, A second switch circuit (SW2a) controls the electrical connection between the first input terminal and the second output terminal, A third switch circuit (SW1b) is connected in parallel with the first switch circuit and controls the electrical connection between the first input terminal and the first output terminal. A fourth switch circuit (SW2b) is connected in parallel with the second switch circuit and controls the electrical connection between the first input terminal and the second output terminal. Equipped with, When switching the connection destination of the first input terminal from the first output terminal to the second output terminal, the switching operations of the third switch circuit and the fourth switch circuit are completed after the switching operations of the first switch circuit and the second switch circuit are completed. High-frequency semiconductor integrated circuit.

[0225] (Note 2) The first switch circuit and the third switch circuit perform the switching operation based on the control signal. The second switch circuit and the fourth switch circuit perform the switching operation based on the inverted signal of the control signal. The high-frequency semiconductor integrated circuit described in Appendix 1.

[0226] (Note 3) When switching the connection destination of the first input terminal from the first output terminal to the second output terminal, the first switch circuit and the third switch circuit are initially in the ON state and the second switch circuit and the fourth switch circuit are initially in the OFF state, then the first switch circuit is initially in the OFF state and the second switch circuit is initially in the ON state, and then the third switch circuit is initially in the OFF state and the fourth switch circuit is initially in the ON state. The high-frequency semiconductor integrated circuit described in Appendix 1.

[0227] (Note 4) A first buffer (3) connected to the second input terminal and including a third input terminal for receiving the control signal, a third output terminal (+) for outputting the control signal, and a fourth output terminal (-) for outputting the inverted signal of the control signal, A fifth resistor (4_1) has one terminal connected to the third output terminal of the first buffer and the other terminal connected to the third switch circuit, A sixth resistor (4_2) has one terminal connected to the fourth output terminal of the first buffer and the other terminal connected to the fourth switch circuit. It also has, The high-frequency semiconductor integrated circuit described in Appendix 2.

[0228] (Note 5) The first switch circuit includes a plurality of first transistors (11a) connected in series and a plurality of first resistors (13a) connected to the gates of the plurality of first transistors, The second switch circuit includes a plurality of second transistors (21a) connected in series and a plurality of second resistors (23a) connected to the gates of the plurality of second transistors, The third switch circuit includes a plurality of third transistors (11b) connected in series and a plurality of third resistors (13b) connected to the gates of the plurality of third transistors, The fourth switch circuit includes a plurality of fourth transistors (21b) connected in series and a plurality of fourth resistors (23b) connected to the gates of the plurality of fourth transistors, The resistance values ​​of each of the plurality of first resistive elements, the plurality of second resistive elements, the plurality of third resistive elements, and the plurality of fourth resistive elements are the same. The gate widths of each of the plurality of first transistors, plurality of second transistors, plurality of third transistors, and plurality of fourth transistors are the same. The high-frequency semiconductor integrated circuit described in Appendix 4.

[0229] (Note 6) A fifth switch circuit (SW1c) is connected in parallel with the first switch circuit and the third switch circuit, and controls the electrical connection between the first input terminal and the first output terminal. A sixth switch circuit (SW2c) is connected in parallel with the second switch circuit and the fourth switch circuit, and controls the electrical connection between the first input terminal and the second output terminal. Furthermore, The fifth switch circuit performs the switching operation based on the control signal. The sixth switch circuit performs the switching operation based on the inverted signal of the control signal. When switching the connection destination of the first input terminal from the first output terminal to the second output terminal, After the switching operations of the third and fourth switch circuits are completed, the switching operations of the fifth and sixth switch circuits are completed. The high-frequency semiconductor integrated circuit described in Appendix 4.

[0230] (Note 7) The switching time of the fifth switch circuit is longer than the switching time of the third switch circuit, and the switching time of the third switch circuit is longer than the switching time of the first switch circuit. The switching time of the sixth switch circuit is longer than the switching time of the fourth switch circuit, and the switching time of the fourth switch circuit is longer than the switching time of the second switch circuit. The high-frequency semiconductor integrated circuit described in Appendix 6.

[0231] (Note 8) When switching the connection destination of the first input terminal from the first output terminal to the second output terminal, the first switch circuit, the third switch circuit, and the fifth switch circuit are in the ON state and the second switch circuit, the fourth switch circuit, and the sixth switch circuit are in the OFF state, then the first switch circuit is turned OFF and the second switch circuit is turned ON, then the third switch circuit is turned OFF and the fourth switch circuit is turned ON, then the fifth switch circuit is turned OFF and the sixth switch circuit is turned ON. The high-frequency semiconductor integrated circuit described in Appendix 6.

[0232] (Note 9) A fifth buffer (3) is connected to the second input terminal and includes a seventh input terminal for receiving the control signal, an eleventh output terminal (+) for outputting the control signal, and a twelfth output terminal (-) for outputting an inverted signal of the control signal. A fourth delay circuit (6_1) is connected to the 11th output terminal and transmits the control signal to the third switch circuit with a delay, A fifth delay circuit (6_2) is connected to the 12th output terminal and transmits the inverted signal of the control signal to the 4th switch circuit with a delay, A sixth delay circuit (7_1) is connected to the fourth delay circuit and transmits the control signal, which has been delayed by the fourth delay circuit, to the fifth switch circuit with a further delay, A seventh delay circuit (7_2) is connected to the fifth delay circuit and transmits to the sixth switch circuit the inverted signal of the control signal delayed by the fifth delay circuit with a further delay. It also has, The high-frequency semiconductor integrated circuit described in Appendix 6.

[0233] (Note 10) A sixth buffer (3a) transmits the control signal received from the second input terminal to the first switch circuit and transmits an inverted signal of the control signal to the second switch circuit, An eighth delay circuit (8) connected to the second input terminal, which delays the control signal, A seventh buffer (3b) connected to the eighth delay circuit transmits the control signal delayed by the eighth delay circuit to the third switch circuit, and transmits the inverted signal of the control signal delayed by the eighth delay circuit to the fourth switch circuit, A ninth delay circuit (9) is connected to the eighth delay circuit and further delays the control signal that has been delayed by the eighth delay circuit, An eighth buffer (3c) connected to the ninth delay circuit transmits the control signal delayed by the eighth and ninth delay circuits to the fifth switch circuit, and transmits the inverted signal of the control signal delayed by the eighth and ninth delay circuits to the sixth switch circuit. It also has, The high-frequency semiconductor integrated circuit described in Appendix 6.

[0234] (Note 11) A 13th output terminal (RF3) that outputs the aforementioned high-frequency signal, A seventh switch circuit (SW3a) controls the electrical connection between the first input terminal and the thirteenth output terminal, The electrical connection between the first input terminal and the thirteenth output terminal is controlled by an eighth switch circuit (SW3b) connected in parallel with the seventh switch circuit, A decoder (101) that outputs a first signal (CS1) for controlling the first switch circuit and the third switch circuit, a second signal (CS2) for controlling the second switch circuit and the fourth switch circuit, and a third signal (CS1) for controlling the seventh switch circuit and the eighth switch circuit, A tenth delay circuit (111) that delays the first signal, An eleventh delay circuit (112) that delays the aforementioned second signal, A 12th delay circuit (113) that delays the aforementioned third signal, A ninth buffer (121a) transmits the first signal received from the decoder to the first switch circuit, A tenth buffer (122a) transmits the second signal received from the decoder to the second switch circuit, An eleventh buffer (123a) transmits the second signal received from the decoder to the seventh switch circuit, A 12th buffer (121b) transmits the delayed 1st signal received from the 10th delay circuit to the 3rd switch circuit, A 13th buffer (122b) transmits the delayed 2nd signal received from the 11th delay circuit to the 4th switch circuit, A 14th buffer (123b) transmits the delayed 3rd signal received from the 12th delay circuit to the 8th switch circuit, It also has, The high-frequency semiconductor integrated circuit described in Appendix 6. [Explanation of symbols]

[0235] 1…High-frequency semiconductor integrated circuit, 2, 2a, 2b, 2c…Switching unit, 3, 3a, 3b, 3c, 121a, 121b, 122a, 122b, 123a, 123b…Buffer, 4_1, 4_2, 12, 12a, 12b, 12c, 13a, 13b, 13c, 22, 22a, 22b, 22c, 23a, 23b, 23c, 53…Resistor element, 5, 5_1, 5_2, 6~9, 111~113…Delay circuit, 11a, 11b, 11c, 21a, 21b, 21c…Transistor, 51, 52…Inverter, 54…Capacitor element, 101…Decoder, SW1, SW1a, SW1b, SW1c, SW2a, SW2b, SW2c…Switch circuit

Claims

1. A first input terminal for receiving high-frequency signals, A second input terminal for receiving control signals, A first output terminal that outputs the aforementioned high-frequency signal, A second output terminal that outputs the aforementioned high-frequency signal, A first switch circuit that controls the electrical connection between the first input terminal and the first output terminal, A second switch circuit that controls the electrical connection between the first input terminal and the second output terminal, A third switch circuit, which controls the electrical connection between the first input terminal and the first output terminal and is connected in parallel with the first switch circuit, A fourth switch circuit, which controls the electrical connection between the first input terminal and the second output terminal and is connected in parallel with the second switch circuit, Equipped with, When switching the connection destination of the first input terminal from the first output terminal to the second output terminal, a first switching operation to turn the first switch circuit from the ON state to the OFF state and a second switching operation to turn the second switch circuit from the OFF state to the ON state are completed, followed by a third switching operation to turn the third switch circuit from the ON state to the OFF state and a fourth switching operation to turn the fourth switch circuit from the OFF state to the ON state. High-frequency semiconductor integrated circuit.

2. The first switching operation of the first switch circuit and the third switching operation of the third switch circuit are performed based on the control signal, The second switching operation of the second switch circuit and the fourth switching operation of the fourth switch circuit are performed based on the inverted signal of the control signal, respectively. The high-frequency semiconductor integrated circuit according to claim 1.

3. The switching time of the third switching operation of the third switch circuit is longer than the switching time of the first switching operation of the first switch circuit, and the switching time of the fourth switching operation of the fourth switch circuit is longer than the switching time of the second switching operation of the second switch circuit. The high-frequency semiconductor integrated circuit according to claim 1.

4. The first switch circuit includes a plurality of first transistors connected in series and a plurality of first resistors connected to the gates of the plurality of first transistors, The second switch circuit includes a plurality of second transistors connected in series and a plurality of second resistive elements connected to the gates of the plurality of second transistors, The third switch circuit includes a plurality of third transistors connected in series and a plurality of third resistors connected to the gates of the plurality of third transistors, The fourth switch circuit includes a plurality of fourth transistors connected in series and a plurality of fourth resistors connected to the gates of the plurality of fourth transistors, The gate width of each of the plurality of first transistors and the plurality of second transistors is shorter than the gate width of each of the plurality of third transistors and the plurality of fourth transistors. The high-frequency semiconductor integrated circuit according to claim 3.

5. The resistance values ​​of each of the plurality of first resistive elements, the plurality of second resistive elements, the plurality of third resistive elements, and the plurality of fourth resistive elements are the same. The high-frequency semiconductor integrated circuit according to claim 4.

6. The first switch circuit includes a plurality of first transistors connected in series and a plurality of first resistors connected to the gates of the plurality of first transistors, The second switch circuit includes a plurality of second transistors connected in series and a plurality of second resistive elements connected to the gates of the plurality of second transistors, The third switch circuit includes a plurality of third transistors connected in series and a plurality of third resistors connected to the gates of the plurality of third transistors, The fourth switch circuit includes a plurality of fourth transistors connected in series and a plurality of fourth resistors connected to the gates of the plurality of fourth transistors, The resistance value of each of the plurality of first resistive elements and the plurality of second resistive elements is smaller than the resistance value of each of the plurality of third resistive elements and the plurality of fourth resistive elements. The high-frequency semiconductor integrated circuit according to claim 3.

7. The gate widths of each of the plurality of first transistors, plurality of second transistors, plurality of third transistors, and plurality of fourth transistors are the same. The high-frequency semiconductor integrated circuit according to claim 6.

8. A first buffer including a third input terminal connected to the second input terminal for receiving the control signal, a third output terminal connected to the first switch circuit for outputting the control signal, and a fourth output terminal connected to the second switch circuit for outputting the inverted signal of the control signal, A fifth resistor element having one terminal connected to the third output terminal of the first buffer and the other terminal connected to the third switch circuit, A sixth resistor element having one terminal connected to the fourth output terminal of the first buffer and the other terminal connected to the fourth switch circuit. It also has, The high-frequency semiconductor integrated circuit according to claim 2.

9. A second buffer including a fourth input terminal connected to the second input terminal for receiving the control signal, a fifth output terminal connected to the first switch circuit for outputting the control signal, and a sixth output terminal connected to the second switch circuit for outputting the inverted signal of the control signal, A first delay circuit connected to the second input terminal and delaying the control signal, A third buffer including a fifth input terminal connected to the first delay circuit and receiving the control signal delayed by the first delay circuit, a seventh output terminal connected to the third switch circuit and outputting the control signal delayed by the first delay circuit, and an eighth output terminal connected to the fourth switch circuit and outputting the inverted signal of the control signal delayed by the first delay circuit. It also has, The high-frequency semiconductor integrated circuit according to claim 2.

10. A fourth buffer including a sixth input terminal connected to the second input terminal for receiving the control signal, a ninth output terminal connected to the first switch circuit for outputting the control signal, and a tenth output terminal connected to the second switch circuit for outputting the inverted signal of the control signal, A second delay circuit is connected to the ninth output terminal and transmits the control signal to the third switch circuit with a delay, A third delay circuit is connected to the tenth output terminal and transmits the inverted signal of the control signal to the fourth switch circuit with a delay. It also has, The high-frequency semiconductor integrated circuit according to claim 2.

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