Low-voltage differential signaling device and low-voltage differential signaling driver
By introducing output circuits, shutdown circuits, and substrate clamping circuits into the LVDS driver, the problem of excessive leakage current under power-off conditions is solved, achieving effective leakage protection for LVDS devices, meeting standard requirements, and improving device reliability.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- SG MICRO CORP
- Filing Date
- 2025-05-30
- Publication Date
- 2026-05-28
AI Technical Summary
Existing LVDS drivers exhibit large leakage current when the output node is short-circuited during power-off, failing to meet the self-protection requirements of the TIA/EIA-644-A standard.
The design employs an output circuit, a shutdown circuit, and a substrate clamping circuit, including a differential push-pull output circuit, a first current source, a substrate clamping circuit, and a shutdown circuit. By shutting off the current source and clamping the substrate potential in the power-off state, leakage protection is achieved.
It effectively reduces leakage current, meets the self-protection requirements of the TIA/EIA-644-A standard, and improves the reliability of LVDS equipment.
Smart Images
Figure CN2025098380_28052026_PF_FP_ABST
Abstract
Description
Low-voltage differential signaling equipment and its drivers Cross-references to related applications
[0001] This application claims priority to Chinese Patent Application No. 202411698982.6, filed on November 25, 2024, entitled “Low-voltage differential signaling device and driver thereof”, the entire contents of which are incorporated herein by reference. Technical Field
[0002] This invention relates to the field of integrated circuit technology, and in particular to a low-voltage differential signaling device and its driver. Background Technology
[0003] LVDS (Low Voltage Differential Signaling) is a point-to-point high-speed differential electrical interface designed for applications requiring ultra-low power consumption, low noise, and high data rates.
[0004] Under normal circumstances, LVDS interface circuits need to meet the TIA / EIA-644-A standard published by the Electronic Industries Association (TIA). This standard specifies the electrical and switching characteristics that LVDS interface circuits must meet, as well as the self-protection functions required by LVDS devices, including low leakage current (in some cases less than 20µA) in the event of an open or short circuit at the output node. LVDS devices typically include an LVDS driver and a receiver. In existing LVDS drivers, if the output node is short-circuited to the power supply when power is off, a large leakage current will flow into the LVDS device, thus failing to meet the self-protection requirements of the TIA / EIA-644-A standard.
[0005] Therefore, there is a need to propose a new low-voltage differential signaling device and its driver to solve the above problems. Summary of the Invention
[0006] In view of the above problems, the purpose of this invention is to provide a low-voltage differential signal device and its driver, so as to provide effective leakage protection for the low-voltage differential signal driver when it is in a power-off state.
[0007] According to one aspect of the present invention, a low-voltage differential signal driver is provided, comprising an output circuit including a first current source and a differential push-pull output circuit, wherein the first current source is connected between a power supply terminal and the differential push-pull output circuit, the differential push-pull output circuit is connected to the differential output terminal of the driver, and is used to generate a first output voltage and a second output voltage according to a first input signal and a second input signal; a shutdown circuit connected to the differential output terminal of the driver, used to shut off the first current source by using a short-circuited power supply on the differential output terminal when the driver is in a leakage protection state; and a substrate clamping circuit, wherein a first terminal is connected to the power supply terminal, a second terminal provides a substrate potential for the MOS transistor in the first current source, and the substrate clamping circuit is in a shutdown state in the direction from the second terminal to the first terminal when the driver is in a leakage protection state.
[0008] Optionally, the differential push-pull output circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The first current source includes a third PMOS transistor and a fourth PMOS transistor connected sequentially between the power supply terminal and the first terminals of the first PMOS transistor and the second PMOS transistor. The substrates of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all connected to a first voltage terminal, and the substrates of the first NMOS transistor and the second NMOS transistor are all connected to a second voltage terminal.
[0009] Optionally, the second terminal of the substrate clamping circuit is connected to the first voltage terminal; the shutdown circuit is connected to the control terminal of the fourth PMOS transistor, and is used to turn off the fourth PMOS transistor by using the short-circuited power supply on the differential output terminal when the driver is in the leakage protection state, so as to shut down the first current source.
[0010] Optionally, the output circuit further includes a second current source, wherein the first current source, the differential push-pull output circuit, and the second current source are sequentially connected between the power supply terminal and the ground terminal, and the second current source includes a third NMOS transistor, wherein the first end of the third NMOS transistor is connected to the second end of the first NMOS transistor and the second NMOS transistor, and the substrate of the third NMOS transistor is connected to the second voltage terminal.
[0011] Optionally, the driver further includes an open-circuit protection circuit for pulling the power supply terminal down to the ground terminal when the power supply terminal is open-circuited.
[0012] Optionally, the substrate clamping circuit includes a first transistor connected between the power supply terminal and the first voltage terminal, with its control terminal connected to the power supply terminal and its substrate connected to the second voltage terminal, which is a ground terminal.
[0013] Optionally, the shutdown circuit includes a second transistor connected between the control terminal and the positive differential output terminal of the fourth PMOS transistor, with its control terminal connected to the power supply terminal and its substrate connected to the first voltage terminal; and a third transistor connected between the control terminal and the negative differential output terminal of the fourth PMOS transistor, with its control terminal connected to the control terminal of the second transistor and its substrate connected to the first voltage terminal.
[0014] Optionally, the substrate clamping circuit further includes a first resistor connected between the power supply terminal and the control terminal of the first transistor; and a second resistor connected between the second terminal of the first transistor and the first voltage terminal.
[0015] Optionally, the shutdown circuit further includes a third resistor connected between the power supply terminal and the control terminal of the second transistor; a fourth resistor connected between the second terminal of the second transistor and the positive differential output terminal; and a fifth resistor connected between the second terminal of the third transistor and the negative differential output terminal.
[0016] According to another aspect of the present invention, a low-voltage differential signaling device is provided, comprising a low-voltage differential signal driver as described above; and a low-voltage differential signal receiver connected to the low-voltage differential signal driver via a differential signal line.
[0017] The present invention provides a low-voltage differential signal device and its driver. The LVDS driver includes an output circuit, a shutdown circuit, and a substrate clamping circuit. The shutdown circuit is connected to the differential output terminal of the LVDS driver. The first terminal of the substrate clamping circuit is connected to the power supply terminal, and the second terminal provides the substrate potential for the MOS transistor in the first current source. When the LVDS driver is in a leakage protection state, the shutdown circuit uses the short-circuited power supply on the differential output terminal to shut off the first current source. The substrate clamping circuit is in a shutdown state from its second terminal to its first terminal, thereby enabling the LVDS driver to meet the self-protection requirements of the TIA / EIA-644-A standard. Attached Figure Description
[0018] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:
[0019] Figure 1 shows a circuit diagram of a low-voltage differential signal driver;
[0020] Figure 2 shows a schematic diagram of leakage current test when the differential output terminal of the low-voltage differential signal driver shown in Figure 1 is short-circuited to the second power supply terminal in the power-off state.
[0021] Figure 3 shows a leakage current diagram of the differential output terminal being short-circuited to the second power supply terminal when the low-voltage differential signal driver shown in Figure 1 is in a power-off state.
[0022] Figure 4 shows a circuit diagram of a low-voltage differential signal driver according to an embodiment of the present invention;
[0023] Figure 5 shows a leakage current diagram of the differential output terminal being short-circuited to the second power supply terminal when the low-voltage differential signal driver shown in Figure 4 is in a power-off state. Detailed Implementation
[0024] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements or modules are indicated by the same or similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale.
[0025] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.
[0026] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in function.
[0027] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0028] Figure 1 shows a circuit diagram of a low-voltage differential signal driver.
[0029] Referring to Figure 1, the LVDS driver 100 includes an output circuit and a common-mode feedback circuit. The output circuit includes transistors M1, M2, M4, M5, and M3 connected sequentially between a first power supply terminal and a ground terminal, and transistors M6 and M7 connected sequentially between the intermediate nodes of transistors M2 and M4 and the intermediate nodes of transistors M5 and M3. Transistors M1-M2, M4, and M6 are PMOS transistors, and their substrates are all connected to the first power supply terminal. Transistors M3, M5, and M7 are NMOS transistors, and their substrates are all connected to the ground terminal. The control terminals of transistors M4-M5 receive the input signal Vin1, the control terminals of transistors M6-M7 receive the input signal Vin2, the control terminal of transistor M1 receives the bias voltage Vbias1, the control terminal of transistor M2 receives the bias voltage Vbias2, the intermediate node of transistors M6 and M7 serves as the first output node providing the output voltage Vout+, and the intermediate node of transistors M4 and M5 serves as the second output node providing the output voltage Vout-. The input signals Vin1 and Vin2 are inverted signals, and the ground terminal provides a ground voltage GND. The first power supply terminal is the chip power supply terminal, which provides the power supply voltage VDD. The first output node is connected to the positive differential output terminal of the LVDS driver 100, and the second output node is connected to the negative differential output terminal of the LVDS driver 100.
[0030] The common-mode feedback circuit includes an error amplifier 110 and resistors R1 and R2 connected in sequence between the positive and negative differential output terminals of the LVDS driver 100. The positive input terminal of the error amplifier 110 is connected to the midpoint of resistors R1 and R2, the negative input terminal receives the reference voltage Vref, and the output terminal is connected to the control terminal of transistor M3.
[0031] Furthermore, the positive and negative differential outputs of the LVDS driver 100 are also connected to the LVDS receiver. The LVDS receiver includes a terminating resistor Rt, capacitors CL1 and CL2. The terminating resistor Rt is connected between the positive and negative differential outputs, capacitor CL1 is connected between the positive differential output and ground, and capacitor CL2 is connected between the negative differential output and ground. The current flowing through the terminating resistor Rt is the drive current Iout.
[0032] The LVDS driver 100 uses the drains of PMOS transistors M6 and M7 to provide the output voltage Vout+, and the drains of PMOS transistors M4 and M5 to provide the output voltage Vout-, which can meet the requirements of large output drive current Iout and rapid switching of output voltages Vout+ and Vout-. When the LVDS driver 100 is in normal operation, the PMOS and NMOS transistors on the opposite side are alternately turned on (i.e., when M4 and M7 are on, M5 and M6 are off, and when M5 and M6 are on, M4 and M7 are off). The output current Is provided by the current source formed by transistors M1 and M2 flows through transistors M4-M7 and the terminating resistor Rt, thereby obtaining the differential output voltages Vout+ and Vout-. The signs of the differential output voltages Vout+ and Vout- are related to the on and off states of transistors M4-M7.
[0033] Figure 2 shows a leakage current test diagram of the low-voltage differential signal driver shown in Figure 1 when the differential output terminal is short-circuited to the second power supply terminal in the power-off state; Figure 3 shows a leakage current test diagram of the low-voltage differential signal driver shown in Figure 1 when the differential output terminal is short-circuited to the second power supply terminal in the power-off state.
[0034] Referring to Figures 2 and 3, when the LVDS driver 100 is in a power-off state, if the differential output terminals (positive differential output terminal and / or negative differential output terminal) are short-circuited to the second power supply terminal, the LVDS driver 100 will experience leakage current. Taking the positive differential output terminal being short-circuited to the second power supply terminal when the LVDS driver 100 is in a power-off state as an example, the potential of the positive differential output terminal of the LVDS driver 100 is raised to the power supply voltage VDD1 of the second power supply terminal, and the first power supply terminal is in a floating (open circuit) or short-circuited state, resulting in leakage current flowing from the positive differential output terminal to the first power supply terminal. The leakage current path is positive differential output terminal - M6 - M2 - M1 - first power supply terminal. In addition, at this time, the body diodes between the drain and substrate of transistors M6 and M2 are forward biased, which will also generate leakage current. This leakage current will be injected into the substrates of transistors M1 and M2 and the source terminal of transistor M1, i.e., the first power supply terminal. Therefore, the LVDS driver 100 cannot meet the self-protection requirements of the TIA / EIA-644-A standard, which affects the reliability of the entire LVDS device.
[0035] Figure 4 shows a circuit diagram of a low-voltage differential signal driver according to an embodiment of the present invention; Figure 5 shows a leakage current diagram of the low-voltage differential signal driver shown in Figure 4 when the differential output terminal is short-circuited to the second power supply terminal in the power-off state.
[0036] Referring to Figures 4 and 5, the LVDS driver 200 includes an output circuit 210, a common-mode feedback circuit 220, a substrate clamping circuit 230, a shutdown circuit 240, and an open-circuit protection circuit 250.
[0037] The output circuit 210 is used to generate output voltages Vout+ and Vout- based on the input signals Vin1 and Vin2. The output circuit 210 includes a first current source, a differential push-pull output circuit, and a second current source connected sequentially between a first power supply terminal and a ground terminal. The differential push-pull output circuit is connected to the differential output terminal of the LVDS driver 200. The first power supply terminal refers to the chip's power supply terminal.
[0038] The first terminal of the substrate clamping circuit 230 is connected to the first power supply terminal, and the second terminal provides the substrate potential for the MOS transistor in the first current source. When the LVDS driver 200 is in a leakage protection state, the substrate clamping circuit 230 is in a turned-off state from its second terminal to its first terminal. The second terminal of the substrate clamping circuit 230 is connected to the first voltage terminal A. The leakage protection state refers to the state where the LVDS driver 200 is de-energized and the differential output terminals (positive differential output terminal and / or negative differential output terminal) are short-circuited to the second power supply terminal.
[0039] The shutdown circuit 240 is connected to the differential output terminal of the LVDS driver 200 and is used to shut off the first current source by using the short-circuited power supply on the differential output terminal when the LVDS driver 200 is in the leakage protection state.
[0040] The differential push-pull output circuit includes a first PMOS transistor M4, a second PMOS transistor M6, a first NMOS transistor M5, and a second NMOS transistor M7. The first current source includes a third PMOS transistor M1 and a fourth PMOS transistor M2, and the second current source includes a third NMOS transistor M3. The third PMOS transistor M1, the fourth PMOS transistor M2, the first PMOS transistor M4, the first NMOS transistor M5, and the third NMOS transistor M3 are sequentially connected between a first power supply terminal and a ground terminal. The second PMOS transistor M6 and the second NMOS transistor M7 are sequentially connected between the intermediate node of the fourth PMOS transistor M2 and the first PMOS transistor M4 and the intermediate node of the first NMOS transistor M5 and the third NMOS transistor M3. The substrates of the first to fourth PMOS transistors are connected to a first voltage terminal A, and the substrates of the first to third NMOS transistors are connected to a second voltage terminal, such as a ground terminal. The control terminals of the first PMOS transistor M4 and the first NMOS transistor M5 receive the input signal Vin1, and the control terminals of the second PMOS transistor M6 and the second NMOS transistor M7 receive the input signal Vin2. The intermediate node of the second PMOS transistor M6 and the second NMOS transistor M7 serves as the first output node, providing the output voltage Vout+, and the intermediate node of the first PMOS transistor M4 and the first NMOS transistor M5 serves as the second output node, providing the output voltage Vout-. The input signals Vin1 and Vin2 are inverted signals. The first power supply terminal provides the power supply voltage VDD, and the ground terminal provides the ground voltage GND. The first output node is connected to the positive differential output terminal of the LVDS driver 200, and the second output node is connected to the negative differential output terminal of the LVDS driver 200.
[0041] The shutdown circuit 230 is also connected to the control terminal of the fourth PMOS transistor M2, and is used to turn off the fourth PMOS transistor M2 by using the power supply short-circuited on the differential output terminal when the LVDS driver 200 is in the leakage protection state, so as to shut down the first current source.
[0042] The common-mode feedback circuit 220 is used to compare the common-mode feedback voltages of the output voltages Vout+ and Vout- with the reference voltage Vref, and generate a control voltage Vc based on the comparison result, so as to adjust the output voltages Vout+ and Vout- through the control voltage Vc, so that the common-mode feedback voltages of the output voltages Vout+ and Vout- are stabilized near the reference voltage Vref.
[0043] The open-circuit protection circuit 250 is used to pull down the first power supply terminal to ground when the LVDS driver 200 is in a power-off state and the first power supply terminal is in an open-circuit state, so that the shutdown circuit 240 can function normally. It is understood that the open-circuit protection circuit 250 can be implemented using any existing circuit that can pull down the first power supply terminal to ground when the LVDS driver 200 is in a power-off state and the first power supply terminal is in an open-circuit state. For example, the open-circuit protection circuit 250 is implemented using a resistor R1 connected between the first power supply terminal and the ground terminal.
[0044] The common-mode feedback circuit 220 includes an error amplifier 221 and resistors R7 and R8 connected sequentially between the positive differential output terminal and the negative differential output terminal. The positive input terminal of the error amplifier 221 is connected to the intermediate node of resistors R7 and R8, the negative input terminal receives the reference voltage Vref, and the output terminal is connected to the control terminal of transistor M3 to provide the control voltage Vc for the control terminal of transistor M3.
[0045] The substrate clamping circuit 230 includes a transistor M11, which is connected between a first power supply terminal and a first voltage terminal A. The substrate of the transistor M11 is connected to a ground terminal, and the control terminal of the transistor M11 is connected to the first power supply terminal.
[0046] The substrate clamping circuit 230 also includes a resistor R6 connected between the control terminal and the first power supply terminal of transistor M11, and a resistor R5 connected between the second terminal and the first voltage terminal A of transistor M11. Resistors R5 and R6 are used to implement electrostatic discharge (ESD) protection.
[0047] The shutdown circuit 240 includes transistors M12 and M13. The control terminals of transistors M12 and M13 are connected to the first power supply terminal. The first terminals of transistors M12 and M13 are connected to the control terminal of the fourth PMOS transistor M2. The substrates of transistors M12 and M13 are connected to the first voltage terminal A. The second terminal of transistor M12 is connected to the first output node, and the second terminal of transistor M13 is connected to the second output node.
[0048] The shutdown circuit 240 also includes resistors R2-R4. Resistor R2 is connected between the first power supply terminal and the control terminal of transistor M12, resistor R3 is connected between the second terminal of transistor M12 and the first output node, and resistor R4 is connected between the second terminal of transistor M13 and the second output node. Resistors R2-R4 are used to implement electrostatic discharge (ESD) protection.
[0049] Optionally, transistors M12-M13 are also P-channel metal-oxide-semiconductor field-effect transistors (PMOS transistors), and transistor M11 is also an N-channel metal-oxide-semiconductor field-effect transistor (NMOS transistor). For a PMOS transistor, the first terminal is the source, the second terminal is the drain, and the control terminal is the gate. For an NMOS transistor, the first terminal is the drain, the second terminal is the source, and the control terminal is the gate.
[0050] The LVDS driver 200 operates as follows: In its normal operating state, the substrate of the PMOS transistor is connected to the power supply voltage VDD through transistor M11. At this time, transistor M11 acts as a forward-biased diode, providing a substrate potential slightly lower than the power supply voltage VDD to the first voltage terminal A, ensuring the normal operation of the LVDS driver 200 is unaffected. The gate voltage Vb of transistors M12 and M13 is pulled high to the power supply voltage VDD, and transistors M12 and M13 are turned off. Simultaneously, the gate voltage of the fourth PMOS transistor M2 depends on the bias voltage Vbias2, ensuring its normal operation. The current flowing through resistor R1 is equivalent to a constant quiescent operating current, not affecting the normal operation of the LVDS driver 200.
[0051] When the LVDS driver 200 is in leakage protection mode, if the first power supply terminal is short-circuited to ground voltage GND, the gate voltage Vb of transistors M12 and M13 is pulled to ground voltage GND, and transistors M12 and M13 are turned on. The gate voltage Va of the fourth PMOS transistor M2 is pulled high by the high voltage of the differential output terminal, causing the fourth PMOS transistor M2 to be turned off. Therefore, the leakage path to the source terminal of the fourth PMOS transistor M2 is cut off. In addition, at this time, the leakage current introduced by the forward conduction of the drain-substrate diodes of PMOS transistors M2, M4, M6 and M12-M13 flows to the source terminal of transistor M11 through resistor R5. The gate voltage of transistor M11 is pulled low by the first power supply terminal, causing transistor M11 to be turned off. Moreover, the parasitic diode between the source terminal and the substrate of transistor M11 is reverse biased, so there is no leakage current flowing into the first power supply terminal through transistor M11. Therefore, when the first power supply terminal is short-circuited to the ground terminal, the LVDS driver 200 has no leakage path to the first power supply terminal, forcing the leakage current to be in a very small state. If the first power supply terminal is open-circuited, since the gate voltage Vb of transistors M12 and M13 is in an uncertain state at this time, transistors M12 and M13 may not be able to conduct, and the leakage current flows into the first power supply terminal through the source terminal of transistor M2, resulting in a large leakage current. Therefore, at this time, it is necessary to set resistor R1 to pull the first power supply terminal down to the ground terminal, thereby turning on transistors M12 and M13 so that the shutdown circuit 240 can work normally.
[0052] In the leakage protection state, the LVDS driver 200 provided in this embodiment of the invention shuts off the first current source by using the power supply short-circuited on the differential output terminal of the shutdown circuit 240, and the substrate clamping circuit is in the off state in the direction from its second terminal to the first terminal, so that the LVDS driver 200 can meet the self-protection requirements of the TIA / EIA-644-A standard.
[0053] It is understood that the present invention also provides an LVDS device, which includes an LVDS driver 200 and an LVDS receiver, wherein the LVDS driver 200 and the LVDS receiver are connected via a differential data line. The LVDS driver may, for example, be the LVDS receiver shown in Figure 1.
[0054] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims and their equivalents.
Claims
1. A low voltage differential signal driver, comprising: an output circuit comprising a first current source connected between a power supply terminal and a differential push-pull output circuit, the differential push-pull output circuit connected to differential output terminals of the driver and configured to generate first and second output voltages in response to first and second input signals; a shutdown circuit connected to the differential output terminals of the driver and configured to shut down the first current source using a shorted power supply on the differential output terminals when the driver is in a leakage protection state; a substrate clamping circuit having a first terminal connected to the power supply terminal and a second terminal providing a substrate potential for a MOS transistor in the first current source, the substrate clamping circuit being in a shutdown state from the second terminal to the first terminal when the driver is in the leakage protection state.
2. The driver of claim 1, wherein, the differential push-pull output circuit comprises first and second PMOS transistors and first and second NMOS transistors, the first current source comprises third and fourth PMOS transistors connected in series between the power supply terminal and first terminals of the first and second PMOS transistors, and the substrates of the first, second, third and fourth PMOS transistors are connected to a first voltage terminal, and the substrates of the first and second NMOS transistors are connected to a second voltage terminal.
3. The driver of claim 2, wherein: the second terminal of the substrate clamping circuit is connected to the first voltage terminal; the shutdown circuit is connected to a control terminal of the fourth PMOS transistor and configured to shut down the fourth PMOS transistor using a shorted power supply on the differential output terminals to shut down the first current source when the driver is in the leakage protection state.
4. The driver of claim 2, wherein, the output circuit further comprises: a second current source connected in series with the first current source, the differential push-pull output circuit and the second current source between the power supply terminal and a ground terminal, the second current source comprises a third NMOS transistor having a first terminal connected to second terminals of the first and second NMOS transistors, and a substrate connected to the second voltage terminal.
5. The driver of claim 1, further comprising: an open circuit protection circuit configured to pull down the power supply terminal to the ground terminal when the power supply terminal is open circuited.
6. The driver of claim 3, wherein, the substrate clamping circuit comprises: a first transistor connected between the power supply terminal and the first voltage terminal, having a control terminal connected to the power supply terminal and a substrate connected to the second voltage terminal, the second voltage terminal being a ground terminal.
7. The driver of claim 4, wherein, the shutdown circuit comprises: a second transistor connected between the control terminal of the fourth PMOS transistor and a positive differential output terminal, having a control terminal connected to the power supply terminal and a substrate connected to the first voltage terminal; a third transistor connected between the control terminal of the fourth PMOS transistor and a negative differential output terminal, having a control terminal connected to the control terminal of the second transistor and a substrate connected to the first voltage terminal.
8. The driver of claim 6, wherein, the substrate clamping circuit further comprises: A first resistor is connected between the power supply terminal and the control terminal of the first transistor; The second resistor is connected between the second terminal of the first transistor and the first voltage terminal.
9. The driver of claim 7, wherein, The shutdown circuit also includes: The third resistor is connected between the power supply terminal and the control terminal of the second transistor; A fourth resistor is connected between the second terminal of the second transistor and the positive differential output terminal; The fifth resistor is connected between the second terminal of the third transistor and the negative differential output terminal.
10. A low-voltage differential signaling device, comprising: The low-voltage differential signal driver as described in any one of claims 1-9; as well as The low-voltage differential signal receiver is connected to the low-voltage differential signal driver via a differential signal line.