A high-frequency driving system for power semiconductor devices

Abstract

This invention discloses a high-frequency driving system for power semiconductor devices, comprising: an input signal filtering module, a high-speed driving and isolation processing module, an isolated high-speed push-pull gate driving module, and a gate output and absorption network module, cascaded in sequence. The input signal filtering module performs high-frequency noise suppression, PWM signal shaping, and spike pulse limitation on the PWM signal output by the microcontroller. The high-speed driving and isolation processing module isolates the PWM signal and converts the isolated PWM signal into a high-speed gate driving signal. The isolated high-speed push-pull gate driving module includes an isolated power supply module, a multi-stage decoupling network, and a push-pull output stage. The gate output and absorption network module performs shaping, current limiting, vibration absorption, and high-frequency energy compensation on the gate charging and discharging process of the power semiconductor device. It provides a high-frequency driving circuit for power devices with low parasitic inductance in the driving circuit, strong staged adjustable driving capability, and excellent anti-misoperation capability.

Description

Technical Field

[0001] This invention belongs to the field of power electronics and semiconductor device driving technology, and in particular, a high-frequency driving system for power semiconductor devices. Background Technology

[0002] With the widespread adoption of wide-bandgap and high-performance power semiconductor devices, such as silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs) and insulated-gate bipolar transistors (IGBTs), power electronic systems are rapidly developing towards higher frequencies, higher power densities, and higher efficiency. These new-generation power devices possess excellent characteristics such as fast switching speeds, high operating junction temperatures, and low on-resistance. However, their inherent nanosecond-level switching speeds and extremely high voltage change rates (dv / dt, typically reaching 50-100V / ns or even higher) also place unprecedentedly stringent demands on the core drive circuit. The reliability, accuracy, and anti-interference capabilities of the drive circuit have become key bottlenecks determining the overall system performance and lifespan.

[0003] Faced with the current demands for high-frequency power devices, traditional drive circuits suffer from large parasitic inductance in the drive loop, leading to severe voltage overshoot and oscillation during turn-on / turn-off. Fixed and singular drive resistors cannot provide differentiated drive capabilities at different operating stages and struggle to balance switching speed and overshoot suppression. Insufficient or excessive drive current during the Miller plateau makes it difficult to optimize switching losses and EMI performance. Weak negative voltage turn-off capability or fixed negative voltage values ​​fail to meet the more stringent anti-dv / dt false triggering requirements at high frequencies. These problems severely limit the performance of power devices in high-frequency, high-power-density scenarios, making them urgent technical challenges to address. Summary of the Invention

[0004] The purpose of this invention is to provide a high-frequency driving system for power semiconductor devices to overcome the shortcomings of the prior art. It provides a high-frequency driving circuit for power devices with low parasitic inductance in the driving circuit, strong staged adjustable driving capability, and excellent anti-misoperation capability.

[0005] One embodiment of this application provides a high-frequency driving system for a power semiconductor device, the system comprising: The input signal filtering module, high-speed drive and isolation processing module, isolated high-speed push-pull gate drive module, and gate output and absorption network module are cascaded in sequence. The input signal filtering module is used to perform high-frequency noise suppression, PWM signal shaping, and spike pulse limiting on the PWM signal output by the microcontroller. The high-speed drive and isolation processing module is used to isolate the PWM signal and convert the isolated PWM signal into a high-speed gate drive signal. The isolated high-speed push-pull gate drive module includes an isolated power supply module, a multi-stage decoupling network, and a push-pull output stage. The isolated power supply module is used to achieve electrical isolation between the input and output. The multi-stage decoupling network includes a wideband decoupling system constructed from multi-band capacitors to suppress power ripple caused by transient drive current. The push-pull output stage is composed of high-speed complementary drive structures made of driver chip transistors to achieve rapid charging and discharging of the gate of the power semiconductor device. The gate output and absorption network module is used to perform shaping, current limiting, vibration absorption and high-frequency energy compensation during the gate charging and discharging process of power semiconductor devices to ensure the stable operation of power semiconductor devices.

[0006] Optionally, the input signal filtering module includes an RC filter network, which includes at least two input resistors and two filter capacitors.

[0007] Optionally, the high-speed drive and isolation processing module includes an isolated high-speed gate drive chip; The isolated high-speed gate driver chip includes a magnetically coupled isolation structure with high common-mode transient immunity, an undervoltage lockout structure, a short-circuit protection structure, and a propagation delay matching mechanism.

[0008] Optionally, the isolated power supply module includes two isolated power supplies, and provides independent isolated power supply to the driver chip through a transformer isolation structure, and the wideband decoupling system is set at the output end of the isolated power supply.

[0009] Optionally, the push-pull output stage is composed of a first transistor and a second transistor inside the isolated high-speed gate driver chip. The first transistor is used to implement the fast pull-up function in the gate drive, and the second transistor is used to implement the fast pull-down function in the gate drive. The forward and reverse drive signals of the isolated high-speed gate drive chip are respectively sent to the first transistor and the second transistor to form a high-speed complementary drive structure.

[0010] Optionally, the gate output and absorption network module is disposed between the push-pull driver stage and the gate of the power semiconductor device; The gate output and absorption network module includes a gate series damping resistor, a parallel absorption capacitor, and a decoupling capacitor; wherein, the decoupling capacitor includes a low-frequency electrolytic decoupling capacitor, a medium-frequency ceramic decoupling capacitor, and a high-frequency bypass capacitor arranged adjacent to the driver chip.

[0011] Optionally, the gate series damping resistor is used to limit the current slope of the push-pull stage output and suppress overshoot caused by rapid changes in gate charge, so as to control the turn-on and turn-off speed of the power semiconductor device.

[0012] Optionally, the parallel absorption capacitor is used to absorb the high-frequency oscillation components formed by parasitic parameters between the output terminal of the push-pull drive stage and the gate of the power semiconductor device, so as to reduce the spikes and severe amplitude fluctuations of the gate voltage during switching transients.

[0013] Optionally, the decoupling capacitor is placed close to the gate drive output path to construct a high-frequency energy compensation channel, enabling the push-pull output stage to obtain stable energy support at the very near end when providing high peak drive current, and suppressing drive circuit ringing caused by high-frequency switching.

[0014] Optionally, the power semiconductor device includes a metal-oxide-semiconductor field-effect transistor and an insulated-gate bipolar transistor.

[0015] Compared with existing technologies, this invention provides a cascaded input signal filtering module, a high-speed drive and isolation processing module, an isolated high-speed push-pull gate drive module, and a gate output and absorption network module. The input signal filtering module performs high-frequency noise suppression, PWM signal shaping, and spike pulse limiting on the PWM signal output by the microcontroller. The high-speed drive and isolation processing module isolates the PWM signal and converts the isolated PWM signal into a high-speed gate drive signal. The isolated high-speed push-pull gate drive module includes an isolated power supply module, a multi-stage decoupling network, and a push-pull output stage. The isolated power supply module achieves electrical isolation between the input and output. The multi-stage decoupling network includes a wideband decoupling system constructed from multi-band capacitors to suppress power ripple caused by transient drive current. The push-pull output stage uses driver chip transistors to form a high-speed complementary drive structure to achieve rapid charging and discharging of the power semiconductor device's gate. The gate output and absorption network module performs shaping, current limiting, vibration absorption, and high-frequency energy compensation on the power semiconductor device's gate charging and discharging process to ensure stable operation of the power semiconductor device. It can provide a high-frequency drive circuit for power devices with low parasitic inductance in the drive circuit, strong staged adjustable drive capability, and excellent anti-misoperation capability. Attached Figure Description

[0016] Figure 1 A structural block diagram of a high-frequency driving system for a power semiconductor device provided in an embodiment of the present invention; Figure 2 A circuit diagram provided for an embodiment of the present invention includes an input signal filtering module, a high-speed driving and isolation processing module, and a gate output and absorption network module; Figure 3 A circuit diagram of an isolated high-speed push-pull gate drive module provided in an embodiment of the present invention; Figure 4 A circuit diagram of a driver chip power supply module provided in an embodiment of the present invention; Figure 5 This is a circuit diagram for inputting a PWM signal to outputting a drive voltage, provided as an embodiment of the present invention. Detailed Implementation

[0017] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] See Figure 1 , Figure 1 This is a structural block diagram of a high-frequency driving system for a power semiconductor device provided in an embodiment of the present invention. The high-frequency driving system 100 for the power semiconductor device includes: an input signal filtering module 101, a high-speed driving and isolation processing module 102, an isolated high-speed push-pull gate driving module 103, and a gate output and absorption network module 104, which are cascaded in sequence. The input signal filtering module 101 is used to perform high-frequency noise suppression, PWM signal shaping, and spike pulse limiting on the PWM signal output by the microcontroller. The high-speed driving and isolation processing module 102 is used to isolate the PWM signal and convert the isolated PWM signal into a high-speed gate driving signal. The isolated high-speed push-pull gate drive module 103 includes an isolated power supply module, a multi-stage decoupling network, and a push-pull output stage. The isolated power supply module is used to achieve electrical isolation between the input and output. The multi-stage decoupling network includes a wideband decoupling system constructed from multi-band capacitors to suppress power ripple caused by transient drive currents. The push-pull output stage is composed of high-speed complementary drive structures made of driver chip transistors to achieve rapid charging and discharging of the power semiconductor device gate. The gate output and absorption network module 104 is used to perform shaping, current limiting, vibration absorption, and high-frequency energy compensation during the charging and discharging process of the power semiconductor device gate to ensure stable operation of the power semiconductor device.

[0019] The input signal filtering module 101 includes an RC filter network, which includes at least two input resistors and two filter capacitors.

[0020] The high-speed drive and isolation processing module 102 includes an isolated high-speed gate drive chip; the isolated high-speed gate drive chip includes a magnetic coupling isolation structure with high common-mode transient immunity, an undervoltage lockout structure, a short-circuit protection structure, and a propagation delay matching mechanism.

[0021] The isolated power supply module includes two isolated power supplies, and provides independent isolated power supply to the driver chip through a transformer isolation structure. The wideband decoupling system is set at the output end of the isolated power supply.

[0022] The push-pull output stage consists of a first transistor and a second transistor inside the isolated high-speed gate driver chip. The first transistor is used to implement the fast pull-up function in the gate drive, and the second transistor is used to implement the fast pull-down function in the gate drive. The forward and reverse drive signals of the isolated high-speed gate driver chip are respectively sent to the first transistor and the second transistor to form a high-speed complementary drive structure.

[0023] The gate output and absorption network module is disposed between the push-pull driver stage and the gate of the power semiconductor device; the gate output and absorption network module includes a gate series damping resistor, a parallel absorption capacitor and a decoupling capacitor; wherein the decoupling capacitor includes a low-frequency electrolytic decoupling capacitor, a medium-frequency ceramic decoupling capacitor and a high-frequency bypass capacitor arranged adjacent to the driver chip.

[0024] It should be noted that the gate series damping resistor is used to limit the current slope of the push-pull stage output and suppress overshoot caused by rapid changes in gate charge, thereby controlling the turn-on and turn-off speed of the power semiconductor device. The parallel absorption capacitor is used to absorb the high-frequency oscillation components formed by parasitic parameters between the output terminal of the push-pull driver stage and the gate of the power semiconductor device, thereby reducing the spikes and severe amplitude fluctuations of the gate voltage during switching transients. The decoupling capacitor is located close to the gate drive output path to construct a high-frequency energy compensation channel, enabling the push-pull output stage to obtain stable energy support at the very near end when providing high peak drive current, and suppressing drive circuit ringing caused by high-frequency switching.

[0025] For example, the power semiconductor device may include a metal-oxide-semiconductor field-effect transistor (MOSFET) and an insulated-gate bipolar transistor (IGBT).

[0026] See Figure 2 , Figure 3 , Figure 4 and Figure 5 , Figure 2 A circuit diagram provided for an embodiment of the present invention includes an input signal filtering module, a high-speed driving and isolation processing module, and a gate output and absorption network module. Figure 3 This invention provides a circuit diagram of an isolated high-speed push-pull gate driver module. Figure 4 This invention provides a circuit diagram of a driver chip power supply module. Figure 5 This invention provides a circuit diagram for inputting a PWM signal to driving voltage output. Figure 2In the diagram, PWMIN represents the PWM signal input terminal, R18 and R19 represent input resistors, C35 and C37 represent filter capacitors, PWMGND represents the PWM signal ground, and VCC1 represents the positive power supply. In the high-speed drive and isolation processing module, U21 represents the isolated high-speed gate drive chip, IN represents the signal input terminal, OUT and OUTFC represent the drive signal output terminals, VCC2 represents the positive power supply, VEE2 represents the negative power supply, and GND1 represents the input side ground terminal. In the gate output and absorption network module, R21 and R22 represent the gate series damping resistors, C34 represents the parallel absorption capacitor, C28 represents the power supply decoupling / filtering capacitor, Q1 represents the first transistor or push-pull output stage pull-up transistor, Q2 represents the second transistor or push-pull output stage pull-down transistor, C36 represents the local decoupling capacitor, GATE represents the power semiconductor device gate connection terminal, and GND represents the ground terminal. Figure 3 In the isolated high-speed push-pull gate driver module, U17 and U18 represent isolated power supplies, VCC represents the main power supply, VIN, +VO, -VO, and 0V represent the input voltage, positive output voltage, negative output voltage, and zero potential of the isolated power supply module, C11, C14, C15, C18, C19, and C21 represent decoupling capacitors, R24, R28, R30, R32, R38, and R42 represent resistor networks used for adjustment or voltage division, U21 and U22 represent auxiliary voltage regulator or adjustment chips, Q1 represents the first transistor of the push-pull output stage, used for fast pull-up, and is connected to Q1 in the neutral output and absorption network module, and Q2 represents the second transistor of the push-pull output stage, used for fast pull-down, and is connected to Q2 in the neutral output and absorption network module. Figure 4 In the power supply module of the driver chip, U20 represents the isolated power supply module, VCC represents the input power supply voltage, VCC1 represents the regulated power supply output to the input side of the driver chip, C32 represents the regulated power supply output to the input side of the driver chip, C33 represents the output filter capacitor, and PWMGND represents the signal ground. Figure 5 In the flowchart of a PWM signal input to drive voltage output circuit, MCU represents a microcontroller unit, and drive voltage output represents the drive waveform that is finally applied to the gate of the power device.

[0027] The input signal filtering module is used to pass the PWM signal output by the microcontroller unit (MCU) through two input resistors R18 and R19 and filter capacitors C35 and C37 to form an RC filter network, thereby suppressing high-frequency noise and shaping the PWM signal output by the MCU, while limiting the spike pulses from entering the driver chip and ensuring the stability of the drive input signal.

[0028] The high-speed drive and isolation processing module can employ an isolated high-speed gate driver chip. This chip integrates a magnetically coupled isolation structure with high common-mode transient immunity (CMTI), providing high-speed, symmetrical, high-current push-pull output capability, and incorporates undervoltage lockout (UVLO), short-circuit protection, and propagation delay matching mechanisms. This chip converts the isolated PWM signal into a high-speed gate drive signal, driving the first transistor Q1 and the second transistor Q2 in the external push-pull enhancement stage, enabling rapid charging and discharging of the power device's gate. The driver chip's power supply ports are equipped with adjacent multi-stage decoupling networks to suppress transient voltage disturbances and ensure stable drive voltage, thereby achieving high dV / dt immunity, high-speed switching, and low-oscillation gate control for high-speed power devices such as SiC MOSFETs and IGBTs.

[0029] An isolated high-speed push-pull gate driver module can be comprised of three parts: a push-pull output stage, an isolated power supply module, and a multi-stage decoupling network. These components work together to form the core gate driver unit for high-speed power devices. The isolated power supply module provides an independent and stable isolated operating power supply for the driver stage. This module includes an isolated DC / DC power supply unit with complete electrical isolation between its input and output, effectively cutting off ground potential coupling between the power circuit and the control circuit. The output of the isolated power supply is equipped with a multi-stage decoupling network, including low-frequency, high-capacity electrolytic decoupling capacitors, medium-frequency ceramic decoupling capacitors, and high-frequency bypass capacitors located adjacent to the driver chip. The combination of decoupling capacitors across multiple frequency bands forms a wideband decoupling system, used to suppress power ripple caused by transient drive currents, stabilize the power supply voltage of the driver chip, and reduce the high-frequency impedance of the power supply circuit, ensuring stable power supply to the driver stage even under high dv / dt conditions. The stable drive voltage output from the isolated power supply and decoupling network is sent to the aforementioned isolated high-speed gate driver chip and the push-pull output stage within the isolated high-speed gate driver chip. The push-pull output stage can be composed of the first transistor Q1 and the second transistor Q2 inside the isolated high-speed gate driver chip, which respectively undertake the fast pull-up and fast pull-down functions in the gate drive. The forward and reverse drive signals of the isolated high-speed gate driver chip are sent to Q1 and Q2 respectively, making them form a high-speed complementary drive structure. Through the push-pull configuration, both the charging and discharging paths of the gate have low impedance and large peak current capability, thereby reducing the rise and fall delay of the gate, enabling the power device to complete the turn-on and turn-off at high speed and with a symmetrical waveform.

[0030] The gate output and absorption network module, positioned between the push-pull driver stage and the power device gate, is a crucial functional module for achieving high-speed, stable drive. This module includes devices such as a gate series damping resistor, a parallel absorption capacitor, and local decoupling capacitors. By shaping, limiting current, and absorbing vibrations during the gate charging and discharging process, it forms a high-speed gate control unit suitable for wide-bandgap power devices. The gate series damping resistor limits the current slope of the push-pull stage output, suppressing overshoot caused by rapid changes in gate charge and controlling the turn-on and turn-off speeds of the power device. This damping resistor functions on both the rising and falling edges of the device, ensuring symmetrical switching speeds and reducing switching losses and stress accumulation caused by inconsistent switching. By appropriately designing the damping resistor value, the drive system can leverage the switching advantages of high-speed power devices while avoiding oscillations and EMI problems caused by excessively rapid switching. The parallel absorption capacitor forms a high-frequency gate buffer path, absorbing high-frequency oscillation components caused by parasitic parameters between the push-pull driver stage output and the power device gate, reducing gate voltage spikes and severe amplitude fluctuations during switching transients. This absorption network effectively dissipates the energy generated by drain-gate parasitic coupling, preventing the gate voltage from being unintentionally boosted by dv / dt, thereby suppressing false turn-on and improving the stability of SiC MOSFETs during rapid turn-off. The local decoupling capacitor is placed close to the gate drive output path, creating a high-frequency energy compensation channel. This allows the push-pull output stage to obtain stable energy support very close to the edge when providing peak drive current, reducing voltage drops caused by parasitic loops on the power supply line. The local decoupling capacitor also further suppresses drive loop ringing caused by high-frequency switching, improving the smoothness of the gate voltage waveform and its anti-interference capability.

[0031] The gate output and absorption network works closely with the aforementioned isolated high-speed push-pull gate drive module. This isolated high-speed push-pull gate drive module provides high-speed, high-current drive and independent, stable energy, ensuring extremely low power supply ripple. Meanwhile, the gate output and absorption network shapes and filters the voltage waveform ultimately fed into the gate of the power semiconductor device, achieving comprehensive performance with high dv / dt disturbance rejection, high-speed switching, low oscillation, and low electromagnetic interference. This ensures the safe and reliable operation of SiC MOSFETs and IGBTs under high-frequency, high-voltage, and high-stress environments.

[0032] Therefore, the purpose of this invention is to provide a high-frequency driving circuit for power semiconductor devices. By using input filtering, isolation driving, high-speed push-pull output, multi-stage decoupling network and gate buffer structure, it improves dv / dt immunity, high-speed switching capability and switching reliability of the driving system, and ensures stable driving voltage output, thereby improving the overall performance and reliability of the power device system.

[0033] To better understand this invention, the following is combined with... Figure 2 , Figure 3 , Figure 4 and Figure 5 The present invention will be further described below. The present invention provides a high-frequency driving circuit for a power semiconductor device, the final output of which mainly includes the following steps: Step 1: The input signal filtering module consists of an RC filter network composed of resistors R19 and R18 and capacitors C37 and C35. This network is used for front-end shaping and anti-interference processing of the PWM_IN signal output by the controller. The electrical signal output by the microcontroller first passes through resistors R19 and R18 to limit current and reduce the amplitude of spike pulses. Then, it forms a low-pass filter structure with capacitor C37 to suppress high-frequency interference from the power circuit. Simultaneously, capacitor C35 and ground form a parallel absorption path, ensuring that the input signal reaches a stable, spike-free, and low-noise logic level before entering the isolated high-speed gate driver chip.

[0034] Step 2: The filtered PWM signal is first fed into an isolated high-speed gate driver chip. Inside the isolated high-speed gate driver chip, complete electrical isolation between the input and output sides is achieved through magnetic coupling. The isolator has high common-mode transient immunity, capable of withstanding dv / dt interference of up to tens of kV / µs generated by SiC MOSFETs or high-speed IGBTs during turn-off, ensuring that the control signal is not distorted or falsely triggered by power loop noise. The output terminal of the isolator inside the isolated driver chip is directly connected to the input port of the high-speed driver chip. The isolated high-speed gate driver chip integrates a high-speed drive buffer stage, undervoltage lockout protection, low propagation delay design, and gate drive output matching mechanism, which can convert the isolated PWM signal into a push-pull drive signal with high peak charge and discharge capability. The OUTP and OUTN pins of the isolated high-speed gate driver chip output complementary pull-up and pull-down signals, respectively, providing high-speed pulse drive capability for the subsequent push-pull drive stage.

[0035] Step 3: The isolated high-speed push-pull gate driver module consists of isolated power supply units U17 and U18, a multi-stage decoupling network, and push-pull output transistors Q1 and Q2 inside the isolated high-speed gate driver chip, collectively forming the core drive circuit of this invention. The isolated power supplies U17 and U18 provide independent isolated power to the isolated high-speed gate driver chip through a transformer isolation structure. A multi-stage decoupling network is arranged at its output terminal. This wideband decoupling system ensures that the drive voltage does not sag during high-speed switching, providing stable energy to the push-pull drive transistors. The OUTP and OUTN pins of the high-speed isolated high-speed gate driver chip drive the first transistor Q1 (pull-up) and the second transistor Q2 (pull-down), respectively, forming a high-speed complementary push-pull structure. When the isolated high-speed gate driver chip outputs a high level, Q1 is turned on and Q2 is turned off, achieving fast gate charging; when the isolated high-speed gate driver chip outputs a low level, Q1 is turned off and Q2 is turned on, achieving fast gate discharge. The push-pull stage structure results in low and symmetrical gate charging and discharging path impedance, providing a large peak drive current capability. This allows power devices to reach the target gate voltage in a very short time, thereby significantly improving switching speed, reducing switching losses, and enhancing anti-misoperation capability.

[0036] Step 4: The gate output and absorption network module is located between the push-pull driver stage and the gate of the power device. It consists of gate series damping resistors R21 and R22, gate absorption capacitor C34, and near-end decoupling capacitors. Damping resistors R21 and R22 limit the rate of change of the current in the push-pull stage output and precisely control the turn-on and turn-off slopes according to the characteristics of the power device, avoiding excessively rapid switching that could cause ringing, overshoot, or excessive EMI. Absorption capacitor C34 forms a high-frequency bypass structure between the gate and ground, absorbing high-frequency spike currents generated by parasitic path coupling during high-speed switching of the power device. This significantly suppresses gate ringing, reduces gate voltage overshoot caused by high dv / dt, prevents false turn-on, and improves system reliability. Furthermore, the local decoupling capacitor in the module provides near-end transient energy compensation for the push-pull output stage, keeping the gate voltage stable during high-speed switching without significant sag. The gate output and absorption network works in conjunction with the front-end push-pull drive structure to enable SiC MOSFETs or IGBTs to maintain a stable, clean, and low-noise gate waveform under high-frequency, high-voltage, and strong interference conditions.

[0037] Compared with the prior art, the present invention has the following significant advantages: High adaptability to operating conditions: The required turn-off negative voltage can be flexibly set according to the actual application scenario, and high dv / dt output can be achieved during voltage conversion by adjusting the resistance value of the gate series damping resistor. It adapts to the driving requirements of different power devices and different operating conditions, and solves the limitations of fixed negative voltage and non-adjustable driving parameters in traditional driving circuits.

[0038] Excellent anti-interference capability: The RC filter network of the input signal filtering module suppresses high-frequency interference and spike pulses. Combined with the high CMTI magnetic coupling isolation structure of the high-speed drive and isolation processing module, the interference coupling between the power circuit and the control circuit is effectively cut off. With the vibration absorption and filtering design of the gate output and absorption network, full-link anti-interference protection is achieved, ensuring stable drive signal and stable output voltage, and has strong interference resistance.

[0039] Excellent high-frequency drive performance: It adopts an isolated high-speed push-pull gate drive structure with low gate charging and discharging path impedance and large current, which significantly improves the switching speed and reduces switching losses; the wide-band decoupling system ensures stable power supply during high-frequency switching without significant voltage sag; the gate output and absorption network effectively suppress overshoot and oscillation, reduce EMI, and make the circuit suitable for the high-frequency drive requirements of MOSFETs and IGBTs, solving the problems of large parasitic inductance and difficulty in balancing switching characteristics and EMI in traditional drive circuits.

[0040] High reliability: The driver chip has built-in functions such as undervoltage lockout and short circuit protection. The gate output and absorption network effectively suppress false turn-on. The modules work together to reduce the switching stress of power devices and extend the service life of devices. At the same time, the modular design of the circuit structure facilitates debugging and maintenance and can be widely adapted to different types of power semiconductor device driving scenarios.

[0041] Compared with existing technologies, this invention provides a cascaded input signal filtering module, a high-speed drive and isolation processing module, an isolated high-speed push-pull gate drive module, and a gate output and absorption network module. The input signal filtering module performs high-frequency noise suppression, PWM signal shaping, and spike pulse limiting on the PWM signal output by the microcontroller. The high-speed drive and isolation processing module isolates the PWM signal and converts the isolated PWM signal into a high-speed gate drive signal. The isolated high-speed push-pull gate drive module includes an isolated power supply module, a multi-stage decoupling network, and a push-pull output stage. The isolated power supply module achieves electrical isolation between the input and output. The multi-stage decoupling network includes a wideband decoupling system constructed from multi-band capacitors to suppress power ripple caused by transient drive current. The push-pull output stage uses driver chip transistors to form a high-speed complementary drive structure to achieve rapid charging and discharging of the power semiconductor device's gate. The gate output and absorption network module performs shaping, current limiting, vibration absorption, and high-frequency energy compensation on the power semiconductor device's gate charging and discharging process to ensure stable operation of the power semiconductor device. It can provide a high-frequency drive circuit for power devices with low parasitic inductance in the drive circuit, strong staged adjustable drive capability, and excellent anti-misoperation capability.

[0042] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0043] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0044] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0045] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0046] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0047] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0048] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A high-frequency driving system for power semiconductor devices, characterized in that, The system includes: The input signal filtering module, high-speed drive and isolation processing module, isolated high-speed push-pull gate drive module, and gate output and absorption network module are cascaded in sequence. The input signal filtering module is used to perform high-frequency noise suppression, PWM signal shaping, and spike pulse limiting on the PWM signal output by the microcontroller. The high-speed drive and isolation processing module is used to isolate the PWM signal and convert the isolated PWM signal into a high-speed gate drive signal. The isolated high-speed push-pull gate drive module includes an isolated power supply module, a multi-stage decoupling network, and a push-pull output stage. The isolated power supply module is used to achieve electrical isolation between the input and output. The multi-stage decoupling network includes a wideband decoupling system constructed from multi-band capacitors to suppress power ripple caused by transient drive current. The push-pull output stage is composed of high-speed complementary drive structures made of driver chip transistors to achieve rapid charging and discharging of the gate of the power semiconductor device. The gate output and absorption network module is used to perform shaping, current limiting, vibration absorption and high-frequency energy compensation during the gate charging and discharging process of power semiconductor devices to ensure the stable operation of power semiconductor devices.

2. The system according to claim 1, characterized in that, The input signal filtering module includes an RC filter network, which includes at least two input resistors and two filter capacitors.

3. The system according to claim 2, characterized in that, The high-speed drive and isolation processing module includes an isolated high-speed gate drive chip; The isolated high-speed gate driver chip includes a magnetically coupled isolation structure with high common-mode transient immunity, an undervoltage lockout structure, a short-circuit protection structure, and a propagation delay matching mechanism.

4. The system according to claim 3, characterized in that, The isolated power supply module includes two isolated power supplies, and provides independent isolated power supply to the driver chip through a transformer isolation structure. The wideband decoupling system is set at the output end of the isolated power supply.

5. The system according to claim 4, characterized in that, The push-pull output stage is composed of a first transistor and a second transistor inside the isolated high-speed gate driver chip. The first transistor is used to implement the fast pull-up function in the gate drive, and the second transistor is used to implement the fast pull-down function in the gate drive. The forward and reverse drive signals of the isolated high-speed gate drive chip are respectively sent to the first transistor and the second transistor to form a high-speed complementary drive structure.

6. The system according to claim 5, characterized in that, The gate output and absorption network module is disposed between the push-pull driver stage and the gate of the power semiconductor device. The gate output and absorption network module includes a gate series damping resistor, a parallel absorption capacitor, and a decoupling capacitor; wherein, the decoupling capacitor includes a low-frequency electrolytic decoupling capacitor, a medium-frequency ceramic decoupling capacitor, and a high-frequency bypass capacitor arranged adjacent to the driver chip.

7. The system according to claim 6, characterized in that, The gate series damping resistor is used to limit the current slope of the push-pull stage output and suppress overshoot caused by rapid changes in gate charge, so as to control the turn-on and turn-off speed of the power semiconductor device.

8. The system according to claim 7, characterized in that, The parallel absorption capacitor is used to absorb the high-frequency oscillation components formed by parasitic parameters between the output terminal of the push-pull drive stage and the gate of the power semiconductor device, so as to reduce the spikes and severe amplitude fluctuations of the gate voltage during switching transients.

9. The system according to claim 8, characterized in that, The decoupling capacitor is located near the gate drive output path to construct a high-frequency energy compensation channel, enabling the push-pull output stage to obtain stable energy support at the very near end when providing high peak drive current, and suppressing drive circuit ringing caused by high-frequency switching.

10. The system according to any one of claims 1 to 9, characterized in that, The power semiconductor devices include metal-oxide-semiconductor field-effect transistors and insulated-gate bipolar transistors.

Images