Embodiments of storing fuse data in a memory device

Abstract

This application relates to implementations of storing fuse data in a memory device. Some implementations can include an array of memory cells having different portions of cells for storing data. A first portion of the array can store fuse data and can contain a chalcogenide storage element, while a second portion of the array can store user data. Sensing circuitry can be coupled with the array and can determine a value of the fuse data using various signaling techniques. In some cases, the sensing circuitry can implement differential storage and differential signaling to determine the value of the fuse data stored in the first portion of the array.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT application No. PCT / US2020 / 041436, filed July 9, 2020, entitled “Implementations to Store Fuse Data InMemory Devices” by Boniardi et al., which claims priority to U.S. Patent Application No. 16 / 514,431, also entitled “Implementations to Store Fuse Data InMemory Devices” by Boniardi et al., each of which is assigned to the assignee herein and the entire contents of each of which are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to implementation schemes for storing fuse data in a memory device. Background Technology

[0004] The following generally relates to operating at least one memory device, and more specifically to an implementation of storing fuse data in the memory device.

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, typically represented by logic "1" or logic "0". In other devices or systems, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program states into the memory device.

[0006] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and other chalcogenide-based memory technologies. Memory devices can be volatile or non-volatile. Generally, improvements to memory devices include increasing memory cell density, increasing read / write speed, increasing reliability, increasing data integrity, reducing power consumption or manufacturing costs, and other metrics. In some cases, memory devices can store data in several filament-like structures or cells located around the periphery of the main memory array. Summary of the Invention

[0007] Describe an apparatus. The apparatus may include a memory cell array comprising: a first memory cell portion for storing fuse data; a second memory cell portion for storing user data, wherein each memory cell in the first portion and each memory cell in the second portion includes a chalcogenide element; a sensing circuitry system coupled to the first memory cell portion and configured to identify values ​​of the fuse data stored in the first memory cell portion; and a controller coupled to the memory cell array and the sensing circuitry system and configured to access the memory cell array at least in part based on the fuse data stored in the first memory cell portion.

[0008] Describe a method. The method may include generating a first signal indicating a first state stored in a first set of memory cells of a memory device and a second signal indicating a second state stored in a second set of memory cells of the memory device, the second state being the complement of the first state; comparing the first signal indicating the first state with the second signal indicating the second state; identifying a value of fuse data of the memory device based at least in part on the comparison of the first signal and the second signal; and operating the memory device based at least in part on the value of the fuse data.

[0009] Describe another device. The device may include a first memory cell array of a first type configured to store user data; a second memory cell array of a second type, the second array including a chalcogenide element and configured to store fuse data associated with operating the first memory cell array; a sensing circuitry system coupled to the second memory cell array and configured to identify values ​​of the fuse data stored in the second array; and a controller coupled to the first array, the second array, and the sensing circuitry system and configured to access the memory cells of the first array at least in part based on the values ​​of the fuse data stored in the second array identified by the sensing circuitry system. Attached Figure Description

[0010] Figure 1 Examples of systems that support the implementation of storing fuse data in a memory device, based on examples disclosed herein.

[0011] Figure 2 Examples of memory dies that support implementations for storing fuse data in a memory device, based on examples disclosed herein.

[0012] Figure 3Examples of block diagrams illustrating a memory device that supports an implementation of storing fuse data in a memory device, based on examples disclosed herein.

[0013] Figure 4 Examples of block diagrams illustrating a memory device that supports an implementation of storing fuse data in a memory device, based on examples disclosed herein.

[0014] Figure 5A and 5B This document illustrates an example of a block diagram illustrating a signaling operation that supports an implementation of storing fuse data in a memory device, based on examples disclosed herein.

[0015] Figure 6 A block diagram illustrating an implementation scheme for storing fuse data in a memory device, based on examples disclosed herein.

[0016] Figure 7 The illustration shows flowcharts of one or more methods for supporting the storage of fuse data in a memory device, based on examples disclosed herein. Detailed Implementation

[0017] Memory devices can employ several different technologies to store data. In some cases, the memory device can permanently store data at the device, ensuring that the data is not overwritten or lost even when the device loses power. This data can be an example of information used by the memory device to operate the memory device. In some cases, this data can be stored using a fuse array to ensure that the data is not lost. The fuse array can be an example of a read-only memory (ROM) or a programmable read-only memory (PROM) and can be useful in cases where unchangeable data or instructions are stored in memory. In some cases, a programmable ROM or PROM may contain fuses or fusible chains that "blow" certain fuses. The combination of blown and unblowed fuses can represent a state of the fuse data (e.g., a binary state of "1" or "0"). In some embodiments, the fuse array can be integrated as a dedicated structure or circuit system located at the periphery of the memory device or array, or as a fuse array separated from a larger portion of the memory device or array.

[0018] However, such fuse architectures and write processes can have several drawbacks. For example, the portion of the memory device used for the fuse and driver can occupy a large area, and the driver used to blow the fuse (e.g., MOSFET transistor, bipolar transistor, etc.) can use relatively high programming current, thereby increasing the total power consumption of the memory device.

[0019] Instead of a dedicated fuse array at the periphery of a memory array, a memory array can be configured within a memory device or memory array to store fuse data. In some cases, the array storing fuse data may be a subarray or portion of the memory cells contained within the memory device. In some cases, the array storing fuse data may be separate from a portion of the memory array storing other types of data (e.g., user data). In either case, the array for storing fuse data may contain chalcogenide memory elements and be programmable or reprogrammable multiple times. Furthermore, because the cells of the array for storing fuse data can be programmed rather than irreversibly blown, the number of current drivers and / or the size of the current drivers can be reduced, along with other potential benefits.

[0020] First, as referenced Figure 1 and 2 The features of this disclosure are described in the context of the memory system and memory die described herein. (See references...) Figures 3 to 5B Features of this disclosure are described in the context of a memory device or memory array. (This is achieved through and referenced to references such as...) Figures 6 to 7 The apparatus diagrams and flowcharts describing the embodiment of storing fuse data in a memory device further illustrate and describe these and other features of this disclosure.

[0021] Figure 1 The example memory device 100 disclosed herein is described. The memory device 100 may also be referred to as an electronic memory device. Figure 1 This is an illustrative representation of the various components and features of the memory device 100. Therefore, it should be understood that the components and features of the memory device 100 are shown to illustrate functional interrelationships rather than their actual physical location within the memory device 100. Figure 1 In an illustrative example, memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 programmable to store different states. In some instances, each memory cell 105 is programmable to store two states represented as logic 0 and logic 1. In some instances, memory cells 105 may be configured to store more than two logic states. Although... Figure 1 Some of the elements contained herein are labeled with numerical indicators, while other corresponding elements are not labeled, but are identical or will be interpreted as similar in an attempt to increase the visibility and clarity of the depicted features.

[0022] 3D memory array 102 may comprise two or more two-dimensional (2D) memory arrays 103 formed on top of each other. Compared to 2D arrays, this increases the number of memory cells that can be placed or generated on a single die or substrate, which in turn reduces manufacturing costs or increases the performance of memory device 100, or both. Memory array 102 may comprise two levels of memory cells 105 and thus can be considered a 3D memory array; however, the number of levels is not limited to two. Each level may be aligned or positioned such that memory cells 105 can be aligned (exactly, overlapping, or approximately) with each other across each level, thereby forming a memory cell stack 145. In some cases, as described below, memory cell stack 145 may comprise multiple memory cells 105 laid on top of each other while sharing access lines for both. In some cases, memory cells 105 may be multilevel memory cells configured to store more than one data bit using multilevel memory technology.

[0023] In some instances, each row of memory cells 105 is connected to word lines 110, and each column of memory cells 105 is connected to bit lines 115. The term access line may refer to word lines 110, bit lines 115, or a combination thereof. Word lines 110 and bit lines 115 may be perpendicular (or nearly perpendicular) to each other and may create an array of memory cells 105. Figure 1 As shown, two memory cells 105 in a memory cell stack 145 may share a common conductive line, such as a bit line 115. That is, the bit line 115 may be coupled to the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations are possible; for example, a third stack may share a word line 110 with the lower stack. Generally, a memory cell 105 may be located at the intersection of two conductive lines (e.g., word line 110 and bit line 115). This intersection may be referred to as the address of the memory cell. A target memory cell 105 may be a memory cell 105 located at the intersection of an energized word line 110 and a bit line 115; that is, the word line 110 and the bit line 115 may be energized to read or write to the memory cell 105 at its intersection. Other memory cells 105 coupled (e.g., connected) to the same word line 110 or bit line 115 may be referred to as undefined memory cells 105.

[0024] Electrodes may be coupled to memory cell 105 and word line 110 or bit line 115. The term electrode may refer to an electrical conductor and in some cases may be used as an electrical contact to memory cell 105. Electrodes may comprise traces, wires, conductive lines, conductive materials, or the like that providing a conductive path between elements or components of memory device 100. In some instances, memory cell 105 may comprise a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode may be coupled to word line 110 and the other side of the first electrode may be coupled to the chalcogenide material. Additionally, one side of the second electrode may be coupled to bit line 115 and the other side of the second electrode may be coupled to the chalcogenide material. The first and second electrodes may be made of the same material (e.g., carbon) or different materials.

[0025] Operations such as reading and writing can be performed on memory cell 105 by activating or selecting word line 110 and bit line 115. In some instances, bit line 115 may also be referred to as digital line 115. References to access lines, word line 110, and bit line 115, or the like, are interchangeable without loss of understanding or operation. Activating or selecting word line 110 or bit line 115 may involve applying a voltage to the respective line. Word line 110 and bit line 115 may be made of, for example, metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive materials doped with conductive semiconductors, or other conductive materials, alloys, compounds, or the like.

[0026] Access to memory cells 105 can be controlled via row decoder 120 and column decoder 130. For example, row decoder 120 may receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 may receive a column address from memory controller 140 and activate the appropriate bit line 115. For example, memory array 102 may include multiple word lines 110 (labeled WL_1 to WL_M) and multiple digital lines 115 (labeled BL_1 to BL_N), where M and N depend on the array size. Thus, by activating word lines 110 and bit lines 115 (e.g., WL_2 and BL_3), memory cells 105 at their intersections can be accessed. As discussed in more detail below, access to memory cells 105 can be controlled via row decoder 120 and column decoder 130, which may comprise one or more doped materials extending in a direction away from the surface of the substrate coupled to memory array 102.

[0027] After access, the memory cell 105 can be read or sensed by the sensing component 125 to determine the stored state of the memory cell 105. For example, a voltage can be applied to the memory cell 105 (using corresponding word lines 110 and bit lines 115), and the presence of the resulting current may depend on the applied voltage and the threshold voltage of the memory cell 105. In some cases, more than one voltage may be applied. Alternatively, if the applied voltage does not cause current flow, other voltages may be applied until current is detected by the sensing component 125. By evaluating the voltage that causes current flow, the stored logic state of the memory cell 105 can be determined. In some cases, the voltage may be ramped up in magnitude until current flow is detected. In other cases, predetermined voltages may be applied sequentially until current is detected. Similarly, current may be applied to the memory cell 105, and the magnitude of the voltage that generates the current may depend on the resistance or threshold voltage of the memory cell 105. In some instances, the cell may be programmed by providing electrical pulses to the memory cell 105, and the cell may contain memory storage elements. Pulses can be provided via word line 110, bit line 115, or a combination thereof.

[0028] Sensing component 125 may include various transistors or amplifiers to detect and amplify signal differences, which may be referred to as latching. The detected logic state of the memory cell 105 can then be output as output 135 via column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 may be connected or coupled to column decoder 130 or row decoder 120. Sensing component 125 may be associated with column decoder 130 or row decoder 120.

[0029] Memory cell 105 can be set or written by activating the relevant word line 110 and bit line 115, and at least one logic value can be stored in memory cell 105. Column decoder 130 or row decoder 120 can accept data (e.g., input / output 135) to be written to memory cell 105. In the case of memory cells containing chalcogenide material, a first voltage can be applied to memory cell 105 to store a logic state in memory cell 105 by applying a first voltage to memory cell 105 as part of an access operation based on the first conductive line of the coupling decoder (e.g., row decoder 120 or column decoder 130) and the access line (e.g., word line 110 or bit line 115).

[0030] The memory controller 140 can control the operation (e.g., read, write, rewrite, refresh, discharge) of the memory cell 105 via various components (e.g., row decoder 120, column decoder 130, and sensing component 125). In some cases, one or more of the row decoder 120, column decoder 130, and sensing component 125 may be co-located with the memory controller 140. The memory controller 140 can generate row and column address signals to activate the desired word line 110 and bit line 115. The memory controller 140 can also generate and control various voltages or currents used during the operation of the memory device 100.

[0031] Memory controller 140 may be configured to select memory cell 105 by applying a first voltage to a first conductive line of a decoder (e.g., row decoder 120 or column decoder 130). In some cases, memory controller 140 may be configured to couple the first conductive line of the decoder to the access line associated with memory cell 105 (e.g., word line 110 or bit line 115) based on the selection of memory cell 105. Memory controller 140 may be configured to apply the first voltage to memory cell 105 at least in part based on the coupling of the first conductive line of the decoder to the access line.

[0032] In some instances, the memory controller 140 may be configured to apply a second voltage to a second conductive line of the decoder as part of an access operation. In some cases, the second voltage may cause selective coupling of the first conductive line of the decoder to the access line associated with the memory cell 105 via a doped material. Applying the first voltage to the memory cell 105 may be based on applying the second voltage to the second conductive line. For example, the memory controller 140 may select the memory cell 105 based on the intersection of the first and second voltages. In some cases, the signal applied to the memory cell 105 as part of an access operation may have positive or negative polarity.

[0033] In some instances, the memory controller 140 may receive a command, including instructions, to perform an access operation on the memory cell 105 and identify the address of the memory cell 105 based on the received command. In some cases, applying a second voltage to the second conductive line may be based on the identified address. If the access operation is a read operation, the memory controller 140 may be configured to output a logical state stored in the memory cell 105 based on applying a first voltage to the memory cell 105. If the access operation is a write operation, the memory controller 140 may store a logical state in the memory cell 105 based on applying a first voltage to the memory cell 105.

[0034] Figure 2This document illustrates an example of a memory array 200 that supports the storage of fuse data in a memory device, as disclosed herein. The memory array 200 may be used as a reference. Figure 1 An example of a portion of the described memory array 102. The memory array 200 may include a first memory cell array or stack 205 positioned above a substrate 204 and a second memory cell array or stack 210 on top of the first array or stack 205. The memory array 200 may also include word lines 110-a and 110-b and bit line 115-a, which may be as described in reference... Figure 1 Examples of word line 110 and bit line 115 are described. The memory cells of the first stack 205 and the second stack 210 may each have one or more memory cells (e.g., memory cell 220-a and memory cell 220-b, respectively). Although Figure 2 Some of the elements contained herein are labeled with numerical indicators, while other corresponding elements are not labeled, but are identical or will be interpreted as similar in an attempt to increase the visibility and clarity of the depicted features.

[0035] The memory cells of the first stack 205 may include a first electrode 215-a, a memory cell 220-a (e.g., containing a chalcogenide material), and a second electrode 225-a. Similarly, the memory cells of the second stack 210 may include a first electrode 215-b, a memory cell 220-b (e.g., containing a chalcogenide material), and a second electrode 225-b. In some embodiments, the memory cells of the first stack 205 and the second stack 210 may have a common conductive line, such that corresponding memory cells of each stack 205 and 210 can share a bit line 115 or a word line 110, as referenced. Figure 1 Description. For example, the first electrode 215-b of the second stack 210 and the second electrode 225-a of the first stack 205 may be coupled to bit line 115-a such that bit line 115-a is shared by vertically adjacent memory cells. According to the teachings herein, if the memory array 200 comprises more than one stack, the decoder may be located above or below each stack. For example, the decoder may be located above the first stack 205 and above the second stack 210. In some cases, memory cell 220 may be an instance of a phase-change memory cell or a self-selecting memory cell.

[0036] In some cases, the architecture of memory array 200 may be referred to as a cross-point architecture, where memory cells are formed at the topological cross-points between word lines and bit lines, such as... Figure 2 The explanation is as follows. Compared to other memory architectures, this crossover architecture offers relatively high-density data storage and lower manufacturing costs. For example, compared to other architectures, the crossover architecture can have memory cells with a smaller area and thus increased memory cell density. For example, compared to architectures with 6F... 2Compared to other architectures with different memory cell areas (such as those with three-terminal selection components), this architecture can have 4F. 2 The memory cell area, where F is the minimum feature size. For example, DRAM can use transistors (which are three-terminal devices) as the selected component for each memory cell and can have a larger memory cell area compared to a cross-point architecture.

[0037] Although Figure 2 The example shows two memory cell stacks, but other configurations are possible. In some instances, a single memory stack of memory cells can be built on top of substrate 204, which may be referred to as a two-dimensional memory. In some instances, three or four memory stacks of memory cells can be configured in a similar manner in a three-dimensional cross-point architecture.

[0038] In some instances, one or more of the memory stacks may include memory cells 220 containing chalcogenide materials. Memory cells 220 may, for example, comprise chalcogenide glasses, such as alloys of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some instances, chalcogenide materials primarily containing selenium (Se), arsenic (As), and gallium (Ge) may be referred to as SAG alloys. In some instances, SAG alloys may contain silicon (Si) or indium (In), or combinations thereof, and such chalcogenide materials may be referred to as SiSAG alloys or InSAG alloys, or combinations thereof. In some instances, the chalcogenide glass may contain additional elements in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0039] In some instances, a memory cell 220 containing a chalcogenide material can be programmed into a logical state by applying a first voltage. By way of example, when a particular memory cell 220 is programmed, elements within the cell separate, causing ion migration. Ions may migrate toward a specific electrode depending on the polarity of the voltage applied to the memory cell. For example, in memory cell 220, ions may migrate toward the negative electrode. The cell can then be read by sensing through the application of a voltage across the cell. The threshold voltage observed during the read operation may be based on the ion distribution within the memory cell and the polarity of the read pulse.

[0040] In some cases, a first voltage may be applied to a first conductive line of the decoder as part of an access operation of memory cell 220. After the first voltage is applied, the first conductive line may be coupled to an access line associated with memory cell 220 (e.g., word line 110-a, word line 110-b, or bit line 115-a). For example, the first conductive line may be coupled to the access line based on a doped material of the decoder that extends in a first direction between the first conductive line and the access line.

[0041] In some instances, a first voltage may be applied to memory cell 220 based on the first conductive line of the coupled decoder and the access line. The decoder may comprise one or more doped materials extending in a first direction away from the surface of substrate 204 between the first conductive line and the access line of the memory array 200 of the memory cell. In some cases, the decoder may be coupled to substrate 204.

[0042] Figure 3 This describes an example of a block diagram 300 of a memory device 305 supporting an embodiment for storing fuse data in a memory device, as disclosed herein. The memory device 305 may include a first array 310 for storing fuse data, a second array 315 for storing user data, and a sensing circuit system 320. The first array 310 for storing fuse data, the second array 315 for storing user data, and the sensing circuit system 320 may each be coupled to a memory controller 325 using one or more communication lines 330, 335, and 340, respectively. Additionally, the first array 310 for storing fuse data may be coupled to the sensing circuit system 320 using a communication line 345.

[0043] The first array 310 and the second array 315 can be used as a reference. Figure 1 An example of the described memory device 100. Arrays 310 and 315 may include a plurality of memory cells. The first array 310 for storing fuse data may be configured to store information for operating the memory device. In some cases, the fuse data may include operational information, such as redundancy information (e.g., information indicating defective components within the memory device) and trimming information (e.g., device-specific adjustments to the internal characteristics and operating parameters of the memory device), and other information. In some cases, the first array 310 for storing fuse data may include memory cells containing chalcogenides. Additionally, the first array 310 may occupy a smaller area on the memory device 305 compared to the second array 315 for storing user data.

[0044] In some cases, a memory array (e.g., a first array 310) may be configured within the memory device 305 to store fuse data rather than storing the data in a dedicated fuse array located at the periphery of the memory device 305. Storing fuse data in the first array 310 offers several advantages over other methods, as it stores the fuse data in a fuse or fuse-like structure (e.g., various polysilicon resistors or other metal resistive components) that requires a current of a threshold driving the fuse chain to "blow" the data. For example, instead of irreversibly "blowing" the fuse using relatively large driver components (e.g., MOSFET transistors, bipolar transistors, and the like), the first array 310 may contain memory cells comprising chalcogenide elements that are reprogrammable. Moreover, since the cells of the first array 310 do not need to be blown (programmed), the number and / or size of current drivers present at the memory device 305 can be reduced. Additionally, the first array 310 can utilize less area on the memory device 305 compared to several individual fuses located at the periphery of the array. Furthermore, the first array 310 for storing fuse data can be better integrated with other components located in more central portions of the memory device 305, such as the additional sensing circuitry 320, the memory controller 325, and the second array 315 for storing user data.

[0045] In some cases, the first array 310 for storing fuse data may be located in various locations within the memory device 305. For example, as previously described, the first array 310 for storing fuse data may be a subarray located within a larger portion of the memory device 305 and may be integrated with other components, such as a second array 315 for storing user data. In other instances, the first array 310 may be separate from a larger portion of the memory array (e.g., separate from a portion of the array storing user data). In either or both cases, the first array 310 may store information assigned to the fuse, such as certain binary states represented in the fuse data.

[0046] A second array 315 for storing user data may be configured to store user data, which may include codewords, pages, or other values ​​received from a host device (e.g., a personal computer). The user data may typically include data generated by user logic, which may be stored and retrieved in memory that can otherwise be used for different data types. In some cases, the second array 315 may include memory cells containing chalcogenides. In other cases, the second array 315 may contain other types of memory cells (e.g., ferroelectric cells).

[0047] The sensing circuitry 320 may include other circuitry elements configured to perform the functions of the memory device 305. In some cases, the sensing circuitry 320 may be coupled to a first array 310 for storing fuse data. The sensing circuitry 320 may be configured to receive several signals indicating values ​​of the fuse data stored in the first array 310. The second array 315 may be coupled to the sensing circuitry 320 in some cases, or to a different set of sensing circuitry systems in others.

[0048] In some instances, the first array 310 for storing fuse data may use a single memory cell or a group of memory cells programmable in the same state (e.g., "1" or "0") to store a single value of the fuse data. In such instances, a read operation may involve non-differential (e.g., single-ended) signaling to determine the value of the fuse data stored in the memory cell.

[0049] In one example, the sensing circuitry 320 may employ non-differential (e.g., single-ended) signaling techniques to determine the value of fuse data stored in the first array 310. For instance, the sensing circuitry 320 may receive signals from the first array 310 via communication line 345 and compare the received signals with a given fixed reference potential or reference signal. Based on this comparison, the sensing circuitry 320 may send an output signal indicating the value of the fuse data stored in the first array 310 to the memory controller 325.

[0050] In other instances, the sensing circuitry 320 may employ differential signaling techniques to determine the value of fuse data stored in the first array 310, where two complementary signals can be used to output a signal indicating the value of the fuse data. The output signal may be a single-ended signal or a differential signal. In some cases, the sensing circuitry 320 may extract information by detecting the potential difference between the two complementary signals used in the differential signaling.

[0051] A first array 310 for storing fuse data may include two memory cells or two sets of separate memory cells that can be programmed into opposite or complementary states (e.g., "1" and "0") based on fuse data values. For example, a first state corresponding to a first value of the fuse data is programmed into a first memory cell or a portion of the memory cell, and a complementary state of the first value of the fuse data is programmed into a second memory cell or a portion of the memory cell. In such instances, the first state may correspond to the true value of the fuse data stored using differential techniques, and the second state may correspond to the complementary value of the true value of the fuse data stored using differential techniques. Differential signaling techniques can be used to determine the value of the fuse data stored in the memory cells.

[0052] The sensing circuit system 320 can receive a first signal from a first portion of the memory cells located at the first array 310, and can receive a second signal from a second portion of the memory cells. Since the second portion of the memory cells is programmed in a state opposite to or complementary to that of the first portion, the second signal can similarly be the complement of the first signal (e.g., the second signal can have the same amplitude as the first signal but opposite polarity). In some cases, the first and second signals can be transmitted as a differential signal pair.

[0053] The sensing circuit system 320 can compare a first signal and a second signal, and can output a differential signal indicating the value of fuse data stored in the first array 310 to the memory controller 325. In other words, the sensing circuit system 320 can compare two complementary signals and determine the value of fuse data stored in the first array 310 based on the comparison.

[0054] The differential signaling and storage techniques used can offer several advantages. For example, by using two signals instead of one, differential signaling can be more reliable (e.g., more accurate) than non-differential alternatives. Additionally, differential signaling is more resistant to noise and electromagnetic interference and is better suited for low-power applications and applications where the signal-to-noise ratio is a challenge for signal accuracy.

[0055] The first array 310 for storing fuse data, the second array 315 for storing user data, and the sensing circuit system 320 can output several signals to the memory controller 325. The memory controller 325 may be as described in the reference. Figure 1 An example of the memory controller 140 described. In some cases, the memory controller may be configured to access a second array 315 for storing user data based on fuse data stored in the first array 310.

[0056] Figure 4 This describes an example of a block diagram 400 of a memory device 405 supporting an embodiment for storing fuse data in a memory device, as disclosed herein. The memory device 405 may include a memory cell array 410, which may include a first portion 415 for storing fuse data and a second portion 420 for storing user data. The memory cell array 410 (including the first portion 415 for storing fuse data and the second portion 420 for storing user data) together with the sensing circuitry 430 may be coupled to a memory controller 440 using one or more communication lines 435 and 445, respectively. Additionally, the first portion 415 for storing fuse data may be coupled to the sensing circuitry 430 using communication line 425.

[0057] In some embodiments, array 410 may include memory cells containing chalcogenide storage elements. Therefore, the first portion 415 for storing fuse data and the second portion 420 for storing user data may similarly include chalcogenide storage cells. In such embodiments, a single memory array containing chalcogenide storage elements can store both fuse data and user data. However, in some cases, a portion of array 410 for fuse data (e.g., the first portion 415) may be coupled to a sensing circuitry system different from the sensing circuitry system of the portion of array 410 for user data (e.g., the second portion 420).

[0058] The first portion 415 within the memory array 410 for storing fuse data may be an alternative to a dedicated fuse array at the periphery of the memory array, or an array separate from the larger portion of the memory array containing user data. In some instances, the first portion 415 for storing fuse data may be an array or subarray of memory cells contained within the memory array 410, and may be further integrated with a portion of the array containing user data (e.g., a second portion 420). Similar to the reference... Figure 3 The described configuration allows for a reduction in the number and / or size of current drivers, and the device can be reprogrammed, since there is no need to program (instead of fuse) the memory device corresponding to the first portion 415 for storing fuse data.

[0059] The memory cell array 410, together with the first portion 415 and the second portion 420, can each serve as a reference. Figure 1 An example of the described memory device 100. Array 410 (including portions 415 and 420) may include several memory cells. The first portion 415 for storing fuse data may be configured to store information for operating the memory device, including redundancy information and trimming information. In some cases, the first portion 415 for storing fuse data may occupy a smaller area on the memory device 405 compared to the second portion 420 for storing user data.

[0060] The second portion 420 for storing user data may be configured to store user data, which may include codewords, pages, or other values ​​received from a host device (e.g., a personal computer). User data may typically include data generated by user logic, which may be stored and retrieved in memory that can otherwise be used for different data types.

[0061] The sensing circuitry 430 may include other circuitry elements configured to perform the functions of the memory device 405. In some cases, the sensing circuitry 430 may be coupled to a first portion 415 for storing fuse data. The sensing circuitry 430 may be configured to receive several signals indicating values ​​of the fuse data stored in the first portion 415. In some cases, a set of different sensing circuitry systems may be coupled to a second portion 420 and may be configured to retrieve data stored in the second portion 420.

[0062] In some instances, the first portion 415 for storing fuse data may use a single memory cell or a small group of memory cells programmed to the same state (e.g., "1" or "0") to store a single value of the fuse data. In such instances, a non-differential (e.g., single-ended) signal may be used to determine the value of the fuse data stored in the memory cell.

[0063] In some instances, the sensing circuitry 430 may implement non-differential (e.g., single-ended) storage and signaling techniques to determine the value of fuse data stored in a first portion 415 for storing fuse data. For example, the sensing circuitry 430 may compare a signal received from the first portion 415 via communication line 425 with a given fixed reference potential. The sensing circuitry 430 may send an output signal indicating the value of the fuse data stored in the first portion 415 to the memory controller 440 based on the comparison of the signal received via communication line 425 with the given fixed reference potential.

[0064] In other instances, the sensing circuitry 430 may employ differential storage and signaling techniques to determine the value of the fuse data stored in the first portion 415, where two complementary signals may be used to output a signal indicating the value of the fuse data. The output signal may be a single-ended signal or a differential signal. In some cases, the sensing circuitry 430 may extract information by detecting the potential difference between the two complementary signals used in the differential signal.

[0065] The first portion 415 for storing fuse data may include two memory cells or two sets of separate memory cells that can be programmed into opposite or complementary states (e.g., binary states of "1" and "0") based on the fuse data value. Such an arrangement may be an example of differential memory technology. For example, a first state corresponding to a first value of the fuse data is programmed into a first memory cell or group of memory cells, and a complementary state of the first value of the fuse data is programmed into a second memory cell or group of memory cells. In such an example, the first state may correspond to the true value of the fuse data stored using differential technology, and the second state may correspond to the complementary value of the true value of the fuse data stored using differential technology. Differential signaling techniques can be used to determine the value of the fuse data stored in the memory cells.

[0066] The sensing circuit system 430 can receive a first signal from a first group of memory cells located at a first portion 415 for storing fuse data, and can receive a second signal from a second group of memory cells. Since the second group of memory cells is programmed in a state opposite to or complementary to the first group of memory cells, the second signal can similarly be the complement of the first signal (e.g., the second signal can have the same amplitude as the first signal but opposite polarity). In some cases, the first and second signals can be transmitted as a differential signal pair.

[0067] The sensing circuit system 430 can compare a first signal and a second signal, and can output a differential signal indicating the value of fuse data stored in the first portion 415 to the memory controller 440. In other words, the sensing circuit system 430 can compare two complementary signals and determine the value of fuse data stored in the first portion 415 based on the comparison.

[0068] The memory cell array 410 (containing a first portion 415 for storing fuse data and a second portion 420 for storing user data), together with the sensing circuitry 430, can output various signals to the memory controller 440. The memory controller 440 may be as described in the reference... Figure 1 An example of the memory controller 140 described. In some cases, the memory controller 440 may be configured to access the memory cell array 410 and the second portion 420 for storing user data based on fuse data stored in the first portion 415.

[0069] Figure 5A This section illustrates an example of a block diagram 500-a illustrating a signaling operation supporting an embodiment for storing fuse data in a memory device, as disclosed herein. The memory cell array 505-a may include memory cells 515 that may contain chalcogenide elements. In the example of block diagram 500-a, memory cell 515 is depicted as a single memory cell; however, the techniques described herein can be similarly applied to groups of memory cells.

[0070] In some instances, memory cell 515 can be programmed to a state (e.g., a binary state of "1" or "0") based on a given truth value of the fuse data. In cases where memory cell 515 is programmed to a single state (e.g., without complementary programming of different sets of memory cells), non-differential (e.g., single-ended) sensing techniques can be implemented at the memory device. A read pulse 510 can be applied to memory cell 515, causing memory cell 515 to output a signal 525 in response to the read pulse 510. A reference signal 520 can be output at 530, which in some cases can be a fixed reference signal or a reference potential. Signals 530 and 525 can be further processed using sensing circuitry 535. Sensing circuitry 535 may include a non-differential current-mode sensing amplifier. Sensing circuitry 535 can output a signal 540 indicating the value of the fuse data stored in memory cell 515 based on a comparison of the fuse data value with a given reference potential of reference signal 520.

[0071] In some instances, the reference potential or reference signal 520 may be fixed. Alternatively, the reference signal 520 may be a moving reference, which may be maintained relative to time as separate from the constant voltage of the signal 525 generated at memory cell 515. A non-differential current-mode sense amplifier that can be used in the sensing circuitry system 535 may include a pin designated for the input current (e.g., signal 525) and a separate pin designated for the reference signal 520. The non-differential current-mode sense amplifier may additionally include a pin designated for the output signal 540. Generally, the input signal from memory cell 515 can be compared with the reference signal 520 to generate the output signal 540.

[0072] Figure 5B This section illustrates an example of block diagram 500-b illustrating a signaling operation supporting an embodiment for storing fuse data in a memory device, as disclosed herein. Memory cell array 505-b may include a first memory cell 550 and a second memory cell 560. Both memory cells 550 and 560 may contain chalcogenide elements. In the example of block diagram 500-b, the first memory cell 550 and the second memory cell 560 are depicted as a single memory cell; however, the techniques described herein can be similarly applied to groups of memory cells.

[0073] In some instances, the first memory cell 550 and the second memory cell 560 are programmed to implement differential memory technology. For example, the first memory cell 550 can be programmed to a binary state (e.g., "1" or "0") based on the truth value of the fuse data, and the second memory cell 560 can be programmed to a state opposite to (complementary to) the state stored in the first memory cell 550. In other words, in an instance where the first memory cell 550 stores a "1" state, the second memory cell 560 can store a "0" state, and in other instances where the first memory cell 550 stores a "0" state, the second memory cell 560 can store a "1" state.

[0074] A first state corresponding to a first value of the fuse data is programmed into a first memory unit 550, and a complementary state of the first value of the fuse data is programmed into a second memory unit 560. In such an example, the first state may correspond to the true value of the fuse data stored using differential techniques, and the second state may correspond to the complementary value of the true value of the fuse data stored using differential techniques.

[0075] In some cases, it is stored in memory array 505 (e.g., reference). Figure 5A The memory array 505-a described and referenced Figure 5B The fuse data in the described memory array 505-b) may contain redundancy and trimming information, as well as other information for operating the memory device. This information may indicate defective components, adjustments to operating parameters, etc. In some cases, fuse data may be stored or programmed into the memory array 505 during manufacturing (e.g., prior to implementation at the user device). However, in other cases, additional manufacturing processes may occur after the fuse data is stored. For example, the memory array 505 containing programmed fuse data may be soldered to a package after manufacturing or may otherwise be integrated into a separate device (e.g., a graphics processing unit (GPU) or other computing device). However, in some cases, the additional manufacturing processes may introduce several external stresses onto the memory array 505, which in some cases may destroy the fuse data previously stored in the memory array 505.

[0076] For example, in cases where the memory device or memory array is subjected to external stress or damage after manufacturing, it may be advantageous to use differential techniques (such as the differential techniques described herein) to store and signal fuse data. In one example, the memory array 505-b storing fuse data may be subjected to increased thermal stress due to the high temperatures used in welding, which could destroy the stored data states in the memory array 505-b. However, in cases where differential storage is used, a single value of the fuse data can be stored as two complementary states (e.g., as "0" and "1"). In some cases, a first state may be stored in a first memory cell 550, and a second complementary state may be stored in a second memory cell 560, and the value of the fuse data can be determined by the difference between the two complementary states (rather than by the value of the individual stored states). Thus, destruction can occur proportionally across the stored states, such that the difference between the stored states remains constant even when subjected to high temperatures or other stresses. Compared to single-ended memory techniques that compare individual memory cell values ​​with a reference, differential memory techniques reduce the likelihood that thermal events (such as welding) will introduce errors into the fuse data stored in reprogrammable memory cells.

[0077] In another example, the differential signaling and storage method described herein is less affected by input signal noise compared to the non-differential method. The fuse data value can be stored as two complementary states, and signal noise can affect each state in a similar manner. Therefore, the difference between the two states remains constant, and the output of the fuse data can be determined more reliably. In some cases, the noise from signals 565 and 570 can manifest as a common-mode voltage at sensing circuitry 575.

[0078] In cases where the first memory cell 550 and the second memory cell 560 are programmed to opposite states, differential sensing technology can be implemented to determine the value of the fuse data stored in the memory cells. Read pulses 545 and 555 can be applied to the first memory cell 550 and the second memory cell 560, respectively, causing the memory cells 550 and 560 to output signals 565 and 570 in response to the read pulses. Signal 565 may contain a first state stored in the first memory cell 550, and signal 570 may contain a second state stored in the second memory cell 560. Read pulses 545 and 555 may have the same polarity in some cases and different polarities in others.

[0079] Signals 565 and 570 can be further processed using sensing circuitry 575. In this case, sensing circuitry 575 may include a differential current-mode sensing amplifier. The differential current-mode sensing amplifier may include input pins designated for signals 565 and 570, respectively, from both the first memory cell 550 and the second memory cell 560. In some cases, signals 565 and 570 may be instances of input currents. In some cases, a first state stored in the first memory cell 550 and a second state stored in the second memory cell 560 may be a pair of differential states representing the truth value of fuse data stored in the memory cell array.

[0080] In some cases, the differential current-mode sense amplifier may include a single output or alternatively include two output pins for two output voltages in a differential configuration. The sensing circuitry 575 can compare two complementary signals from the first memory cell 550 and the second memory cell 560 and can determine the value of fuse data stored in the array based on the comparison. For example, the differential current-mode sense amplifier can determine the value of the fuse data by detecting the differential voltage level between signals 565 and 570. In other words, determining whether the fuse data is in a "1" or "0" state is based on the voltage difference between the complementary signals. The sensing circuitry 575 can generate an output signal 580 based on comparing signals 565 and 570 from the first memory cell 550 and the second memory cell 560. In some cases, the output signal 580 may be a differential signal indicating the value of fuse data stored in the memory cell array 505-b. Alternatively, the output signal 580 may be proportional to the difference between signals 565 and 570.

[0081] In some cases, using differential techniques to store and retrieve fuse data can increase the accuracy or reliability of the output signal 580 because differential current-mode sense amplifiers can address signal noise (SNR considerations), low-power signals, or other signal variance. Additionally, differential sensing schemes allow for fast readouts and can be operated with low-power considerations in mind.

[0082] Figure 6 A block diagram 600 illustrates a memory device 605 supporting an implementation of storing fuse data in a memory device, according to examples disclosed herein. The memory device 605 may be as described in the references... Figure 1 Examples of at least a portion of the memory device described in section 5. Memory device 605 may include a signal generator 610, a comparison manager 615, a data manager 620, a device manager 625, a storage component 630, and a status identification component 635. Each of these modules may communicate directly with each other or indirectly (e.g., via one or more buses).

[0083] Signal generator 610 can generate a first signal indicating a first state stored in a first set of memory cells of the memory device and a second signal indicating a second state stored in a second set of memory cells of the memory device, the second state being the complement of the first state. In some embodiments, signal generator 610 can apply a first read pulse having a first polarity to the first set of memory cells, wherein the generation of the first signal is based on applying the first read pulse to the first set of memory cells.

[0084] In some instances, signal generator 610 may apply a second read pulse with a first polarity to a second set of memory cells, wherein the generation of the second signal is based on applying the second read pulse to the second set of memory cells. In some instances, signal generator 610 may apply a first read pulse with a first polarity to a first set of memory cells, wherein the generation of the first signal is based on applying the first read pulse to the first set of memory cells. In some instances, signal generator 610 may apply a second read pulse with a second polarity to a second set of memory cells, wherein the generation of the second signal is based on applying the second read pulse to the second set of memory cells. In some instances, signal generator 610 may output a differential signal indicating the value of fuse data.

[0085] Comparison manager 615 can compare a first signal indicating a first state with a second signal indicating a second state. Data manager 620 can identify the value of fuse data of the memory device based on the comparison of the first signal and the second signal.

[0086] The device manager 625 can operate the memory device based on the value of the fuse data. In some cases, the memory device includes an array of memory cells for storing fuse data and user data, the array of memory cells including chalcogenide elements in the memory cells. In some cases, a first set of memory cells and a second set of memory cells include a portion of a subarray dedicated to storing fuse data for the memory cell array. In some cases, the first set of memory cells includes a single memory cell and the second set of memory cells includes a single memory cell. In some cases, the first signal and the second signal include a pair of differential signals indicating the value of the fuse data.

[0087] Storage component 630 can identify a first state to be stored in a first set of memory cells and a second state to be stored in a second set of memory cells based on the value of the fuse data, the first state and the second state representing the value of the fuse data. In some instances, storage component 630 can store the first state in the first set of memory cells and the second state in the second set of memory cells. In some cases, the first state stored in the first set of memory cells and the second state stored in the second set of memory cells comprise a pair of differential states representing the value of the fuse data.

[0088] The state recognition component 635 can recognize a first state stored in a first set of memory cells, wherein the generation of a first signal is based on recognizing the first state. In some instances, the state recognition component 635 can recognize a second state stored in a second set of memory cells, wherein the generation of a second signal is based on recognizing the second state.

[0089] Figure 7 The illustration shows a flowchart of one or more methods 700 supporting an implementation of reading fuse data from a memory device according to examples disclosed herein. Operation of method 700 can be implemented using a memory device or its components as described herein. For example, operation of method 700 can be achieved through reference to... Figure 6 The described memory device performs the function. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform portions of the described function.

[0090] At 705, the memory device can generate a first signal indicating a first state stored in a first set of memory cells of the memory device and a second signal indicating a second state stored in a second set of memory cells of the memory device, the second state being the complement of the first state. The operation of 705 can be performed according to the method described herein. In some instances, the operation of 705 can be performed as described in reference... Figure 6 The described signal generator is executed.

[0091] In 710, the memory device can compare a first signal indicating a first state with a second signal indicating a second state. The operation of 710 can be performed according to the methods described herein. In some instances, the operation of 710 can be performed as described in reference... Figure 6 The comparison manager described is executed.

[0092] At 715, the memory device can identify the value of the fuse data of the memory device based on a comparison of a first signal and a second signal. The operation of 715 can be performed according to the method described herein. In some instances, the operation of 715 can be performed as described in the reference... Figure 6 The described data manager execution.

[0093] At 720, the memory device can be operated based on the value of the fuse data. The operation of 720 can be performed according to the methods described herein. In some instances, the operation of 720 can be performed as described in the reference... Figure 6 The device manager described is executed.

[0094] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: generating a first signal indicating a first state stored in a first set of memory cells of a memory device and a second signal indicating a second state stored in a second set of memory cells of the memory device, the second state being the complement of the first state; comparing the first signal indicating the first state with the second signal indicating the second state; identifying the value of fuse data of the memory device based on the comparison of the first signal and the second signal; and operating the memory device based on the value of the fuse data.

[0095] In some examples of method 700 and the apparatus described herein, the memory device includes an array of memory cells for storing fuse data and user data, the memory cell array including chalcogenide elements in the memory cells, and a first set of memory cells and a second set of memory cells including portions of a subarray dedicated to storing fuse data of the memory cell array. In some examples of method 700 and the apparatus described herein, a first state stored on the first set of memory cells and a second state stored on the second set of memory cells include a pair of differential states representing values ​​of the fuse data.

[0096] Method 700 and some examples of the devices described herein may further include operations, features, components, or instructions for: identifying a first state to be stored in a first set of memory cells and a second state to be stored in a second set of memory cells based on the value of fuse data, the first state and the second state representing the value of fuse data; and storing the first state in the first set of memory cells and storing the second state in the second set of memory cells.

[0097] Method 700 and some examples of the devices described herein may further include operations, features, components, or instructions for: applying a first read pulse having a first polarity to a first set of memory cells, wherein generating a first signal may be based on applying the first read pulse to the first set of memory cells; and applying a second read pulse having a first polarity to a second set of memory cells, wherein generating a second signal may be based on applying the second read pulse to the second set of memory cells.

[0098] Method 700 and some examples of the devices described herein may further include operations, features, components, or instructions for: applying a first read pulse having a first polarity to a first set of memory cells, wherein generating a first signal may be based on applying the first read pulse to the first set of memory cells; and applying a second read pulse having a second polarity to a second set of memory cells, wherein generating a second signal may be based on applying the second read pulse to the second set of memory cells.

[0099] Method 700 and some examples of the apparatus described herein may further include operations, features, components, or instructions for outputting a differential signal indicating a value of fuse data. Method 700 and some examples of the apparatus described herein may further include operations, features, components, or instructions for: identifying a first state stored in a first set of memory cells, wherein generating a first signal may be based on identifying the first state; and identifying a second state stored in a second set of memory cells, wherein generating a second signal may be based on identifying the second state.

[0100] In some instances of method 700 and the apparatus described herein, the first set of memory cells comprises a single memory cell and the second set of memory cells comprises a single memory cell. In some instances of method 700 and the apparatus described herein, the first signal and the second signal comprise a pair of differential signals indicating the value of fuse data.

[0101] It should be noted that the methods described above describe possible implementation schemes, and the operations and steps can be rearranged or modified in other ways, and other implementation schemes are possible.

[0102] Describe an apparatus. The apparatus may include a memory cell array comprising: a first memory cell portion for storing fuse data; a second memory cell portion for storing user data, wherein each memory cell in the first portion and each memory cell in the second portion comprises a chalcogenide element; a sensing circuitry system coupled to the first memory cell portion and configured to identify values ​​of the fuse data stored in the first memory cell portion; and a controller coupled to the memory cell array and the sensing circuitry system and configured to access the memory cell array based on the fuse data stored in the first memory cell portion.

[0103] In some instances, the sensing circuitry may be configured to receive a differential signal from the first memory cell portion indicating a value of fuse data stored in the first memory cell portion, the differential signal comprising a first signal from a first group of signals from the first memory cell portion and a second signal from a second group of signals from the first memory cell portion. Some instances may further include: comparing the first signal with the second signal to identify the value of the fuse data; and outputting a second differential signal indicating the value of the fuse data based on the comparison. In some instances, the value of the fuse data may be stored in at least two memory cells comprising a first memory cell storing a first state associated with the value and a second memory cell storing a second state associated with the value.

[0104] In some instances, the first state and the second state comprise a pair of differential states representing the value of the fuse data. In some instances, the sensing circuitry may be configured to receive a signal indicating the value of the fuse data from the first memory cell portion and compare the signal with a reference signal to identify the value of the fuse data. Some instances of the device may include a fuse array for storing the fuse data. Some instances may further include at least a portion of the fuse data that can be stored on both the fuse array and the first memory cell portion of the memory cell array.

[0105] In some instances, the value of the fuse data may be stored in a single memory cell of the first memory cell portion. In some instances, the first memory cell portion used to store the fuse data may be reprogrammable. In some instances, the controller may be configured to prevent unauthorized access to the first memory cell portion. In some instances, the fuse data includes information used by the memory device to operate the memory device, and the user data includes information received from the host device and that may be stored on the memory device.

[0106] Describe an apparatus. The apparatus may include: a first memory cell array of a first type configured to store user data; a second memory cell array of a second type, the second array including chalcogenide elements and configured to store fuse data associated with operating the first memory cell array; a sensing circuit system coupled to the second memory cell array and configured to have operations, features, components, or instructions for identifying values ​​of the fuse data stored in the second array; and a controller coupled to the first array, the second array, and the sensing circuit system and configured to access the memory cells of the first array based on the values ​​of the fuse data stored in the second array identified by the sensing circuit system.

[0107] In some instances, the sensing circuitry system may be configured to have operations, features, components, or instructions for receiving differential signals from the second array that include a first signal from a first set of memory cells and a second signal from a second set of memory cells, the differential signals indicating the value of the fuse data stored in the second array.

[0108] In some instances, the value of the fuse data may be stored in at least two memory cells of the second array, which includes a first memory cell storing a first state and a second memory cell storing a second state.

[0109] Another device is described. The device may include a memory cell array comprising: a first memory cell portion for storing fuse data; a second memory cell portion for storing user data, wherein each memory cell in the first portion and each memory cell in the second portion comprises a chalcogenide element; a sensing circuit system coupled to the first memory cell portion and configured with operations, features, components, or instructions for identifying values ​​of the fuse data stored in the first memory cell portion; and a controller coupled to the memory cell array and the sensing circuit system and configured with operations, features, components, or instructions for accessing the memory cell array at least in part based on the fuse data stored in the first memory cell portion.

[0110] In some instances, the sensing circuitry system may be configured to have operations, features, components, or instructions for receiving differential signals from the first memory cell portion indicating the value of the fuse data stored in the first memory cell portion, the differential signals including a first signal from a first group of the first memory cell portion and a second signal from a second group of the first memory cell portion.

[0111] In some instances, the sensing circuitry system may be configured with operations, features, components, or instructions for comparing the first signal and the second signal to identify the value of the fuse data, and operations, features, components, or instructions for outputting a second differential signal indicating the value of the fuse data, at least in part based on the comparison. In some instances, the value of the fuse data is stored in at least two memory units comprising a first memory unit storing a first state associated with the value and a second memory unit storing a second state associated with the value. In some instances, the first state and the second state comprise a pair of differential states representing the value of the fuse data.

[0112] In some instances, the sensing circuitry is configured to receive a signal indicating the value of the fuse data from the first memory cell portion and compare the signal with a reference signal to identify the value of the fuse data. In some instances, the device may include a fuse array for storing the fuse data. In some instances, at least a portion of the fuse data is stored on both the fuse array and the first memory cell portion of the memory cell array. In some instances, the value of the fuse data is stored in a single memory cell of the first memory cell portion. In some instances, the first memory cell portion for storing the fuse data is reprogrammable.

[0113] In some instances, the controller is configured to have operations, features, components, or instructions for preventing unauthorized access to the first memory cell portion. In some instances, the fuse data includes information used by the memory device to operate the memory device, and the user data includes information received from the host device and stored on the memory device.

[0114] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, where the bus can have various bit widths.

[0115] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at approximately zero volts (0V) but is not directly coupled to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0V in a steady state. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "via virtual ground" means connected to approximately 0V.

[0116] The terms "electronic communication," "conductive contact," "connected," and "coupled" refer to a relationship between components that supports signal flow between them. Components are considered to be in electronic communication (or electrically connected, connected, or coupled) with each other if any conductive path exists between them to support signal flow at any given time. At any given time, the conductive path between components that are in electronic communication (or electrically connected, connected, or coupled) may be open or closed depending on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some cases, signal flow between connected components may be interrupted for a period of time by one or more intermediate components (e.g., switches or transistors).

[0117] The term "coupling" refers to the condition of moving from an open-circuit relationship between components (where signals cannot currently travel between components via a conductive path) to a closed-circuit relationship between components (where signals can travel between components via a conductive path). When a component (e.g., a controller) is coupled to other components, the component initiates changes to allow signals to flow between the other components via conductive paths that were previously not permitted.

[0118] The term "isolated" refers to a relationship between components where signals are currently unable to flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, it modifies the circuit, preventing signals from flowing between the components using a previously permitted conductive path.

[0119] As used herein, the term "electrode" can refer to a conductor and, in some cases, to an electrical contact to a memory cell or other component of a memory array. An electrode may comprise a trace, wire, conductive line, conductive layer, or the like that providing a conductive path between elements or components of the memory array.

[0120] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOS)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0121] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0122] The descriptions presented herein, in conjunction with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that can be implemented or are within the scope of the claims. The term "example" as used herein means "serving as an example, illustration, or diagram" and is not "preferred" or "superior to other examples." Detailed descriptions include specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and arrangements are shown in block diagram form to avoid obscuring the concept of the described examples.

[0123] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar components. When only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, without regard to the second reference label.

[0124] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips described above can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0125] The various illustrative blocks and modules described herein can be implemented or executed using a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0126] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or program codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations. Moreover, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates a list of inclusions, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, without departing from the scope of this disclosure, an instance step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0127] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, but not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The combination above also includes computer-readable media.

[0128] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory cell array, comprising: The first memory unit section is used to store fuse data; The second memory unit portion is used to store user data, and each of the memory units in the first portion and the second portion includes a chalcogenide element. A sensing circuit system coupled to and configured to identify the value of fuse data stored in the first memory cell portion; and A controller, coupled to the memory cell array and the sensing circuitry, and configured to access the memory cell array based at least in part on the fuse data stored in the first memory cell portion. The value of the fuse data is stored in at least two memory units, including a first memory unit storing a first state associated with the value and a second memory unit storing a second state associated with the value, wherein the second state is different from the first state and is the complement of the first state.

2. The device of claim 1, wherein the sensing circuitry is configured to receive a differential signal from the first memory cell portion indicating a value of the fuse data stored in the first memory cell portion, the differential signal comprising a first signal from a first group of the first memory cell portion and a second signal from a second group of the first memory cell portion.

3. The device of claim 2, wherein the sensing circuitry is configured to: Compare the first signal with the second signal to identify the value of the fuse data; and A second differential signal indicating the value of the fuse data is output, at least in part based on the comparison.

4. The device of claim 1, wherein the first state and the second state include a pair of differential states representing the value of the fuse data.

5. The device of claim 1, wherein the sensing circuitry is configured to: receive from the first memory cell portion a signal indicating the value of the fuse data; and compare the signal with a reference signal to identify the value of the fuse data.

6. The device according to claim 1, further comprising: A fuse array for storing the fuse data.

7. The device of claim 6, wherein at least a portion of the fuse data is stored on both the fuse array and the first memory cell portion of the memory cell array.

8. The device of claim 1, wherein the value of the fuse data is stored in a single memory cell of the first memory cell portion.

9. The apparatus of claim 1, wherein the first memory cell portion for storing the fuse data is reprogrammable.

10. The device of claim 1, wherein the controller is configured to prevent unauthorized access to the first memory cell portion.

11. The device according to claim 1, wherein: The fuse data includes information used by the memory device to operate the memory device; and The user data includes information received from the host device and stored on the memory device.

12. A method comprising: A first signal is generated indicating a first state stored in a first set of memory cells of the memory device, and a second signal is generated indicating a second state stored in a second set of memory cells of the memory device, wherein the second state is different from the first state and is the complement of the first state. Compare the first signal indicating the first state with the second signal indicating the second state; The value of the fuse data of the memory device is identified at least in part based on the comparison of the first signal and the second signal; and The memory device is operated based at least in part on the value of the fuse data.

13. The method according to claim 12, wherein: The memory device includes an array of memory cells for storing the fuse data and user data, the memory cell array including a chalcogenide element in each memory cell; and The first group of memory cells and the second group of memory cells include a portion of a subarray dedicated to storing the fuse data of the memory cell array.

14. The method of claim 12, wherein the first state stored on the first set of memory cells and the second state stored on the second set of memory cells comprise a pair of differential states representing the value of the fuse data.

15. The method of claim 12, further comprising: The first state to be stored in the first set of memory cells and the second state to be stored in the second set of memory cells are identified at least in part based on the value of the fuse data, wherein the first state and the second state represent the value of the fuse data; and The first state is stored in the first set of memory units and the second state is stored in the second set of memory units.

16. The method of claim 12, further comprising: A first read pulse having a first polarity is applied to the first group of memory cells, wherein the generation of the first signal is at least partially based on applying the first read pulse to the first group of memory cells; and A second read pulse having the first polarity is applied to the second set of memory cells, wherein the generation of the second signal is at least in part based on applying the second read pulse to the second set of memory cells.

17. The method of claim 12, further comprising: A first read pulse having a first polarity is applied to the first group of memory cells, wherein the generation of the first signal is at least partially based on applying the first read pulse to the first group of memory cells; and A second read pulse having a second polarity is applied to the second set of memory cells, wherein the generation of the second signal is at least in part based on applying the second read pulse to the second set of memory cells.

18. The method of claim 12, further comprising: Output a differential signal indicating the value of the fuse data.

19. The method of claim 12, further comprising: The first state stored in the first set of memory cells is identified, wherein the generation of the first signal is at least partially based on the identification of the first state; and The second state stored in the second set of memory cells is identified, wherein the generation of the second signal is at least partially based on the identification of the second state.

20. The method of claim 12, wherein the first group of memory cells comprises a single memory cell and the second group of memory cells comprises a single memory cell.

21. The method of claim 12, wherein the first signal and the second signal comprise a pair of differential signals indicating the value of the fuse data.

22. An apparatus comprising: A first type of first memory cell array, configured to store user data; The second type of second memory cell array includes a chalcogenide element and is configured to store fuse data associated with operating the first memory cell array; A sensing circuit system coupled to the second memory cell array and configured to identify the value of the fuse data stored in the second array; and A controller coupled to the first array, the second array, and the sensing circuitry system and configured to access memory cells of the first array based at least in part on the sensing circuitry system identifying the value of the fuse data stored in the second array, wherein the value of the fuse data is stored in at least two memory cells of the second memory cell array comprising a first memory cell storing a first state and a second memory cell storing a second state, the second state being different from the first state and being the complement of the first state.

23. The device of claim 22, wherein the sensing circuitry is configured to receive a differential signal from the second array comprising a first signal from a first set of memory cells and a second signal from a second set of memory cells, the differential signal indicating the value of the fuse data stored in the second array.

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