Word line protection method in the back process of a vertical dynamic random access memory (DRAM) device

Abstract

A semiconductor memory device comprises trench insulations arranged in the bit line direction, gate structures arranged in the word line direction perpendicular to the bit line direction, and an array of vertical transistor channels arranged in a vertical direction perpendicular to the bit line direction and the word line direction, separated by the trench insulations and gate structures—the upper end of the array of vertical transistor channels in each column is connected to a semiconductor structure line extending in the bit line direction from the rear of the semiconductor memory device—and air gap tunnels along the word line direction—each air gap tunnel crosses below the semiconductor structure line in a first region on the rear of the semiconductor memory device and is located between two adjacent vertical transistor channels.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device and a manufacturing process thereof. The semiconductor device may be a vertical gate dynamic random access memory (DRAM) device. Background Technology

[0002] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches a lower limit, planar process and manufacturing technologies become difficult and expensive. Consequently, memory density for planar memory cells approaches an upper limit. To overcome the density limitations in planar memory cells by using vertical gate transistors, a three-dimensional (3D) memory architecture can be utilized.

[0003] An aspect of the present disclosure provides a method for manufacturing a semiconductor memory device. The method comprises the steps of: thinning a semiconductor memory device from the rear of a semiconductor device having, at the present stage, trench insulations formed in the bit line direction, gate structures formed in the word line direction perpendicular to the bit line direction, and an array of vertical transistor channel structures extending in a vertical direction perpendicular to the bit line direction and the word line direction and separated by the trench insulations and gate structures; after thinning, the trench insulations are exposed on the rear of the semiconductor device, and the upper ends of the vertical transistor channel structures in each column along the bit line direction are connected to a semiconductor structure line extending along the bit line direction on the rear of the semiconductor memory device to form a bridge-shaped structure, and the trench insulations separate adjacent bridge-shaped structures; and, in a first region on the rear of the semiconductor memory device, recessing the trench insulations between adjacent bridge-shaped structures to expose the gate structures formed in the word line direction; and etching the gate structures formed in the word line direction to form tunnels along each gate structure; the tunnels traverse under each semiconductor structure line; and, the trench insulations and gate structures The method may include the steps of filling the etched-away space with a sacrificial material, covering a portion of a first region on the back of a semiconductor memory device with an insulating layer—wherein the insulating layer surrounds the sacrificial material between each neighboring bridge-shaped structure under the insulating layer in the covered portion of the first region—and removing the sacrificial material within the space where trench insulating parts and gate structures have been etched away while the portion of the first region is covered with an insulating layer—wherein the sacrificial material surrounded by the insulating layer is removed through a tunnel running under each semiconductor structure line.

[0004] In one embodiment, the insulating layer covers a second region adjacent to a portion of the first region covered by the insulating layer, and the trench insulating portions of the second region are retained while the trench insulating portions of the first region are etched.

[0005] In one embodiment, the semiconductor memory device has metal shields formed between every two adjacent channel structures along the word line direction.

[0006] In one embodiment, the method further comprises the steps of: etching metal shields formed in the direction of word lines to form tunnels along each metal shield that run across each semiconductor structure line; filling the space from which trench insulation and metal shields have been etched away with a sacrificial material; and removing the sacrificial material within the space from which trench insulation and metal shields have been etched away while a portion of the first region is covered with an insulating layer, wherein the sacrificial material surrounded by the insulating layer is removed through tunnels along each metal shield that run across each semiconductor structure line.

[0007] In one embodiment, the method further includes the step of covering the surfaces of the space from which the trench insulation and gate structures have been etched out with a spacer layer before filling the space from which the trench insulation and gate structures have been etched out with a sacrificial material.

[0008] In one embodiment, the method further includes the step of forming bit line structures on semiconductor structure lines not covered by the insulating layer in the first region while a portion of the first region is covered by the insulating layer.

[0009] An embodiment of the present disclosure provides a semiconductor memory device. The semiconductor memory device comprises trench insulations arranged in a bit line direction, gate structures arranged in a word line direction perpendicular to the bit line direction, and an array of vertical transistor channels arranged in a vertical direction perpendicular to the bit line direction and the word line direction and separated by the trench insulations and gate structures—the upper ends of the array of vertical transistor channels in each column are connected to a line of semiconductor structures extending in the bit line direction from the rear surface of the semiconductor memory device—and air gap tunnels along the word line direction—each air gap tunnel is located in a first region on the rear surface of the semiconductor memory device, crossing below the line of semiconductor structures and between two adjacent vertical transistor channels.

[0010] An embodiment of the present disclosure provides a memory system comprising a memory controller and a semiconductor memory device coupled to the memory controller. The semiconductor memory device comprises trench insulators arranged in a bit line direction, gate structures arranged in a word line direction perpendicular to the bit line direction, and an array of vertical transistor channels arranged in a vertical direction perpendicular to the bit line direction and the word line direction and separated by the trench insulators and gate structures—the upper ends of the array of vertical transistor channels in each column are connected to a semiconductor structure line extending in the bit line direction from the rear surface of the semiconductor memory device—and air gap tunnels along the word line direction—each air gap tunnel is located between two adjacent vertical transistor channels in a first region on the rear surface of the semiconductor memory device, crossing below the semiconductor structure line. Brief explanation of the drawing

[0011] Aspects of the present disclosure can be understood from the following detailed description when read together with the accompanying drawings. Note that, in accordance with standard industry practice, various features are not depicted to scale. In fact, the dimensions of various features may be increased or decreased for clarity of discussion. FIG. 1 illustrates a block diagram of an exemplary system having a memory device according to some aspects of the present disclosure. FIG. 2 illustrates a schematic diagram of a memory device comprising peripheral circuits and an array of memory cells (each memory cell having a vertical transistor) according to some aspects of the present disclosure. FIG. 3 illustrates a schematic circuit diagram of a memory device comprising peripheral circuitry and an array of dynamic random-access memory (DRAM) cells, according to some aspects of the present disclosure. FIG. 4 illustrates a schematic circuit diagram of a memory device comprising peripheral circuits and an array of phase-change memory (PCM) cells according to some aspects of the present disclosure. FIGS. 5A and 5B illustrate the manufacturing results of the overlap between the trench recess region and the insulating layer for forming a bit line on the back of a semiconductor device. FIGS. 6a and 6b illustrate the fabrication results of a trench recess region and an insulating layer for forming a bit line on the back of a semiconductor device. FIGS. 7aa and 7ab / FIGS. 7ba and 7bb / FIGS. 7ca and 7cb / FIGS. 7da to 7de / FIGS. 7e / FIGS. 7fa to 7fe / FIGS. 7ga to 7gg / FIGS. 7ha to 7hg / FIGS. 7ia to 7ig / FIGS. 7ja to 7jg / FIGS. 7ka to 7kg illustrate a manufacturing process for forming a memory device according to some aspects of the present disclosure. FIG. 8 illustrates a flowchart of a manufacturing process (800) for forming a semiconductor memory device according to an embodiment of the present disclosure. Specific details for implementing the invention

[0012] While specific configurations and arrangements are discussed, it should be understood that this is done merely for illustrative purposes. Accordingly, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be used in various other applications. The functional and structural features described in this disclosure may be combined, adjusted, and modified in ways not specifically illustrated in the drawings, and such combinations, adjustments, and modifications are within the scope of this disclosure.

[0013] Generally, terms may be understood at least in part from their usage in context. For example, the term “one or more” as used herein may, at least in part depending on the context, be used to describe any feature, structure, or characteristic in a singular sense or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may also be understood to convey a singular usage or a plural usage, at least in part depending on the context. Furthermore, the term “based on” is not intended to convey an exclusive set of factors; instead, it may be understood, also at least in part depending on the context, to allow for the existence of additional factors not explicitly described.

[0014] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted in the broadest possible way, such that “on” means not only “directly on” something but also includes the meaning of “on” something with an intermediate feature or layer between them, and “above” or “over” means not only “on” or “over” something but also the meaning of “on” or “over” something without an intermediate feature or layer between them (being directly on something).

[0015] Additionally, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used in this specification to describe the relationship between one element or feature and another element(s) or feature(s) as illustrated in the drawings for ease of explanation. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientations illustrated in the drawings. The device may be oriented differently (it may be rotated 90 degrees or in a different direction), and spatially relative descriptors used in this specification may likewise be interpreted accordingly.

[0016] As used herein, the term “substrate” refers to a material upon which subsequent layers of material are added. The substrate itself may be patterned. The materials added to the top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of electrically nonconductive materials such as glass, plastic, or sapphire wafers.

[0017] As used herein, the term “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Additionally, a layer may be a region having a thickness smaller than that of a homogeneous or heterogeneous continuous structure. For example, a layer may be located between any pair of horizontal planes that are on or between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, may contain one or more layers within it and / or have one or more layers on, above, and / or below the substrate. A layer may comprise a plurality of layers. For example, an interconnect layer may comprise one or more conductors and contact layers (where interconnect lines and / or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

[0018] I. Memory device having a vertical transistor

[0019] Transistors are used as switch or select devices in memory cells of some memory devices, such as dynamic random access memory (DRAM), phase-change memory (PCM), and ferroelectric DRAM (FRAM). However, planar transistors commonly used in conventional memory cells usually have a horizontal structure with word lines embedded within the substrate and bit lines above the substrate. Since the source and drain of a planar transistor are positioned laterally at different locations, this increases the area occupied by the transistor. The design of planar transistors also complicates the arrangement of interconnection structures, such as word lines and bit lines coupled to the memory cell, which, for example, limits the pitch of word lines and / or bit lines, thereby increasing manufacturing complexity and reducing production yield. Furthermore, because bit lines and storage units (e.g., capacitors or PCM elements) are arranged on the same side of the planar transistor (above the transistor and the substrate), the bit line process margin is limited by the storage units, and the coupled capacitance between the bit lines and storage units (e.g., capacitors) increases. Planar transistors can also experience difficulties due to high leakage current as the saturation drain current continues to increase, which is undesirable for the performance of memory devices.

[0020] Meanwhile, the memory cell array and the peripheral circuitry for controlling the memory cell array are usually arranged side by side on the same plane. As the number of memory cells continues to increase, in order to maintain the same chip size, the dimensions of components within the memory cell array, such as transistors, word lines, and / or bit lines, need to be continuously reduced so as not to significantly reduce the efficiency of the memory cell array.

[0021] To solve one or more of the aforementioned problems, vertical transistors can replace planar transistors as switch and select devices in memory cell arrays of memory devices (e.g., DRAM, PCM, and FRAM). Compared to planar transistors, vertically arranged transistors (e.g., drain and source overlap in the plan view) can reduce the area of ​​the transistors and also simplify the layout of interconnect structures, such as metal wiring for word lines and bit lines, thereby reducing manufacturing complexity and improving yield. For example, the pitch of word lines and / or bit lines can be reduced for ease of manufacturing. The vertical structure of the transistors also allows the bit lines and storage units (e.g., capacitors) to be arranged on opposite sides of the transistors in a vertical direction (e.g., one above and one below the transistor), which can increase the process margin of the bit lines and reduce the coupling capacitance between the bit lines and storage units.

[0022] In addition, memory cell arrays with vertical transistors and the peripheral circuits of the memory cell array can be formed on different wafers and bonded together face-to-face. Therefore, the thermal budget for manufacturing the memory cell array does not affect the manufacturing of the peripheral circuits. Stacked memory cell arrays and peripheral circuits can also improve array efficiency by reducing chip size compared to parallel arrangements. In some implementations, two or more memory cell arrays are stacked on top of each other using bonding technology to further increase array efficiency. In some implementations, due to the vertically arranged transistors, word lines and bit lines are positioned close to the bonding interface, which can be bonded to the peripheral circuits through a large number (e.g., millions) of parallel bonding contacts across the bonding interface. This creates a direct, short-distance (e.g., micron-level) electrical connection between the memory cell array and the peripheral circuits, which can increase the throughput and input / output (I / O) speed of the memory device.

[0023] In some implementations, the vertical transistor disclosed herein includes a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a triple-gate transistor, or a double-gate transistor) that may have a larger gate control region to achieve better channel control with a smaller subthreshold swing. Because the channel is completely depleted, the leakage current of the multi-gate transistor can also be significantly reduced. Therefore, using a multi-gate transistor instead of a planar transistor can achieve much better speed (saturation drain current) / leakage current performance.

[0024] In some embodiments, the vertical transistors disclosed herein include single-gate transistors (also referred to as single-side gate transistors) that form a mirror-symmetric arrangement with respect to adjacent transistors in the bit line direction, as a result of dividing multi-gate transistors (e.g., double-gate transistors) using trench insulations extending along the word line direction. Accordingly, memory cell density in the bit line direction can be significantly (e.g., doubled) increased without overcomplicated manufacturing processes compared to using processes such as self-aligned double patterning (SADP). Additionally, mirror-symmetric single-gate transistors have a wider process window for word line, bit line, and transistor pitch reduction compared to either planar transistors or multi-gate vertical transistors (e.g., having double-sided or all-around gates).

[0025] FIG. 1 illustrates a block diagram of a system (100) having a memory device according to some aspects of the present disclosure. The system (100) may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having internal storage. As illustrated in FIG. 1, the system (100) may include a host (108) and a memory system (102) having one or more memory devices (104) and a memory controller (106). The host (108) may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host (108) may be configured to transmit data to or receive from the memory device (104).

[0026] The memory device (104) may be any memory device disclosed herein. In some implementations, the memory device (104) comprises an array of memory cells each comprising a vertical transistor as described herein.

[0027] A memory controller (106) is coupled to a memory device (104) and a host (108) and, depending on some implementation, is configured to control the memory device (104). The memory controller (106) can manage data stored in the memory device (104) and communicate with the host (108). The memory controller (106) may be configured to control operations of the memory device (104), such as read, write, and refresh operations. The memory controller (106) may also be configured to manage various functions regarding data stored or to be stored in the memory device (104), including but not limited to refresh and timing control, command / request conversion, buffer and scheduling, and power management. In some implementations, the memory controller (106) is further configured to determine the maximum memory capacity available to the computer system, the number of memory banks, memory type and speed, memory particle data depth and data width, and other important parameters.

[0028] Any other suitable function may also be performed by the memory controller (106). The memory controller (106) may communicate with an external device (e.g., a host (108)) according to a specific communication protocol. For example, the memory controller (106) may communicate with an external device through at least one of various interface protocols such as the USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial-ATA protocol, parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0029] FIG. 2 illustrates a schematic diagram of a memory device (200) comprising peripheral circuitry and an array of memory cells (each memory cell having a vertical transistor) according to some aspects of the present disclosure. The memory device (200) may include a memory cell array (201) and peripheral circuitry (202) coupled to the memory cell array (201). The memory cell array (201) may be any suitable memory cell array in which each memory cell (208) comprises a vertical transistor (210) and a storage unit (212) coupled to the vertical transistor (210). In some embodiments, the memory cell array (201) is a DRAM cell array, and the storage unit (212) is a capacitor for storing charge as binary information stored by each DRAM cell. In some embodiments, the memory cell array (201) is a PCM cell array, and the storage unit (212) is a PCM element (e.g., including a chalcogenide alloy) for storing binary information of each PCM cell based on the different resistivity of the PCM element in the amorphous phase and the crystalline phase. In some embodiments, the memory cell array (201) is an FRAM cell array, and the storage unit (212) is a ferroelectric capacitor for storing binary information of each FRAM cell based on switching between two polarization states of the ferroelectric material under an external electric field.

[0030] As illustrated in FIG. 2, memory cells (208) may be arranged in a two-dimensional (2D) array having rows and columns. The memory device (200) may include a word line (204) that combines a peripheral circuit (202) and a memory cell array (201) to control the switch of a vertical transistor (210) within a memory cell (208) located in a row, as well as a bit line (206) that combines a peripheral circuit (202) and a memory cell array (201) to transmit data to and / or receive data from a memory cell (208) located in a column. That is, each word line (204) is combined to each row of memory cells (208), and each bit line is combined to each column of memory cells (208).

[0031] To reduce the area occupied by the pass transistor, coupling capacitance, and interconnect routing complexity, a vertical transistor (210), such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET), can replace a planar transistor as the pass transistor of the memory cell (208). As shown in FIG. 2, in some embodiments, unlike a planar transistor in which the active region is formed within the substrate, the vertical transistor (210) includes a semiconductor body (214) that extends vertically (in the z-direction) over a substrate (not shown). That is, the semiconductor body (214) can extend over the top surface of the substrate so that a channel can be formed not only on the top surface of the semiconductor body (214) but also on one or more side surfaces thereof.

[0032] As illustrated in FIG. 2, for example, the semiconductor body (214) may have a rectangular shape to expose its four sides. It is understood that the semiconductor body (214) may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body (214) in the plan view (e.g., in the xy plane) may have a square shape, a rectangular shape (or trapezoidal shape), a circular shape (or elliptical shape), or any other suitable shape. In the case of a semiconductor body in which the cross-section in the plan view has a circular or elliptical shape, it is understood that the semiconductor body may still be considered to have multiple sides so that the gate structure contacts two or more sides of the semiconductor body. As described below regarding the manufacturing process, in some cases, the semiconductor body (214) may be formed from a substrate (e.g., by etching or epitaxy) and thus has the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., silicon substrate).

[0033] As illustrated in the example of FIG. 2, the vertical transistor (210) may also include a gate structure (216) in contact with one or more sides of the semiconductor body (214), for example, one or more planes of the side surface(s) of the active region. In other words, the active region of the vertical transistor (210), for example, the semiconductor body (214), may be at least partially surrounded by the gate structure (216). The gate structure (216) may include a gate dielectric (218) on one or more sides of the semiconductor body (214) in contact with four side surfaces of the semiconductor body (214), for example, as illustrated in FIG. 2. The gate structure (216) may also include a gate electrode (220) in contact with the gate dielectric (218). The gate dielectric (218) may include any suitable dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric (218) may comprise silicon oxide, which is a form of gate oxide. The gate electrode (220) may comprise any suitable conductive material such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode (220) may comprise doped polysilicon, which is a form of gate poly. In some embodiments, the gate electrode (220) comprises a plurality of conductive layers, such as a W layer on top of a TiN layer. In some embodiments, it is understood that the gate electrode (220) and the word line (204) may be a continuous conductive structure. In other words, the gate electrode (220) can be considered as part of the word line (204) forming the gate structure (216), or the word line (204) can be considered as an extension of the gate electrode (220) to be coupled to the peripheral circuit (202).

[0034] As illustrated in FIG. 2, the vertical transistor (210) may further include a pair of source and drain (also referred to as S / D, dope region, source electrode and drain electrode) formed at each of the two ends of the semiconductor body (214) in the vertical direction (z-direction). The source and drain may be doped with any suitable P-type dopant, such as boron (B) or gallium (Ga), or any suitable N-type dopant, such as phosphorus (P) or arsenic (As). The source and drain may be separated in the vertical direction (z-direction) by a gate structure (216). That is, the gate structure (216) is formed vertically between the source and drain. Consequently, when the gate voltage applied to the gate electrode (220) of the gate structure (216) is higher than the threshold voltage of the vertical transistor (210), one or more channels (not shown) of the vertical transistor (210) may be formed vertically between the source and drain within the semiconductor body (214). That is, according to some implementations, each channel of a vertical transistor (210) is also formed in a vertical direction in which the semiconductor body (214) extends.

[0035] In some implementations, as illustrated in FIG. 2, the vertical transistor (210) is a multi-gate transistor. That is, the gate structure (216) may come into contact with two or more sides of the semiconductor body (214) (e.g., four sides in FIG. 2) to form two or more gates, thereby allowing two or more channels to be formed between the source and the drain during operation. That is, unlike a planar transistor that includes only a single planar gate (and thus forms a single planar channel), the vertical transistor (210) illustrated in FIG. 2 may include multiple vertical gates on multiple sides of the semiconductor body (214) due to the 3D structure of the gate structure (216) surrounding the semiconductor body (214) and multiple sides of the semiconductor body (214). Consequently, compared to a planar transistor, the vertical transistor (210) illustrated in FIG. 2 can achieve better channel control with a smaller subthreshold swing by having a larger gate control area. Because the channel is completely depleted, the leakage current (Ioff) of the vertical transistor (210) can also be significantly reduced. In various examples, the multi-gate vertical transistor may include a double-gate vertical transistor (e.g., a two-sided gate vertical transistor), a triple-gate vertical transistor (e.g., a three-sided gate vertical transistor), and a GAA vertical transistor.

[0036] In FIG. 2, the vertical transistor (210) is depicted as a multi-gate transistor, but it is understood that the vertical transistor disclosed herein may also include a single-gate transistor. That is, the gate structure (216) may, for example, be in contact with a single side of the semiconductor body (214) for the purpose of increasing transistor and memory cell density. Also, although the gate dielectric (218) is depicted as being separated from other gate dielectrics of adjacent vertical transistors (not shown) (separated structure), it is understood that the gate dielectric (218) may be part of a continuous dielectric layer having multiple gate dielectrics of vertical transistors.

[0037] In planar transistors and some transverse multi-gate transistors (e.g., FinFETs), an active region, such as a semiconductor body (e.g., a fin), extends transversely (in the xy plane), and the source and drain are positioned at different locations within the same transverse plane (xy plane). In contrast, in a vertical transistor (210), the semiconductor body (214) extends vertically (in the z-direction), and the source and drain are positioned in different transverse planes depending on some implementation. In some implementations, the source and drain are formed at two ends of the semiconductor body (214) in the vertical direction (z-direction), respectively, and thus overlap in the planar view. Consequently, the area occupied (in the xy plane) by the vertical transistor (210) can be reduced compared to planar transistors and transverse multi-gate transistors. Additionally, since interconnects can be routed in different planes, the metal wiring coupled to the vertical transistor (210) can likewise be simplified. For example, the bit line (206) and the storage unit (212) may be formed on opposite sides of the vertical transistor (210). In one example, the bit line (206) may be coupled to a source or drain at the upper end of the semiconductor body (214), while the storage unit (212) may be coupled to a different source or drain at the lower end of the semiconductor body (214).

[0038] As illustrated in FIG. 2, a storage unit (212) may be coupled to the source or drain of a vertical transistor (210). The storage unit (212) may include any device capable of storing binary data (e.g., 0 and 1), including but not limited to capacitors for DRAM cells and FRAM cells, and PCM elements for PCM cells. In some implementations, the vertical transistor (210) controls a selection and / or state switch of each storage unit (212) coupled to the vertical transistor (210). In some implementations, as illustrated in FIG. 3, each memory cell (208) is a DRAM cell (302) comprising a transistor (304) (e.g., implemented using the vertical transistor (210) of FIG. 2) and a capacitor (306) (e.g., an example of the storage unit (212) of FIG. 2). The gate of the transistor (304) (e.g., corresponding to the gate electrode (220)) can be coupled to the word line (204), one of the source and drain of the transistor (304) can be coupled to the bit line (206), the other of the source and drain of the transistor (304) can be coupled to one electrode of the capacitor (306), and the other electrode of the capacitor (306) can be coupled to ground.

[0039] In some implementations, as illustrated in FIG. 4, each memory cell (208) is a PCM cell (402) comprising a transistor (404) (e.g., implemented using the vertical transistor (210) of FIG. 2) and a PCM element (406) (e.g., an example of the storage unit (212) of FIG. 2). The gate of the transistor (404) (e.g., corresponding to the gate electrode (220)) may be coupled to the word line (204), one of the source and drain of the transistor (404) may be coupled to ground, the other of the source and drain of the transistor (404) may be coupled to one electrode of the PCM element (406), and the other electrode of the PCM element (406) may be coupled to the bit line (206).

[0040] Peripheral circuitry (202) may be coupled to the memory cell array (201) via bit lines (206), word lines (204), and any other suitable metal wiring. As described above, peripheral circuitry (202) may include any suitable circuitry to facilitate the operation of the memory cell array (201) by applying and detecting voltage and / or current signals to and from each memory cell (208) via word lines (204) and bit lines (206). For example, peripheral circuitry (202) may include various types of peripheral circuitry formed using CMOS technologies.

[0041] II. Manufacturing process to protect the word line in the backend process

[0042] FIGS. 5A and 5B illustrate the result of a manufacturing process in which a trench recess region overlaps with an insulating layer to form a bit line on the back of a semiconductor device. FIG. 5A illustrates a top view of the overlapped trench recess region and the insulating layer. FIG. 5B illustrates a cross-sectional view of the semiconductor device along the word line direction. During the manufacturing process, on the back of the semiconductor device, a trench recess region (501) may be defined to recess a trench insulating portion (504) and a gate structure (word line (516)) along the bit line direction. A spacer (505) may be deposited to cover the surface of the space created from the recess. The space may later be filled with a sacrificial material (506). The spacer (505) may be any suitable dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or a high dielectric constant dielectric. The sacrificial material (506) may be any suitable conductive or non-conductive material such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide.

[0043] Subsequently, an insulating layer (502) may be formed on the back surface of the semiconductor device. As illustrated in FIGS. 5a and 5b, the insulating layer (502) covers a portion of the trench recess region (501), causing an overlap between the insulating layer (502) and the trench recess region (501). The sacrificial material (506) not covered by the insulating layer (502) is removed by performing an etching process to form an air gap between the semiconductor bodies (514). Subsequently, a bit line (518) may be formed on the top of the semiconductor body (514) along the bit line direction within the trench recess region (501) not covered by the insulating layer (502). However, due to the insulating layer (502), the sacrificial material (506) covered by the insulating layer (502) is not removed. The presence of the sacrificial material (506) can potentially cause leakage current. It is desirable to completely remove the sacrificial material (506) under the insulating layer (502).

[0044] FIGS. 6A and 6B illustrate the results of a manufacturing process in which a trench recess region and an insulating layer for forming a bit line do not overlap each other on the back of a semiconductor device. FIG. 6A illustrates a top view of the non-overlapping trench recess region and insulating layer. FIG. 6B illustrates a cross-sectional view of the semiconductor device along the word line direction. On the back of the semiconductor device, the trench recess region (601) may be defined to recess the trench insulating portion (604) and the gate structure (616) along the bit line direction. Similarly, after the deposition of the spacer (605), the space created from the recess may then be filled with a sacrificial material (606). The spacer (605) may be any suitable dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or a high dielectric constant dielectric. The sacrificial material (606) may be any suitable conductive material such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide.

[0045] Subsequently, an insulating layer (602) may be formed on the back surface of the semiconductor device. As illustrated in FIGS. 6a and 6b, since the insulating layer (602) and the trench recess region (601) do not overlap, a small number of trench insulating portions (604) and semiconductor bodies (614) are formed that are not covered by either the insulating layer (602) or the trench recess region (601). The sacrificial material (606) is removed by performing an etching process to form an air gap between the semiconductor bodies (614). Subsequently, a bit line (618) may be formed along the bit line direction on the semiconductor body (614) that is not covered by the insulating layer (602). Because it is difficult to control the uniform depth of the trench for the gate structure within the semiconductor device using a vertical all-in-one etch process, a specific gate structure (616) may have an abnormal height when viewed from the back surface of the semiconductor device. During the removal process of the sacrificial material (606), a gate structure (616) having an abnormal height that is not covered by the trench recess area (601) and not covered by the insulating layer (602) may be removed together from the back of the semiconductor device, which may result in the loss (or disconnection) of the word line as shown in FIG. 6b. To mitigate this word line disconnection problem, the present disclosure provides a back processing method in which the insulating layer (602) is positioned to overlap with the trench recess area (601) to reduce or eliminate the possibility of unintentionally etching the word line. At the same time, a tunnel structure crossing under the bit line is used to remove the sacrificial material (506) under the insulating layer (502) (as shown in FIG. 5b), which can solve the leakage problem.

[0046] FIGS. 7aa and 7ab / FIGS. 7ba and 7bb / FIGS. 7ca and 7cb / FIGS. 7da to 7de / FIGS. 7e / FIGS. 7fa to 7fe / FIGS. 7ga to 7gg / FIGS. 7ha to 7hg / FIGS. 7ia to 7ig / FIGS. 7ja to 7jg / FIGS. 7ka to 7kg illustrate a manufacturing process for forming a memory device according to some aspects of the present disclosure.

[0047] FIG. 7aa illustrates a plan view of a semiconductor memory device (700) having four sections, viewed from the top surface (701). FIG. 7ab illustrates a partial cross-sectional view corresponding to the cutting line X1-X1. In FIG. 7aa / 7ab, a trench insulation portion (704) (e.g., STI) is formed in the bit line direction (e.g., y direction) within the semiconductor substrate (702) of the semiconductor memory device (700). The semiconductor substrate (702) may be a silicon substrate. The semiconductor memory device (700) (and the semiconductor substrate (702)) may have a top surface (701) and a rear surface (703). The trench insulation portion (704) is formed from the top surface (701). In some implementations, for example, based on the design of the bit line, a lithography process is performed to pattern trenches and semiconductor walls (705) within the semiconductor substrate (702) using an etching mask (e.g., a photoresist mask and / or a hard mask). One or more dry etching and / or wet etching processes, such as reactive ion etching (RIE), are performed on the semiconductor substrate (702). In some implementations, a dielectric material, such as silicon oxide, is deposited using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, to completely fill the trenches and form trench insulation (704). In some implementations, a planarization process, such as CMP, is performed to remove excess dielectric material deposited beyond the top surface of the top surface (701).

[0048] FIG. 7ba illustrates a top view of a semiconductor memory device (700) having four sections, viewed from the top plane (701). FIG. 7bb illustrates a partial cross-sectional view corresponding to the cutting line Y1-Y1. In FIG. 7ba / FIG. 7bb, a word line trench (706) is formed along the word line direction (e.g., the x-direction). In some implementations, for example, based on the design of the word line, a lithography process is performed to pattern the word line trench (706) perpendicular to the trench insulation (704) using an etching mask (e.g., a photoresist mask and / or a hard mask). One or more dry etching and / or wet etching processes, such as RIE, are performed on the semiconductor wall (705) and the trench insulation (704) to etch the word line trench (706) within the semiconductor substrate (702). As a result, a semiconductor body (708) is formed by forming a word line trench (706) and a trench insulation (704). The semiconductor body (708) may be extended in a vertical direction (e.g., the z-direction). A word line layer (711) may be formed along the sidewall of the semiconductor body (708) within the word line trench (706), and this may be connected to the sidewall of the semiconductor body (708) in a row. The word line layer (711) includes word lines, and the gate structure (not shown) of the semiconductor body (708) may be formed in a manner similar to that described in FIG. 2 above. At this stage, the word line layer (711) is connected at the bottom of each corresponding word line trench (706). The word lines connecting the rows of the semiconductor body (708) are formed in a subsequent process discussed below. A metal shield (710) can be formed within a word line trench (706) between two adjacent word line layers (711) by a process similar to forming a word line. Then, the word line trench (706) can be filled with an insulating material such as silicon oxide.

[0049] FIG. 7ca illustrates a top view of a semiconductor memory device (700) having four sections as seen from the top surface (701). FIG. 7cb illustrates a partial cross-sectional view corresponding to the cutting line Y1-Y1. In FIG. 7ca / Fig. 7cb, a portion (714) of a word line layer (711) is recessed downward from the top surface (701) at a predetermined location. Each word line layer (711) has two portions (714) recessed downward to form two separate word lines separated in the recessed area. That is, each row of the semiconductor body (708) along the word line direction (x direction) comes into contact with only one word line. At this stage, the word line layer (711) within each word line trench (706) includes two separate word lines that are still connected at the bottom of each word line trench (706). The bottom connection portion will be separated in a back process described in detail below. In some implementations, for example, based on the design of the word lines, a lithography process is performed to pattern the portion (714) using an etching mask (e.g., a photoresist mask and / or a hard mask). One or more dry etching and / or wet etching processes, such as reactive ion etching (RIE), may be performed to etch and recess the word line layer (711). In some implementations, the portion (714) of the word line layer (711) being recessed is positioned close to the end of each word line trench (706) within the trench insulation (704) to maximize the number of semiconductor bodies (708) connected in a row by a single word line. The portion (714) may then be filled with an insulating material such as silicon nitride.

[0050] FIG. 7da illustrates an enlarged plan view of one of the sections of a semiconductor memory device (700) viewed from the rear (703). FIG. 7db and FIG. 7dc illustrate partial cross-sectional views corresponding to the cutting line Y1-Y1 and the cutting line Y2-Y2, respectively. FIG. 7dd and FIG. 7de illustrate partial cross-sectional views corresponding to the cutting line X1-X1 and the cutting line X2-X2, respectively. In FIG. 7da / FIG. 7db / FIG. 7dc / FIG. 7dd / FIG. 7de, the semiconductor substrate (702) is thinned from the rear (703) after a storage unit (720) is formed on each semiconductor body (708). The upper end of the semiconductor body (708) on the upper surface (701) may be doped. The exposed end of each semiconductor body (708) is doped to form a source / drain (e.g., the source terminal of a vertical transistor). In some embodiments, an injection process and / or a thermal diffusion process is performed to dope a P-type dopant or an N-type dopant onto the exposed upper end of the semiconductor body (708) to form a source / drain. In some embodiments, a silicide layer is formed on the source / drain by performing a silicide process on the exposed upper end of the semiconductor body (708).

[0051] Storage units are formed in contact with a semiconductor body (e.g., its doped first ends). The storage unit may include a capacitor or a PCM element. In some embodiments, to form a storage unit that is a capacitor, a first electrode is formed on the doped upper end of the semiconductor body, a capacitor dielectric is formed on the first electrode, and a second electrode is formed on the capacitor dielectric.

[0052] For example, one or more interlayer dielectric (ILD) layers (716) are formed on the upper surface (701) by depositing a dielectric using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. Subsequently, within the ILD layer (716), a storage unit contact (capacitor contact) (718), a first electrode of a storage unit (capacitor) (720), a capacitor dielectric and a second electrode, and a common plate (722) are formed and coupled to the semiconductor body (708). In some embodiments, the capacitor contact (718) is formed on each source / drain, for example, the doped upper end of each semiconductor body (708), by patterning and etching electrode holes aligned with each source / drain using a lithography and etching process, and filling the electrode holes by depositing a conductive material using a thin film deposition process. In some embodiments, a common plate (722) is formed on the second electrode of the capacitor (720) by patterning and etching the electrode trench aligned with the capacitor (720) using a lithography and etching process and filling the electrode trench by depositing a conductive material using a thin film deposition process.

[0053] The semiconductor substrate (702) can be thinned at the back (703) using CMP, grinding, dry etching and / or wet etching. In some embodiments, the CMP process is performed to thin the semiconductor substrate (702) until it reaches the trench insulation (704). After thinning the back (703), the trench insulation (704) is exposed. Lines of the semiconductor structure (707) in the bit line direction (y-direction) are exposed to connect rows of semiconductor bodies (708) at the back (703). Together with each row of connected semiconductor bodies (708), the lines of the semiconductor structure (707) form a bridge-shaped structure, where the lines of the semiconductor structure (707) are beams and the connected semiconductor bodies (708) are piers. As illustrated in FIG. 7dd, because it is difficult to control the uniform depth of the gate structure of the word line (712) with vertical batch etching, the word line (712) may have an abnormally higher region (713) within the trench insulation (704).

[0054] FIG. 7e illustrates an enlarged plan view of one of the sections of a semiconductor memory device (700) as seen from the rear (703). A trench recess region (727) can be patterned by applying a mask (723) to the rear (703). The location of the trench recess region (727) can be determined according to the function of a specific design of the semiconductor memory device.

[0055] FIG. 7fa illustrates an enlarged plan view of one of the sections of a semiconductor memory device (700) as seen from the rear (703). FIG. 7fb and FIG. 7fc illustrate partial cross-sectional views corresponding to the cutting lines Y1-Y1 and Y2-Y2, respectively. FIG. 7fd and FIG. 7fe illustrate partial cross-sectional views corresponding to the cutting lines X1-X1 and X2-X2, respectively. In FIG. 7fa / FIG. 7fb / FIG. 7fc / FIG. 7fd / FIG. 7fe, the trench insulation (704) within the trench recess area (727) is recessed to expose the word line layer (711) and the metal shield (710). The word line layer (711) at the bottom of the word line trench (706) is etched away to form two individual word lines (712) that each connect one row of the semiconductor body (708). The word line (712) and the metal shield (710) are recessed further down toward the top surface (701) within the trench recess area (727). FIG. 7fd illustrates the word line (712) further recessed toward the top surface (701) within the trench recess area (727). FIG. 7fe illustrates the metal shield (710) further recessed toward the top surface (701) within the trench recess area (727). One or more dry etching and / or wet etching processes, such as reactive ion etch (RIE), may be performed to etch and recess the trench insulation (704), the word line (712), and the metal shield (710) within the trench recess area (727).

[0056] A tunnel (724) is formed within a trench recess area (727) along the bit line direction (y-direction) at the bottom of the bridge-shaped structure. The tunnel (724) may have different shapes depending on each word line (712) or metal shield (710). For example, as shown in FIG. 7fb, when viewed from the Y1-Y1 cutting line, the tunnel (724) connected to the word line (712) has a "P" shape, and the tunnel (724) connected to the metal shield (710) has a "T" shape. For example, as shown in FIG. 7fc, when viewed from the Y2-Y2 cutting line, the tunnel (724) connected to the word line (712) has an "n" shape.

[0057] In some implementations, for example, based on the design of the bit line, a lithography process may be performed to pattern the trench recess region (727) using an etching mask (e.g., a photoresist mask and / or a hard mask). One or more dry etching and / or wet etching processes, such as RIE, may be performed on the semiconductor substrate (702) to etch away the trench insulation (704). After the trench insulation (704) is recessed, a second lithography process may be performed to pattern the word line (712) and the metal shield (710) within the trench recess region (727). One or more dry etching and / or wet etching processes, such as RIE, may be performed to etch away the word line (712) and the metal shield (710) within the trench recess region (727).

[0058] FIG. 7ga illustrates an enlarged plan view of one of the sections of a semiconductor memory device (700) viewed from the rear side (703). FIG. 7gb and FIG. 7gc illustrate partial cross-sectional views corresponding to the cutting lines Y1-Y1 and Y2-Y2, respectively. FIG. 7gd illustrates a partial cross-sectional view between the cutting lines Y1-Y1 and Y3-Y3. FIG. 7ge illustrates a partial cross-sectional view between the cutting lines Y2-Y2 and Y4-Y4. FIG. 7gf and FIG. 7gg illustrate partial cross-sectional views corresponding to the cutting lines X1-X1 and X2-X2, respectively. In FIG. 7ga / FIG. 7gb / FIG. 7gc / FIG. 7gd / FIG. 7ge / FIG. 7gf / FIG. 7gg, a thin spacer layer (726) is deposited on the sidewall (725) of the recessed trench insulation (704) and the tunnel (724). As illustrated in FIGS. 7gd and FIGS. 7ge, a thin spacer layer (726) is formed only on the sidewall (725) of the tunnel (724) and does not fill the tunnel (724) and the trench insulation (704). The thin spacer layer (726) is formed by depositing a layer of dielectric material, such as silicon nitride, using one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof, without completely filling the trench insulation (704) and the tunnel (724).

[0059] FIG. 7ha illustrates an enlarged plan view of one of the sections of a semiconductor memory device (700) viewed from the rear side (703). FIG. 7hb and FIG. 7hc illustrate partial cross-sectional views corresponding to the cutting lines Y1-Y1 and Y2-Y2, respectively. FIG. 7hd, FIG. 7he, FIG. 7hf, and FIG. 7hg illustrate partial cross-sectional views corresponding to the cutting lines X1-X1, X2-X2, X3-X3, and X4-X4, respectively. In FIG. 7ha / FIG. 7hb / FIG. 7hc / FIG. 7hd / FIG. 7he / FIG. 7hf / FIG. 7hg, a sacrificial layer (728) is deposited on a semiconductor substrate (702) from the rear side (703). The sacrificial layer (728) completely fills the trench insulation (704) and the tunnel (724). The sacrificial layer (728) may be any suitable sacrificial material that can be selectively removed later, such as a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.) or a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.). The sacrificial layer (728) may be deposited to completely fill the trench insulation (704) and tunnel (724) using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0060] FIG. 7ia illustrates an enlarged plan view of one of the sections of a semiconductor memory device (700) as viewed from the rear side (703). FIG. 7ib and FIG. 7ic illustrate partial cross-sectional views corresponding to the cutting lines Y1-Y1 and Y2-Y2, respectively. FIG. 7id, FIG. 7ie, FIG. 7if, and FIG. 7ig illustrate partial cross-sectional views corresponding to the cutting lines X1-X1, X2-X2, X3-X3, and X4-X4, respectively. In FIG. 7ia / FIG. 7ib / FIG. 7ic / FIG. 7id / FIG. 7ie / FIG. 7if / FIG. 7ig, excess sacrificial material of the sacrificial layer (728) and excess dielectric material of the thin spacer layer (726) are removed from the surface of the rear side (703). In some implementations, a planarization process such as CMP is performed to remove the excess material.

[0061] FIG. 7ja illustrates an enlarged plan view of one of the sections of a semiconductor memory device (700) as viewed from the rear side (703). FIG. 7jb and FIG. 7jc illustrate partial cross-sectional views corresponding to the cutting lines Y1-Y1 and Y2-Y2, respectively. FIG. 7jd, FIG. 7je, FIG. 7jf, and FIG. 7jg illustrate partial cross-sectional views corresponding to the cutting lines X1-X1, X2-X2, X3-X3, and X4-X4, respectively. In FIG. 7ja / FIG. 7jb / FIG. 7jc / FIG. 7jd / FIG. 7je / FIG. 7jf / FIG. 7jg, an insulating layer (730) is formed on the rear side (703) of a semiconductor substrate (702). The insulating layer (730) selectively covers the semiconductor structure (707) and the trench insulating portion (704) within the trench recess region (727). That is, the insulating layer (730) overlaps with the trench recess region (727). In other words, the portion (731) of the back surface (703) not covered by the insulating layer (730) is smaller than each trench recess region (727). As illustrated in FIGS. 7jd and 7je, the insulating layer (730) also covers an abnormally higher region (713) of the word line (712). In this way, the word line (712) is protected from any unintended etching. The portion (731) not covered by the insulating layer (730) is selected as the location where the bit line of the semiconductor memory device (700) will be formed in a subsequent process. In some implementations, the insulating layer (730) may comprise any suitable insulating material, such as silicon oxide, to be deposited on the back surface (703) using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. In some implementations, a planarization process such as CMP is performed to remove excess insulating material.For example, based on the design of the bit line, a lithography process may be performed to pattern the insulating layer (730) using an etching mask (e.g., a photoresist mask and / or a hard mask) to selectively cover the back surface (703) and have an uncovered portion (731). One or more dry etching and / or wet etching processes, such as RIE, may be performed on the insulating layer (730) to etch away the portion (731).

[0062] FIG. 7ka illustrates an enlarged plan view of one of the sections of a semiconductor memory device (700) viewed from the rear (703). FIG. 7kb illustrates a partial cross-sectional view corresponding to the cutting line Y1-Y1. FIG. 7kc illustrates a partial cross-sectional view between the cutting lines Y2-Y2 and Y4-Y4. FIG. 7kd and FIG. 7kf illustrate partial cross-sectional views corresponding to the cutting lines X1-X1 and X3-X3, respectively. FIG. 7ke illustrates a partial cross-sectional view between the cutting lines X1-X1 and X2-X2. FIG. 7kg illustrates a partial cross-sectional view between the cutting lines X3-X3 and X4-X4. In FIG. 7ka / FIG. 7kb / FIG. 7kc / FIG. 7kd / FIG. 7ke / FIG. 7kf / FIG. 7kg, a bit line (732) is formed on the exposed semiconductor structure (707), and then the sacrificial layer (728) is removed. The semiconductor structure (707) exposed in the portion (731) may be doped with an N-type dopant (e.g., P or As) or a P-type dopant (e.g., B or Ga) to a predetermined doping level by performing an injection process, a thermal diffusion process, a combination thereof, or any suitable process. In some implementations, the back surface (703) of the semiconductor substrate (702) may be pre-doped in a prior process. The doping discussed above may be used to further adjust the doping level of the semiconductor structure (707). In some implementations, the doping operation may be omitted.

[0063] A metal layer may be deposited on top of the semiconductor structure (707) to fill the portion (731). The metal layer may comprise W, Co, Cu, Al, or any other suitable metal having higher conductivity than the doped substrate. A high-temperature annealing process may be performed on the semiconductor substrate (702) (e.g., a silicon substrate) to form a metal silicide (i.e., bit line (732)) on the semiconductor structure (707). Metal atoms within the metal layer diffuse into the lower semiconductor structure (707) (i.e., the silicon substrate) to form the metal silicide (i.e., bit line (732)). Since a metal or metal compound is selected as the sacrificial material as described in FIG. 7ha, the metal atoms will not react when in contact with the sacrificial layer (728).

[0064] A metal removal process may be performed to remove any excess metal layer and sacrificial layer (728). One or more dry etching and / or wet etching processes, such as RIE, may be performed to etch away the residual metal layer and sacrificial layer (728). As illustrated in FIGS. 7ke and FIGS. 7kg, the sacrificial layer (728) covered by an insulating layer (730) under each covered semiconductor structure (707) may be removed by allowing selective etchant flow through a tunnel (724). An abnormally higher region (713) of the word line (712) is protected by the insulating layer (730) while all sacrificial material of the sacrificial layer (728) is etched away.

[0065] By introducing a tunnel structure (i.e., tunnel (724)) and utilizing the overlap between the trench recess region (727) and the insulating layer (730), all sacrificial material can be removed, which prevents leakage current from any unremoved sacrificial material. Additionally, an abnormally higher region (713) of the word line (712) is protected by the insulating layer (730) so that it is not unintentionally etched away during the removal of the sacrificial layer (728), thereby preventing the problem of word line loss.

[0066] III. Manufacturing Process Flowchart for Protecting Word Lines in Back-end Processes

[0067] FIG. 8 illustrates a flowchart of a manufacturing process (800) for forming a 3D memory device including a vertical transistor according to some aspects of the present disclosure. The manufacturing process (800) is merely an example of the various methods and techniques disclosed in the present disclosure. Not all steps are performed in the various embodiments. The steps may be performed in a different order or in parallel in the various embodiments. The manufacturing process (800) starts at S801 and proceeds to S810.

[0068] In S810, the semiconductor memory device may be thinned from the rear of the semiconductor device to expose trench insulation sections. The semiconductor memory device may have trench insulation sections formed in the bit line direction, gate structures formed in the word line direction perpendicular to the bit line direction, and an array of vertical transistor channel structures extending in a vertical direction perpendicular to the bit line direction and the word line direction and separated by the trench insulation sections and gate structures. After thinning, the trench insulation sections are exposed from the rear of the semiconductor device. The upper ends of the vertical transistor channel structures of each column along the bit line direction are connected to a semiconductor structure line extending along the bit line direction from the rear of the semiconductor memory device to form a bridge-shaped structure. The trench insulation sections separate adjacent bridge-shaped structures. The semiconductor memory device may also have metal shields formed between every two adjacent channel structures along the word line direction.

[0069] In S820, trench insulation between adjacent bridge shape structures can be recessed in a first region on the back of the semiconductor memory device to expose gate structures formed in the word line direction.

[0070] In S830, the gate structures formed in the direction of the word line are etched to form tunnels along each gate structure. The tunnels run under each semiconductor structure line.

[0071] In S840, the surfaces of the space where the trench insulation and gate structures have been etched away can be covered with a spacer layer.

[0072] In S850, the space where trench insulation and gate structures are etched away can be filled with sacrificial material on the spacer layer.

[0073] In S860, a portion of a first region on the back of a semiconductor memory device may be covered by an insulating layer. The insulating layer may seal a sacrificial material located between each adjacent bridge-shaped structure beneath the insulating layer in the covered portion of the first region. The insulating layer may cover a second region adjacent to the portion of the first region covered by the insulating layer, and the trench insulating portions of the second region are retained while the trench insulating portions of the first region are etched.

[0074] In S870, while a portion of the first region is covered by an insulating layer, bit line structures can be formed on semiconductor structure lines that are not covered by the insulating layer in the first region.

[0075] In S880, the sacrificial material within the space where the trench insulation and gate structures have been etched away can be removed while part of the first region is covered with an insulating layer. The sacrificial material surrounded by the insulating layer is removed through tunnels running beneath each semiconductor structure line. The process proceeds to S899 and ends at S899.

[0076] Although the embodiments of the present disclosure have been described in relation to specific embodiments proposed as examples, alternatives, modifications, and changes to these examples may be made. Accordingly, the embodiments described herein are illustrative and not restrictive. There are modifications that may be made without departing from the scope of the claims set forth below.

Claims

Claim 1 A method for manufacturing a semiconductor memory device, comprising the steps of: thinning the semiconductor memory device from the rear surface of the semiconductor memory device having, at the present stage, trench insulating portions formed in a bit line direction, gate structures formed in a word line direction perpendicular to the bit line direction, and an array of vertical transistor channel structures extending in a vertical direction perpendicular to the bit line direction and the word line direction and separated by the trench insulating portions and the gate structures; wherein, after thinning, the trench insulating portions are exposed on the rear surface of the semiconductor memory device, and the upper ends of the vertical transistor channel structures in each column along the bit line direction are connected to a semiconductor structure line extending along the bit line direction on the rear surface of the semiconductor memory device to form a bridge-shaped structure, and the trench insulating portions separate adjacent bridge-shaped structures; and, in a first region of the rear surface of the semiconductor memory device, recessing the trench insulating portions between adjacent bridge-shaped structures to expose the gate structures formed in the word line direction, and etching the gate structures formed in the word line direction. A step of forming tunnels along each gate structure—said tunnels crossing under each semiconductor structure line—and a step of filling the space etched away from the trench insulating portions and the gate structures with a sacrificial material, and a step of covering a portion of the first region on the back of the semiconductor memory device with an insulating layer—said insulating layer surrounding the sacrificial material between each adjacent bridge shape structure under the insulating layer in the covered portion of the first region—and,A method comprising the step of removing the sacrificial material within the space where the trench insulating portions and the gate structures are etched away while the portion of the first region is covered by the insulating layer—the sacrificial material surrounded by the insulating layer is removed through the tunnels crossing under each semiconductor structure line. Claim 2 A method according to claim 1, wherein the insulating layer covers a second region adjacent to a portion of the first region covered by the insulating layer, and the trench insulating portions in the second region are retained while the trench insulating portions in the first region are etched. Claim 3 The method of claim 1, wherein the semiconductor memory device has metal shielding portions formed between every two adjacent channel structures along the word line direction. Claim 4 A method according to claim 3, further comprising the steps of: etching the metal shielding portions formed in the direction of the word line to form tunnels along each metal shielding portion while crossing below each semiconductor structure line; filling the space where the trench insulation portions and the metal shielding portions have been etched away with the sacrificial material; and removing the sacrificial material within the space where the trench insulation portions and the metal shielding portions have been etched away while the portion of the first region is covered by the insulating layer, wherein the sacrificial material surrounded by the insulating layer is removed through the tunnels along each metal shielding portion while crossing below each semiconductor structure line. Claim 5 A method according to claim 1, further comprising the step of covering the surfaces of the space from which the trench insulation portions and the gate structures have been etched out with a spacer layer before filling the space from which the trench insulation portions and the gate structures have been etched out with the sacrificial material. Claim 6 A method according to claim 1, further comprising the step of forming bit line structures on semiconductor structure lines not covered by the insulating layer in the first region while the portion of the first region is covered by the insulating layer. Claim 7 A semiconductor memory device comprising: trench insulation arranged in a bit line direction; gate structures arranged in a word line direction perpendicular to the bit line direction; an array of vertical transistor channels arranged in a vertical direction perpendicular to the bit line direction and the word line direction, separated by the trench insulation and the gate structures—the upper ends of the array of vertical transistor channels in each column are connected to a semiconductor structure line extending in the bit line direction from the rear surface of the semiconductor memory device—and air gap tunnels along the word line direction—each air gap tunnel is located in a first region on the rear surface of the semiconductor memory device, crossing below the semiconductor structure line and between two adjacent vertical transistor channels. Claim 8 In claim 7, the air gap tunnels are adjacent to the gate structures, in a semiconductor memory device. Claim 9 A semiconductor memory device according to claim 7, further comprising metal shielding portions between every two adjacent vertical transistor channels along the word line direction. Claim 10 In claim 9, the air gap tunnels are adjacent to the metal shielding portions, in a semiconductor memory device. Claim 11 A semiconductor memory device according to claim 7, wherein at least one surface of the air gap tunnels is covered by a spacer layer surrounding the air gap. Claim 12 In claim 7, the upper portions of the trench insulation on the rear side of the semiconductor memory device are recessed to form air gaps on the trench insulation between bridge-shaped structures formed by each semiconductor structure line and each vertical transistor channel in each column, and the air gaps are connected to the air gap tunnels, the semiconductor memory device. Claim 13 A semiconductor memory device according to claim 12, wherein a spacer layer covers the surfaces of air gap tunnels connected to the air gaps and the air gaps between the bridge-shaped structures formed by each semiconductor structure line and each vertical transistor channel in each column. Claim 14 A semiconductor memory device according to claim 7, wherein an insulating layer covers a part of the first region and a second region adjacent to the part of the first region, and no air gap tunnel is formed within the second region. Claim 15 A memory system comprising a memory controller and a semiconductor memory device coupled to the memory controller, wherein the semiconductor memory device is Trench insulation sections arranged in the direction of the bit line, and Gate structures arranged in a word line direction perpendicular to the bit line direction, and An array of vertical transistor channels arranged in a vertical direction perpendicular to the bit line direction and the word line direction, separated by the trench insulation portions and the gate structures—the upper ends of the array of vertical transistor channels in each column are connected to a semiconductor structure line extending in the bit line direction from the rear surface of the semiconductor memory device—and, A memory system comprising air gap tunnels along the direction of the word line—each air gap tunnel being located in a first region on the rear side of the semiconductor memory device, crossing below the semiconductor structure line and between two adjacent vertical transistor channels. Claim 16 In paragraph 15, the air gap tunnels are adjacent to the gate structures, in a memory system. Claim 17 A memory system according to claim 15, further comprising metal shielding between every two adjacent vertical transistor channels along the word line direction. Claim 18 In paragraph 17, the air gap tunnels are adjacent to the metal shields, in a memory system. Claim 19 In claim 15, a memory system in which at least one surface of the air gap tunnels is covered by a spacer layer surrounding the air gap. Claim 20 In claim 15, the upper portions of the trench insulation on the rear side of the semiconductor memory device are recessed to form air gaps on the trench insulation between bridge-shaped structures formed by each semiconductor structure line and each vertical transistor channel in each row, said air gaps are connected to air gap tunnels, and a spacer layer covers the surfaces of the air gaps between the bridge-shaped structures formed by each semiconductor structure line and each vertical transistor channel in each row and the air gap tunnels connected to said air gaps.

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