Method and circuitry for handling defective memory cells and wordlines in memory module

Abstract

A method for processing a defective conventional local word line in a memory module includes: providing one or more sets of backup local word lines; using backup control logic to compare an input address with a plurality of fault addresses to generate a plurality of match signals; using the backup control logic to generate at least one assignable bit based on the plurality of match signals; using a local word line pre-decoder to generate a local word line activation signal based on at least one bit of the input address and the at least one assignable bit; and using one or more backup word line decoders to activate one of the one or more sets of backup local word lines to repair / replace a defective conventional local word line based on the input address and the local word line activation signal, thereby repairing / replacing the defective conventional local word line.

Claims

1. A method for processing a defective conventional local word line in a memory module, comprising: providing one or more sets of spare local word lines; using spare control logic to generate a plurality of match signals by comparing an input address with a plurality of fault addresses; using the spare control logic to generate a hit signal and at least one assignable bit based on the plurality of match signals; selectively replacing a first portion of bits of the input address with the at least one assignable bit in response to the hit signal to form a set of internal decoded bits; using a local word line pre-decoder to generate a local word line activation signal based on the set of internal decoded bits and a second portion of bits of the input address; and activating one of the spare local word lines from the one or more sets of spare local word lines based on the input address and the local word line activation signal, using one or more spare word line decoders to repair / replace a defective conventional local word line.

2. The method of claim 1, wherein the step of generating the local word line start signal comprises: providing a plurality of address comparators to compare the plurality of fault addresses with at least a portion of the input address, thereby generating the plurality of match signals; and assigning a value of the at least one assignable bit based on the plurality of match signals.

3. The method of claim 2, wherein the step of generating the at least one assignable bit based on the plurality of matching signals comprises: assigning a value of two assignable bits based on the plurality of matching signals; and assigning the two assignable bits as (0, 0) in response to the triggering of a first matching signal among the plurality of matching signals, assigning the two assignable bits as (0, 1) in response to the triggering of a second matching signal among the plurality of matching signals, assigning the two assignable bits as (1, 0) in response to the triggering of a third matching signal among the plurality of matching signals, and assigning the two assignable bits as (1, 1) in response to the triggering of a fourth matching signal among the plurality of matching signals.

4. The method as described in request item 1, wherein, The internal decoding bits of the group are two assignable bits (B2, B1), the second part of the input address is the last bit A0 of the input address, and the step of generating the local word line start signal includes: using the local word line pre-decoder, decoding in the order of (B2, B1, A0) to generate the local word line start signal.

5. The method of claim 4, wherein the step of activating one of the one or more sets of spare local word lines using the one or more spare word line decoders comprises: activating a first or a second spare local word line in the set of spare local word lines to repair / replace any defective conventional local word line pointed to by a first fault address in the plurality of fault addresses; activating a third or a fourth spare local word line in the set of spare local word lines to repair / replace any defective conventional local word line pointed to by a second fault address in the plurality of fault addresses; activating a fifth or a sixth spare local word line in the set of spare local word lines to repair / replace any defective conventional local word line pointed to by a third fault address in the plurality of fault addresses; and activating a seventh or an eighth spare local word line in the set of spare local word lines to repair / replace any defective conventional local word line pointed to by a fourth fault address in the plurality of fault addresses.

6. The method of claim 4, wherein the step of activating one of the one or more sets of spare local word lines using the one or more spare word line decoders comprises: activating a first or a second spare local word line in the set of spare local word lines to repair / replace a first or a second local word line in a first set of regular local word lines pointed to by a first fault address in the plurality of fault addresses; and activating a third or a fourth spare local word line in the set of spare local word lines to repair / replace a first or a second local word line in a second set of regular local word lines pointed to by a second fault address in the plurality of fault addresses.

7. The method as described in request item 1, wherein, The internal decoding bits of the group are two assignable bits (B2, B0), the second part of the input address is the last bit A0 of the input address, and the step of generating the local word line start signal includes: using the local word line pre-decoder, decoding in the order of (B2, A0, B0) to generate the local word line start signal.

8. The method of claim 7, wherein the step of activating one of the one or more sets of spare local word lines using the one or more spare word line decoders comprises: activating a first or third spare local word line in the set of spare local word lines to repair / replace any defective conventional local word line pointed to by a first fault address in the plurality of fault addresses; activating a second or fourth spare local word line in the set of spare local word lines to repair / replace any defective conventional local word line pointed to by a second fault address in the plurality of fault addresses; activating a fifth or seventh spare local word line in the set of spare local word lines to repair / replace any defective conventional local word line pointed to by a third fault address in the plurality of fault addresses; and activating a sixth or eighth spare local word line in the set of spare local word lines to repair / replace any defective conventional local word line pointed to by a fourth fault address in the plurality of fault addresses.

9. The method of claim 7, wherein the step of activating one of the one or more sets of spare local word lines using the one or more spare word line decoders comprises: activating a first or a third spare local word line in the set of spare local word lines to repair / replace a first local word line or a second local word line in a first set of regular local word lines pointed to by a first fault address in the plurality of fault addresses; and activating a second or a fourth spare local word line in the set of spare local word lines to repair / replace a first local word line or a second local word line in a second set of regular local word lines pointed to by a second fault address in the plurality of fault addresses.

10. A circuit for processing defective conventional local word lines in a memory module, comprising: one or more backup local word line decoders for controlling one or more sets of backup local word lines, each of the one or more backup local word line decoders being configured to selectively activate one backup local word line from a corresponding set of backup local word lines based on a local word line activation signal and an input address, thereby repairing / replacing a defective conventional local word line; and backup control logic coupled to the one or more backup local word line decoders for comparing the input address with a plurality of fault addresses to generate a plurality of match signals, and generating a hit signal and at least one assignable bit based on the plurality of fault addresses; wherein... The at least one assignable bit is used to selectively replace a first portion of the input address in response to the hit signal to form a set of internal decode bits; and a local word line pre-decoder, coupled to the backup control logic, is used to generate the local word line start signal based on the set of internal decode bits and a second portion of the input address.

11. The circuit of claim 10, wherein the backup control logic comprises: a plurality of address comparators for comparing the plurality of fault addresses with at least a portion of the input address to generate the plurality of match signals; and a first multiplexer coupled to the plurality of address comparators for assigning a value of the at least one assignable bit based on the plurality of match signals.

12. The circuit of claim 10, wherein the first multiplexer is configured to assign a value of two assignable bits according to the plurality of matching signals, and the first multiplexer: assigns the two assignable bits as (0, 0) in response to the triggering of a first matching signal among the plurality of matching signals; assigns the two assignable bits as (0, 1) in response to the triggering of a second matching signal among the plurality of matching signals; assigns the two assignable bits as (1, 0) in response to the triggering of a third matching signal among the plurality of matching signals; and assigns the two assignable bits as (1, 1) in response to the triggering of a fourth matching signal among the plurality of matching signals.

13. The circuit as claimed in claim 10, wherein, The internal decoding bits of this group are two assignable bits (B2, B1), the second part of the input address is the last bit A0 of the input address, and the local word line pre-decoder decodes in the order of (B2, B1, A0) to generate the local word line start signal.

14. The circuitry of claim 13, wherein the one or more backup local word line decoders are configured to: activate a first or second backup local word line from a set of backup local word lines to repair / replace any defective conventional local word line pointed to by a first fault address from the plurality of fault addresses; activate a third or fourth backup local word line from the set of backup local word lines to repair / replace any defective conventional local word line pointed to by a second fault address from the plurality of fault addresses; activate a fifth or sixth backup local word line from the set of backup local word lines to repair / replace any defective conventional local word line pointed to by a third fault address from the plurality of fault addresses; and activate a seventh or eighth backup local word line from the set of backup local word lines to repair / replace any defective conventional local word line pointed to by a fourth fault address from the plurality of fault addresses.

15. The circuitry of claim 13, wherein the one or more backup local word line decoders are configured to: activate a first or a second backup local word line in a set of backup local word lines to repair / replace a first local word line or a second local word line in a first set of regular local word lines pointed to by a first fault address in the plurality of fault addresses; and activate a third or a fourth backup local word line in the set of backup local word lines to repair / replace a first local word line or a second local word line in a second set of regular local word lines pointed to by a second fault address in the plurality of fault addresses.

16. The circuit as claimed in claim 10, wherein, The internal decoding bits of this group are two assignable bits (B2, B0), the second part of the input address is the last bit A0 of the input address, and the local word line pre-decoder decodes in the order of (B2, A0, B0) to generate the local word line start signal.

17. The circuitry of claim 16, wherein the one or more backup local word line decoders are configured to: activate a first or third backup local word line from a set of backup local word lines to repair / replace any defective conventional local word line pointed to by a first fault address from the plurality of fault addresses; activate a second or fourth backup local word line from the set of backup local word lines to repair / replace any defective conventional local word line pointed to by a second fault address from the plurality of fault addresses; activate a fifth or seventh backup local word line from the set of backup local word lines to repair / replace any defective conventional local word line pointed to by a third fault address from the plurality of fault addresses; and activate a sixth or eighth backup local word line from the set of backup local word lines to repair / replace any defective conventional local word line pointed to by a fourth fault address from the plurality of fault addresses.

18. The circuitry of claim 16, wherein the one or more backup local word line decoders are configured to: activate a first or a third backup local word line in a set of backup local word lines to repair / replace a first local word line or a second local word line in a first set of regular local word lines pointed to by a first fault address in the plurality of fault addresses; and activate a second or a fourth backup local word line in the set of backup local word lines to repair / replace a first local word line or a second local word line in a second set of regular local word lines pointed to by a second fault address in the plurality of fault addresses.

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