Integrated circuit device and method of fabricating the same

Abstract

The problem of providing a transistor that can be manufactured to have any specified threshold voltage over a wide range of threshold voltages without leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into the gate dielectric of a first dielectric composition. The second dielectric composition is chosen relative to the first dielectric composition such that a dipole is formed around the interface of the two dielectrics. The dipole generates an electric field that shifts the threshold voltage. The buried layer has a higher dielectric constant than the gate dielectric, is thinner than the gate dielectric, and is located close to the channel.

Description

Prior Art

[0001] Over the past few decades, the integrated circuit (IC) manufacturing industry has experienced exponential growth. As ICs have evolved, functional density (the number of interconnected devices per unit chip area) has generally increased, while geometry size (the smallest component that can be produced) has generally decreased. Another development is BCD technology, a combination of bipolar junction transistor (BJT), complementary metal-oxide-semiconductor (CMOS), and double-diffused metal-oxide-semiconductor (DMOS) technologies. BCD technology allows logic, analog, and power devices to be formed on a single semiconductor chip. However, BCD technology presents challenges in terms of process compatibility requirements and the need to limit the proliferation of process steps. Simple diagram description

[0002] The aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. 1-2 illustrate cross-sectional side views of bottom gate transistors according to some embodiments of the present disclosure. FIG. 3 provides an enlarged view of a portion shown in FIG. 2 . 4 to 6 illustrate cross-sectional side views of bottom gate transistors according to some other embodiments. 7-8 illustrate cross-sectional side views of top-gate transistors according to some embodiments of the present disclosure. FIG. 9 provides an enlarged view of a portion shown in FIG. 8 . 10 to 12 illustrate cross-sectional side views of bottom gate transistors according to some other embodiments. 13-14 illustrate cross-sectional side views of integrated circuit (IC) devices according to some embodiments of the present disclosure. 15-30 are a series of cross-sectional views illustrating methods of forming a device such as the device shown in FIG. 13 according to the present disclosure. 31-41 are a series of cross-sectional views illustrating a method of forming a device such as the device shown in FIG. 14 according to the present disclosure. 42-43 provide flow charts illustrating some methods according to the present disclosure for forming IC devices according to the present disclosure. Implementation Method

[0003] The present disclosure provides many different embodiments or examples for implementing various features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature being formed on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, thereby preventing the first and second features from directly contacting each other. Furthermore, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0005] The problem of providing a transistor that can be fabricated to any desired threshold voltage within a wide range of threshold voltages without causing leakage, capacitance, or process compatibility issues is solved by introducing a buried layer of a second dielectric composition into the gate dielectric of a first dielectric composition. The second dielectric composition is selected relative to the first dielectric composition so that a dipole forms around the interface between the two dielectric compositions. The dipole generates an electric field that shifts the threshold voltage. Depending on the orientation of the dipole and whether the semiconductor channel is p-type or n-type, the threshold voltage shift can be positive or negative.

[0006] The influence of the dipoles increases as they approach the semiconductor channel. In some embodiments, the buried layer is closer to the semiconductor channel than it is to the gate electrode. In some embodiments, half or more of the gate dielectric structure is located between the buried layer and the gate electrode. In some embodiments, the distance between the buried layer and the gate electrode is greater than the thickness of the buried layer.

[0007] In some embodiments, the buried layer has a higher dielectric constant than the gate dielectric. In some embodiments, the gate dielectric is silicon dioxide or a similar material. In some embodiments, the buried layer is a high-κ dielectric. Materials with higher dielectric constants are more suitable for the buried layer. The thickness of the buried layer is limited because its effect on gate capacitance is also limited.

[0008] In some embodiments, both the gate dielectric and the buried layer are oxides, and the buried layer has an electronegativity different from that of the gate dielectric. The significant difference in electronegativity between the dielectric compositions facilitates dipole formation. In some embodiments, the electronegativity difference is at least as great as the electronegativity difference between silicon dioxide (SiO2) and hafnium oxide (HfO2). In some embodiments, the electronegativity difference is greater than the electronegativity difference between silicon dioxide (SiO2) and hafnium oxide (HfO2).

[0009] In some embodiments, both the gate dielectric and the buried layer are oxides, and the buried layer has an oxygen areal density that differs from the gate dielectric. The significant difference in oxygen areal density between these dielectric compositions facilitates dipole formation. In some embodiments, the oxygen areal density difference is at least as great as the oxygen areal density difference between silicon dioxide (SiO2) and hafnium oxide (HfO2). In some embodiments, the oxygen areal density difference is greater than the oxygen areal density difference between silicon dioxide (SiO2) and hafnium oxide (HfO2).

[0010] In some embodiments, the buried layer comprises a mixture of two or more dielectrics. Mixing two or more dielectrics allows for fine tuning of the threshold voltage. In some embodiments, the buried layer comprises a mixture of two dielectrics, both of which have a higher oxygen areal density than the gate dielectric. For example, if the gate dielectric is silicon dioxide (SiO2), the buried layer may be a mixture of two or more of gallium oxide (Ga2O3), indium oxide (In2O3), zinc oxide (ZnO), aluminum oxide (Al2O3), titanium oxide (TiO2), hafnium oxide (HfO2), or similar materials. In some embodiments, the buried layer comprises a mixture of two dielectrics, both of which have a lower oxygen areal density than the gate dielectric. For example, if the gate dielectric is silicon dioxide (SiO2), the buried layer can be a mixture of two or more of yttrium oxide (Y2O3), strontium oxide (SrO), lanthanum oxide (La2O3), or similar materials. The threshold voltage is increased or decreased depending on whether the buried layer has a higher or lower oxygen density than the gate dielectric. Enabling both dielectrics in the buried layer to have higher or lower oxygen densities than the gate dielectric ensures that the two dielectrics operate synergistically.

[0011] In some embodiments, a second buried layer is embedded in the gate dielectric. In some embodiments, the second buried layer is adjacent to the first buried layer. In some embodiments, the second buried layer is separated from the first buried layer by a thin layer of gate dielectric. Two buried layers provide a larger threshold voltage shift than a single buried layer. Furthermore, the inventors have discovered that two buried layers of different compositions can provide a larger threshold voltage shift than can be achieved using a single buried layer composition.

[0012] In some embodiments, the transistor is a top-gate device. A top-gate device may have a channel provided by a crystalline substrate (e.g., a silicon substrate). In the disclosed fabrication process, a thin layer of gate dielectric is first deposited, followed by a buried layer, followed by the remainder of the gate dielectric, the gate electrode, spacers, and doping of the source / drain regions. The thin layer of gate dielectric prevents undesirable interactions between the buried layer and the substrate. Using the buried layer to control the threshold voltage prevents undesirable variations in transistor height and increases compatibility with other device structures formed on the same semiconductor substrate.

[0013] In some embodiments, the transistor is a bottom-gate device. A bottom-gate device may have a channel provided by a deposited layer, such as amorphous silicon, polycrystalline silicon, or a metal oxide semiconductor. In the disclosed manufacturing process, a gate dielectric is first deposited, followed by a buried layer and a channel layer. The gate stack is patterned, followed by spacers, an interlayer dielectric layer, and source and drain regions formed within the interlayer dielectric. A thin layer of gate dielectric may be deposited over the buried layer to prevent interaction with the semiconductor channel. Using a buried layer to control the threshold voltage prevents undesirable variations in transistor height and facilitates integration of the transistor into metal interconnect structures.

[0014] FIG1 is a cross-sectional view of a transistor 100 according to some embodiments. Transistor 100 includes a gate dielectric structure 115A located between a bottom gate electrode 113 and a channel layer 107. Above the channel layer 107, a source region 101 and a drain region 105 may be disposed as conductive structures within an interlevel dielectric (ILD) layer 103. Gate dielectric structure 115A includes a buried layer 109 located within a gate dielectric 111. A thin layer 110 of gate dielectric 111 separates buried layer 109 from channel layer 107.

[0015] The buried layer 109 is embedded within the gate dielectric 111, forming a first interface 117A between the buried layer 109 and the thin layer 110, and a second interface 117B between the buried layer 109 and the bulk region of the gate dielectric 111. The interaction between the buried layer 109 and the gate dielectric 111 at the first interface 117A and the second interface 117B shifts the threshold voltage of the transistor 100 to a much greater extent than can be explained by the thickness and dielectric constant of the buried layer 109. The primary mechanism for this shift is likely the formation of dipoles around the first interface 117A and the second interface 117B.

[0016] The buried layer 109 is closer to the channel layer 107 than it is to the bottom gate electrode 113. The buried layer 109 is separated from the channel layer 107 by a distance D1 (see FIG. 3 ), where D1 is the thickness of the thin layer 110. In some embodiments, the distance D1 is approximately equal to the thickness of the buried layer 109. In some embodiments, the distance D1 is less than the thickness of the buried layer 109. In some embodiments, the distance D1 is between about 1 angstrom and about 10 angstroms. In some embodiments, the distance D1 is between about 1 angstrom and about 5 angstroms.

[0017] In some embodiments, the thickness T1 of the gate dielectric structure 115A ranges from about 1 nm to about 10 nm. The thickness of the buried layer 109 is less than half the thickness T1. In some embodiments, the thickness of the buried layer 109 combined with the thickness of the thin layer 110 is less than half the thickness T1. In some embodiments, the thickness of the buried layer 109 is about one-quarter the thickness T1 or less. In some embodiments, the thickness of the buried layer 109 ranges from about 1 angstrom to about 10 angstroms.

[0018] The buried layer 109 has a higher dielectric constant than the gate dielectric 111. In some embodiments, the buried layer 109 is a high-κ dielectric. In some embodiments, the buried layer 109 is an oxide or includes an oxide. The buried layer 109 may be, for example, aluminum oxide (Al2O3), titanium oxide (TiO2), hafnium oxide (HfO2), zinc oxide (ZnO), yttrium oxide (Y2O3), lanthanum oxide (La2O3), gallium oxide (Ga2O3), indium oxide (In2O3), combinations thereof, or similar materials, or may include, for example, aluminum oxide (Al2O3), titanium oxide (TiO2), hafnium oxide (HfO2), zinc oxide (ZnO), yttrium oxide (Y2O3), lanthanum oxide (La2O3), gallium oxide (Ga2O3), indium oxide (In2O3), combinations thereof, or similar materials. In some embodiments, the buried layer 109 has a single dielectric composition. In some embodiments, the buried layer 109 is a mixture of two or more dielectrics. Mixing two or more dielectrics in the buried layer 109 allows for fine tuning of the threshold voltage.

[0019] The gate dielectric 111 can have any suitable composition. In some embodiments, the gate dielectric 111 is an oxide or includes an oxide. The gate dielectric 111 can be, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), strontium oxide (SrO), combinations thereof, or similar materials, or can include, for example, silicon oxide (SiO2), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), strontium oxide (SrO), combinations thereof, or similar materials. In cases where the gate dielectric 111 is a mixture of two or more oxides, the oxides can be uniformly mixed or can be arranged in alternating layers. If the oxides are arranged in alternating layers, each layer is thinner than the buried layer 109. In some embodiments, the gate dielectric 111 is silicon oxide (SiO 2 ) or a similar material.

[0020] FIG2 is a cross-sectional view of transistor 200 according to some embodiments. FIG3 provides an enlarged view of region 300 in FIG2 . Transistor 200 is similar to transistor 100 shown in FIG1 , except that transistor 200 includes a gate dielectric structure 115B. Gate dielectric structure 115B is similar to gate dielectric structure 115A shown in FIG1 , except that gate dielectric structure 115B includes a second buried layer 209. A second thin layer 210 of gate dielectric 111 separates second buried layer 209 from buried layer 109.

[0021] The second buried layer 209 is embedded within the gate dielectric 111, forming a third interface 217A between the second buried layer 209 and the second thin layer 210, and a fourth interface 217B between the second buried layer 209 and the bulk region of the gate dielectric 111. The interaction between the second buried layer 209 and the gate dielectric 111 at the third interface 217A and at the fourth interface 217B shifts the threshold voltage of the transistor 100 to a much greater extent than could be explained by the thickness and dielectric constant of the second buried layer 209.

[0022] The second buried layer 209 is closer to the channel layer 107 than it is to the bottom gate electrode 113. The second buried layer 209 is separated from the buried layer 109 by a distance D2 (see FIG. 3 ), where the distance D2 is the thickness of the second thin layer 210. In some embodiments, the distance D2 is approximately equal to the thickness of the second buried layer 209. In some embodiments, the distance D2 is less than the thickness of the second buried layer 209. In some embodiments, the distance D2 is between about 1 angstrom and about 10 angstroms. In some embodiments, the distance D2 is between about 1 angstrom and about 5 angstroms.

[0023] The thickness and composition of the second buried layer 209 are the same as those of the buried layer 109. In some embodiments, the second buried layer 209 has a different composition than the buried layer 109. In some embodiments, the combined thickness of the thin layer 110, the buried layer 109, the second thin layer 210, and the second buried layer 209 is less than half the thickness T1 of the gate dielectric structure 115B.

[0024] The channel layer 107 is a semiconductor and may have any suitable composition. Examples of potentially suitable compositions include amorphous silicon, polycrystalline silicon, metal oxide semiconductors, or similar materials. Examples of usable metal oxide semiconductors include, but are not limited to, indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), indium tin oxide (InSnO or ITO), combinations thereof, or similar materials.

[0025] In some embodiments, channel layer 107 is a metal oxide semiconductor. Thin layer 110 can be used to prevent undesirable interactions between channel layer 107, which is silicon, and buried layer 109, which is a high-κ dielectric. Selecting an appropriate metal oxide semiconductor for channel layer 107 is an alternative way to prevent such undesirable interactions.

[0026] FIG4 is a cross-sectional view of a transistor 400 according to another embodiment. Transistor 400 is similar to transistor 100 shown in FIG1 , except that transistor 200 has a gate dielectric structure 115C. Gate dielectric structure 115C is similar to gate dielectric structure 115A shown in FIG1 , except that thin layer 110 (see FIG1 ) is absent and buried layer 109 abuts channel layer 107. Gate dielectric structure 115C has a second interface 117B but lacks first interface 117A (see FIG1 ).

[0027] FIG5 is a cross-sectional view of a transistor 500 according to another embodiment. Transistor 500 is similar to transistor 200 shown in FIG2 , except that transistor 500 includes a gate dielectric structure 115D. Gate dielectric structure 115D is similar to gate dielectric structure 115B shown in FIG2 , except that second thin layer 210 is absent in gate dielectric structure 115D and buried layer 109 abuts second buried layer 209 to form interface 517. In transistor 500, buried layer 109 and second buried layer 209 have different compositions and three interfaces exist that can form a dipole: first interface 117A, interface 517, and fourth interface 217B.

[0028] FIG6 is a cross-sectional view of a transistor 600 according to another embodiment. Transistor 600 is similar to transistor 500 shown in FIG5 , except that transistor 500 includes a gate dielectric structure 115E. Gate dielectric structure 115E is similar to gate dielectric structure 115D shown in FIG5 , except that thin layer 110 separating buried layer 109 from channel layer 107 is absent in gate dielectric structure 115E. In transistor 600, buried layer 109 can function similarly to thin layer 110 in gate dielectric structure 115A shown in FIG1 . Each of the gate dielectric structures 115A to 115E shown in FIG1-2 and FIG4-6 can provide unique advantages in varying the threshold voltage while maintaining capacitance within a desired range.

[0029] Figures 7 through 12 are cross-sectional views of top-gate transistors corresponding to the bottom-gate transistors shown in Figures 1 through 6 and using the same gate dielectric structure. Figure 7 shows a top-gate transistor 700 using a gate dielectric structure 115A. In top-gate transistor 700, the gate dielectric structure 115A is inverted, so that the buried layer 109 is adjacent to the semiconductor substrate 707, which provides the channel. A gate electrode 713 is located above the gate dielectric structure 115A. The source region 701 and the drain region 703 are provided by regions of the semiconductor substrate 707 having opposite doping types and are aligned with the sidewall spacers 705.

[0030] Semiconductor substrate 707 can be of any suitable type. It can be, for example, a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. The semiconductor can be silicon (Si), a III-V group or some other binary semiconductor, a ternary semiconductor (e.g., AlGaAs), a higher-order semiconductor, or the like. The semiconductor can be a single crystal structure or an epitaxially grown structure.

[0031] FIG8 illustrates a top-gate transistor 800 using the gate dielectric structure 115B shown in FIG2 . FIG9 illustrates the region 900 shown in FIG8 . As shown in FIG9 , the dimensions of the gate dielectric structure 115B are the same as those shown in FIG3 . The only difference is that, for the top-gate transistor 800, the gate dielectric structure 115B is inverted.

[0032] FIG10 illustrates a top-gate transistor 1000 using the gate dielectric structure 115C shown in FIG4 . As shown in this example, the thin layer 110 (see FIG7 ) separating the buried layer 109 from the semiconductor substrate 707 is optional, but the material choice that makes the thin layer 110 removable is more likely to be suitable for a bottom-gate transistor. FIG11 illustrates a top-gate transistor 1100 using the gate dielectric structure 115D shown in FIG5 , and FIG12 illustrates a top-gate transistor 1200 using the gate dielectric structure 115E shown in FIG6 .

[0033] FIG13 provides a cross-sectional view of an integrated circuit (IC) device 1300 including a bottom gate transistor 1304A, a bottom gate transistor 1304B, and a bottom gate transistor 1304C. Bottom gate transistors 1304A through 1304C are formed on substrate regions 1302A through 1302C, respectively. Substrate regions 1302A through 1302C may be regions of three different substrates or may be different regions on a single substrate 1301. Substrate 1301 may include a semiconductor substrate and may include one or more metal interconnect layers formed thereon. Bottom gate transistors 1304A through 1304C are shown as being formed entirely between metallization layer MX and metallization layer MX+1 of a metal interconnect structure.

[0034] Bottom gate transistors 1304A through 1304C have gate dielectric structures 115F, 115A shown in FIG. 1 , and 115B shown in FIG. 2 , respectively. Gate dielectric structure 115F is similar to gate dielectric structures 115A and 115B, but does not include any buried layer. Gate dielectric structures 115F, 115A, and 115B can all have approximately the same height. Bottom gate transistors 1304A through 1304C can all have approximately the same capacitance and approximately the same footprint, but with significantly different threshold voltages. In some embodiments, the threshold voltage is within a range from approximately 0.1 volt to approximately 20 volts. In some embodiments, the threshold voltage is within a range from approximately 1 volt to approximately 5 volts. As shown in IC device 1300, the buried layer of the present disclosure provides design flexibility and modularity by allowing the threshold voltage to be varied without simultaneously changing transistor width, thickness, or capacitance.

[0035] In some embodiments, the threshold voltage of one of the bottom gate transistors 1304A-1304C is approximately 25% or more greater than the threshold voltage of another of the bottom gate transistors 1304A-1304C. In some embodiments, the threshold voltage of one of the bottom gate transistors 1304A-1304C is approximately 50% or more greater than the threshold voltage of another of the bottom gate transistors 1304A-1304C. In some embodiments, the threshold voltage of one of the bottom gate transistors 1304A-1304C is twice or more the threshold voltage of another of the bottom gate transistors 1304A-1304C.

[0036] FIG14 provides a cross-sectional view of an integrated circuit (IC) device 1400 including top gate transistors 1404A, 1404B, and 1404C. Top gate transistors 1404A through 1404C are formed on substrate regions 707A through 707C, respectively. Substrate regions 707A through 707C can be regions of three different substrates or can be different regions on a single semiconductor substrate 707. In the case of different substrates, IC device 1400 can represent three different devices produced in a single foundry under a set of process constraints. In some embodiments, semiconductor substrate 707 is a P-type substrate. In some embodiments, semiconductor substrate 707 is an N-type substrate.

[0037] Top gate transistors 1404A through 1404C have gate dielectric structures 115F, 115A shown in FIG. 7 , and 115B shown in FIG. 8 , respectively. Gate dielectric structure 115F is similar to gate dielectric structures 115A and 115B, but does not include any buried layer. Top gate transistors 1404A through 1404C may all have approximately the same capacitance and approximately the same footprint, but with significantly different threshold voltages. In some embodiments, the voltage is in a range from approximately 0.1 volt to approximately 20 volts. In some embodiments, the voltage is in a range from approximately 1 volt to approximately 5 volts. As shown in IC device 1400 , the buried layers of the present disclosure provide design flexibility and modularity for both top and bottom gate transistors. The direction of the change in threshold voltage caused by the insertion of one or both of the buried layer 109 and the second buried layer 209 will vary depending on the doping type of the semiconductor substrate 707 .

[0038] In some embodiments, the threshold voltage of one of the top gate transistors 1404A-1404C is approximately 25% or more greater than the threshold voltage of another of the top gate transistors 1404A-1404C. In some embodiments, the threshold voltage of one of the top gate transistors 1404A-1404C is approximately 50% or more greater than the threshold voltage of another of the top gate transistors 1404A-1404C. In some embodiments, the threshold voltage of one of the top gate transistors 1404A-1404C is twice or more the threshold voltage of another of the top gate transistors 1404A-1404C.

[0039] Figures 15 through 30 are cross-sectional views illustrating a method for forming an IC device having a transistor according to the present disclosure according to the present disclosure. Although Figures 15 through 30 are described with reference to various embodiments of the method, it should be understood that the structures shown in Figures 15 through 30 are not limited to the method and may exist independently of the method. Figures 15 through 30 are described as a series of actions. In other embodiments, the order of these actions may be varied. Although Figures 15 through 30 illustrate and describe a particular set of actions, some actions may be omitted in other embodiments. Furthermore, other embodiments may include actions not shown and / or described. Although the method shown in Figures 15 through 30 is described with respect to forming the IC device 1300 shown in Figure 13 or similar devices, the method and its variations may be used to form other IC devices.

[0040] As shown in cross-sectional view 1500 of FIG. 15 , the method may first form a metallization layer MX on substrate 1301. X is a number greater than or equal to 1, and substrate 1301 has X-1 metallization layers below metallization layer MX. Metallization layer MX includes metal lines 1305, 1305B, and 1305C, respectively, located above substrate regions 1302A through 1302C. Metal lines 1305, 1305B, and 1305C are surrounded by interlayer dielectric 1303 and are used to contact bottom electrodes. Alternatively, bottom electrode vias may be formed and used to fabricate the contacts.

[0041] As shown in cross-sectional view 1600 of FIG16 , a gate stack 1601 can be formed over substrate regions 1302A, 1302B, and 1302C. Gate stack 1601 includes layers corresponding to transistor 200 shown in FIG2 . Gate stack 1601 includes an electrode layer 1603, a gate dielectric layer 1605, a second buried layer 1604, a second thin gate dielectric layer 1608, a first buried layer 1606, a first thin gate dielectric layer 1610, a channel layer 1607, and a hard mask layer 1609. The deposition process can be atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), similar processes, or combinations thereof. In some embodiments, second buried layer 1604, second thin gate dielectric layer 1608, first buried layer 1606, and first thin gate dielectric layer 1610 are formed by ALD. ALD precisely controls the thickness of these layers.

[0042] 17, a mask 1701 is formed while etching away the gate stack 1601 from the base regions 1302A and 1302B and is used to cover the base region 1302C. After etching, the mask 1701 is stripped off.

[0043] As shown in cross-sectional view 1800 of FIG18 , a gate stack 1801 is formed on the structure shown in cross-sectional view 1700 of FIG17 . Gate stack 1801 is formed in substrate region 1302C above gate stack 1601. Gate stack 1801 includes layers corresponding to transistor 100 shown in FIG1 . Gate stack 1801 includes an electrode layer 1803, a gate dielectric layer 1805, a first buried layer 1806, a first thin gate dielectric layer 1810, a channel layer 1807, and a hard mask layer 1809.

[0044] As shown in cross-sectional view 1900 of FIG19 , a mask 1901 is formed while etching away gate stack 1801 from base regions 1302A and 1302C, and is used to cover base region 1302B. Above base region 1302C, the etching stops on hard mask layer 1609. After etching, mask 1901 is stripped off.

[0045] As shown in the cross-sectional view 2000 of Figure 20, a gate stack 2001 is formed on the structure shown in the cross-sectional view 1900 of Figure 19. The gate stack 2001 includes an electrode layer 2003, a gate dielectric layer 2005, a channel layer 2007, and a hard mask layer 2009.

[0046] As shown in cross-sectional view 2100 of FIG21 , while etching away gate stack 2001 from substrate regions 1302B and 1302C, a mask 2101 is formed and used to pattern bottom gate transistor 1304A from gate stack 2001 in substrate region 1302A. Above substrate region 1302B, the etching stops on hard mask layer 1809. Above substrate region 1302C, the etching stops on hard mask layer 1609. Patterning bottom gate transistor 1304A includes patterning bottom gate electrode 113A from electrode layer 2003, patterning gate dielectric 111A from gate dielectric layer 2005, and patterning channel layer 107A from channel layer 2007.

[0047] As shown in the cross-sectional view 2200 of FIG22 , a mask 2209 is formed and used to pattern the gate stack 1801 in the base region 1302B while covering the base regions 1302A and 1302C. In the base region 1302B, etching defines the bottom gate transistor 1304B. Defining the bottom gate transistor 1304B includes patterning a bottom gate electrode 113B from the electrode layer 1803, patterning a gate dielectric 111B from the gate dielectric layer 1805, patterning a buried layer 109B from the first buried layer 1806, patterning a thin layer 110 from the first thin gate dielectric layer 1810, and patterning a channel layer 107B from the channel layer 1807.

[0048] As shown in the cross-sectional view 2300 of FIG. 23 , a mask 2301 is formed and the gate stack 1601 is patterned in the base region 1302C while covering the base regions 1302A and 1302B using the mask 2301 . In the base region 1302C, etching defines a bottom gate transistor 1304C. Defining the bottom gate transistor 1304C includes patterning a bottom gate electrode 113C from the electrode layer 1603, patterning a gate dielectric 111C from the gate dielectric layer 1605, patterning a second buried layer 209C from the second buried layer 1604, patterning a second thin layer 210C from the second thin gate dielectric layer 1608, patterning a first buried layer 109C from the first buried layer 1606, patterning a first thin layer 110C from the first thin gate dielectric layer 1610, and patterning a channel layer 107C from the channel layer 1607. Given the similarities between the gate stack 1801 and the gate stack 1601, the etching of FIG. 22 and the etching of FIG. 23 can be combined into a single patterning process.

[0049] As shown in cross-sectional view 2400 of FIG. 24 , sidewall spacers 1307 may be formed around bottom gate transistors 1304A, 1304B, and 1304C. Sidewall spacers 1307 may be nitride, carbide, oxide, similar materials, combinations thereof, or any other suitable dielectric structure. Sidewall spacers 1307 may be formed by deposition followed by etching. The spacer material may be deposited by CVD, PVD, or similar processes.

[0050] As shown in cross-sectional view 2500 of FIG. 25 , an anti-reflective coating (ARC) 2501 or other suitable filler material is deposited over the structure shown in cross-sectional view 2400 of FIG. ARC 2501 fills the gaps between bottom gate transistors 1304A, 1304B, and 1304C. Planarization may then be performed, as shown in cross-sectional view 2600 of FIG. 26 . The planarization process may be chemical mechanical polishing (CMP) or a similar process. Planarization removes hard mask layers 1609, 1809, and 2009. After planarization, ARC 2501 is stripped off, as shown in cross-sectional view 2700 of FIG. 27 .

[0051] As shown in cross-sectional view 2800 of FIG. 28 , an ILD layer 103 may then be deposited. The ILD layer 103 may be silicon oxide (SiO), a low-κ dielectric, a similar material, or any other suitable dielectric. The ILD layer 103 may be formed by CVD, PVD, or any other suitable process. As shown in cross-sectional view 2900 of FIG. 29 , a mask 2901 may be formed and used to etch openings 2903 in the ILD layer 103. As shown in cross-sectional view 3000 of FIG. 30 , the openings 2903 may be filled with a conductive material to form the source region 101 and the drain region 105. The conductive material may be a metal, a similar material, or any other suitable conductive material.

[0052] An interlayer dielectric layer 1311, vias 1309, and a metallization layer MX+1 may be formed over the structure shown in cross-sectional view 3000 of Figure 30 to produce an IC device similar to IC device 1300 shown in Figure 13. Vias 1309 couple source region 101 and drain region 105 to metal lines 1314 in metallization layer MX+1.

[0053] Figures 31-41 are cross-sectional views illustrating a method for forming an IC device having a top-gate transistor according to the present disclosure. Although Figures 31-41 are described with reference to various embodiments of the method, it should be understood that the structures shown in Figures 31-41 are not limited to the method and can exist independently of the method. Figures 31-41 are described as a series of actions. In other embodiments, the order of these actions may be varied. Although Figures 31-41 illustrate and describe a particular set of actions, some actions may be omitted in other embodiments. Furthermore, other embodiments may include actions not shown and / or described. Although the method of Figures 31-41 is described with reference to forming the IC device 1400 shown in Figure 14 or similar devices, the method and its variations can be used to form other IC devices.

[0054] As shown in the cross-sectional view 3100 of FIG31 , the process begins by forming a gate stack 3101 on the semiconductor substrate 707. The gate stack 3101 includes layers corresponding to the top gate transistor 800 shown in FIG8 . The gate stack 3101 includes a first thin gate dielectric layer 3110, a first buried layer 3106, a second thin gate dielectric layer 3108, a second buried layer 3104, a gate dielectric layer 3105, an electrode layer 3103, and a hard mask layer 3109. These layers can be formed by PVD, CVD, ALD, similar processes, or any other suitable process.

[0055] 32, a mask 3201 may be used to cover the base region 707C while the gate stack 3101 is etched away from the base region 707A and the base region 707B. After etching, the mask 3201 is stripped off.

[0056] As shown in cross-sectional view 3300 of FIG33 , a gate stack 3301 is formed on the structure shown in cross-sectional view 3200 of FIG32 . Gate stack 3301 includes layers corresponding to top gate transistor 700 shown in FIG7 . Gate stack 3301 includes a first thin gate dielectric layer 3310, a first buried layer 3306, a gate dielectric layer 3305, an electrode layer 3303, and a hard mask layer 3309.

[0057] As shown in cross-sectional view 3400 of FIG34, a mask 3401 can be used to cover base region 707B while etching away gate stack 3301 from base region 707A and base region 707C. After etching, mask 3401 is stripped off.

[0058] As shown in cross-sectional view 3500 of FIG35 , a gate stack 3501 is formed on the structure shown in cross-sectional view 3200 of FIG32 . Gate stack 3501 includes layers corresponding to top gate transistor 700 shown in FIG7 . Gate stack 3501 includes a gate dielectric layer 3505, an electrode layer 3503, and a hard mask layer 3509.

[0059] As shown in cross-sectional view 3600 of FIG36 , while etching away gate stack 3501 from base region 707B and base region 707C, mask 3601 is used to pattern top gate transistor 1404A from gate stack 3501 in base region 707A. After etching, mask 3601 is stripped off.

[0060] As shown in cross-sectional view 3700 of FIG37 , mask 3701 is used to pattern output transistor 1404B from gate stack 3301 in base region 707B and output transistor 1404C from gate stack 3101 in base region 707C, while simultaneously covering top gate transistor 1404A in base region 707A. After patterning, mask 3701 is peeled off.

[0061] As shown in cross-sectional view 3800 of FIG. 38 , sidewall spacers 705 may be formed around top gate transistors 1404A, 1404B, and 1404C. Sidewall spacers 705 may be nitride, carbide, oxide, similar materials, combinations thereof, or any other suitable dielectric. Sidewall spacers 705 may be formed by deposition followed by etching. The spacer material may be deposited by CVD, PVD, or similar processes.

[0062] 39, the source region 701 and the drain region 703 may be formed by doping the semiconductor substrate 707 in a manner aligned with the sidewall spacers 705. The doping may include ion implantation followed by annealing.

[0063] As shown in cross-sectional view 4000 of Figure 40, an ILD layer 715 may be deposited over the structure shown in cross-sectional view 3900 of Figure 39. As shown in cross-sectional view 4100 of Figure 41, planarization may then be used to remove hard mask layers 3109, 3309, and 3509.

[0064] FIG42 presents a flow chart of a process 4200 that can be used to form an IC device having a bottom-gate transistor according to the present disclosure. Although process 4200 of FIG42 is shown and described herein as a series of acts or events, it should be understood that the order in which these acts or events are shown should not be construed as limiting. For example, some acts may occur in a different order and / or concurrently with other acts or events than those shown and / or described herein. Furthermore, not all shown acts are required to implement one or more aspects or embodiments described herein, and one or more of the acts illustrated herein may be performed in one or more separate acts and / or stages.

[0065] The process 4200 may begin with action 4201 (front end of line (FEOL) processing) and may continue with action 4203, which forms several metallization layers. An example is provided by the cross-sectional view 1500 of FIG. 15 .

[0066] Act 4205 forms a first gate stack. The first gate stack and all other depositions extend over the first, second, and third regions of the substrate. Forming the first gate stack includes: Act 4207, forming a bottom electrode layer; Act 4209, forming a gate dielectric layer; Act 4219, forming a channel layer; and Act 4221, forming a hard mask layer. Act 4205 may optionally include one or more of the following acts: Act 4211, depositing a second buried layer; Act 4213, depositing a second thin layer; Act 4215, depositing a first buried layer; and Act 4217, depositing a first thin layer. Depositing the thin layer may include depositing a few angstroms of gate dielectric material. By appropriately selecting from these optional acts, a gate stack corresponding to any of transistors 100, 200, 400, 500, or 600 shown in Figures 1-2 and 4-6 can be formed. Cross-sectional view 1600 of FIG. 16 provides an example of action 4205 .

[0067] Act 4223 is etching away the first gate stack from the first region and the second region. The cross-sectional view 1700 of Figure 17 provides an example.

[0068] Action 4225 forms a second gate stack. Action 4225 is similar to action 4205 but may use different options among the optional steps and may use different layer compositions or thicknesses. Cross-sectional view 1800 of Figure 18 provides an example.

[0069] Act 4227 is etching away the second gate stack from the first region and the third region. The cross-sectional view 1900 of Figure 19 provides an example.

[0070] Action 4229 forms a third gate stack. Action 4229 is similar to action 4205 but may use different options among the optional steps and may use different layer compositions or thicknesses. The cross-sectional view 2000 of Figure 20 provides an example.

[0071] Act 4231 is patterning the third gate stack in the first region while etching away the third gate stack from the second and third regions. The cross-sectional view 2100 of Figure 21 provides an example.

[0072] Action 4233 is patterning the first gate stack in the third region and patterning the second gate stack in the second region. This patterning can be accomplished using one patterning process or two patterning processes. The cross-sectional views 2200 and 2300 of Figures 22 and 23 provide examples.

[0073] Act 4235 is forming a spacer adjacent to a transistor resulting from patterning the first gate stack, the second gate stack, and the third gate stack. An example is provided in cross-sectional view 2400 of FIG.

[0074] Action 4237 is planarization for removing the hard mask layer from the transistors. Prior to planarization, a material is deposited to fill the spaces between the transistors. The filler material can be an ILD layer or a temporary material (e.g., an ARC coating) that can be removed after planarization. Cross-sectional views 2500 to 2700 of Figures 25 to 27 provide examples.

[0075] Act 4239 is to form source and drain regions above the gate electrode of the transistor. This may include depositing an ILD layer, etching openings in the ILD layer, and filling the openings with metal or other conductive material to provide the source and drain regions. Cross-sectional views 2800 to 3000 of Figures 28 to 30 provide examples.

[0076] Act 4241 is to form an upper metallization layer in contact with the source and drain regions. An example of the resulting structure is provided by the IC device 1300 of Figure 13 .

[0077] FIG43 presents a flow chart of a process 4300 that can be used to form an IC device with a top-gate transistor according to the present disclosure. While the process 4300 of FIG43 is shown and described herein as a series of acts or events, it should be understood that the order in which these acts or events are presented should not be construed as limiting. For example, some acts may occur in a different order and / or concurrently with other acts or events than those shown and / or described herein. Furthermore, not all shown acts are required to implement one or more aspects or embodiments described herein, and one or more of the acts depicted herein may be performed in one or more separate acts and / or stages.

[0078] Process 4300 may begin with act 4301 of providing a semiconductor substrate and act 4303 of forming a first gate stack on the substrate. Forming the first gate stack includes: act 4313 of forming a gate dielectric layer; act 4315 of forming an electrode layer; and act 4317 of forming a hard mask layer. Act 4303 may optionally include one or more of the following acts: act 4305 of forming a first thin layer; act 4307 of depositing a first buried layer; act 4309 of depositing a second thin layer; and act 4311 of depositing a second buried layer. Cross-sectional view 3100 in FIG. 31 provides an example. Depositing the thin layer may include depositing a few angstroms of gate dielectric material. By appropriately selecting from these optional acts, a gate stack corresponding to any of transistors 700, 800, 1000, 1100, or 1200 shown in FIG. 7-8 and FIG. 10-12 may be formed.

[0079] Act 4319 is etching away the first gate stack from the first region and the second region. The cross-sectional view 3200 of Figure 32 provides an example.

[0080] Action 4321 is to form a second gate stack. An example is provided in cross-sectional view 3300 of Figure 33. Action 4321 is similar to action 4303 but may use different options among the optional steps and may use different layer compositions or thicknesses.

[0081] Act 4323 is etching away the second gate stack from the first region and the third region. The cross-sectional view 3400 of Figure 34 provides an example.

[0082] Action 4325 is to form a third gate stack. An example is provided in cross-sectional view 3500 of Figure 35. Action 4325 is similar to action 4303 but may use different options among the optional steps and may use different layer compositions or thicknesses.

[0083] Act 4327 is patterning the third gate stack in the first region while etching away the third gate stack from the second and third regions. The cross-sectional view 3600 of Figure 36 provides an example.

[0084] Action 4329 is to pattern the first gate stack in the third region and the second gate stack in the second region. This patterning can be accomplished using one patterning process or two patterning processes. The cross-sectional view 3700 of FIG. 37 provides an example.

[0085] Act 4331 is forming a spacer adjacent to a transistor resulting from patterning the first gate stack, the second gate stack, and the third gate stack. An example is provided in cross-sectional view 3800 of FIG.

[0086] Action 4333 is to perform doping to form source and drain regions aligned with the spacers. The cross-sectional view 3900 of Figure 39 provides an example.

[0087] Act 4335 is depositing an ILD layer over the transistor. The cross-sectional view 4000 of Figure 40 provides an example.

[0088] Action 4337 is the planarization for removing the hard mask layer from the transistor. The cross-sectional view 4100 of Figure 41 provides an example.

[0089] Some aspects of the present disclosure relate to an integrated circuit device including a transistor having a gate electrode, a gate dielectric, and a semiconductor channel. The gate dielectric is located between the gate electrode and the semiconductor channel. A second dielectric layer is embedded in the gate dielectric. The second dielectric layer has a higher dielectric constant than the gate dielectric.

[0090] In some embodiments, the second dielectric layer is closer to the semiconductor channel than to the gate electrode. In some embodiments, the thickness of the second dielectric layer is less than the distance from the second dielectric layer to the gate electrode. In some embodiments, the gate dielectric and the second dielectric layer are oxides. In some embodiments, the gate dielectric is silicon dioxide (SiO2). In some embodiments, the second dielectric layer is a mixture of two dielectrics. The oxygen areal densities of the two dielectrics are either higher than the oxygen areal density of the gate dielectric or lower than the oxygen areal density of the gate dielectric. In some embodiments, the third dielectric layer is embedded in the gate dielectric. The third dielectric layer has a higher dielectric constant than the gate dielectric. In some embodiments, a thin layer of gate dielectric separates the second dielectric layer from the third dielectric layer.

[0091] In some embodiments, the gate dielectric and the second dielectric layer have an electronegativity difference greater than the electronegativity difference between silicon dioxide and hafnium oxide. In some embodiments, the gate dielectric and the second dielectric layer have an oxygen surface density difference greater than the oxygen surface density difference between silicon dioxide and hafnium oxide. In some embodiments, the semiconductor channel is located above the semiconductor channel. In some embodiments, the semiconductor channel is located below the semiconductor channel.

[0092] Some aspects of the present disclosure relate to an integrated circuit device including a transistor having a gate electrode, a gate dielectric structure, and a semiconductor channel. The gate dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is at least half the thickness of the gate dielectric structure and is located between the second dielectric layer and the gate electrode. The second dielectric layer has a higher dielectric constant than the first dielectric layer.

[0093] In some embodiments, the second dielectric layer is spaced apart from the semiconductor channel. In some embodiments, the gate dielectric structure further includes a third dielectric layer. The third dielectric layer has a different composition than the first and second dielectric layers and has a higher dielectric constant than the first dielectric layer. In some embodiments, the third dielectric layer is spaced apart from the second dielectric layer. In some embodiments, the second dielectric layer comprises a mixture of two dielectrics, each of which has a higher dielectric constant than the first dielectric layer.

[0094] Some aspects of the present disclosure relate to an integrated circuit device including a transistor having a gate electrode, a gate dielectric structure, and a semiconductor channel. The gate dielectric structure includes a first dielectric layer and a second dielectric layer. A first interface between the first dielectric layer and the second dielectric layer is closer to the semiconductor channel than to the gate electrode. The composition of the first dielectric layer and the composition of the second dielectric layer form an electric dipole in the gate dielectric structure near the first interface. The electric dipole significantly affects the threshold voltage of the transistor.

[0095] Some aspects of the present disclosure relate to a method for forming a dielectric structure between a semiconductor and a gate electrode. Forming the dielectric structure includes embedding a high-κ dielectric layer within a gate dielectric. The high-κ dielectric layer has a higher dielectric constant than the gate dielectric. In some embodiments, embedding the high-κ dielectric layer within the gate dielectric includes: depositing a first layer of gate dielectric; depositing the high-κ dielectric layer over the first layer; and depositing a second layer of gate dielectric over the high-κ dielectric layer. In some embodiments, the high-κ dielectric layer is thinner than the gate dielectric and closer to the semiconductor.

[0096] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

[0097] 100, 200, 400, 500, 600: transistors 101, 701: Source region 103, 715, 1311: interlayer dielectric (ILD) layer 105, 703: Drain area 107, 107A, 107B, 107C, 1607, 1807, 2007: Channel layer 109, 109B: buried layer 109C, 1606, 1806, 3106, 3306: first buried layer 110: Thin layer 110C: First thin layer 111, 111A, 111B, 111C: Gate dielectric 113, 113A, 113B, 113C: bottom gate electrodes 115A, 115B, 115C, 115D, 115E, 115F: Gate dielectric structure 117A: First interface 117B: Second interface 209, 209C, 1604, 3104: second buried layer 210, 210C: Second thin layer 217A: Third Interface 217B: Fourth Interface 300, 900: area 517: Interface 700, 800, 1000, 1100, 1200, 1404A, 1404B, 1404C: Top-gate transistors 705, 1307: side wall spacers 707: semiconductor substrate 707A, 707B, 707C, 1302A, 1302B, 1302C: basement area 713: Gate electrode 1300, 1400: Integrated circuit (IC) devices 1301: Base 1303: Interlayer dielectric 1304A, 1304B, 1304C: bottom gate transistors 1305, 1305B, 1305C, 1314: Metal wire 1309:Through hole 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, 4000, 4100: Cross-sectional view 1601, 1801, 2001, 3101, 3301, 3501: Gate stacking 1603, 1803, 2003, 3103, 3303, 3503: electrode layer 1605, 1805, 2005, 3105, 3305, 3505: Gate dielectric layer 1608, 3108: second thin gate dielectric layer 1609, 1809, 2009, 3109, 3309, 3509: Hard mask layer 1610, 1810, 3110, 3310: first thin gate dielectric layer 1701, 1901, 2101, 2209, 2301, 2901, 3201, 3401, 3701: screen 2501: Anti-reflective coating (ARC) 2903: Opening 4200, 4300: Process 4201, 4203, 4205, 4207, 4209, 4211, 4213, 4215, 4217, 4219, 4221, 4223, 4225, 4227, 4229, 4231, 4233, 4235, 4237, 4239, 4241, 4301, 4303, 4305, 4307, 4309, 4311, 4313, 4315, 4317, 4319, 4321, 4323, 4325, 4327, 4329, 4331, 4333, 4335, 4337: Action D1, D2: distance MX, MX+1: Metallization layer T 1: Thickness

Claims

1. An integrated circuit device comprising: A transistor having a gate electrode, a gate dielectric and a semiconductor channel, wherein the gate dielectric is located between the gate electrode and the semiconductor channel; and a second dielectric layer embedded in the gate dielectric, wherein the second dielectric layer has a higher dielectric constant than the gate dielectric.

2. The integrated circuit device of claim 1, wherein the second dielectric layer is closer to the semiconductor channel than to the gate electrode.

3. The integrated circuit device according to claim 1, wherein a thickness of the second dielectric layer is smaller than a distance from the second dielectric layer to the gate electrode.

4. The integrated circuit device of claim 1, wherein the gate dielectric and the second dielectric layer comprise oxide.

5. The integrated circuit device of claim 4, wherein the gate dielectric comprises silicon dioxide.

6. The integrated circuit device of claim 1, wherein: The second dielectric layer includes a second dielectric mixed with a third dielectric; and the oxygen surface density of the second dielectric and the oxygen surface density of the third dielectric are in either of the following situations: both of the oxygen surface densities are higher than the oxygen surface density of the gate dielectric or both of the oxygen surface densities are lower than the oxygen surface density of the gate dielectric.

7. The integrated circuit device of claim 1, further comprising a third dielectric layer embedded in the gate dielectric, wherein the third dielectric layer has a higher dielectric constant than the gate dielectric.

8. The integrated circuit device of claim 7, wherein a thin layer of gate dielectric separates the second dielectric layer from the third dielectric layer.

9. The integrated circuit device of claim 1, wherein the gate dielectric and the second dielectric layer have an electronegativity difference greater than an electronegativity difference between silicon dioxide and hafnium oxide.

10. The integrated circuit device of claim 1, wherein the gate dielectric and the second dielectric layer have an oxygen surface density difference that is greater than an oxygen surface density difference between silicon dioxide and hafnium oxide.

11. The integrated circuit device of claim 1, wherein the semiconductor channel is located above the semiconductor channel.

12. The integrated circuit device of claim 1, wherein the semiconductor channel is located below the semiconductor channel.

13. An integrated circuit device comprising: A transistor having a gate electrode, a gate dielectric structure, and a semiconductor channel; wherein the gate dielectric structure comprises a first dielectric layer and a second dielectric layer; The first dielectric layer is at least half the thickness of the gate dielectric structure and is located between the second dielectric layer and the gate electrode; and the second dielectric layer has a higher dielectric constant than the first dielectric layer.

14. The integrated circuit device of claim 13, wherein the second dielectric layer is spaced apart from the semiconductor channel.

15. The integrated circuit device of claim 13, wherein: The gate dielectric structure further includes a third dielectric layer; the third dielectric layer has a composition different from that of the first dielectric layer and the second dielectric layer; and the third dielectric layer has a higher dielectric constant than that of the first dielectric layer.

16. The integrated circuit device of claim 15, wherein the third dielectric layer is spaced apart from the second dielectric layer.

17. The integrated circuit device of claim 15, wherein the second dielectric layer comprises a mixture of two dielectrics, the two dielectrics having a higher dielectric constant than the first dielectric layer.

18. A method comprising: forming a dielectric structure between the semiconductor and the gate electrode; The dielectric structure is formed by embedding a high-k dielectric layer in a gate dielectric. The high-k dielectric layer has a higher dielectric constant than the gate dielectric.

19. The method of claim 18, wherein embedding the high-k dielectric layer within the gate dielectric comprises: depositing a first layer of the gate dielectric; depositing the high-k dielectric layer over the first layer; and depositing a second layer of the gate dielectric on the high-k dielectric layer.

20. The method of claim 19, wherein the high-k dielectric layer is thinner than the gate dielectric, and the high-k dielectric layer is closer to the semiconductor than to the gate electrode.