FPGA-based memory array testing system

Abstract

Disclosed is a memory array testing system based on FPGA, which is used to test a memory that has not been packaged and has not had peripheral circuits added, comprising: an FPGA, which serves as a control module for the entire testing system; an excitation source, which is used to output an operating voltage for a memory cell; a read circuit, which is used to read the resistance value of a selected memory cell; an array gating module, comprising a row gating circuit and a column gating circuit, and used to select a single memory cell in an array; an upper computer, which is used to, according to a user operation, output a pulse width and amplitude of a pulse voltage, a step time, step voltage and number of scanning points of a scanning voltage, and a control signal of a word line and a bit line of a selected memory cell, and present the resistance data received from FPGA in the form of a chart. The present invention constructs a test circuit on a PCB, effectively reducing testing time and improving testing efficiency compared with traditional probe tests, and performs prototype verification before constructing a peripheral integrated circuit for a memory array.

Description

A memory array test system based on FPGA

Technical field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit device testing, and more particularly, relates to a memory array testing system based on FPGA. [Background Technology]

[0002] With the continuous expansion and development of computer applications, people's requirements for memory are also increasing. However, traditional memories such as flash memory, dynamic random access memory (DRAM), and static random access memory (SRAM) have various shortcomings and limitations. Different new-generation memories have their own advantages and characteristics, and their testing requirements are huge. Currently, the more mature technology routes in the field of new non-volatile memory are phase change memory (PCM), magnetic random access memory (MRAM), and resistive random access memory (RRAM). PCM achieves different resistance values ​​by changing the phase state of phase change materials and is mainly used for stand-alone storage. MRAM changes resistance by changing the orientation of magnetic domains in magnetic materials and is mainly used for embedded storage. RRAM achieves resistance change by creating or closing conductive channels in resistive materials.

[0003] In memory, a 1T1R (One Transistor One Resistor) configuration is a memory cell. It consists of one transistor and one resistor. The 1T1R structure is commonly used in two-dimensional planar non-volatile memory technologies, such as resistive random access memory (RRAM) and phase-change memory (PCM). This configuration consists of a transistor as a selector and a resistor as a storage element. A transistor is a three-terminal device that controls read and write operations in a memory cell. It selects a specific memory cell to be accessed and implements read or write operations by controlling current or voltage. The resistor stores information. Applying voltage or current to the resistor changes its resistance state, representing the stored data value. The 1T1R structure is relatively simple and has a small footprint, making it widely used in some new memory technologies. Its low power consumption, high density, and fast read and write speeds make it a promising candidate for next-generation memory technologies.

[0004] The 1S1R (One Selector One Resistance) array is a storage architecture in which each memory cell consists of a storage device and a selection device, and is commonly used in three-dimensional memory architectures. The storage device can be a magnetic memory, resistive memory, phase change memory, ferroelectric memory, etc. The selection device is a two-terminal device, and a bidirectional threshold selection transistor (OTS) can be used. To prevent leakage current from the PCM array, the OTS was introduced into the PCM. The OTS is a two-terminal device based on the Ovsinski threshold conduction theory. When the voltage across it reaches the threshold voltage (Uth), the OTS enters the on state and its resistance decreases rapidly. When the OTS voltage in the on state is higher than the holding voltage (Uhold), the OTS maintains a low-resistance on state.

[0005] Regarding the array structure, the most common crossbar structure is currently adopted, whereby memory cells in the array are selected by word lines and bit lines. This structure requires attention to the crosstalk caused by leakage current generated by the selected cell to the surrounding cells.

[0006] For memory arrays in the lab that haven't been packaged and don't have peripheral circuitry, researchers typically use a probe station. This station typically has four probes, which are placed on electrodes to establish electrical connections with test equipment. However, four probes are too few for memories with multiple word lines and bit lines, and only a small number of memory cells can be tested at a time. This testing method is inefficient and requires repeated lifting and lowering of the probes.

[0007] Nowadays, various new memory technologies are developing rapidly, and the trend of industrialization is becoming increasingly obvious. Whether it is factory production or laboratory research and development, it is necessary to test certain characteristics of the memory array. In addition, the integrated test systems currently on the market also have problems such as high price, low efficiency, foreign imports, and long development cycles. Therefore, the development of a domestic, low-cost, high-performance FPGA-based memory array test system will play an important role in promoting the industrialization of new memories, laboratory research and early product quality testing.

[0008] [Summary of the invention]

[0009] In view of the defects of the prior art, the purpose of the present invention is to provide a memory array test system based on FPGA, so that the memory cells in the array can be correctly selected on a wafer without peripheral circuits and read, erase and write operations can be performed on them.

[0010] The present invention provides a memory array test system based on FPGA, which is used to test a memory that has not been packaged and has no peripheral circuits added, including:

[0011] The FPGA, having a first input end connected to the output end of the host computer, a second input end connected to the output end of the read circuit, a first output end connected to the input end of the excitation source, a second output end connected to the first input end of the read circuit, and a third output end connected to the first input end of the array gating module, serves as the core control unit of the test system, is used to output digital control signals to the analog-to-digital converter ADC, the digital-to-analog converter DAC, the analog switch, and the multiplexer in other modules, receives and analyzes data from the analog-to-digital converter ADC, and can communicate data with the host computer;

[0012] An excitation source, whose output end is connected to the second input end of the array gating module, is used to output an operating voltage and a bias voltage for the memory unit according to parameters set by the host computer;

[0013] a read circuit, a second input terminal of which is connected to the output terminal of the array gating module, for reading the resistance value of the selected memory cell according to the path selected by the array gating module;

[0014] An array gating module is used to distribute read, write, and erase operation voltages to the selected word lines according to control signals, connect the selected bit lines to the read circuit, and distribute bias voltages to all unselected word lines and bit lines;

[0015] The host computer is used to output the pulse width and amplitude of the pulse voltage, the step time, step voltage and number of scan points of the scan voltage, the control signals of the word line and bit line of the selected storage unit according to user operations, and present the resistance data received from the FPGA in the form of a chart.

[0016] Furthermore, the pulse voltage generated by the excitation source can reach the ns level, with a resolution of 5ns, a pulse rise and fall time of about 15ns, and adjustable amplitude and pulse width.

[0017] Furthermore, the excitation source includes: a digital-to-analog converter DAC and a single-pole double-throw analog switch; the input end of the digital-to-analog converter DAC serves as the input end of the excitation source, and is used to receive the voltage amplitude information set by the FPGA output; one end S2 of the single-pole double-throw analog switch is connected to the output end of the digital-to-analog converter DAC, and the other end S1 is grounded, and is used to output an excitation signal according to the voltage pulse waveform generated by the FPGA.

[0018] Furthermore, the array gating module includes: a row gating circuit and a column gating circuit; the row gating circuit is used to connect to the word lines in the array and distribute the read and erase voltages to the word lines selected by the host computer, and distribute the bias voltage to all unselected word lines; the column gating circuit is used to connect to the bit lines in the array and connect the read circuit port or ground to the bit line selected by the host computer, and distribute the bias voltage to all unselected bit lines.

[0019] Furthermore, the row selection circuit and the column selection circuit both include a multiplexer selector and an analog switch; the multiplexer selector is used to distribute the read, write and erase operation voltages to the selected word line according to the control signals for the word line and the bit line, and connect the selected bit line to the read circuit input or ground; the analog switch is used to distribute the bias voltage to all unselected word lines and bit lines according to the control signals for the word line and the bit line.

[0020] Furthermore, the number of channels of the multiplexer matches the number of word lines and bit lines in the array, and the number of interfaces of the analog switch matches the number of word lines and bit lines in the array.

[0021] Furthermore, the reading circuit includes: a sampling resistor, an operational amplifier, a low-pass filter and an ADC connected in sequence; when working, the voltage on the sampling resistor is collected, and the voltage value is amplified by the operational amplifier, and then the noise is filtered out by the low-pass filter. Finally, this voltage is connected to the input port of the ADC, and the read digital signal is transmitted back to the FPGA for processing.

[0022] The resistance of the sampling resistor can be set to 100Ω.

[0023] Furthermore, the memory is electrically connected to the PCB printed circuit board through wire bonding, and the memory array strobe test system is built on the PCB printed circuit board.

[0024] Furthermore, the host computer uses the RS232 serial port to communicate data with the FPGA.

[0025] The above technical solutions conceived by the present invention are compared with the prior art because the test solutions of the existing probe stations are expensive and inefficient. FPGA has rich wiring resources, is reprogrammable and highly integrated. The present invention is based on the construction of a test system for FPGA. It does not need to repeatedly lift and place probes on unpackaged wafers. Wire bonding technology is directly used to connect multiple electrodes to an external PCB. It can select whether to increase bias voltages for unselected word lines and bit lines for different array forms. Therefore, the present invention can achieve low cost, high efficiency, and can test the memory arrays of 1T1R and 1S1R different array forms. The present invention is applicable to the testing of various memory arrays without the addition of peripheral integrated circuits, including but not limited to phase change memory, magnetic random access memory, memristor, ferroelectric memory, etc.

Brief Description of the Drawings

[0026] FIG1 is a schematic structural diagram of a memory array testing system provided by an embodiment of the present invention;

[0027] FIG2 is a schematic structural diagram of an excitation source provided by an embodiment of the present invention;

[0028] FIG3 is a functional block diagram of the ADG752 used in one embodiment of the present invention;

[0029] FIG4 is a timing diagram of relevant control signals and output signal IN of an FPGA in pulse mode according to an embodiment of the present invention;

[0030] FIG5 is a circuit diagram of an excitation source provided by an embodiment of the present invention; wherein (a) is a logic level conversion circuit, (b) is a connection diagram of the selected DAC7621, and (c) is a connection diagram of the selected ADG752;

[0031] FIG6 is a test circuit of a read circuit module provided by an embodiment of the present invention;

[0032] 7 is a schematic structural diagram of a read circuit module provided by an embodiment of the present invention;

[0033] FIG8 is a schematic structural diagram of an array gating module provided in one embodiment of the present invention;

[0034] FIG9 is a software operation interface of the present invention;

[0035] 10 is a test result of a pulse output of a memory array test system according to an embodiment of the present invention;

[0036] 11 is a test result of a continuous SET of an actual phase change memory cell by a memory array test system according to an embodiment of the present invention;

[0037] FIG. 12 is a test result of a scan voltage output of a memory array test system provided by an embodiment of the present invention. [Specific implementation method]

[0038] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0039] The memory array test system provided by the present invention targets unpackaged wafer arrays. By building a test circuit on a PCB, the system eliminates the need for probe lifts and lowers, reducing test time compared to traditional probe testing. Furthermore, the system uses LabVIEW software to power the host computer, enabling automated testing of array-type phase-change memory, improving test efficiency and facilitating prototype verification before peripheral circuitry is built.

[0040] The present invention provides an FPGA-based memory array test system, which can correctly select memory cells in the array and perform read, erase, and write operations on them on a wafer without peripheral circuits. The memory array test system includes:

[0041] FPGA serves as the control module of the entire test system. It is used to receive instructions from the host computer. After judgment, it controls the excitation source to send pulses or scan voltages, controls the selection circuit to select the unit, and can receive data returned by the read circuit, and finally return the value to the host computer.

[0042] The excitation source, used to output operating and bias voltages for the memory cells, includes a DAC and a high-speed single-pole, double-throw analog switch. The excitation source built using this method can output nanosecond-level pulse voltages with a resolution of 5 nanoseconds and a pulse rise and fall time of approximately 15 nanoseconds. It can also output DC voltages or sweep voltages.

[0043] The read circuit includes a sampling resistor, an operational amplifier, a low-pass filter, and an ADC module. The module works as follows: it collects the voltage across the sampling resistor connected in series with the storage unit, amplifies it through an operational amplifier, filters out noise through a low-pass filter, and finally connects this voltage to the ADC input. The resulting digital signal is then transmitted back to the FPGA for processing.

[0044] An array gating module includes a row gating circuit and a column gating circuit. Both gating circuits include a multiplexer selector and an analog switch. The number of channels of the multiplexer selectors in the two gating circuits matches the number of word lines and bit lines in the array, and the number of interfaces of the analog switches in the two gating circuits matches the number of word lines and bit lines in the array. The multiplexer selector is used to distribute read, write, and erase operation voltages to selected word lines and ground the selected bit lines based on control signals for the word lines and bit lines. The analog switch is used to distribute bias voltages to all unselected word lines and bit lines based on control signals for the word lines and bit lines.

[0045] The host computer, written in LabVIEW, communicates with the FPGA via an RS232 serial port. It sends commands and user-configured parameters to the FPGA, such as the width and amplitude of operating pulses, the row and column addresses of the selected array, and the step time, step voltage, and number of scan points for the scan voltage. It also receives cell resistance or current values ​​from the FPGA and provides functions such as graphing and information export.

[0046] As shown in FIG1 , the memory array test system provided by an embodiment of the present invention includes a host computer, an FPGA, an excitation source, a read circuit, and an array gating module. The excitation source is composed of two parts, including a digital-to-analog converter (DAC) and a single-pole double-throw analog switch, and its module schematic is shown in FIG2 .

[0047] The DAC uses the Texas Instruments DAC7621, a 12-bit parallel digital-to-analog converter (DAC) with guaranteed 12-bit monotonic performance over the industrial temperature range. For a full-scale step, the output settles to 1LSB within 7μs. The maximum voltage is 4.095V, meeting the read, erase, and write voltage requirements for phase-change memory.

[0048] The single-pole, double-throw analog switch uses the Analog Devices ADG752, which features low power consumption, high off-state isolation, fast switching speed, and low on-resistance. A functional diagram is shown in Figure 3. The input IN controls the direction of the analog switch, with an on-time of 8 ns and an off-time of 3 ns. These switching times meet subsequent design requirements.

[0049] The digital signal output by the FPGA is connected to the DAC, whose value is converted from the voltage amplitude input by the user through the host computer. The DC voltage output by the DAC is connected to the S2 terminal of the analog switch, the S1 terminal is connected to the ground GND, and the control signal IN is connected to the FPGA. This connection method can output pulse voltages with adjustable amplitude and pulse width, DC voltage, or sweep voltage. The specific implementation method is as follows:

[0050] (1) If the pulse voltage is output, the DAC continuously outputs a voltage of the set amplitude, and the FPGA inputs logic "1" and "0" to the analog switch. When it is logic "0", the switch is directed to the ground GND connected to S1. When it is logic "1", the switch is directed to the DAC connected to S2. Therefore, the FPGA only needs to output a pulse signal with a set pulse width to form a voltage pulse excitation with adjustable pulse width and amplitude at the D end;

[0051] (2) If the output voltage is scanned, the FPGA only outputs logic "1", and the D terminal of the analog switch is always connected to the S2 terminal. Therefore, by simply changing the digital information output by the FPGA, the DAC can form a scan or DC voltage at the D terminal.

[0052] The control signal IN directly affects the pulse width of the output voltage pulse. However, the FPGA's system clock, sys_clk, has a period of 20ns, making pulse voltages with this resolution insufficient for erase and write testing of phase-change memory. Therefore, a phase-locked loop (PLL) IP core is invoked within the FPGA to multiply the system clock to 5ns. Counting is performed based on this multiplied clock, pll_clk. When the start signal goes high, the pulse width control signal IN goes high; when the count reaches the pulse width set by the test user, the pulse width control signal IN goes low. This approach allows the output pulse voltage to achieve a pulse width resolution of 5ns, enabling nanosecond-level adjustment of the pulse voltage. Figure 4 shows the timing diagram of the relevant control signals. When the start signal goes high, the pulse width control signal IN goes high; when the count reaches the pulse width set by the test user, the pulse width control signal IN goes low. This approach allows the output pulse voltage to achieve a pulse width resolution of 5ns, enabling nanosecond-level adjustment of the pulse voltage, facilitating the search for optimal erase and write pulse parameters in phase-change memory testing.

[0053] Figure 5 shows the circuit schematic of the excitation source, where D0_IN to D11_IN represent the 12-bit digital signals output by the FPGA, and VOUT is the output port of the excitation source. The DAC7621's logic input high-level threshold voltage is 0.7 times the supply voltage, or 3.5V. However, the FPGA's maximum output voltage is 3.3V, which cannot exceed this value and is interpreted as a high level. Therefore, logic level conversion is required. Devices A1 and A2 act as level shifters, raising the logic high level to 4.6V. The various control signals output by the level shifters can then be connected to the DAC.

[0054] This embodiment takes the testing of a phase change memory array as an example. The process of achieving phase change is generally to apply an electric pulse signal to the memory cell. For example, applying an electric pulse with a narrow pulse width, high amplitude, and fast falling edge to perform a RESET operation, causing the ordered crystalline phase change material to melt and rapidly cool to a disordered amorphous state, achieving a phase change from a low resistance state "0" to a high resistance state "1"; conversely, applying an electric pulse with a wide pulse width and low amplitude can perform a SET operation on the phase change cell, causing the amorphous phase change material to crystallize into a crystalline state after undergoing an annealing process and achieve a phase change from "1" to "0"; and the specific process of performing a read operation on the phase change memory cell is: applying a very low amplitude electric pulse that has no effect on the state of the phase change material, or applying a low amplitude electric pulse scanning signal, and reading its state by measuring the resistance value of the device. Similarly, it can be seen that the present invention can also be used for testing memories such as memristors, magnetic random access memories, and ferroelectric memories, and this embodiment will not be repeated.

[0055] Resistance measurement is a crucial component of phase-change memory testing. It provides information about the electrical characteristics of a memory cell, including its resistance state (high or low) and its magnitude. The resistance state of a memory cell can be used to determine the information stored within it. Therefore, resistance measurement is an integral part of phase-change memory testing.

[0056] When performing resistance measurements, a test circuit is usually required, as shown in Figure 6. The excitation source needs to apply an electric pulse of appropriate width and small amplitude. Since the state of the phase-change memory cell cannot be changed during reading, a small electric pulse is applied to prevent the heat generated from causing the temperature of the phase-change material to rise above the crystallization temperature.

[0057] In Figure 6, RPCM represents the phase-change memory cell under test, R represents the sampling resistor, V1 represents the voltage emitted by the excitation source, and V2 represents the voltage read by the analog-to-digital converter (ADC) in the read circuit of the test system. The current I flowing through the PCM is: I = V2 / R; the voltage drop across the PCM is: PCM = V1 - V2; and the measured resistance of the PCM under this pulse is: RPCM = VPCM / I. Because the resistance of the phase-change memory is large (in kΩ and MΩ), the voltage divider of V2 can be ignored, so the resistance can be approximately calculated as: RPCM = V1 / I.

[0058] The specific value of the sampling resistor R plays a crucial role in the test circuit. If R is too small, the ripple in the power supply can cause inaccurate voltage measurements at certain magnification ratios. Furthermore, if R is too large, the presence of numerous parasitic factors in the circuit, particularly parasitic capacitance, can slow the pulses acting on the phase-change memory due to RC filtering, significantly impacting memory write operations. In the memory array test system provided in the present invention, a 100Ω sampling resistor is preferred.

[0059] As shown in Figure 7, the read circuit module of the memory array test system provided by an embodiment of the present invention consists of a sampling resistor, an operational amplifier, a low-pass filter, and an ADC. The module operates as follows: it collects the voltage across the sampling resistor, amplifies it through the operational amplifier, filters out noise through a low-pass filter, and finally connects this voltage to the ADC input. The resulting digital signal is then transmitted back to the FPGA for processing.

[0060] Figure 8 is a structural schematic diagram of the array selection module, which includes a row selection circuit and a column selection circuit. Both selection circuits include a multiplexer selector and an analog switch. The number of channels of the multiplexer selectors in the two selection circuits corresponds to the number of word lines and bit lines in the array, and the number of interfaces of the analog switches in the two selection circuits corresponds to the number of word lines and bit lines in the array. Among them, the multiplexer selector is used to distribute the read, write and erase operation voltages to the selected word lines according to the control signal, and connect the selected bit lines to the read circuit; the analog switch is used to distribute the bias voltage to all unselected word lines and bit lines according to the control signal.

[0061] It should be noted that for 1T1R memory, the word line is used to send the excitation signal, and the bit line is used to control the transistor selection. Therefore, the selection can be completed by setting the bias voltage to 0 through the host computer. For 1S1R memory, a bias voltage is added to the unselected word lines and bit lines to control the voltage on the unselected cells to be lower than the threshold voltage of the selection device. This bias voltage is generally half of the operating voltage (Vop). Therefore, the voltage of the selected cell is Vop, the voltage of the remaining cells on the selected word line or bit line is Vop / 2, and the voltage of the cells on the unselected word line and bit line is 0. The Vop value is greater than the threshold voltage of the selection device, and the Vop / 2 value is less than the threshold voltage of the selection device, thus completing the selection function of the array.

[0062] This embodiment adds a host computer using LabVIEW software, which primarily implements FPGA control and communication functions. Testers use a visual software interface to input operating parameters and select word lines and bit lines for cells. Figure 9 shows the software interface. This module is designed to provide convenience for testers and improve the operability of the system.

[0063] The host computer sets the pulse width to 500ns and the amplitude to 2.4V. Figure 10 shows the pulse voltage emitted by this excitation source after receiving the command. The actual pulse measured by an oscilloscope is consistent with the parameters set by the host computer. The pulse high-level duration is 500ns, the maximum voltage is 2.4V, and the rise time from 0V to the maximum voltage is approximately 15ns. This result verifies that the memory array test system provided by this embodiment of the present invention successfully outputs nanosecond-level pulse voltages, and the pulse quality meets the requirements for phase change in phase-change memory cells.

[0064] Figure 11 shows a test of an actual phase change unit using voltage pulses generated by the memory array test system provided by an embodiment of the present invention. The phase change unit was made of GST147 material and subjected to five consecutive SET operations, with continuous input voltage pulse parameters of 1V and 200ns. The initial resistance was approximately 120GΩ. The first SET transformed the resistance of the phase change memory into a crystalline state, and the resistance of the test unit decreased significantly. As the number of SETs increased, the resistance gradually decreased, indicating that the pulses sent successfully caused the memory to undergo a phase change. Furthermore, as the number of pulses increased, the resistance of the memory unit gradually decreased, successfully verifying the communication between the pulse module of the memory array test system provided by an embodiment of the present invention and the host computer, and that the generated programmable pulses successfully caused the phase change unit to undergo a phase change.

[0065] The host computer sets the maximum scanning voltage to 600mV, the number of scanning points to 6, and the scanning step time to 200μs. Figure 12 shows the scanning voltage emitted by this excitation source after receiving the instruction. The actual scanning measured by the oscilloscope is consistent with the parameters set by the host computer. The pulse signal starts at -200μs and increases by 200mV every 200μs, for a total of 6 times, reaching the set maximum voltage of 600mV, and consuming a total of 1200μs. This result verifies that the memory array test system provided by the embodiment of the present invention successfully outputs the scanning voltage and can be used in the resistance reading and IV scanning tests in phase change memory.

[0066] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A memory array test system based on FPGA, used for testing a memory that has not been packaged and has not added peripheral circuits, characterized in that: include: FPGA, a first input end of which is connected to an output end of a host computer, a second input end of which is connected to an output end of a reading circuit, a first output end of which is connected to an input end of an excitation source, a second output end of which is connected to a first input end of the reading circuit, a third output end of which is connected to a first input end of an array gating module, outputs digital control signals for controlling analog-to-digital converters ADC, digital-to-analog converters DAC, analog switches, and multiplexers in other modules, receives and analyzes data from the analog-to-digital converter ADC, and can perform data communication with the host computer; An excitation source, whose output end is connected to the second input end of the array gating module, is used to output an operating voltage and a bias voltage for the memory unit according to parameters set by the host computer; a read circuit, the second input end of which is connected to the output end of the array gating module, for reading the resistance value of the selected storage cell according to the path selected by the array gating module; An array gating module is used to distribute the read, write and erase operation voltages to the selected word lines according to the control signal, connect the selected bit lines to the read circuit, and distribute the bias voltage to all unselected word lines and bit lines; The host computer is used to output the pulse width and amplitude of the pulse voltage, the step time, step voltage and number of scan points of the scan voltage, the control signals of the word line and bit line of the selected storage unit according to the user operation, and present the resistance data received from the FPGA in the form of a chart.

2. The memory array test system according to claim 1, wherein: The pulse voltage generated by the excitation source can reach the ns level, with a resolution of 5ns, a pulse rising edge and falling edge time of about 15ns, and both the amplitude and pulse width can be adjusted.

3. The memory array test system according to claim 2, wherein: The excitation source includes: a digital-to-analog converter DAC and a single-pole double-throw analog switch; The input end of the digital-to-analog converter DAC is used as the input end of the excitation source to receive FPGA outputs the set voltage amplitude information; One end S2 of the single-pole double-throw analog switch is connected to the output end of the digital-to-analog converter DAC, and the other end S1 is grounded, and is used to output an excitation signal according to the voltage pulse waveform generated by the FPGA.

4. The memory array test system according to claim 1, wherein: The array gating module comprises: a row gating circuit and a column gating circuit; The row gating circuit is used to connect to the word lines in the array and distribute the read and erase voltages to the word lines selected by the host computer and the bias voltage to all unselected word lines; The column selection circuit is used to connect with the bit lines in the array, and connect the read circuit port or ground to the bit line selected by the host computer, and the bias voltage is distributed to all unselected bit lines.

5. The memory array test system according to claim 4, wherein: The row gating circuit and the column gating circuit both include a multiplexer selector and an analog switch; The multiplexer selector is used to distribute the read, write and erase operation voltage to the selected word line according to the control signal for the word line and the bit line, and connect the selected bit line to the read circuit input terminal or the ground; The analog switch is used to distribute the bias voltage to all unselected word lines and bit lines according to the control signal for the word lines and bit lines.

6. The memory array test system according to claim 5, wherein: The number of channels of the multiplexer matches the number of word lines and bit lines in the array, and the number of interfaces of the analog switch matches the number of word lines and bit lines in the array.

7. The memory array test system according to any one of claims 1 to 6, characterized in that: The reading circuit comprises: a sampling resistor, an operational amplifier, a low-pass filter and an analog-to-digital converter ADC connected in sequence; When working, the voltage on the sampling resistor is collected and amplified by the operational amplifier. The noise is then filtered out by a low-pass filter. Finally, the voltage is connected to the input port of the analog-to-digital converter ADC, and the digital signal is read and transmitted back to the FPGA for processing.

8. The memory array test system according to claim 7, characterized in that: The resistance of the sampling resistor is 100Ω.

9. The memory array test system according to any one of claims 1 to 6, characterized in that: The memory is electrically connected to a PCB printed circuit board through wire bonding, and the memory array strobe test system is built on the PCB printed circuit board.

10. The memory array test system according to claim 1, characterized in that: The host computer uses the RS232 serial port to communicate data with the FPGA.

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