Hyper-multiplexed homodyne photonic circuits for high-throughput, energy-efficient tensor processing

Abstract

The increase of use of neural networks demands computing power. Optical computing can improve the computing power by orders of magnitude compared to digital electronics. Scalability of existing optical computing architectures is limited by the large number of device counts, energy cost in electro-optic (EO) input / output (I / O) conversion, device fabrication errors, etc. In some embodiments, a photonic circuit architecture employs a unique combination of space-, time-, and wavelength-multiplexing, based on optical interference of laser fields in homodyne coherent detection. Homodyne photonic meshes provide high density integration in an on-chip two-dimensional layout, where the computing energy cost is amortized by beam splitting (data copying) and time accumulation. System analysis (with feasible parameters) predicts a 1000-fold improvement in computing power, energy efficiency and computing density over state-of-the-art processors.

Description

OPU-00125 HYPER-MULTIPLEXED HOMODYNE PHOTONIC CIRCUITS FOR HIGH- THROUGHPUT, ENERGY-EFFICIENT TENSOR PROCESSING CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 544,122, filed October 13, 2023, which is hereby incorporated by reference in its entirety. BACKGROUND OF THE DISCLOSED SUBJECT MATTER

[0002] Deep learning methods and many optimization problems (e.g., travel planning, route planning) may be decomposed to large-scale matrix computations. The operation of matrix multiplications is a memory intensive operation that requires large amounts of data communications between memory and processors. In electronic computing, however, moving data on a chip requires charging electronic wires because of wire capacitance, which generates energy dissipation. Wire capacitance sets critical bottlenecks on the computing clock rates (~1 GHz), energy efficiency (~1 pJ / operation) and throughput density on chip (<1 TeraOP s-1mm-2).

[0003] New physics can be employed to overcome these bottlenecks. Optical computing offers the possibility of orders of magnitude improvement of computing power and energy efficiency, due to the ultra-broadband optical bandwidth (10’s THz) and nearly lossless data movement. However, due to the large device footprint and energy consumption in electro-optic data conversion (e.g., high-speed data encoding and readout), the performance of existing optical computing systems still does not compare favorably to electronic circuits. SUMMARY OF THE DISCLOSED SUBJECT MATTER FH12548482.1OPU-00125

[0004] In some embodiments, a method includes encoding a first subtensor of weight tensor into a first plurality of coherent light signals. Each of the first plurality of coherent light signals represent a scalar of the first subtensor, thereby spatially multiplexing the first subtensor. The method further includes encoding a second subtensor of an input tensor into a second plurality of coherent light signals. Each of the second plurality of coherent light signals representing a scalar of the second subtensor, thereby spatially multiplexing the second subtensor. The method further includes directing the first and second plurality of coherent light signals to a plurality of homodyne detectors. Each of the homodyne detectors is configured to detect an interference between a unique pair of one of the first plurality and one of the second plurality of coherent light signals. The method further includes integrating the interferences detected by the plurality of homodyne detectors to determine a photo- voltage representing a scalar component of a tensor multiplication result. The first plurality of coherent light signals and the second plurality of coherent light signals can be each multiplexed in one or more of time and wavelength.

[0005] In some embodiments, the first plurality of coherent light signals is multiplexed, in the time domain, into a first plurality of time channels. The second plurality of coherent light signals are multiplexed, in the time domain, into a second plurality of time channels. The method can further include iterating, for each of the first plurality of time channels and the second plurality of time channels, encoding the weight matrix, encoding the input tensor, and integrating the plurality of interferences. The amount of the first plurality of time channels and second plurality of time channels is proportional to a common dimension of the weight tensor and input tensor (e.g., the common dimension of a input tensor X with dimensions j x k and weight tensor k x i being the common dimension k, however, the respective matrices may be transposed as is known in the art such that the rows and columns of each tensor may be flipped). -2- FH12548482.1OPU-00125

[0006] In some embodiments, the first plurality of coherent light signals provides a first plurality of wavelength channels separated by wavelength multiplexing and the second plurality of coherent light signals provides a second plurality of wavelength channels separated by wavelength multiplexing. Further, integrating the plurality of interferences further includes integrating interferences measured at the respective overlap of each the first plurality of wavelength channels and the second plurality of wavelength channels.

[0007] In some embodiments, the first plurality of coherent light signals and second plurality of coherent light signals employ a mode spacing of at least 100 GHz between each wavelength channel of the first plurality of wavelength channels and second plurality of wavelength channels.

[0008] In some embodiments, the first plurality of coherent light signals is multiplexed, in the time domain, into a first plurality of time channels, and the second plurality of coherent light signals are multiplexed, in the time domain, into a second plurality of time channels. The first plurality of time channels is multiplexed into a plurality of respective wavelength channels for each of the first plurality of time channels, and the second plurality of time channels are multiplexed into a plurality of respective wavelength channels for each of the second plurality of time channels. The method can further include iterating, for each of the first plurality of respective wavelength channels and second plurality of respective wavelength channels of each of the first plurality of time channels and second plurality of time channels, encoding the weight tensor, encoding the input tensor, and integrating the plurality of interferences.

[0009] In some embodiments, encoding the input tensor and encoding the weight tensor is performed by a digital to analog converter (DAC). The DAC can be an optical modulator, a ring modulator, a micro-ring modulator, a Mach-Zehnder micro-ring modulator, and / or a chirp-free micro-ring modulator. -3- FH12548482.1OPU-00125

[0010] In some embodiments, integrating the plurality of interferences further integrates each interference measured by a homodyne detector of a homodyne detector array. The homodyne detector array is configured to match path length and the optical loss of the first and second pluralities of coherent light signals at each respective homodyne detector of the array.

[0011] In some embodiments, a system includes at least one coherent light source configured generate a first plurality of coherent light signals and a second plurality of coherent light signals. The system also includes a plurality of digital to analog converters (DAC) configured to encode a first subtensor from a weight tensor into the first plurality of coherent light signals and encode a second subtensor from an input tensor into the second plurality of coherent light signals. Each of the first plurality of coherent light signals represents a scalar of the first subtensor, thereby spatially multiplexing the first subtensor. Each of the second plurality of coherent light signals represents a scalar of the second subtensor, thereby spatially multiplexing the second subtensor. The system further includes a plurality of homodyne detectors. The system further includes an optical waveguide configured to direct the first and second plurality of coherent light signals to the plurality of homodyne detectors. Each of the plurality of homodyne detectors is configured to detect an interference between a unique pair of one of the first plurality and one of the second plurality of coherent light signals. The system further includes a capacitor configured to integrate the interferences detected by the plurality of homodyne detectors to determine a photo-voltage representing a scalar component of a tensor multiplication result. The first plurality of coherent light signals and the second plurality of coherent light signals are each multiplexed in one or more of time and wavelength.

[0012] In some embodiments, the first plurality of coherent light signals is multiplexed, in a time domain, into a first plurality of time channels, and second plurality of -4- FH12548482.1OPU-00125 coherent light signals are being multiplexed, in the time domain, into a second plurality of time channels. The system further includes a capacitor configured to additively store photo- voltages representing a plurality of interferences integrated by the homodyne detector after, for each of the first plurality of time channels and second plurality of time channels, iteratively encoding the weight tensor, encoding the input tensor, and integrating the plurality of interferences. The amount of the first plurality of time channels and second plurality of time channels is proportional to a common dimension of the weight tensor and input tensor (e.g., the common dimension of a input tensor X with dimensions j x k and weight tensor k x i being the common dimension k, however, the respective matrices may be transposed as is known in the art such that the rows and columns of each tensor may be flipped).

[0013] In some embodiments, the DAC converters are configured to encode a first plurality of wavelength channels separated by wavelength multiplexing within each of the coherent light signals of the first plurality of coherent light signals and configured to encode a second plurality of wavelength channels separated by wavelength multiplexing within each of the coherent light signals of the second plurality of coherent light signals. The homodyne detectors of the homodyne detector array are configured to integrate interferences measured at the respective overlap of each of the first plurality of wavelength channels and the second plurality of wavelength channels.

[0014] In some embodiments, the first plurality of coherent light signals and second plurality of coherent light signals employ a mode spacing of at least 100 GHz between each wavelength channel of the respective first plurality of wavelength channels and second plurality of wavelength channels.

[0015] In some embodiments, the first plurality of coherent light signals is multiplexed, in the time domain, into a first plurality of time channels, and the second plurality of coherent light signals are multiplexed, in the time domain, into a second plurality -5- FH12548482.1OPU-00125 of time channels. The first plurality of time channels is multiplexed into a plurality of respective wavelength channels for each of the first plurality of time channels, and the second plurality of time channels are multiplexed into a plurality of respective wavelength channels for each of the second plurality of time channels. The system further includes a capacitor configured to additively store photo-voltages representing plurality of interferences integrated by the homodyne detectors of homodyne detector array after iteratively, for each of the first plurality of respective wavelength channels and second plurality of respective wavelength channels of each of the first plurality of time channels and second plurality of time channels, encoding the weight tensor, encoding the input tensor, and integrating the plurality of interferences.

[0016] In some embodiments, the DAC can be an optical modulator, a ring modulator, a micro-ring modulator, a Mach-Zehnder micro-ring modulator, and / or a chirp- free micro-ring modulator.

[0017] In some embodiments, the homodyne detector array is configured to match path length and the optical loss of the first and second pluralities of coherent light signals at each respective homodyne detector of the array.

[0018] In some embodiments, the system further includes a beam splitter arranged with one or more of the at least one coherent light source. The beam splitter is configured to split a coherent light signal emitted from the at least one coherent light source into the first plurality of coherent light signals and a second plurality of coherent light signals.

[0019] In some embodiments, the system includes a complementary metal-oxide- semiconductor (CMOS) chip. The at least one coherent light source, the plurality of DACs, and the homodyne detector array reside on the CMOS chip. -6- FH12548482.1OPU-00125

[0020] In some embodiments of the method or the system, the weight tensor is a matrix. In some embodiments of the method or system, the first subtensor is a row or column of the weight tensor.

[0021] In some embodiments of the method or system, the input tensor is a matrix. In some embodiments of the method or system, the second subtensor is a row or column of the input matrix. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] A detailed description of various aspects, features, and embodiments of the subject matter described herein is provided with reference to the accompanying drawings, which are briefly described below. The drawings are illustrative and are not necessarily drawn to scale, with some components and features being exaggerated for clarity. The drawings illustrate various aspects and features of the present subject matter and may illustrate one or more embodiment(s) or example(s) of the present subject matter in whole or in part.

[0023] Fig. 1 is a graph illustrating a comparison of a various computing systems with regard to computing power, throughput density, and energy efficiency.

[0024] Figs. 2A-C is a diagram of a general deep learning model with matrix-matrix multiplication for batch operations.

[0025] Fig. 3 is a block diagram illustrating an exemplary photonic processor according to embodiments of the present disclosure.

[0026] Figs. 4A-D are diagrams illustrating embodiments of spatial-time multiplexing according to the present disclosure.

[0027] Figs. 5A-D are diagrams illustrating exemplary embodiments of spatial-time- wavelength multiplexing according to the present disclosure. -7- FH12548482.1OPU-00125

[0028] Fig. 6 is a diagram illustrating use of optical hybrids within a homodyne detector mesh according to the present disclosure.

[0029] Figs. 7A-C are diagrams illustrating high energy efficiency broadband Optical frequency combs using coupled SiN microresonator(s) according to the present disclosure.

[0030] Figs. 8A-B are diagrams illustrating exemplary embodiments of chirp free optical digital-to-analog converters (ODACs) according to the present disclosure.

[0031] Figs. 9A-B are diagrams illustrating exemplary embodiments of chirp free optical digital-to-analog converters (ODACs) according to the present disclosure.

[0032] Fig. 10 is a diagram illustrating a computing node according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0033] Disclosed herein are architectural designs of an optical circuit that provides one or more advantages over current solutions.

[0034] A neural network is a collection of one or more neurons. A neural network is often divided into groups of neurons called layers. A layer is a collection of one or more neurons that all receive input from the same layers and all send output to the same layers, and typically perform a similar function. An input layer is a layer that receives input from a source outside the neural network. An output layer is a layer that sends output to a target outside the neural network. All other layers are intermediate processing layers. A multilayer neural network is a neural network with more than one layer. A deep neural network is a multilayer neural network with many layers.

[0035] Arrays of neural processing units, called neural cores, provide an architecture to execute various types of neural networks and deep neural networks. A variety of core architectures are suitable for implementing neural network computations. In general, such -8- FH12548482.1OPU-00125 computations involve computing neuron activations based on input values, synaptic weights, and neural activation functions. It will be appreciated that neuron activations may be distributed in various ways, including via an on-chip network. Various examples herein refer to neuron activations transmitted over a network, however, it will be appreciated that the present disclosure applies more generally to any neurosynaptic systems, including GPUs and specialized ASIC chips, and to neuron activations irrespective of transport mechanism.

[0036] According to various embodiments of the present disclosure, a neural program represents a neural network. A neural program includes information relating to the neural network. In some embodiments, the information includes neuronal properties and dynamics that determine an electronic neuron’s response to input neuron activations. For example, neuronal properties and dynamics can include a threshold parameter, a leak parameter, a delay parameter, or a reset parameter. In some embodiments, the neural program information includes synaptic connections of the neuron (e.g., synaptic connections made via a synaptic weight matrix). In some embodiments, the neural program information includes axon properties (e.g., axon types). In some embodiments, the neural program information includes one or more destinations (e.g., target axons) that the neuron’s output activation should be delivered to.

[0037] According to various embodiments, a neural network represents an instantiation of a neural program. A neural network may be instantiated in hardware, in simulation or in both. For example, a neural program may give rise to one or more instances of a neural network, wherein the instances may reside on a single core, multiple cores, or multiple chips. While typically a neural network has existed on electronic circuits, disclosed herein are methods and corresponding systems for implementing neural network architecture using optical circuits / design. -9- FH12548482.1OPU-00125

[0038] Fig. 1 is a graph 100 illustrating a comparison of an exemplary system according to the present disclosure to alternative computing systems in the metrics of in computing power, throughput density, and energy efficiency. Chen, Nat. Photon, 2023 (“Chen”), Ashtiani, Nat. 2022 (“Ashtiani”), Xu Nature, 2021 (“Xu”), and Feldmann, Nature 2021 (“Feldmann”) describe exemplary alternative computing systems. Throughput of NVIDIA is illustrated by 106t, throughput of Graphcore is illustrated by 110t, throughput of Google TPU is illustrated by 108t, throughput of Xu is illustrated by 112t, throughput of Ahstiani is illustrated by 114t. Density of NVIDIA is illustrated by 106d, density of Graphcore is illustrated by 110d, density of Google TPU is illustrated by 108d, density of Xu is illustrated by 112d, density of Ahstiani is illustrated by 114d. Chen, NVIDIA, Graphcore, and Google TPU are 6 bit systems. Xu and Ashtiani are 4–5-bit systems. The system of the present disclosure, in some embodiments, is a 9-bit system. Of existing systems, Chen’s free- space homodyne computing system has demonstrated the best-in-class throughput / energy efficiency (Ⓣ) (100x) 104t and throughput density (Ⓓ) 104d (20x). Embodiments of the system and method disclosed herein surpass Chen’s system in both metrics.

[0039] Table 1A illustrates examples of approaches to optical computation, including MZI mesh, Silicon attenuators, Chromatic dispersion, Homodyne VCSEL arrays, and PCM beam combining crossbars. A person of ordinary skill in the art can understand the following acronyms and abbreviations:

[0040] MVM: matrix-vector multiplication.

[0041] VVM: vector-vector multiplication.

[0042] MMM: matrix-matrix multiplication.

[0043] PCM: phase-change material.

[0044] MZI: Mach–Zehnder interferometer. -10- FH12548482.1OPU-00125Table 1A – Exemplary optical computing architectures.

[0045] Embodiments of the present disclosure employ a combination of spectral, temporal, and spatial multiplexing for massively parallel processing to improve the throughput. The comparison between the architecture and various alternative techniques is summarized in Table 1B, and detailed below: 1) Time-, space-, and wavelength-multiplexing enables high computing parallelism for matrix-matrix multiplication. A person of ordinary skill in the art can understand that time-multiplexing can be referred to as temporal multiplexing, space-multiplexing can be referred to as spatial multiplexing, and wavelength-multiplexing can be referred to as frequency multiplexing. 2) Low energy consumption in data input / output (I / O) operations using on-chip beam splitting and time integration. 3) System simplicity with low device counts due to time-domain data encoding. 4) The system is compatible with standard foundry process for large-scale production. 5) The system of the present disclosure further implements a high integration density. Wavelength-selective micro-rings do not require additional wavelength-division- multiplexing (WDM) components that takes up a large chip area. In addition, all the optical modulators in the disclosed system can be single-wavelength ring-based -11- FH12548482.1OPU-00125 optical modulators. Ring-based optical modulators are much smaller than broadband modulators. 6) Coherent detection allows complex value operations, which are required for multi- scale system simulation. 7) Both the input matrix and the weight matrix can be programmed and updated in real- time, which is suited for neural network training. Table 1B – Alternative optical computing approaches compared to the disclosed system and method

[0046] In some embodiments, the tensor cores disclosed herein can be employed for machine learning acceleration. However, in some embodiments, it can be used in any application that requires matrix multiplication.

[0047] Existing electronic processors compute matrix-vector multiplication, where the weight matrix multiplies one input vector at a time. In contrast, the present tensor core operates matrix-matrix multiplication, which processes K vectors in parallel.

[0048] Figs. 2A-C are diagrams illustrating an example embodiment of matrix multiplication for a machine-learning system. Fig. 2A is a diagram 200 illustrating an N-layer neural network where each layer can process a batch of K input vectors simultaneously. The -12- FH12548482.1OPU-00125 N-layer neural network receives an input layer X having dimensions k x i (e.g., an input matrix) being multiplied against a weight matrix W of the neural network having dimensions i x j to yield an output layer having dimensions k x j (e.g., an output matrix). The dimension i, common to the number of columns of the input matrix and the number of rows of the weight matrix, can be referred to as the number of layers of the neural network. Fig. 2B is diagram 220 illustrating the multiplication operations occurring in each decomposed layer of the network. The matrix multiplications result in the output matrix illustrated by Fig. 2C. Fig. 2C is a diagram 240 illustrating a particular cell of the matrix output, Y36, being the result of the cross product of X31…i andsuch that all cells of the output will be the result of corresponding operations.

[0049] Fig. 3 is a block diagram 300 illustrating an exemplary computing core according to embodiments of the present disclosure. The computing core is based on optoelectronic co-integration or flip-chip bonding with photonic chips connecting to CMOS electronics / electronic drivers 310. Two tiles (e.g., 302a, 304a, 306a, and 308a; 302b, 304b, 306b, and 308b) of the photonic processors are illustrated.

[0050] In some embodiments, the present computing core is an optoelectronic hybrid engine. Data stored in the CMOS digital memory from the CMOS electronics 310 is converted from digital data to an analog form for use on a photonic chip for large-scale matrix operations using optical modulators. In some embodiments, each tile of the photonic chip includes a coherent light source or laser source 302a-b (e.g., single-wavelength, multi- wavelength, or a frequency comb), arrays of optical modulators 304a-b, 306a-b for input and weight matrices encoding, and a homodyne detector mesh 308a-b for multiplication and readout. The CMOS electronics 310 (memory, DACs, ADCs, integrators) are co- integrated / flip-chip bonded in close proximity, thereby reducing parasitic capacitance for high speed and low noise consideration. -13- FH12548482.1OPU-00125

[0051] In some embodiments, the homodyne detector mesh is a homodyne detector array.

[0052] Three photonic architectures for a matrix-matrix multiplication of the form Y (K× J)= X(K × I)W(I × J)are described below in relation to Figs. 4-5.

[0053] Space-time multiplexing:

[0054] Fig. 4A is a diagram 400 illustrating an example of the matrix multiplication operation of the form Y(k x j) = X(k x i) W(i x j) to be performed, and in particular, the nthlayer of the neural network. In some embodiments, the ithdimension of each matrix is encoded in the time domain, thus a total K + J modulators is sufficient to encode the two matrices. Fig. 4B is a diagram 420 illustrating a computing unit of vector-vector multiplication employed to provide a result of a cell of the output matrix. In Fig. 4B, the weight vector Wjand the input vector Xj with size (1 x i) and (I x 1) is encoded to the amplitude (or phase) of the laser field with i time steps. The interference of the two laser fields generates photo currents proportional to the multiplication amplitude. The photo currents are integrated over i time- steps with the charge accumulation amplifier, which read out the photo-voltage that corresponds to the product of the two vectors.

[0055] Fig. 4C is a diagram 440 illustrating embodiments of the method and system in operation. In some embodiments, a single-wavelength coherent light source 442 (e.g., a laser source, a laser beam source, a laser beam emitter) is split into K + J copies of a coherent light signal (e.g., a laser or laser beam). In other words, the coherent light source 442 is split into K copies, where each copy is encoded to represent an element of a weight vector (W1, W2, W3, …, etc.) and the coherent light source 442 is split into J copies, where each copy is encoded to represent an element of the input vector (X1, X2, X2, …, etc.). In some embodiments, multiple coherent light sources can be used to generate the K + J copies of the signal. In some embodiments, multiple coherent light sources, in combination with a beam -14- FH12548482.1OPU-00125 splitter, can be used to generate the K + J copies of the signal. In some embodiments, using coherent light source in combination with one or more splitters reduces the number of components needed to create the device and further reduces the size of the device.

[0056] In computations needed for machine-learning methods, matrix multiplication between a weight matrix W and an input matrix X is a common operation. In some embodiments of the present disclosure, the system and method encode a weight matrix W and an input matrix X (e.g., a weight matrix and input matrix used for a neural network) by passing each copy of the coherent light signal through a high-speed optical modulator that encodes a respective vector of each matrix into the amplitude (or phase) in I time steps. The coherent light signals enter a homodyne detector mesh (e.g., a homodyne mesh), of which there are multiple designs where two different homodyne detector mesh designs.

[0057] Fig. 4C illustrates a rectangular homodyne detector mesh designed in a grid format. Fig. 4D is a diagram 460 illustrating a path-length matching homodyne mesh. Fig. 4D is a diagram illustrating a path length and power loss matching homodyne detector mesh. Compared to the rectangular mesh illustrated by Fig. 4C, the mesh in Fig. 4D matches the path length and the power loss at each crossing performing the homodyne detection. An optical waveguide can direct the respective coherent light sources (e.g., laser beams) to each respective homodyne detector.

[0058] The homodyne detector mesh is an array of homodyne coherent receivers (e.g., homodyne detectors). The homodyne mesh further includes, or in some embodiments is operatively coupled to, an array of optical couplers that, at each waveguide crossing, overlaps all or a portion an encoded X signal and an encoded W signal and overlaps them into a homodyne coherent receiver. The interference of the two signals leads to photocurrents that are integrated over I time steps using a capacitor, resulting in a photo-voltage:, denotes the amplitude of the ith -15- FH12548482.1OPU-00125 time step of the kth copy of the input, denotes the amplitude of the ithtime step of the jth copy of the weight, and cos(ΔΘ) represents the phase difference between the two interference laser fields. In some embodiments, ΔΘ can be set to 0 by matching the length of the mesh, resulting in cos(ΔΘ)=1. With J × K homodyne coherent receivers, the system throughput scales with ^ = 2 × K × j × ^, where R is the clock rate. When K = J =1000, R=10 GS / s, the throughput T =20 PetaOP / s, which is about 100 times better than current, state-of- the-art, electronic processors (e.g., NVIDIAA100).

[0059] In some embodiments, the optical modulators can be broadband Mach- Zehnder modulators or chirp-free micro-ring modulators.

[0060] Space-wavelength multiplexing:

[0061] Figs. 5A and 5C are diagrams illustrating example embodiments of spatial- wavelength multiplexing employed by the system and method of the present disclosure. In some embodiments, the method and corresponding system throughput can be further improved using M wavelengths (e.g., from a WDM source or a frequency comb generator). Fig. 5A is a diagram 500 illustrating an example embodiment of vector-vector multiplication based on frequency domain interference using I wavelengths. Fig. 5C is a diagram 540 illustrating an example of matrix-matrix multiplication in a “single-shot,” using wavelength multiplexing in one time step. The coherent light signal (e.g., beam) from an optical frequency comb (OFC) of M comb lines is spatially split to N + K spatial beam paths to encode the weight matrix W(N×M) and the input matrix X(M×K) using digital-to-analog converters (e.g., high-speed field programmable gate array (FPGA) electronics). Each spatial beam path encodes a vector using M ring modulators (e.g., one modulator per comb line). In other words, each coherent light signal can itself carry M data signals via wavelength multiplexing. In some embodiments, as illustrated by Fig. 4A, the mode spacing between these data signals is larger than 100 GHz. Therefore, only the beating signal of the same -16- FH12548482.1OPU-00125 wavelengths / colors falls into the detection range. If I = M, the MMM operation can be achieved in a single shot (e.g., without any time multiplexing).

[0062] Space-wavelength-time multiplexing

[0063] While the spatial-multiplexing and wavelength-multiplexing disclosed above improves the throughput of the system, the number of wavelengths available is limited (e.g., M < 200). In embodiments of the disclosed method and system, wavelength and time are interchangeable as representing the I dimension of the matrices involved in the matrix multiplication. In some embodiments, throughput can further be improved by employing both wavelength and time concurrently as representing the I dimension of the matrix to operate on large matrices (e.g., matrices where I >> M). In other words, for each time step, M signals are transmitted by each beam / coherent light signal, and a subsequent beam / coherent light signal transmits another (or as many as) M signals.

[0064] Fig. 5B illustrates an example of signal encoding, where each vector is encoded in I / M time steps, and the system reads out at every I / M time steps. Fig. 5B is a diagram 520 illustrating example embodiments of vector-vector multiplication based on a combination of time-multiplexing and wavelength-multiplexing. For each timestep, a coherent light signal (e.g., beam) from an OFC of M comb lines is spatially split to N + K spatial beam paths to encode the weight matrix W(N×M) and the input matrix X(M×K) using digital-to-analog converters (e.g., high-speed field programmable gate array (FPGA) electronics). For each of multiple timesteps 522a-d, multiple elements are encoded into each beam within the frequency domain 524a-b and 526a-b.

[0065] Fig. 5D is a diagram illustrating an embodiment of implementing a homodyne detector mesh to perform matrix-matrix multiplication with a combination of spatial- multiplexing, time-multiplexing, and wavelength-multiplexing. The mesh design allows matching the path length and optical loss of the two interference arms at every detector. -17- FH12548482.1OPU-00125

[0066] Figs. 5C and 5D illustrate embodiments of homodyne detector meshes that can work with and without time integration. The mesh Fig. 5D matches the path length of two interference arms, can cancel out the wavelength-dependent phase difference.

[0067] Fig. 6 is a diagram 600 illustrating embodiments of coherent detectors, implemented with 50:50 couplers and detectors, using optical hybrids to extract both the phase and amplitude in quadrature detection. The homodyne detector mesh 604 employs 90- degree optical hybrids 602 that enable quadrature detection, which allows retrieval of both amplitude and phase during measurements. This enables removing phase fluctuations during the measurement using digital signal processing.

[0068] In some embodiments, the following paragraphs disclose the improved performance and advantages of the present method. The figures of merit for a computing system are measured with the computing power (number of operations per second), energy efficiency (joule per operation) and chip area efficiency (number of operations per second per chip area).

[0069] In some embodiments, an advantage of the disclosed architecture is high throughput. For example, with space-wavelength-time multiplexing, each coherent detector measures the result of 2 M operations at each clock cycle, the throughput scales with ^ = 2 × J × M × K × ^ =400 PetaOP / s with the parameters listed in Table 2. This computing power is about 1000x better than exemplary GPUs (e.g., NVIDIAA100 and H100). Space-wavelength and space-time multiplexing each provide throughput advantages as well.

[0070] In some embodiments, an advantage of the disclosed architecture is high computing density, as illustrated by Table 2, below. The number of optical modulators scales linearly with O(J+K), while O(N2) is required in all other optical processors (see, e.g., Table 1), and O(N3) is required in electronic computing. Therefore, embodiments of the disclosed system are simplified and more scalable than existing systems. The system employs N x K -18- FH12548482.1OPU-00125 homodyne detectors to read out the matrix-matrix product and N + K modulators for single- wavelength encoding and NM+MK for M wavelength encoding. Assuming the size of each ring modulator and homodyne detectors) is, respectively, 30x30 μm and10x10 μm, the total chip area (with beam splitting) is estimated to be A≈400 mm, which leads to a chip efficiency of T / A =1 POPS / mm, which is 1000x better than SoA electronic computers.

[0071] In some embodiments, the present system provides a low energy cost, while accounting for the input / output electronics for driving modulators and detectors. Each device has energy consumption amortized by either a spatial fan-out factor (e.g., J = K =1000) or a time-domain and / or frequency-domain fan-out factor (e.g., I =10000). As shown in Table 3, below, the total energy cost is 1 fJ / OP, which can be 1000x higher compared to that of electronic processors (1 pJ / OP).-19- FH12548482.1OPU-00125 Table 2 computing power and throughput density

[0072] Table 3 energy budget

[0073] Exemplary Implementations

[0074] The architecture can employ various photonic devices, not limited by the various embodiments, devices, and hardware disclosed below:

[0075] In some embodiments, optical frequency combs (OFC) are suited for this architecture because they avoid loss and packaging complexities compared to integrating hundreds of WDM components and lasers. For example, an integrated OFC generator can simultaneously provide over 200 comb lines via pumping an optical microresonator with a continuous-wave single-frequency laser / coherent light source. Moreover, the comb line spacing can be precisely defined by the microresonator size and mismatch with the free spectral range of the following ring-based silicon modulators through the Vernier effect to minimize channel crosstalk.

[0076] To meet energy requirements, the generated OFC uses coupled SiN microresonators in a normal group velocity dispersion (GVD) to achieve high power -20- FH12548482.1OPU-00125 conversion efficiency. In some embodiments, a second cavity introduces a mode crossing near the pump wavelength.

[0077] Figs. 7A-C are diagrams illustrating high energy efficiency broadband optical OFCs using coupled Silicon Nitride (SiN) microresonator(s). Fig. 7A is a diagram illustrating an embodiment of a schematic of a distributed feedback laser (DFB). A continuous wave / constant wave (CW) laser is used to pump high-Q coupled micro-ring resonators for OFC generation via Kerr nonlinearity at normal group velocity dispersion. Fig. 7B is a graph 740 illustrating an embodiment of a simulated optical spectrum, based on the GVD profile of Fig. 7A, of a dispersion-engineered photonic waveguide with a top width of 1500 nm and waveguide height of 600 nm, additional with at least 180 comb lines and 100-GHz comb line spacing with a ring radius of 225.

[0078] The generation of a dark soliton-based OFC is more robust against thermo- optic and Kerr instabilities and can be deterministically implemented via tuning the integrated heater. The normal GVD comb power is about 400mW using a CW pump power of 0.9 Wa, featuring two orders of magnitude higher power efficiency than bright soliton Kerr combs. In some embodiments, > 40mW comb power is generated at a 100-mW pump power using SiN microresonators of 1 million Q factor. Optimization of the higher order dispersion profile may reach more than 200 comb lines with > 50% conversion efficiency. In some embodiments, additional improvements can be obtained by coherently combining several synchronized OFCs to increase the total comb power to 1 Watts for higher-power requirements. The high-power handling of SiN waveguides enables high-power optical frequency combs to be split and routed to many silicon waveguide modes. In addition, the required SiN thickness can be below the high-stress regime (> 700nm) and thus compatible with the standard CMOS foundry process. -21- FH12548482.1OPU-00125

[0079] Fig. 7C is a graph illustrating an embodiment of a simulation of an OFC spectrum with 100 GHz comb line spacing, > 40% conversion efficiency, and > 180 comb lines.

[0080] Figs. 8A-B is a diagram 800 illustrating an example embodiment of a chirp- free optical digital-to-analog converters with weighted electrode lengths. In some embodiments, low digital bits can be converted to a high precision optical signal. Fig. 8A is a diagram illustrating silicon photonic modulators with PN junctions coupled with respective memories (Mem 1, Mem 2, Mem 3, etc.). Fig. 8B is a diagram 820 illustrating an exemplary embodiment of an 8-bit floating gate coupled with the ODAC. Weighting the electrode lengths allows for higher-bits to be given more weight in the signal than lower weight, thereby easily creating a high-precision signal.

[0081] The optical modulator requires lengthsto achieve a π phase shift. Here the optical digital-to-analog converter includes the electrodes that are divided on a modulator arm into segments of length Lπ× 2− ^ where ^ ∈ [1,..,MSB] varies from the least significant bit of the value to encode to the most significant bit (MSB), as shown in Figs. 8A-B.represents is the length of the junction required to achieve a π phase shift.

[0082] There is a trade-off between the precision, speed, and power consumption of electronic DACs. In the exemplary DACs of Figs. 8A-B, photonic and electronic codesigns improve performance. Using only low-bit precision high-speed digital DACs incorporating electrode designs in optical modulators, a high-bit precision data encoding can be output. The exemplary DAC therefore improves on conventional electronic DAC designs by providing precision and high speed.

[0083] In some embodiments, the input can be dynamically encoded with static random-access memory (SRAM). Figs. 9A-B is a diagram illustrating a novel optical digital- to-analog converters (ODAC) is based on the chirp-free Mach-Zehnder micro-ring -22- FH12548482.1OPU-00125 modulators (MZMM) devices to enable high-precision and low-energy optical memory interface. The optical digital-to-analog converter includes the electrodes that are divided on a modulator arm into segments of length Lπ× 2− ^where ^ ∈ [1,..,MSB] varies from the least significant bit of the value to encode to the most significant bit (MSB), as shown in Figs. 8A- B. Here Lπis the length of the junction required to achieve a π phase shift. The phase shiftapplied is then given by the equation , where bi ^ [0, 1] is the value of the ithdigital bit and the digital drivers (DACs) have x-bits of precision. In some embodiments, the ODAC can be implemented with MZMM doped silicon modulators or electro-optic lithium niobate (TFLN) modulators, however, a person of ordinary skill in the art can recognize that other hardware can be employed.

[0084] In various embodiments, one or more optical computing core as described herein is included as a processing unit in a computing node. In such embodiments, the one or more optical computing core may be combined with one or more conventional CPU or GPU.

[0085] Referring now to Fig. 10, a schematic of an example of a computing node is shown. Computing node 10 is only one example of a suitable computing node and is not intended to suggest any limitation as to the scope of use or functionality of embodiments described herein. Regardless, computing node 10 is capable of being implemented and / or performing any of the functionality set forth hereinabove.

[0086] In computing node 10 there is a computer system / server 12, which is operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, and / or configurations that may be suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set top boxes, programmable consumer electronics, network PCs, minicomputer systems, -23- FH12548482.1OPU-00125 mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

[0087] Computer system / server 12 may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, and so on that perform particular tasks or implement particular abstract data types. Computer system / server 12 may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0088] As shown in Fig. 10, computer system / server 12 in computing node 10 is shown in the form of a general-purpose computing device. The components of computer system / server 12 may include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including system memory 28 to processor 16.

[0089] Bus 18 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example, and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, Peripheral Component Interconnect (PCI) bus, Peripheral Component Interconnect Express (PCIe), and Advanced Microcontroller Bus Architecture (AMBA). -24- FH12548482.1OPU-00125

[0090] Computer system / server 12 typically includes a variety of computer system readable media. Such media may be any available media that is accessible by computer system / server 12, and it includes both volatile and non-volatile media, removable and non- removable media.

[0091] System memory 28 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 can be provided for reading from and writing to a non-removable, non-volatile magnetic media (not shown and typically called a "hard drive"). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus 18 by one or more data media interfaces. As will be further depicted and described below, memory 28 may include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the disclosure.

[0092] Program / utility 40, having a set (at least one) of program modules 42, may be stored in memory 28 by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, may include an implementation of a networking environment. Program modules 42 generally carry out the functions and / or methodologies of embodiments as described herein. -25- FH12548482.1OPU-00125

[0093] Computer system / server 12 may also communicate with one or more external devices 14 such as a keyboard, a pointing device, a display 24, etc.; one or more devices that enable a user to interact with computer system / server 12; and / or any devices (e.g., network card, modem, etc.) that enable computer system / server 12 to communicate with one or more other computing devices. Such communication can occur via Input / Output (I / O) interfaces 22. Still yet, computer system / server 12 can communicate with one or more networks such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via network adapter 20. As depicted, network adapter 20 communicates with the other components of computer system / server 12 via bus 18. It should be understood that although not shown, other hardware and / or software components could be used in conjunction with computer system / server 12. Examples, include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0094] The present disclosure may be embodied as a system, a method, and / or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure.

[0095] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non- exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash -26- FH12548482.1OPU-00125 memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0096] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0097] Computer readable program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language or similar programming -27- FH12548482.1OPU-00125 languages. The computer readable program instructions may execute entirely on the user’s computer, partly on the user’s computer, as a stand-alone software package, partly on the user’s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user’s computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0098] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0099] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer -28- FH12548482.1OPU-00125 readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function / act specified in the flowchart and / or block diagram block or blocks.

[0100] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0101] The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

[0102] The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of -29- FH12548482.1OPU-00125 ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. -30- FH12548482.1

Claims

OPU-00125 CLAIMS What is claimed is:

1. A method comprising: encoding a first subtensor of weight tensor into a first plurality of coherent light signals, each of the first plurality of coherent light signals representing a scalar of the first subtensor, thereby spatially multiplexing the first subtensor; encoding a second subtensor of an input tensor into a second plurality of coherent light signals, each of the second plurality of coherent light signals representing a scalar of the second subtensor, thereby spatially multiplexing the second subtensor; directing the first and second plurality of coherent light signals to a plurality of homodyne detectors, each of the plurality of homodyne detectors configured to detect an interference between a unique pair of one of the first plurality and one of the second plurality of coherent light signals; and integrating the interferences detected by the plurality of homodyne detectors to determine a photo-voltage representing a scalar component of a tensor multiplication result, wherein the first plurality of coherent light signals and the second plurality of coherent light signals are each multiplexed in one or more of time and wavelength.

2. The method of Claim 1, wherein the first plurality of coherent light signals is multiplexed, in the time domain, into a first plurality of time channels, and second plurality of coherent light signals are multiplexed, in the time domain, into a second plurality of time channels, the method further comprising: iterating, for each of the first plurality of time channels and the second plurality of time channels, encoding the weight tensor, encoding the input tensor, and integrating the plurality of interferences; wherein the amount of the first plurality of time channels and second plurality of time channels is proportional to a common dimension of the weight tensor and input tensor. -31- FH12548482.1OPU-00125 3. The method of Claim 1, wherein: the first plurality of coherent light signals provides a first plurality of wavelength channels separated by wavelength multiplexing and the second plurality of coherent light signals provides a second plurality of wavelength channels separated by wavelength multiplexing, and integrating the plurality of interferences further integrates a plurality of interferences measured at the respective overlap of each the first plurality of wavelength channels and the second plurality of wavelength channels.

4. The method of Claim 3, wherein the first plurality of coherent light signals and second plurality of coherent light signals employ a mode spacing of at least 100 GHz between each wavelength channel of the first plurality of wavelength channels and second plurality of wavelength channels.

5. The method of Claim 3, wherein the first plurality of coherent light signals are multiplexed, in the time domain, into a first plurality of time channels, and the second plurality of coherent light signals are multiplexed, in the time domain, into a second plurality of time channels, and wherein the first plurality of time channels are multiplexed into a plurality of respective wavelength channels for each of the first plurality of time channels, and the second plurality of time channels are multiplexed into a plurality of respective wavelength channels for each of the second plurality of time channels, the method further comprising: iterating, for each of the first plurality of respective wavelength channels and second plurality of respective wavelength channels of each of the first plurality of time channels and second plurality of time channels, encoding the weight tensor, encoding the input tensor, and integrating the plurality of interferences.

6. The method of Claim 1, wherein encoding the input tensor and encoding the weight tensor is performed by a digital to analog converter (DAC), wherein the DAC can be at least one of optical modulators, a ring modulator, a micro-ring modulator, a Mach- Zehnder micro-ring modulator and a chirp-free micro-ring modulator.

7. The method of Claim 1, wherein integrating the plurality of interferences further integrates each interference measured by the plurality of homodyne detectors of a -32- FH12548482.1OPU-00125 homodyne detector array, the homodyne detector array configured to match path length and the optical loss of the first and second pluralities of coherent light signals at each respective homodyne detector of the homodyne detector array.

8. The method of any one of Claims 1-7, wherein the weight tensor is a matrix and wherein the first subtensor is a row or column of the weight tensor.

9. The method of any one of Claims 1-7, wherein the input tensor is a matrix and wherein the second subtensor is a row or column of the input tensor.

10. A system comprising: at least one coherent light source configured generate a first plurality of coherent light signals and a second plurality of coherent light signals; a plurality of digital to analog converters (DAC) configured to encode a first subtensor from a weight tensor into the first plurality of coherent light signals, and encode a second subtensor from an input tensor into the second plurality of coherent light signals, each of the first plurality of coherent light signals representing a scalar of the first subtensor, thereby spatially multiplexing the first subtensor, each of the second plurality of coherent light signals representing a scalar of the second subtensor, thereby spatially multiplexing the second subtensor; a plurality of homodyne detectors; and an optical waveguide configured to direct the first and second plurality of coherent light signals to the plurality of homodyne detectors, each of the plurality of homodyne detectors configured to detect an interference between a unique pair of one of the first plurality and one of the second plurality of coherent light signals; and a capacitor configured to integrate the interferences detected by the plurality of homodyne detectors to determine a photo-voltage representing a scalar component of a tensor multiplication result, wherein the first plurality of coherent light signals and the second plurality of coherent light signals are each multiplexed in one or more of time and wavelength.

11. The system of Claim 8, wherein the first plurality of coherent light signals is multiplexed, in a time domain, into a first plurality of time channels, and second -33- FH12548482.1OPU-00125 plurality of coherent light signals are being multiplexed, in the time domain, into a second plurality of time channels, the system further comprising: a capacitor configured to additively store photo-voltages representing a plurality of interferences integrated by the homodyne detector after, for each of the first plurality of time channels and second plurality of time channels, iteratively encoding the weight tensor, encoding the input tensor, and integrating the plurality of interferences; wherein the amount of the first plurality of time channels and second plurality of time channels is proportional to a common dimension of the weight tensor and input tensor.

12. The system of Claim 8, wherein: the DAC converters are configured to encode a first plurality of wavelength channels separated by wavelength multiplexing within each of the coherent light signals of the first plurality of coherent light signals and configured to encode a second plurality of wavelength channels separated by wavelength multiplexing within each of the coherent light signals of the second plurality of coherent light signals, and the homodyne detectors of the homodyne detector array are configured to integrate a plurality of interferences measured at the respective overlap of each of the first plurality of wavelength channels and the second plurality of wavelength channels.

13. The system of Claim 10, wherein the first plurality of coherent light signals and second plurality of coherent light signals employ a mode spacing of at least 100 GHz between each wavelength channel of the respective first plurality of wavelength channels and second plurality of wavelength channels.

14. The system of Claim 10, wherein the first plurality of coherent light signals are multiplexed, in the time domain, into a first plurality of time channels, and the second plurality of coherent light signals are multiplexed, in the time domain, into a second plurality of time channels, and wherein the first plurality of time channels are multiplexed into a plurality of respective wavelength channels for each of the first plurality of time channels, and the second plurality of time channels are multiplexed into a plurality of respective wavelength channels for each of the second plurality of time channels, the system further comprising: -34- FH12548482.1OPU-00125 a capacitor configured to additively store photo-voltages representing plurality of interferences integrated by the homodyne detectors of homodyne detector array after iteratively, for each of the first plurality of respective wavelength channels and second plurality of respective wavelength channels of each of the first plurality of time channels and second plurality of time channels, encoding the weight tensor, encoding the input tensor, and integrating the plurality of interferences.

15. The system of Claim 8, wherein the DAC can be at least one of an optical modulator, a ring modulator, a micro-ring modulator, a Mach-Zehnder micro-ring modulator and a chirp-free micro-ring modulator.

16. The system of Claim 8, wherein the homodyne detector array is configured to match path length and the optical loss of the first and second pluralities of coherent light signals at each respective homodyne detector of the homodyne detector array.

17. The system of Claim 8, further comprising: a beam splitter arranged with one or more of the at least one coherent light source, the beam splitter configured to split a coherent light signal emitted from the at least one coherent light source into the first plurality of coherent light signals and a second plurality of coherent light signals.

18. The system of Claim 8, further comprising: complementary metal-oxide-semiconductor (CMOS) chip; wherein the at least one coherent light source, the plurality of DACs, and the homodyne detector array reside on the CMOS chip.

19. The system of any one of Claims 10-18, wherein the weight tensor is a matrix and wherein the first subtensor is a row or column of the weight tensor.

20. The system of any one of Claims 10-18, wherein the input tensor is a matrix and wherein the second subtensor is a row or column of the input tensor. -35- FH12548482.1

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