Digital-integrated-circuit timing monitoring method based on graph convolutional neural network

Abstract

A digital-integrated-circuit timing monitoring method based on a graph convolutional neural network. The method comprises: determining a plurality of candidate monitoring nodes in a target circuit, and the connection relationship between the plurality of candidate monitoring nodes (101); determining feature information of the target circuit on the basis of device property information of the plurality of candidate monitoring nodes (102); inputting into a trained target graph convolutional neural network model the feature information of the target circuit and the connection relationship between the plurality of candidate monitoring nodes, such that the graph convolutional neural network model outputs determination results of the plurality of candidate monitoring nodes, wherein the determination results comprise a first determination result indicating that a candidate monitoring node is a monitoring node, and a second determination result indicating that a candidate node is not a monitoring node (103); on the basis of the determination results, which are output by the graph convolutional neural network model, determining at least one effective monitoring node from among the plurality of candidate monitoring nodes (104); and performing timing monitoring on the target circuit on the basis of the at least one monitoring node (105).

Description

Digital integrated circuit timing monitoring method based on graph convolutional neural network

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on October 24, 2023, with application number 2023113879321 and application name “Digital integrated circuit timing monitoring method based on graph convolutional neural network”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of deep learning technology, and in particular to a digital integrated circuit timing monitoring method based on graph convolutional neural network. Background Art

[0003] With the continuous development of integrated circuit manufacturing technology, the process size continues to decrease, the integration and operating frequency of chips continue to increase, and the timing analysis and verification of chip design become more important. In the existing technology, methods based on static timing analysis and methods based on path activation rate are often used to select timing monitoring points. Taking static timing analysis as an example, the method based on static timing analysis obtains all critical paths by performing static timing analysis on the circuit netlist, and selects a part of the end triggers of the longest path for monitoring. However, this method has problems such as too many monitoring items, too high area power consumption cost, and long monitoring point selection time. Therefore, how to reduce the area power consumption cost and reduce the monitoring point selection time is an urgent problem to be solved.

[0004] Summary of the Invention

[0005] In view of this, the present application provides a digital integrated circuit timing monitoring method based on graph convolutional neural network, which can effectively reduce the selection time of monitoring points and surface-based power consumption.

[0006] In a first aspect, an embodiment of the present invention provides a digital integrated circuit timing monitoring method based on a graph convolutional neural network, comprising:

[0007] Determining a plurality of candidate monitoring nodes in a target circuit and a connection relationship between the plurality of candidate monitoring nodes;

[0008] determining characteristic information of the target circuit based on device attribute information of the plurality of candidate monitoring nodes;

[0009] Inputting the characteristic information of the target circuit and the connection relationship of the multiple candidate monitoring nodes into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs determination results of the multiple candidate monitoring nodes; the determination results include a first determination result that the candidate monitoring nodes are monitoring nodes and a second determination result that the candidate monitoring nodes are not monitoring nodes;

[0010] Determine at least one valid monitoring node from the multiple candidate monitoring nodes according to the determination result output by the graph convolutional neural network model;

[0011] Timing monitoring is performed on the target circuit based on the at least one monitoring node.

[0012] In a possible implementation, determining a plurality of candidate monitoring nodes in the target circuit includes:

[0013] Obtaining circuit netlist data of the target circuit;

[0014] Generate a corresponding circuit netlist diagram based on the circuit netlist data with standard cells and ports as nodes;

[0015] The node in the circuit netlist diagram is determined as the candidate monitoring node.

[0016] In a possible implementation, the connection relationship of each candidate monitoring node is an adjacency matrix, and the step of determining the connection relationship of the plurality of candidate monitoring nodes includes:

[0017] Determining the connection relationship of each node according to the circuit connection relationship of the target circuit;

[0018] Determining the connection relationship of the plurality of candidate monitoring nodes according to the connection relationship of the respective nodes;

[0019] The adjacency matrix is ​​generated according to the connection relationship of the multiple candidate monitoring nodes.

[0020] In a possible implementation, determining the characteristic information of the target circuit based on the device attribute information of the multiple candidate monitoring nodes includes:

[0021] Determine all device attribute information of the candidate monitoring node based on a process library corresponding to the target circuit;

[0022] Selecting at least one device attribute information from the device attribute information of the candidate monitoring nodes as target device attribute information;

[0023] The characteristic information of the target circuit is determined based on the target device attribute information corresponding to each candidate monitoring node.

[0024] In a possible implementation, the characteristic information of the target circuit is a characteristic matrix, and determining the characteristic information of the target circuit based on the target device attribute information corresponding to each candidate monitoring node includes:

[0025] Determine a node vector corresponding to a candidate monitoring node according to the target device attribute information;

[0026] A feature matrix of the target circuit is constructed according to the node vectors of the candidate monitoring nodes.

[0027] In one possible implementation, the training process of the target graph convolutional neural network model includes:

[0028] Acquire a training data set; the training data set includes characteristic data of each node in the training circuit, connection relationships of each node, and label data of each node; wherein the label data includes: first label data of the monitoring node and second label data of the non-monitoring node;

[0029] Iteratively training the initial graph convolutional neural network model based on the training data set so that the initial graph convolutional neural network model learns node features of different label data;

[0030] When it is detected that the loss function of the initial graph convolutional neural network model meets the preset conditions, the training is determined to be completed, and the target convolutional neural network model is obtained.

[0031] In a possible implementation, the feature data is a feature matrix, the connection relationship is an adjacency matrix, and the step of acquiring the feature data of each node and the connection relationship of each node includes:

[0032] Generate a circuit netlist diagram of the training circuit by using standard cells and ports in the training circuit as nodes;

[0033] Determine the connection relationship of each node according to the circuit netlist diagram;

[0034] An adjacency matrix of the training circuit is generated based on the connection relationship of each node, and a feature matrix of the training circuit is generated based on the device attribute information of each node.

[0035] In a possible implementation, the step of acquiring the label data of each node includes:

[0036] Performing static timing analysis on the training circuit to obtain a critical path in the training circuit;

[0037] Performing dynamic simulation on the training circuit to determine an effective activation path from the critical path;

[0038] determining a plurality of valid monitoring points based on the valid activation path;

[0039] The label data of the node corresponding to the valid monitoring point in the circuit netlist is determined as the first label data, and the label data of the remaining nodes is determined as the second label data.

[0040] In one possible implementation, the target graph convolutional neural network model is composed of a stack of multiple graph convolutional layers, wherein the input of the first graph convolutional layer among the multiple graph convolutional layers is the feature matrix of each node, the adjacency matrix of each node, and the label data of each node; the data of other graph convolutional layers except the first graph convolutional layer is the output of the previous graph convolutional layer;

[0041] The last graph convolution layer among the multiple graph convolution layers is connected to the algorithm layer; the algorithm layer constructs a hypersphere based on the target anomaly detection algorithm based on the node data output by the last graph convolution layer and calculates the Euclidean distance between each node and the center of the hypersphere;

[0042] The output of the algorithm layer is connected to the input of the classifier. The classifier determines abnormal node data from the various node data according to the Euclidean distance corresponding to each node and the radius of the hypersphere, and eliminates the abnormal node data.

[0043] In a second aspect, an embodiment of the present invention provides a digital integrated circuit timing monitoring device based on a graph convolutional neural network, comprising:

[0044] A node determination module, configured to determine a plurality of candidate monitoring nodes in a target circuit and a connection relationship between the plurality of candidate monitoring nodes;

[0045] a characteristic information determining module, configured to determine characteristic information of the target circuit based on device attribute information of the plurality of candidate monitoring nodes;

[0046] a monitoring node prediction module, configured to input characteristic information of the target circuit and connection relationships of the plurality of candidate monitoring nodes into a trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs determination results of the plurality of candidate monitoring nodes; the determination results including a first determination result indicating that the candidate monitoring nodes are monitoring nodes and a second determination result indicating that the candidate monitoring nodes are not monitoring nodes;

[0047] a monitoring node determination module, configured to determine at least one monitoring node from the plurality of candidate monitoring nodes according to the determination result output by the graph convolutional neural network model;

[0048] A timing monitoring module is configured to perform timing monitoring on the target circuit based on the at least one monitoring node.

[0049] In a third aspect, an embodiment of the present invention provides an electronic device, including:

[0050] at least one processor; and

[0051] at least one memory in communication with the processor, wherein:

[0052] The memory stores program instructions that can be executed by the processor, and the processor calls the program instructions to execute the method described in the first aspect.

[0053] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to execute the method described in the first aspect.

[0054] In an embodiment of the present invention, by combining a graph convolutional neural network model to select monitoring nodes, the speed of selecting monitoring nodes can be accelerated while ensuring the accuracy, thereby improving the efficiency of circuit timing monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0056] FIG1 is a flow chart of a circuit timing monitoring method provided by an embodiment of the present invention;

[0057] FIG2 is a schematic diagram of a gate-level circuit conversion provided by an embodiment of the present invention;

[0058] FIG3 is a schematic diagram of an adjacency matrix provided by an embodiment of the present invention;

[0059] FIG4 is a schematic diagram of a feature matrix provided by an embodiment of the present invention;

[0060] 5-a to 5-c are schematic diagrams of a process for generating a circuit netlist diagram according to an embodiment of the present invention;

[0061] FIG6 is a flowchart of a graph convolutional neural network model training method provided by an embodiment of the present invention;

[0062] FIG7 is a schematic diagram showing the principle of a graph convolution operation provided by an embodiment of the present invention;

[0063] FIG8 is a schematic diagram of a graph convolution structure provided by an embodiment of the present invention;

[0064] Figures 9-a and 9-b are schematic diagrams of another adjacency matrix provided by an embodiment of the present invention;

[0065] Figures 10-a and 10-b are schematic diagrams showing the principle of an anomaly detection algorithm provided by an embodiment of the present invention;

[0066] FIG11 is a schematic diagram of a circuit synthesis result provided by an embodiment of the present invention.

[0067] FIG12 is a schematic diagram of a timing report provided by an embodiment of the present invention;

[0068] FIG13 is a schematic diagram of activation rate statistics provided by an embodiment of the present invention;

[0069] FIG14 is a diagram showing the training effect of a graph convolutional neural network model provided by an embodiment of the present invention;

[0070] FIG15 is a schematic diagram showing the accuracy of a graph convolutional neural network model during inference provided by an embodiment of the present invention;

[0071] FIG16 is a schematic diagram of an analysis result output by a graph convolutional neural network provided by an embodiment of the present invention;

[0072] FIG17 is a schematic diagram of the structure of a circuit timing monitoring device provided by an embodiment of the present invention;

[0073] FIG18 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0074] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0075] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0076] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0077] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0078] In an embodiment of the present invention, a graph convolutional neural network model is combined with the selection of monitoring points to reduce the time required to select monitoring points. FIG1 is a flow chart of a circuit timing monitoring method provided by an embodiment of the present invention. As shown in FIG1 , the processing steps of the method include:

[0079] Step 101: Determine multiple candidate monitoring nodes and their connection relationships in a target circuit. The target circuit may be implemented as a digital circuit or an analog circuit. When determining candidate monitoring nodes from the target circuit, the target circuit may be converted into a gate-level circuit.

[0080] Specifically, the circuit netlist data of the target circuit is obtained by loading the circuit netlist file of the target circuit. The circuit netlist file is generated by an electronic design automation (EDA) synthesis tool. Based on the process library file used in the synthesis, the target circuit is converted from a system-level circuit to a gate-level circuit expression, and the specific models of all standard cells and the connection relationships between each standard cell are specified. The file format is Verilog, and its syntax complies with the syntax requirements of the hardware description language Verilog HDL. Subsequently, a corresponding circuit netlist diagram can be generated based on the circuit netlist data, with standard cells and ports as nodes. Figure 2 is a schematic diagram of a gate-level circuit conversion provided by an embodiment of the present invention. As shown in Figure 2, the left figure (a) is a gate-level circuit diagram. The target circuit is converted into a gate-level circuit form using corresponding tools or algorithms. The circuit netlist data corresponding to the gate-level circuit obtained from the circuit netlist file is shown in Figure (b) of Figure 2. Finally, the nodes in the circuit netlist diagram (i.e., all standard cells and ports) can be determined as candidate monitoring nodes.

[0081] The connection relationship of each candidate monitoring node can be implemented as an adjacency matrix. The connection relationship of each node in the circuit netlist diagram can be determined based on the circuit connection relationship of the target circuit. Then, the connection relationship of multiple candidate monitoring nodes can be determined based on the connection relationship of each node. Since the monitoring nodes are essentially the nodes in the circuit netlist diagram, the connection relationship of each monitoring node is the same as the connection relationship of each node in the circuit netlist diagram. Finally, the corresponding adjacency matrix can be generated based on the connection relationship of multiple candidate monitoring nodes. Taking the gate-level circuit shown in Figure 2 as an example, the adjacency matrix obtained based on the connection relationship between each standard unit and the port is shown in Figure 3. The adjacency matrix shown in Figure 3 is a 7×7 matrix. The blank space in the adjacency matrix represents a value of 0.

[0082] Step 102: Determine the characteristic information of the target circuit based on the device attribute information of multiple candidate monitoring nodes. The complete device attribute information of the candidate monitoring nodes can be determined based on a process library corresponding to the target circuit. This process library is the process library corresponding to the aforementioned circuit netlist file. At least one device attribute information can then be selected from the device attribute information of the candidate monitoring nodes as the target device attribute information. Finally, determine the characteristic information of the target circuit based on the target device attribute information corresponding to each candidate monitoring node. Device attribute information includes resistance, capacitance, drive capability, function type, unit type, etc. of the electrical component.

[0083] In a specific example, since the feature information obtained in step 102 cannot be directly input into the target graph convolutional neural network model, it is necessary to convert it into a data form that can be received and recognized by the target graph convolutional neural network. Optionally, the feature data can be implemented in the form of a feature matrix, and the node vector of the corresponding candidate monitoring node can be determined based on the target device data information. Then, the feature matrix of the target circuit is constructed based on the node vector of the candidate monitoring node. Taking the gate-level circuit shown in Figure 2 as an example, the node vector corresponding to each node is generated according to the target device attribute information of each node (standard cell and port), and the feature matrix of the target circuit is constructed based on the node vector. Figure 4 is a schematic diagram of a feature matrix corresponding to the gate-level circuit shown in Figure 2 provided by an embodiment of the present invention. The device attribute information of each node (standard component and port) in Figure 2 is determined by the process library to determine the node vector of each node. Then, the 7×n feature matrix shown in Figure 4 is obtained based on the obtained node vectors.

[0084] In step 103, the characteristic information of the target circuit and the connection relationship of multiple candidate monitoring nodes are input into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs the judgment results of multiple candidate monitoring nodes; the judgment results include a first judgment result that it is a monitoring node and a second judgment result that it is not a monitoring node. The graph convolutional neural network model extracts features based on the input characteristic information (feature matrix) and connection relationship (adjacency matrix) of the target circuit. For each node in the same convolutional layer of the graph convolutional neural network model, the feature records of its neighboring nodes are aggregated to calculate the features of the neighboring nodes. The feature representation of the current node is updated based on the aggregated neighboring node features and the features of the current node itself, thereby updating the parameters of the model. Finally, the target graph convolutional neural network model outputs the judgment results of each candidate monitoring node.

[0085] Step 104: Determine at least one valid monitoring node from the plurality of candidate monitoring nodes based on the determination result output by the graph convolutional neural network model. The candidate monitoring node whose determination result is the first determination result may be determined as the valid monitoring node.

[0086] Step 105: Perform timing monitoring on the target circuit based on at least one monitoring node. A monitoring unit may be embedded at a valid monitoring node by inserting or replacing an existing trigger to obtain a monitoring signal. The monitoring signal is analyzed to monitor the timing of the target circuit.

[0087] In some embodiments, to achieve rapid diagram construction, a regular matching approach is used to first add all circuit elements as nodes (including ports, standard cells, and wire nets) when creating a circuit netlist. This is because the goal is to capture the nodes and their connection information in a single traversal, as multiple traversals are time-consuming. After the traversal is completed, since wire net variables only represent electrical connections in the circuit and contain less information as nodes, deleting them can reduce the number of nodes and streamline the diagram. Therefore, only standard cells and ports are added as nodes, and wire nets need to be deleted while maintaining the original connection relationships.

[0088] The specific steps for generating a circuit netlist diagram in the above steps are shown in Figures 5-a to 5-c. Figure 5-a is a schematic diagram of a circuit netlist file provided by an embodiment of the present invention. Due to the requirements of the Verilog HDL syntax specification, circuit ports are listed at the beginning of the file, and the instantiation statement of the standard cell contains the electrical connections and corresponding pins of the standard cell. Therefore, text traversal and regular matching can be used to locate specific text, and nodes and edges can be conveniently added based on the text. As shown in Figure 5-a, it can be seen that the text conforms to the Verilog HDL syntax specification and has regular patterns, such as fixed period and bracket formats, so these patterns can be conveniently used for regular matching. By traversing the circuit netlist file of the target circuit, all standard cells and ports contained therein (i.e., the portion circled in the rectangular box in Figure 5-a) are determined. The standard cells and ports are treated as nodes, and the electrical connections between each standard cell and port are defined as edges to complete the node addition. The addition result is shown in Figure 5-b. After the traversal is completed, deleting and reconnecting each node can reduce the time of map construction. Since net n2950 in Figure 5-b connects standard cells U3371 and U3370, we need to delete n2950, ​​thereby directly connecting U3370 and U3371. This simplifies the connection by deleting the dotted line in Figure 5-b, while retaining both U3371 and U3370. This results in the circuit netlist shown in Figure 5-c. Based on this circuit netlist, we can obtain the corresponding adjacency matrix.

[0089] In some embodiments, data preprocessing is required before inputting the characteristic information of the target circuit and the connection relationship of multiple candidate monitoring nodes into the trained target graph convolutional network to increase the reliability of the data. Specifically, the characteristic information can be encoded according to the functions of all standard cells and ports under the current process and used as the initial vector of the node. Each standard cell in the process library has attributes such as logical function and drive capability. These attributes are extracted from the file and encoded as the initial vector of the node. The encoding method adopts one-hot encoding. For example, the drive capability of the standard cell INVD3LVT is 3, the functional type is 6, and the cell type is 0. Then the initial vector of the standard cell is (3, 6, 0). After encoding it, the result obtained after encoding is: node U3365 is embedded. The drive capability of the standard cell IOA21D1LVT is 1, the functional type is 28, and the cell type is 0. Then the initial vector of the standard cell is two (1, 28, 0). After encoding it, the result obtained is: node U3368 is embedded.

[0090] At this time, the node identifier is a vector, and its different positions represent different attributes, and the values ​​also vary. Therefore, it needs to be normalized or otherwise standardized to control the scale of the data within a reasonable range. Optionally, the formula The normalization process is performed. Based on the normalized node vectors, the characteristic matrix of the target circuit is obtained. The normalization process of the adjacency matrix of the target circuit is the same as that of the characteristic matrix, and will not be repeated here.

[0091] In an embodiment of the present invention, the graph convolutional neural network model is also improved. Figure 6 is a flow chart of a graph convolutional neural network model training method provided by an embodiment of the present invention. As shown in Figure 6, the training process of the graph convolutional neural network includes:

[0092] Step 601: Obtain a training dataset. The training dataset includes feature data for each node in the training circuit, the connectivity relationships of each node, and label data for each node. The label data includes first label data for nodes that are monitoring nodes and second label data for nodes that are not monitoring nodes. The feature data for each node can be implemented as a feature vector, and the feature matrix of the training circuit can be obtained using the feature vectors of each node. The connectivity relationships of each node can be implemented as an adjacency matrix. The feature matrix and adjacency matrix are obtained by generating a circuit netlist diagram for the training circuit using standard cells and ports in the training circuit as nodes. The connectivity relationships of each node are determined based on the circuit netlist diagram. The adjacency matrix of the training circuit is generated based on the connectivity relationships of each node, and the feature matrix of the training circuit is generated based on the device attribute information of each node. Optionally, directly using these node representations as model input can negatively impact model learning. Therefore, before inputting the feature matrix and adjacency matrix as training data into the initial graph convolutional neural network model, they need to be encoded and normalized. The specific processing steps are the same as those for the feature matrix and adjacency matrix of the target circuit in the above steps and will not be repeated here.

[0093] The label data for each node is the result information of the training sample in machine learning. The label data in this invention is the result indicating whether each node is a monitoring node. For example, the label data value of a monitoring node is 1, and the label data value of a non-monitoring node is -1.

[0094] In step 602, the initial graph convolutional neural network model is iteratively trained based on the training dataset to learn the node features of data with different labels. When training the initial graph convolutional neural network model, mainstream deep learning frameworks such as Pytorch, Caffe, and CNTK can be used. Data processing and model training are conveniently performed using the Python language, and specialized graph neural network frameworks are further employed to rapidly build models and improve implementation efficiency.

[0095] The basic principle of graph convolution operation is to update its own information by aggregating the information of adjacent nodes. Figure 7 is a schematic diagram of the principle of a graph convolution operation provided by an embodiment of the present invention. As shown in Figure 7, the circuit netlist diagram of the input training circuit has 5 nodes, and the feature extraction is completed after two layers of graph convolution operations. Figure 8 is a schematic diagram of a graph convolution structure provided by an embodiment of the present invention. As shown in Figure 8, the graph convolution layer (NodeConv) is based on the GATv2 model with residual connection and drop mechanism. It uses a multi-head attention mechanism to perform multiple operations on adjacent nodes during the aggregation process and calculate the average value to update the node message. The essence of graph convolution is to propagate node information along the edge in the graph. The calculation method is: as well as Among them, V represents the set of nodes, N(v) represents the set of adjacent nodes of node v, k represents the current layer, k-1 represents the previous layer, W represents the network parameters, and α represents the attention coefficient.

[0096] A model typically has multiple graph convolutional layers, which are used to enhance the model's expressive power. Given a graph including its node feature matrix and adjacency matrix, the graph convolutional layer aggregates feature information from its neighborhood to obtain a hidden representation for each node. By stacking multiple layers, the final hidden representation of each node can receive messages from more distant nodes, allowing graph convolutional neural networks to efficiently learn node representations. Residual connections, after aggregating adjacent nodes, add the new node representation to the original representation and update the node representation again. This prevents vanishing gradients during parameter updates caused by excessively deep model layers and long derivative chains. This is because long derivative chains and the multiplication mechanism of partial derivatives can easily cause the magnitude of partial derivatives to drop rapidly. Adding residual connections can avoid this while also reducing model complexity and minimizing overfitting.

[0097] In step 603, training is determined to be complete when the loss function of the initial graph convolutional neural network model meets a preset condition, thereby obtaining a target convolutional neural network model. The preset condition can be achieved by the loss function converging. The error between the predicted result and the known result is calculated using the loss function, and optimization methods such as gradient descent are used to reduce the error, i.e., the loss function converges. If the loss function converges, it indicates that the model can accurately predict the monitoring node based on the input.

[0098] In some embodiments, the step of obtaining the label data of each node in the training circuit includes: performing static timing analysis on the training circuit to obtain the critical path in the training circuit. And performing dynamic simulation on the training circuit to determine the effective activation path from the critical path. Then, multiple effective monitoring points are determined based on the effective activation path. Finally, the label data of the node corresponding to the effective monitoring point in the circuit netlist diagram is determined as the first label data, and the label data of the remaining nodes is determined as the second label data. Among them, the static timing analysis process is used to calculate the delay of each path in the circuit netlist and obtain the critical path, and the dynamic simulation process is used to eliminate the path where the signal is not activated in the critical path. By analyzing the timing report, the critical path containing the input and output ports is further eliminated, and the end triggers of the remaining critical paths are selected as monitoring nodes to obtain a set of monitoring nodes. The monitoring point set is preprocessed to obtain the above-mentioned label data.

[0099] In some embodiments, in order to effectively utilize the sample data, data enhancement can also be used to amplify the data. Data enhancement can prevent the neural network from learning irrelevant features, thereby further improving the performance of the neural network. Specifically, new data that is different from the original data can be obtained by disrupting the order of the nodes and simultaneously disrupting the adjacency matrix. For example, the circuit netlist diagram of the training circuit has a total of 5 nodes, namely node 1, node 2, node 3, node 4 and node 5. The order is 1, 2, 3, 4, and 5. Its adjacency matrix is ​​shown in Figure 9-a. Afterwards, the order of node 1 and node 5 is swapped, and the corresponding adjacency matrix after the order swap is shown in Figure 9-b.

[0100] After the training circuit is synthesized into a circuit netlist, one of its characteristics is that the number of combination units is large, while the proportion of timing units is small. Since the timing monitoring nodes to be selected are timing units, data imbalance problems are inevitable. In practical applications, the proportion of samples with different labels in the data set, especially in classification problems, is likely to be unbalanced. In this case, a fairly high accuracy can be obtained by simply predicting the majority class, but the minority class cannot be captured. Therefore, if algorithm training is used directly for classification, the training effect will be very poor, and the model needs to be further optimized. Based on this, the embodiment of the present invention optimizes the model by introducing a deep semi-supervised anomaly detection (Deep SAD) algorithm.

[0101] Specifically, the target graph convolutional neural network model is composed of multiple stacked graph convolutional layers, and the input of the first graph convolutional layer among the multiple graph convolutional layers is the feature matrix of each node, the adjacency matrix of each node, and the label data of each node. The data of other graph convolutional layers except the first graph convolutional layer is the output of the previous graph convolutional layer. The last graph convolutional layer among the multiple graph convolutional layers is connected to the algorithm layer. The algorithm layer constructs a hypersphere based on the target anomaly detection algorithm (i.e., Deep SAD algorithm) based on the data of each node output by the last graph convolutional layer and calculates the Euclidean distance between each node and the center of the hypersphere.

[0102] The output of the algorithm layer is connected to the input of the classifier. The classifier determines the abnormal node data from each node data based on the Euclidean distance corresponding to each node and the radius of the hypersphere, and eliminates the abnormal node data. The Euclidean distance of all nodes to the center of the hypersphere can be used as the evaluation score of each node. The score is calculated for the sample and then divided using the threshold. The theory of the Deep SAD algorithm is to obtain the high-dimensional embedding representation of the node, and then establish a hypersphere to make the normal sample points fall inside the sphere as much as possible, and the abnormal samples fall outside the sphere. Figure 10-a and Figure 10-b are schematic diagrams of the principles of an anomaly detection algorithm provided by an embodiment of the present invention. As shown in Figure 10-a, before being classified by the anomaly detection algorithm, the normal points (black solid) and the abnormal points (star-shaped hollow) are evenly distributed. After being processed by the anomaly detection algorithm, the normal points fall inside the circle and the abnormal points fall outside the circle. The center c and radius R of the circle can be calculated based on the average value of the node representation and the Euclidean distance from the abnormal point to the center of the circle.

[0103] Most anomaly detection tasks are unsupervised learning tasks, which prevents labeled data from being used to update model parameters. To address this issue, the Deep SAD algorithm is modified in this embodiment. The Deep SAD algorithm uses the labeled data as the exponent of the Euclidean distance of the sample points, taking discrete values ​​of 1 or -1. The value of the minority class sample points is -1, and the reciprocal of the Euclidean distance is taken. That is, when the data belongs to the majority class, the Euclidean distance is not processed. Ultimately, the majority class samples are closer to the center of the hypersphere c (the Euclidean distance is small), while the minority class samples are farther away from the hypersphere center (the reciprocal of the Euclidean distance is small).

[0104] For the loss function, we can use the formula Get. Among them, h (K) represents the Kth layer, i.e. the last hidden layer, c represents the center of the hypersphere, W (k) is a learnable parameter, the exponential part is the true label of the data, represents the L2 norm operation. The first term is the average Euclidean distance from all points to the center of the hypersphere, and the second term is the regularization term for the model parameters. The radius R of the hypersphere does not participate in the model's backpropagation and is only used for classifier classification. Nodes with Euclidean distances less than the radius are considered normal samples, while nodes with distances greater than the radius are considered abnormal samples.

[0105] After obtaining the loss function, the goal of model learning is to find appropriate parameters to minimize the loss function. This process is called optimization, and optimizers such as Adam, SDG, LookAhead, and Lion can be used. After multiple iterations of training, the model parameters are optimized to improve the accuracy of the model selection results.

[0106] Adjustments to the Deep SAD algorithm:

[0107] A single circuit generates a circuit netlist diagram. Since the purpose of the embodiment of the present invention is to predict the monitoring nodes in a new circuit, the training data used for training includes multiple circuits, so there are multiple circuit netlist diagrams. Although there are similarities between nodes, different circuit netlist diagrams can be regarded as independent. During training, it is necessary to loop between multiple circuit netlist diagrams, so when calculating the radius, it is necessary to calculate the average value of the radius of all circuit netlist diagrams. The radius of a single circuit netlist diagram can be obtained by the minimum Euclidean distance of the outlier point, while the original Deep SAD algorithm does not need to consider this problem. The original Deep SAD algorithm only provides a method for calculating the evaluation score, and does not explicitly provide the classification threshold, i.e., the radius.

[0108] The center of the hypersphere is determined by the average of the node representations after convergence in the previous round of training. The training model is still a graph convolutional neural network. The original Deep SAD algorithm was applied to the CNN network, so the center can be calculated using a pre-trained autoencoder, eliminating the complex connections and multiple circuit netlists.

[0109] The original algorithm used a CNN network to represent samples, while the adjusted Deep SAD algorithm in this embodiment uses a graph convolutional neural network as input. The original Deep SAD algorithm is a semi-supervised learning method, and the adjusted loss function removes the portion related to unlabeled data, effectively making it closer to supervised learning.

[0110] After the model is trained, it can make predictions for unknown circuits and obtain predicted label data. Combined with the circuit netlist file of the unknown circuit, the name of the monitoring node trigger can be obtained for subsequent replacement of the standard unit. In machine learning, the logic of the monitoring node selection method learned by the model is contained in the model parameters. In order to apply it to the actual selection process, it is necessary to save the model and its parameters as a local file. After the local file is prepared, the file can be called using a Python script to load the model and its parameters for real-time use. At this time, the model and its parameters are independent of the model training and testing process. After that, the command line can be used externally to run the script to construct the circuit netlist diagram, initialize features, load and infer the model, and implement a circuit timing monitoring method based on the graph convolutional neural network model.

[0111] In a specific example, the complete execution process of the above method can be:

[0112] First, circuit synthesis is performed on the training circuit to obtain circuit netlist data. The training circuit used can be a set of benchmark circuit designs commonly used in scientific research, such as ISCAS89 and ITC99, and can also include some open source hardware designs. Figure 11 shows a circuit synthesis result provided by an embodiment of the present invention. The circuit synthesis result shown in Figure 11 is a partial synthesis result of the S38584 circuit. To obtain label data, it is necessary to first analyze the circuit netlist data with the help of existing EDA tools and select monitoring nodes.

[0113] After circuit synthesis is complete, a circuit netlist file for all circuits is obtained. To obtain label data, static timing analysis is performed using a 65nm process. After timing analysis is complete, the setup time check results are saved to a text file. To facilitate subsequent program analysis, the timing report file only records the start and end points of the path, not the specific delays of the standard cells along the path. Figure 12 shows a timing report diagram provided by an embodiment of the present invention. Figure 12 shows the timing report generated by running the PT tool.

[0114] When building a training dataset, different timing analysis strategies are used, resulting in different logic learned by the model. For example, using both static timing analysis and circuit simulation, we used PT timing analysis and VCS simulation. Based on the simulation results, we further considered the activation of specific paths to eliminate invalid monitoring nodes, ultimately obtaining a set of monitoring nodes. Figure 13 shows some activation rate statistics and the principle of generating label data.

[0115] Next, the circuit netlist is mapped to obtain a circuit netlist graph. This is followed by an adjacency matrix, and data processing is performed on the monitoring node set to obtain label data. All standard cells under the current process are then encoded according to their functions, which serve as the standard cell's own initial feature representation. To effectively utilize the data, data augmentation is used to amplify the data.

[0116] After the training data set is built, the model code is implemented using the graph convolutional neural network framework, and the data is trained using the initial graph convolutional neural network model. Figure 14 is a training effect diagram of a graph convolutional neural network model provided by an embodiment of the present invention. As shown in Figure 14, the decrease in the value of the loss function (loss) indicates that the model has been fully trained. Figure 15 shows the accuracy of the graph convolutional neural network model during inference. As shown in Figure 15, it can be seen that the accuracy is gradually increasing and tends to be stable, indicating that the model can effectively select monitoring nodes.

[0117] After training is complete, the trained graph convolutional neural network model can be used to predict monitoring nodes in unknown circuits. Figure 16 shows an analysis result of the graph convolutional neural network output. As shown in Figure 16, the graph convolutional neural network is applied in a command mode.

[0118] Corresponding to the aforementioned sequential circuit monitoring method, an embodiment of the present invention provides a circuit sequential monitoring device. Figure 17 is a schematic diagram of the structure of a circuit sequential monitoring device provided by an embodiment of the present invention. As shown in Figure 17, the circuit sequential monitoring device includes: a node determination module 1701, a feature information determination module 1702, a monitoring node prediction module 1703, a monitoring node determination module 1704, and a sequential monitoring module 1705.

[0119] A node determination module 1701 is configured to determine a plurality of candidate monitoring nodes in a target circuit and a connection relationship between the plurality of candidate monitoring nodes;

[0120] A characteristic information determining module 1702 is configured to determine characteristic information of the target circuit based on device attribute information of the plurality of candidate monitoring nodes;

[0121] The monitoring node prediction module 1703 is configured to input the characteristic information of the target circuit and the connection relationship of the multiple candidate monitoring nodes into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs determination results of the multiple candidate monitoring nodes; the determination results include a first determination result that the candidate monitoring nodes are monitoring nodes and a second determination result that the candidate monitoring nodes are not monitoring nodes;

[0122] A monitoring node determination module 1704 is configured to determine at least one monitoring node from the plurality of candidate monitoring nodes based on the determination result output by the graph convolutional neural network model;

[0123] The timing monitoring module 1705 is configured to perform timing monitoring on the target circuit based on the at least one monitoring node.

[0124] Figure 18 is a structural diagram of an electronic device provided in an embodiment of the present invention. As shown in Figure 18, the above-mentioned electronic device may include at least one processor, and at least one memory communicatively connected to the above-mentioned processor, wherein: the memory stores program instructions that can be executed by the processor, and the above-mentioned processor calls the above-mentioned program instructions to execute the circuit timing monitoring method provided in the embodiments shown in Figures 1 to 16 of this specification.

[0125] As shown in Figure 18, the electronic device is implemented as a general-purpose computing device. Components of the electronic device may include, but are not limited to, one or more processors 1810, a communication interface 1820, and a memory 1830, and a communication bus 1840 that connects the various system components (including the memory 1830, the communication interface 1820, and the processor 1810).

[0126] Communication bus 1840 represents one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, a processor, or a local bus using any of a variety of bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnection (PCI) bus.

[0127] Electronic devices typically include a variety of computer system readable media. These media can be any available media that can be accessed by the electronic device, including volatile and non-volatile media, removable and non-removable media.

[0128] Memory 1830 may include computer-readable media in the form of volatile memory, such as random access memory (RAM) and / or cache memory. The electronic device may further include other removable / non-removable, volatile / non-volatile computer system storage media. Memory 1830 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of various embodiments of this specification.

[0129] A program / utility having a set (at least one) of program modules may be stored in memory 1830. Such program modules include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. The program modules generally implement the functions and / or methods of the embodiments described herein.

[0130] The processor 1810 executes various functional applications and data processing by running the programs stored in the memory 1830, such as implementing the circuit timing monitoring method provided in the embodiments shown in Figures 1 to 16 of this specification.

[0131] An embodiment of this specification provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions enable the computer to execute the circuit timing monitoring method provided by the embodiments shown in Figures 1 to 16 of this specification.

[0132] The above-mentioned computer-readable storage medium can adopt any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, device or device.

[0133] The foregoing description of this specification describes specific embodiments. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0134] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of this specification. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0135] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout this specification, "plurality" means at least two, such as two or three, unless otherwise specifically defined.

[0136] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of this specification includes alternative implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of this specification belong.

[0137] The word "if," as used herein, may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to the determination" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)," depending on the context.

[0138] It should be noted that the devices involved in the embodiments of this specification may include but are not limited to personal computers (Personal Computer; hereinafter referred to as: PC), personal digital assistants (Personal Digital Assistant; hereinafter referred to as: PDA), wireless handheld devices, tablet computers (Tablet Computer), mobile phones, MP3 displays, MP4 displays, etc.

[0139] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed may be through some interface, indirect coupling or communication connection of devices or units, which may be electrical, mechanical or other forms.

[0140] In addition, the functional units in the various embodiments of this specification may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or hardware plus software functional units.

[0141] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a connector, or a network device, etc.) or a processor to execute some steps of the method described in each embodiment of this specification. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (hereinafter referred to as: ROM), a random access memory (hereinafter referred to as: RAM), a magnetic disk or an optical disk, and other media that can store program code.

[0142] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

[0143] In this specification, reference can be made to the same or similar parts between the various embodiments. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A digital integrated circuit timing monitoring method based on graph convolutional neural network, characterized in that: include: Determine a plurality of candidate monitoring nodes in a target circuit and a connection relationship between the plurality of candidate monitoring nodes; Determining characteristic information of the target circuit based on device attribute information of the plurality of candidate monitoring nodes; Inputting the characteristic information of the target circuit and the connection relationship of the multiple candidate monitoring nodes into the trained target graph convolutional neural network model, so that the graph convolutional neural network model outputs the determination results of the multiple candidate monitoring nodes; the determination results include a first determination result of being a monitoring node and a second determination result of not being a monitoring node; Determine at least one valid monitoring node from the multiple candidate monitoring nodes according to the determination result output by the graph convolutional neural network model; The target circuit is subjected to timing monitoring based on the at least one monitoring node.

2. The method according to claim 1, characterized in that: The determining of a plurality of candidate monitoring nodes in the target circuit comprises: Acquiring circuit netlist data of the target circuit; Generate a corresponding circuit netlist diagram based on the circuit netlist data with standard cells and ports as nodes; The node in the circuit netlist diagram is determined as the candidate monitoring node.

3. The method according to claim 1, characterized in that: The connection relationship of each candidate monitoring node is an adjacency matrix, and the step of determining the connection relationship of the plurality of candidate monitoring nodes includes: Determining the connection relationship of each node according to the circuit connection relationship of the target circuit; Determine the connection relationship of the plurality of candidate monitoring nodes according to the connection relationship of the respective nodes; The adjacency matrix is ​​generated according to the connection relationship of the multiple candidate monitoring nodes.

4. The method according to claim 1, characterized in that The determining the characteristic information of the target circuit based on the device attribute information of the plurality of candidate monitoring nodes includes: Determine all device attribute information of the candidate monitoring node based on a process library corresponding to the target circuit; Selecting at least one device attribute information from the device attribute information of the candidate monitoring nodes as target device attribute information; The characteristic information of the target circuit is determined based on the target device attribute information corresponding to each of the candidate monitoring nodes.

5. The method according to claim 4, characterized in that The characteristic information of the target circuit is a characteristic matrix, and determining the characteristic information of the target circuit based on the target device attribute information corresponding to each of the candidate monitoring nodes includes: Determine a node vector corresponding to a candidate monitoring node according to the target device attribute information; A feature matrix of the target circuit is constructed according to the node vectors of the candidate monitoring nodes.

6. The method according to claim 1, characterized in that The training process of the target graph convolutional neural network model includes: Acquire a training data set; the training data set includes characteristic data of each node in the training circuit, connection relationships of each node, and label data of each node; wherein the label data includes: first label data of a monitoring node, and second label data of a non-monitoring node; Iteratively training the initial graph convolutional neural network model based on the training data set so that the initial graph convolutional neural network model learns node features of different label data; When it is detected that the loss function of the initial graph convolutional neural network model meets a preset condition, the training is determined to be completed, and the target convolutional neural network model is obtained.

7. The method according to claim 6, characterized in that The characteristic data is a characteristic matrix, the connection relationship is an adjacency matrix, and the steps of acquiring the characteristic data of each node and the connection relationship of each node include: Generate a circuit netlist diagram of the training circuit by using standard cells and ports in the training circuit as nodes; Determine the connection relationship of each node according to the circuit netlist diagram; An adjacency matrix of the training circuit is generated based on the connection relationship of each node, and a feature matrix of the training circuit is generated based on the device attribute information of each node.

8. The method according to claim 6, characterized in that The step of acquiring the label data of each node includes: Performing static timing analysis on the training circuit to obtain a critical path in the training circuit; Dynamically simulating the training circuit to determine an effective activation path from the critical path; Determining a plurality of valid monitoring points based on the valid activation path; The label data of the node corresponding to the effective monitoring point in the circuit netlist diagram is determined as the first label data, and the label data of the remaining nodes is determined as the second label data.

9. The method according to claim 6, characterized in that The target graph convolutional neural network model is formed by stacking multiple graph convolutional layers, wherein the input of the first graph convolutional layer among the multiple graph convolutional layers is the feature matrix of each node, the adjacency matrix of each node and the label data of each node; the data of other graph convolutional layers except the first graph convolutional layer is the output of the previous graph convolutional layer; The last graph convolution layer among the multiple graph convolution layers is connected to the algorithm layer; the algorithm layer constructs a hypersphere based on the target anomaly detection algorithm based on the data of each node output by the last graph convolution layer and calculates the Euclidean distance between each node and the center of the hypersphere; The output of the algorithm layer is connected to the input of the classifier. The classifier determines abnormal node data from the various node data according to the Euclidean distance corresponding to the various nodes and the radius of the hypersphere, and removes the abnormal node data.

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