Short-process preparation method for hybrid passivated back-contact cell and use thereof

Abstract

The present disclosure belongs to the technical field of the preparation of hybrid passivated back-contact cells, and specifically relates to a short-process preparation method for a hybrid passivated back-contact cell and the use thereof. The short-process preparation method comprises: S1, texturing both surfaces of a silicon wafer; S2, subjecting the front surface of the silicon wafer to phosphorus diffusion, so as to form a third semiconductor diffusion region, wherein the process of phosphorus diffusion comprises the steps of first performing low-temperature diffusion and then performing cooling and discharging, and during the period, heating is not performed to promote diffusion; S3, removing a diffusion layer that detours to and coats the back surface and a phosphorosilicate glass layer on the front surface, which are both obtained in S2; S4, sequentially depositing a first semiconductor layer and a mask layer on the back surface obtained in S3, and subjecting same to high-temperature annealing crystallization at the same time; S5, forming a second semiconductor opening region; and S6, forming an anti-reflection layer on the front surface of the silicon wafer. In the present disclosure, a passivation effect is good, and the film density is better; moreover, defects such as film holes are effectively ameliorated, the cell conversion efficiency and the cell yield are substantially improved, and the technological process is greatly simplified, thereby greatly reducing the equipment investment cost.

Description

A short-process preparation method for a combined passivated back contact battery and its application

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to application number CN202311385791.X filed with the Patent Office of China on October 25, 2023, entitled “A short-process preparation method for a combined passivated back contact battery and its application,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure belongs to the technical field of combined passivation back contact battery preparation, and particularly relates to a short-process preparation method of a combined passivation back contact battery and its application. Background Art

[0004] At present, the process flow of back-contact heterojunction solar cells is generally as follows: S101, providing a silicon wafer with a single-side textured and single-side polished structure; S102, coating the first semiconductor layer and the first mask layer on the back of the silicon wafer in sequence, the first semiconductor layer is formed by PECVD (plasma enhanced chemical vapor deposition) or Hot-wire (hot wire chemical vapor deposition), and the first semiconductor layer includes an intrinsic amorphous or microcrystalline silicon layer and an N-type doped amorphous or microcrystalline silicon layer; S103, laser or etch an opening on the back of the silicon wafer, remove the first mask layer and part of the first semiconductor layer, and form an opening in the second semiconductor region; S104, clean the silicon wafer, and remove the first semiconductor layer in the second semiconductor region; S105, forming a second semiconductor layer on the back of the silicon wafer, the second semiconductor layer is formed by PECVD or Hot-wire, and the second semiconductor layer includes an intrinsic amorphous or microcrystalline silicon layer and P-type doped amorphous or microcrystalline silicon layer; S106, forming a third semiconductor layer on the front side, the third semiconductor layer comprising a front passivation layer and an anti-reflection layer, the front passivation layer and the anti-reflection layer are formed by PECVD or Hot-wire method, the front passivation layer comprises an intrinsic amorphous silicon layer and an N-type doped amorphous or microcrystalline silicon layer, the anti-reflection layer is at least one of silicon nitride, silicon oxynitride, and silicon oxide; S107, laser or etching openings on the back side of the silicon wafer to form a first semiconductor region arranged alternately with the second semiconductor region; S108, cleaning the silicon wafer to remove the first mask layer in the first semiconductor region; S109, depositing a conductive film on the back side of the silicon wafer; S110, forming an insulating groove between the first semiconductor region and the second semiconductor region by laser or etching; S111, forming metal electrodes on the first semiconductor region and the second semiconductor region of the silicon wafer.

[0005] Currently, back-contact solar cells typically require the preparation of a silicon wafer with a polished backside and textured frontside. This results in a lengthy fabrication process. Furthermore, the first and third semiconductor layers on the backside consist of an intrinsic amorphous silicon layer and an N-type doped amorphous / microcrystalline silicon layer, respectively. These layers are typically formed separately using plate-type PECVD coating, a technique known as plate-type PECVD. Plate-type PECVD equipment is very expensive, resulting in a long process flow and high equipment investment. Furthermore, the third semiconductor layer on the front side of the cell exhibits significant parasitic absorption, reducing the silicon substrate's light absorption efficiency and, consequently, the cell's short-circuit current.

[0006] It should be noted that this part of the present disclosure only provides background technology related to the present disclosure and does not necessarily constitute prior art or public known technology.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the defects of the prior art, such as long process flow, high equipment investment, very large parasitic absorption of the third semiconductor layer, and low short-circuit current of the battery, and to provide a short-process preparation method for a combined passivated back-contact battery and its application. The combined passivated back-contact battery prepared by the short-process preparation method has excellent passivation effect and better film density. At the same time, it effectively improves defects such as film holes, significantly improves battery conversion efficiency and battery yield, and greatly reduces the parasitic absorption of the third semiconductor layer, thereby increasing the short-circuit current of the battery, and reducing the use of plate-type PECVD equipment, greatly simplifying the process flow, and thus greatly reducing equipment investment costs.

[0009] To achieve the above objectives, the present disclosure provides a short-process method for preparing a combined passivated back contact cell, comprising the following steps:

[0010] S1, perform double-sided texturing and cleaning on the silicon wafer;

[0011] S2. Diffusion of phosphorus on the front surface of the silicon wafer to form a third semiconductor diffusion region. The phosphorus diffusion process includes: firstly low-temperature diffusion, then cooling and exiting the furnace, without heating to advance the diffusion. The temperature of the low-temperature diffusion is 760-790° C.

[0012] S3, removing the diffusion layer on the back side of the silicon wafer obtained in S2 and the phosphorus silicon glass layer on the front side;

[0013] S4. Depositing a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer obtained in S3, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and a first doped polysilicon layer, wherein the tunneling silicon oxide layer, the first doped polysilicon layer, and the mask layer are all deposited in sequence using a polysilicon deposition furnace at a deposition temperature of 400-500° C.;

[0014] Then, high-temperature annealing crystallization is performed, wherein the temperature-increased diffusion process of the third semiconductor diffusion region and the first doped polysilicon layer is performed together during the high-temperature annealing crystallization. The conditions of the high-temperature annealing crystallization include: in the presence of a protective gas, controlling the high-temperature annealing crystallization temperature to 880-930° C., the pressure to 300-1000 Pa, and the time to 60-120 minutes;

[0015] S5, performing a first etching opening on the back surface obtained in S4 to form a second semiconductor opening region;

[0016] S6, then forming an anti-reflection layer on the front side of the silicon wafer;

[0017] S7, then cleaning to perform texturing or polishing on the second semiconductor opening area;

[0018] S8. Then, a second semiconductor layer is formed on the back surface of the substrate obtained in S7. The second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer.

[0019] In some preferred embodiments of the present disclosure, the low-temperature diffusion conditions described in S2 include: controlling the volume flow rate of the introduced oxygen to 400 sccm-800 sccm, the total volume flow rate of the small nitrogen carrying phosphorus oxychloride to 50 sccm-200 sccm, the gas pressure to 50 mbar-150 mbar, and the time to 4-8 min.

[0020] In some preferred embodiments of the present disclosure, the effective doping concentration of the third semiconductor diffusion region formed by the low temperature diffusion in S2 is 5e18-9e18cm -3 ; and / or, the thickness of the third semiconductor diffusion region is 100-300nm.

[0021] In some preferred embodiments of the present disclosure, the cooling temperature in S2 is 700-750°C.

[0022] In some preferred embodiments of the present disclosure, the process of removing the diffusion layer on the back side of the silicon wafer obtained in S2 and the phosphosilicate glass layer on the front side described in S3 includes: first single-sided polishing the back side of the silicon wafer to remove the diffusion layer on the back side of the silicon wafer, and then removing the phosphosilicate glass layer on the front side of the silicon wafer through a cleaning process.

[0023] Preferably, the protective gas in S4 is nitrogen, and the volume flow rate of the nitrogen is controlled to be 5000-15000 sccm.

[0024] In some preferred embodiments of the present disclosure, the deposition conditions of the tunneling silicon oxide layer in S4 include: controlling the volume flow rate of the nitrous oxide to be 800-1200 sccm, the pressure to be 100-200 Pa, the power to be 10-20 kW, and the time to be 60-120 s.

[0025] In some preferred embodiments of the present disclosure, the deposition conditions of the first doped polysilicon layer in S4 include: adopting a one-step deposition process of directly introducing a gas including silane, a doping element source gas, and hydrogen.

[0026] More preferably, during the deposition of the first doped polysilicon layer, the volume flow rate of silane is controlled to be 2000-3000sccm, the volume flow rate of the doping element gas source is controlled to be 1000-2500sccm, the volume flow rate of hydrogen is controlled to be 7000-9000sccm, the pressure is 400-500Pa, the power supply is 10-20kW, and the deposition time is 800-1300s.

[0027] In some preferred embodiments of the present disclosure, in S4, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 70-120 nm, and the effective doping concentration of the first doped polysilicon layer is 1e19-9e20 cm -3 .

[0028] Preferably, the thickness of the mask layer is 30-90 nm.

[0029] In some preferred embodiments of the present disclosure, in S8, the thickness of the intrinsic hydrogenated amorphous silicon layer is 4-8 nm, the thickness of the second doped silicon layer is 6-12 nm, and the effective doping concentration of the second doped silicon layer is 1e19-9e20 cm -3 .

[0030] In some preferred embodiments of the present disclosure, the second semiconductor opening area is polished by the cleaning in S7, and the polishing process includes: first polishing with a strong alkali solution, the etching depth of the second semiconductor opening area is 0.2-1 μm, and then cleaning is performed to remove organic matter, metal ions and surface oxide layer; wherein, the strong alkali solution is NaOH solution or KOH solution and its mass concentration is 1%-5%, the polishing reaction temperature is 60-75°C, and the reaction time is 60-180s.

[0031] In some preferred embodiments of the present disclosure, the short-process preparation method further comprises:

[0032] S9, then performing a second etching opening on the back surface obtained in S8 to form a first semiconductor opening region;

[0033] S10, depositing a conductive film layer on the back surface obtained in S9;

[0034] S11, performing a third etching opening on the back surface obtained in S10 to form an insulating trench in a region between the first semiconductor opening region and the second semiconductor opening region;

[0035] S12, forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back surface obtained in S11.

[0036] The present disclosure also provides a short-process preparation method of the aforementioned combined passivation back contact battery, and its application in the preparation of back contact batteries. Beneficial effects:

[0037] The present disclosure utilizes the above-mentioned technical solution, particularly by forming a third semiconductor diffusion region on the front side of the silicon wafer. Instead of performing a temperature-increased diffusion after the low-temperature diffusion of the third semiconductor diffusion region, the temperature-increased diffusion of the third semiconductor diffusion region is integrated with the high-temperature annealing crystallization of the first semiconductor layer. This significantly reduces process cycle time and improves equipment production capacity. It also facilitates achieving an appropriate junction depth for the third semiconductor diffusion region, thereby enhancing the passivation effect, battery conversion efficiency, and battery yield. Under the same conditions, if the temperature-increased diffusion in S2 is followed by a high-temperature annealing crystallization process in S4, the high-temperature annealing crystallization is equivalent to a secondary diffusion process, which can easily cause the junction depth of the third semiconductor layer to be too large, thereby affecting the passivation effect.

[0038] Among them, the present invention uses the silicon wafer body to diffuse phosphorus to form a third semiconductor diffusion region. Compared with the conventional structure in the prior art of depositing a third semiconductor layer such as a tunneling polycrystalline structure on the outer surface of the front side of the silicon wafer, it has better density and effectively improves defects such as holes, thereby improving the battery yield.

[0039] The present disclosure also cooperates with a cleaning process in which an anti-reflection layer is formed on the front side after the second semiconductor opening area is formed and then a texturing or polishing process is performed. Compared with the conventional process in the prior art of first forming an anti-reflection layer and then etching and opening the second semiconductor opening area and cleaning, it is less likely to produce defects such as holes. At the same time, there is no need to prepare a silicon wafer with polished back side and texturing on the front side, which simplifies the process flow and can form a back-contact battery with a texturing structure on the front side in a short process. In addition, the tunneling silicon oxide layer, the first doped polysilicon layer and the mask layer are all deposited in sequence in a polysilicon deposition furnace, which greatly reduces equipment investment, simplifies the process flow, and improves the battery yield.

[0040] Compared with conventional back-contact solar cells, the back-contact cell disclosed in the present invention does not require additional deposition of an intrinsic amorphous silicon layer and an N-type doped amorphous or microcrystalline silicon layer on the front side as a third semiconductor layer, thereby greatly reducing the parasitic absorption of the third semiconductor layer, thereby increasing the short-circuit current of the cell, and reducing the use of plate-type PECVD equipment, greatly simplifying the process flow, and thus significantly reducing equipment investment costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0042] FIG1 is a process flow chart for preparing a combined passivated back contact cell according to a specific embodiment of the present disclosure;

[0043] FIG2 is a schematic structural diagram of the combined passivation back contact cell obtained in FIG1 of the present disclosure.

[0044] Explanation of the accompanying symbols: 1. Silicon wafer, 2. Third semiconductor diffusion region, 3. Anti-reflection layer, 4. Tunneling silicon oxide layer, 5. N-type first doped polysilicon layer, 6. Mask layer, 7. Intrinsic hydrogenated amorphous silicon layer, 8. P-type second doped silicon layer, 9. Conductive film layer, 10. Metal electrode, 101. Interface. DETAILED DESCRIPTION

[0045] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0046] The present disclosure provides a short-process preparation method for a combined passivation back contact battery, comprising the following steps: S1, performing double-sided texturing and cleaning on a silicon wafer; S2, performing phosphorus diffusion on the front side of the silicon wafer to form a third semiconductor diffusion region, wherein the phosphorus diffusion process comprises: first performing low-temperature diffusion, then cooling and taking out of the furnace, without heating to promote diffusion during the period, wherein the temperature of the low-temperature diffusion is 760-790°C.

[0047] In some preferred embodiments of the present disclosure, the low-temperature diffusion conditions described in S2 include: controlling the volume flow rate of oxygen to 400-800 sccm, the total volume flow rate of nitrogen carrying phosphorus oxychloride to 50-200 sccm, the gas pressure to 50-150 mbar, and the duration to 4-8 minutes. This preferred embodiment employs suitable low-temperature diffusion conditions, capable of controlling the effective doping concentration of the third semiconductor diffusion region within a relatively low range, thereby further enhancing the passivation effect.

[0048] In this disclosure, the term "small nitrogen carrying phosphorus oxychloride" has the conventional meaning in the art, meaning that nitrogen gas passes through a liquid bottle containing liquid phosphorus oxychloride, carrying the phosphorus oxychloride into the reaction chamber. The introduced oxygen and the small nitrogen carrying phosphorus oxychloride are collectively referred to as "special gases."

[0049] In some preferred embodiments of the present disclosure, the effective doping concentration of the third semiconductor diffusion region formed by the low temperature diffusion in S2 is 5e18-9e18cm -3 , preferably 5e18-7e18cm -3 and / or the thickness of the third semiconductor diffusion region is 100-300 nm. The effective doping concentration of the third semiconductor diffusion region disclosed herein is much lower than the doping concentration of the third semiconductor layer on the front surface of a conventional PERC cell. The third semiconductor diffusion region disclosed herein only serves a passivation function and does not need to consider issues such as carrier transport and contact resistance with the metal electrode that arise in conventional PERC cell structures. The lower doping concentration and thickness of the diffusion region further enhance the passivation effect.

[0050] In some preferred embodiments of the present disclosure, the cooling temperature in S2 is 700-750°C.

[0051] The process of cooling and taking out of the furnace in S2 can be determined according to actual needs. For example, it can include: vacuuming (i.e., vacuuming the special gas), cooling, and taking out of the furnace after breaking the air.

[0052] The silicon wafer may be a Czochralski single crystal silicon wafer or a cast single crystal silicon wafer.

[0053] The short-process preparation method provided by the present disclosure further includes the following steps: S3, removing the plated diffusion layer on the back side of the silicon wafer obtained in S2 and the phosphorus silicon glass layer on the front side.

[0054] In some preferred embodiments of the present disclosure, the process of removing the diffusion layer on the back side of the silicon wafer obtained in S2 and the phosphosilicate glass layer on the front side described in S3 includes: first single-sided polishing the back side of the silicon wafer to remove the diffusion layer on the back side of the silicon wafer, and then removing the phosphosilicate glass layer on the front side of the silicon wafer through a cleaning process.

[0055] The polishing and cleaning methods described in S3 are performed according to prior art techniques and are not limited in this disclosure. The polishing can be performed, for example, using a chain cleaning machine. The cleaning process described in S3 refers to conventional cleaning techniques, such as using HF aqueous solution, SC1 cleaning solution, or SC2 cleaning solution.

[0056] The short-process preparation method provided by the present disclosure further includes the following steps: S4, sequentially depositing a first semiconductor layer and a mask layer on the back side of the silicon wafer obtained in S3, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and a first doped polysilicon layer, wherein the tunneling silicon oxide layer, the first doped polysilicon layer, and the mask layer are all sequentially deposited using a polysilicon deposition furnace, and the deposition temperature is 400-500°C, preferably 450-500°C; and then performing high-temperature annealing crystallization, and the temperature-promoted diffusion process of the third semiconductor diffusion region and the first doped polysilicon layer is carried out together during the high-temperature annealing crystallization. The tunneling silicon oxide layer, the first doped polysilicon layer, and the mask layer of the present disclosure are all sequentially deposited using a polysilicon deposition furnace, and the deposition temperature is controlled to be 400-500°C, which can greatly simplify the process flow, and is more conducive to reducing equipment costs, improving battery yield, and improving battery conversion efficiency.

[0057] The high-temperature annealing crystallization conditions include: controlling the high-temperature annealing crystallization temperature to 880-930°C, preferably 900-930°C, and more preferably 900-920°C, under a protective gas, at a pressure of 300-1000 Pa, for 60-120 minutes. This preferred embodiment adopts appropriate high-temperature annealing crystallization conditions, which can shorten the annealing crystallization process time while ensuring the crystallization quality of the first doped polysilicon layer, thereby improving the production capacity of the high-temperature annealing equipment.

[0058] Preferably, the protective gas in S4 is nitrogen, and the volume flow rate of the nitrogen is controlled to be 5000-15000 sccm.

[0059] In some preferred embodiments of the present disclosure, the deposition conditions of the tunneling silicon oxide layer in S4 include: controlling the volume flow rate of the nitrous oxide to be 800-1200 sccm, the pressure to be 100-200 Pa, the power to be 10-20 kW, and the time to be 60-120 s.

[0060] In some preferred embodiments of the present disclosure, the deposition conditions for the first doped polysilicon layer in S4 include a one-step deposition process in which gases including silane, a doping element source gas, and hydrogen are directly introduced. This one-step deposition process is more streamlined and can complete the deposition of the tunneling oxide / doping layer and the mask layer in a single step. This compares to the conventional three-step process of depositing the tunneling oxide intrinsic amorphous silicon, then diffusing the doping layer, and then depositing the mask layer.

[0061] More preferably, during the deposition of the first doped polysilicon layer, the volume flow rate of the silane is controlled to be 2000-3000 sccm, the volume flow rate of the doping element source gas is controlled to be 1000-2500 sccm, the volume flow rate of the hydrogen gas is controlled to be 7000-9000 sccm, the pressure is controlled to be 400-500 Pa, the power supply is controlled to be 10-20 kW, and the deposition time is controlled to be 800-1300 s. This preferred embodiment adopts suitable deposition conditions for the first doped polysilicon layer, can better control the doping concentration and thickness of the first doped polysilicon layer, and is more conducive to improving the passivation effect and conversion efficiency of the battery.

[0062] In the present disclosure, when the first doped polysilicon layer is N-type, the doping element is phosphorus, and the doping element gas source can be, for example, phosphine, arsine, etc.; when the first doped polysilicon layer is P-type, the doping element is boron, and the doping element gas source can be, for example, diborane, TMB, etc.

[0063] In the present disclosure, preferably, the doping element gas source is a gas diluted with hydrogen, and the mass ratio of the doping element gas to hydrogen is 1:40-55.

[0064] The thickness of the tunneling silicon oxide layer, the first doped polysilicon layer, the mask layer and the doping concentration of the first doped polysilicon layer can be carried out according to the prior art. In some preferred embodiments of the present disclosure, in S4, the thickness of the tunneling silicon oxide layer is 1-2 nm.

[0065] Preferably, the thickness of the first doped polysilicon layer is 70-120 nm, and the effective doping concentration of the first doped polysilicon layer is 1e19-9e20 cm -3 .

[0066] Preferably, the thickness of the mask layer is 30-90 nm.

[0067] The mask layer may be of a conventional type in the art, such as silicon oxide, silicon nitride, or silicon oxynitride. In one embodiment, the mask layer is silicon dioxide, and the deposition conditions for the silicon dioxide may include, for example, controlling the volume flow rate of silane to be 1000-2000 sccm, the volume flow rate of nitrous oxide to be 7000-15000 sccm, the pressure to be 200-300 Pa, the power to be 10-20 kW, and the deposition time to be 300-800 s.

[0068] The short-process preparation method provided by the present disclosure further includes the following steps: S5, performing a first etching opening on the back surface obtained in S4 to form a second semiconductor opening area.

[0069] The first etching method can be laser or mask etching, as long as the second semiconductor opening region is formed. The laser can be, for example, ultraviolet or green laser, with a pulse width of less than 10 ns. The width of the formed second semiconductor opening region can be, for example, 400-800 μm.

[0070] The short-process preparation method provided by the present disclosure further includes the following steps: S6, then forming an anti-reflection layer on the front side of the silicon wafer.

[0071] The type and thickness of the anti-reflection layer in S6 may be within conventional ranges in the art, for example, silicon oxide, silicon nitride, or silicon oxynitride, and its thickness may be, for example, 70-120 nm. The anti-reflection layer may be deposited by conventional PECVD coating.

[0072] The short-process preparation method provided by the present disclosure further includes the following steps: S7, cleaning is then performed to perform texturing or polishing on the second semiconductor opening area.

[0073] The cleaning step S7 is used to remove damage or dirt caused by the first etching opening to form the second semiconductor opening region. After the corresponding texturing or polishing, the interface of the second semiconductor opening region of the silicon wafer becomes a texturing surface or a polishing surface. The cleaning agent used in the cleaning step can be an alkaline solution, such as an aqueous solution containing sodium hydroxide and / or potassium hydroxide, with a mass concentration of the alkaline solution being 1% to 5%.

[0074] In some preferred embodiments of the present disclosure, the second semiconductor opening area is polished by the cleaning in S7, and the polishing process includes: first polishing with a strong alkali solution, the etching depth of the second semiconductor opening area is 0.2-1μm, and then cleaning to remove organic matter, metal ions and surface oxide layer; wherein, the strong alkali solution is NaOH solution or KOH solution and its mass concentration is 1%-5%, the polishing reaction temperature is 60-75°C, and the reaction time is 60-180s. The cleaning in the process of cleaning to remove organic matter, metal ions and surface oxide layer in S7 can be carried out according to conventional cleaning steps, and the cleaning liquids used are SC1 cleaning liquid, SC2 cleaning liquid, and HF aqueous solution. In the short-process preparation method of the present disclosure, due to the use of a special one-step annealing crystallization process, the damaged layer of the second semiconductor opening area is very thin. The present disclosure uses a lower reaction temperature and a low concentration of strong alkali solution to remove the damaged layer of the second semiconductor opening area by polishing, thereby reducing production costs.

[0075] In some other embodiments of the present disclosure, in S7, the second semiconductor opening region is texturized by the cleaning, and the texturizing process includes: first texturizing with an alkaline texturizing solution, the texturizing etching the second semiconductor opening region to a depth of 0.2-1 μm, and then cleaning (i.e., a conventional cleaning process) to remove organic matter, metal ions, and a surface oxide layer. The alkaline texturizing solution is a mixed aqueous solution containing a KOH solution with a mass concentration of 1%-3% and a texturizing additive with a mass concentration of 0.2%-0.5%, the reaction temperature is 60-75°C, and the reaction time is 300-600 seconds.

[0076] The short-process preparation method provided by the present disclosure further includes the following steps: S8, then forming a second semiconductor layer on the back side obtained in S7, wherein the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer.

[0077] The second doped silicon layer may be a doped amorphous silicon layer or a doped microcrystalline silicon layer. One of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type.

[0078] In some preferred embodiments of the present disclosure, in S8, the thickness of the intrinsic hydrogenated amorphous silicon layer is 4-8 nm, the thickness of the second doped silicon layer is 6-12 nm, and the effective doping concentration of the second doped silicon layer is 1e19-9e20 cm -3 .

[0079] The present disclosure may also include other conventional steps. In some preferred embodiments of the present disclosure, the short process preparation method further includes:

[0080] S9, then performing a second etching opening on the back surface obtained in S8 to form a first semiconductor opening region;

[0081] S10, depositing a conductive film layer on the back surface obtained in S9;

[0082] S11, performing a third etching opening on the back surface obtained in S10 to form an insulating trench in a region between the first semiconductor opening region and the second semiconductor opening region;

[0083] S12, forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back surface obtained in S11.

[0084] The second etched opening in S9 can be formed by laser or mask etching, as long as the second semiconductor layer above the first semiconductor layer is etched away to form the first semiconductor opening region. The laser can be an ultraviolet or green laser with a pulse width of less than 10 ns. The width of the first semiconductor opening region can be, for example, 100-250 μm.

[0085] The conductive film layer in S10 can be deposited using physical vapor deposition (PVD) or activated plasma deposition (RPD). The thickness of the conductive film layer can be, for example, 40-80 nm, and the material of the conductive film layer can be, for example, an indium oxide-based film doped with at least one of tin, tungsten, titanium, and zinc, or a zinc oxide-based film doped with aluminum and / or boron.

[0086] The third etching opening in S11 can be performed by mask etching or laser etching, for example. The width W3 of the formed insulating groove is 20-100 μm, and the resistance between the first semiconductor opening region and the second semiconductor opening region after etching is greater than 1 kΩ.

[0087] The metal electrodes in S12 may be formed using screen printing technology. It is understood that the polarities of the metal electrodes formed on the first semiconductor opening region and the second semiconductor opening region are different.

[0088] The present disclosure also provides a short-process preparation method of the aforementioned combined passivation back contact battery, and its application in the preparation of back contact batteries.

[0089] The embodiments of the present disclosure are described in detail below, which are exemplary and only used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0090] Example 1

[0091] A short-process preparation method for a combined passivated back contact battery, as shown in Figures 1 and 2, includes the following steps:

[0092] S1, Silicon wafer 1 texturing:

[0093] The double-sided texturing and cleaning of an N-type single crystal silicon wafer 1 is performed, wherein the silicon wafer 1 is a Czochralski single crystal silicon wafer.

[0094] S2. Diffusion is performed on the front surface of the silicon wafer 1 to form a third semiconductor diffusion region:

[0095] Phosphorus is diffused on the front of the silicon wafer 1 to form a third semiconductor diffusion region 2 with a thickness of 150nm. When the phosphorus diffusion is filled with special gas (special gas refers to the oxygen and small nitrogen carrying trichlorophosphate, trichlorophosphate is a liquid), the volume flow rate of oxygen is 400sccm, the total volume flow rate of small nitrogen carrying trichlorophosphate is 100sccm, the pressure is 80mbar, the temperature is 780℃, and the time is 5min. There is no need to heat up and promote the diffusion process in the conventional diffusion process. After filling with special gas, the air is evacuated, the temperature is lowered to 700℃, and the air is broken before it can be taken out of the furnace. After diffusion, the effective doping concentration of phosphorus atoms in the third semiconductor diffusion region 2 on the front of the silicon wafer 1 is 5e18cm -3 .

[0096] S3, polishing to remove the diffusion layer on the back side of the silicon wafer 1 and the phosphorus silicon glass layer on the front side:

[0097] The back of the silicon wafer 1 is single-sided polished using a chain cleaning machine to remove the diffusion layer around the back of the silicon wafer 1, and then cleaned with a conventional HF aqueous solution (concentration of 5wt%) to remove the phosphorus silicon glass layer on the surface of the silicon wafer.

[0098] S4, depositing a first semiconductor layer and a mask layer 6 on the back side of the silicon wafer 1, and then annealing at high temperature for crystallization:

[0099] The first semiconductor layer includes a tunneling silicon oxide layer 4 and an N-type first doped polysilicon layer 5. The mask layer 6 is silicon oxide. The tunneling silicon oxide layer 4 has a thickness of 1.5 nm, the N-type first doped polysilicon layer 5 has a thickness of 100 nm, and an effective doping concentration of 2e20 cm -3 , the thickness of the mask layer 6 is 70 nm.

[0100] The tunneling silicon oxide layer 4, the N-type first doped polysilicon layer 5, and the mask layer 6 are all sequentially formed using a polysilicon deposition furnace at a deposition temperature of 450°C. When depositing the tunneling silicon oxide layer 4, the volume flow rate of nitrous oxide (NNO) is 800 sccm, the pressure is 100 Pa, the power is 10 kW, and the deposition time is 80 seconds. When depositing the N-type first doped polysilicon layer 5, the volume flow rate of silane is 2000 sccm, the volume flow rate of hydrogen-diluted phosphine (composition: 2% PH3:98% H2 by mass) is 1000 sccm, the volume flow rate of hydrogen is 8000 sccm, the pressure is 400 Pa, the power is 10 kW, and the deposition time is 900 seconds. When depositing silicon oxide (mask layer 6), the volume flow rate of silane introduced is 1000 sccm, the volume flow rate of nitrous oxide is 8000 sccm, the pressure is 250 Pa, the power is 10 kW, and the time is 500 s.

[0101] During the high-temperature annealing crystallization, nitrogen gas was introduced with a volume flow rate of 5000 sccm, an annealing temperature of 900° C., a pressure of 800 Pa, and a time of 90 minutes.

[0102] S5. Perform a first etching opening on the back side of the silicon wafer 1 to form a second semiconductor opening region:

[0103] The first etching opening is formed by using a laser, which is an ultraviolet laser with a pulse width of 5 ns. The width of the formed second semiconductor opening region is 500 μm.

[0104] S6. Forming an anti-reflection layer 3 on the front surface of the silicon wafer 1:

[0105] The anti-reflection layer 3 is silicon nitride with a thickness of 80 nm and is deposited by conventional PECVD coating method.

[0106] S7, silicon wafer 1 cleaning:

[0107] The second semiconductor opening region W1 on the back side of the silicon wafer 1 is polished by cleaning with an alkaline solution. The interface 101 of the second semiconductor opening region of the silicon wafer 1 serves as the polished surface. The polishing process includes first polishing with a strong alkaline solution, followed by a conventional HF aqueous solution (5 wt %) cleaning to remove organic matter, metal ions, and the surface oxide layer. The strong alkaline solution is a 3 wt % NaOH aqueous solution. The reaction temperature is 75°C and the reaction time is 80 seconds. The polishing results in an etching depth of 0.5-1 μm in the second semiconductor opening region.

[0108] S8. Forming a second semiconductor layer on the back side of the silicon wafer 1:

[0109] The second semiconductor layer includes an intrinsic hydrogenated amorphous silicon layer 7 and a P-type second doped silicon layer 8 (specifically an amorphous silicon layer). The second semiconductor layer is formed by plate-type CVD. The intrinsic hydrogenated amorphous silicon layer 7 has a thickness of 4 nm, and the P-type second doped silicon layer 8 has a thickness of 8 nm and an effective doping concentration of 1e20 cm -3 .

[0110] S9, a second etching opening is performed on the back side of the silicon wafer 1 to form a first semiconductor opening region:

[0111] The second etching opening is formed by laser, wherein the laser is ultraviolet laser with a pulse width of 15 ps. The width of the formed second semiconductor opening region is 100 μm.

[0112] S10, depositing a conductive film layer 9 on the back side of the silicon wafer 1:

[0113] A transparent conductive film layer 9 is deposited on the back of the silicon wafer 1 by physical vapor deposition (PVD). The thickness of the conductive film layer 9 is 60 nm. The material of the conductive film layer 9 is a tin-doped indium oxide-based thin film.

[0114] S11, performing a third etching opening on the back side of the silicon wafer 1 to form an insulating trench:

[0115] A third etching opening is performed on the back of the silicon wafer 1 using mask etching to form an insulating trench W3 between the first semiconductor opening region and the second semiconductor opening region. W3 is 30 μm, and the resistance between the first semiconductor and the second semiconductor after etching is 2 kΩ.

[0116] S12, forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer 1 respectively:

[0117] Metal electrodes 10 are formed on the surfaces of the first semiconductor opening region W1 and the second semiconductor opening region W2 on the back side of the silicon wafer 1 by using screen printing technology.

[0118] Example 2

[0119] The method of Example 1 is followed, except that the effective doping concentration of the third semiconductor diffusion region formed in S2 is 9e18cm -3 The process parameters that need to be changed to obtain this doping concentration are: the temperature during phosphorus diffusion and special gas filling is 790℃ and the time is 7 minutes.

[0120] Example 3

[0121] The method of Example 1 is referred to, except that in S4, the tunneling silicon oxide layer, the first doped polysilicon layer and the mask layer are all deposited in a polysilicon deposition furnace at a temperature of 400°C.

[0122] Example 4

[0123] The method of Example 1 is referred to, except that in S4, the temperature of high temperature annealing crystallization is controlled to be 880°C.

[0124] Example 5

[0125] The method of Example 1 is referred to, except that in S4, the temperature of high-temperature annealing crystallization is controlled to be 930°C.

[0126] Example 6

[0127] The method of Example 1 is followed, except that in S7, the second semiconductor opening region is texturized by the cleaning process. The texturizing process includes: first texturizing with an alkaline texturizing solution, and then cleaning with an HF aqueous solution (concentration: 5 wt%) to remove organic matter, metal ions, and the surface oxide layer. The alkaline texturizing solution is a mixed aqueous solution of a 1 wt % KOH solution and a 0.2 wt % texturizing additive. The reaction temperature is 75°C, the reaction time is 500 s, and the texturizing process etches the second semiconductor opening region to a depth of 0.5-1 μm.

[0128] Comparative Example 1

[0129] The method of Example 1 is referred to, except that, in S2, after the low-temperature diffusion, the temperature-promoted diffusion is further performed. The conditions for the temperature-promoted diffusion include: introducing oxygen with a volume flow rate of 5000 sccm, an annealing temperature of 900°C, a pressure of 500 Pa, and a time of 35 minutes; and then cooling and taking out of the furnace.

[0130] Comparative Example 2

[0131] The method of Example 1 is referred to, except that in S2, phosphorus is not directly diffused into the silicon wafer. Instead, a conventional intrinsic amorphous silicon layer and an N-type doped amorphous silicon layer are additionally deposited on the front side of the silicon wafer by plate-type PECVD as a third semiconductor layer. The thickness of the intrinsic amorphous silicon layer is 5 nm, and the thickness of the N-type doped amorphous silicon layer is 10 nm.

[0132] Comparative Example 3

[0133] The method of Example 1 is referred to, except that in S4, the temperature of high temperature annealing crystallization is 800°C.

[0134] Test Case

[0135] The combined passivated back contact cells obtained in the above examples and comparative examples were subjected to various performance tests, and the results are shown in Table 1.

[0136] Table 1

[0137] The equipment investment cost, other examples and comparative examples are compared with Example 1 as a reference benchmark, and Example 1 is calculated as 1.

[0138] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present disclosure can reduce the process cycle, increase the current density, help reduce the equipment investment cost, and improve the battery conversion efficiency and battery yield.

[0139] Furthermore, according to the comparison between Example 1 and Examples 2-6, it can be seen that the use of the preferred diffusion process, doping polycrystalline deposition process, crystallization annealing process or polishing and cleaning process disclosed in the present invention can further improve the current density of the battery, which is more conducive to improving the conversion efficiency and battery yield of the battery.

[0140] The preferred embodiments of the present disclosure are described in detail above, but the present disclosure is not limited thereto. Within the technical concept of the present disclosure, various simple variations of the technical solution of the present disclosure may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed by the present disclosure and fall within the scope of protection of the present disclosure. Industrial Applicability

[0141] The present invention forms a third semiconductor diffusion region on the front side of the silicon wafer, and does not perform temperature-promoted diffusion after the low-temperature diffusion of the third semiconductor diffusion region. Instead, the temperature-promoted diffusion of the third semiconductor diffusion region is integrated with the high-temperature annealing crystallization of the first semiconductor layer, which greatly reduces the process cycle time and improves the equipment production capacity. At the same time, it can help the third semiconductor diffusion region obtain a suitable junction depth, thereby improving the passivation effect, improving the battery conversion efficiency and battery yield, and has very good industrial application prospects.

Claims

1. A short process method for preparing a combined passivation back contact battery, characterized in that: The following steps are involved: S1, double-sided texturing and cleaning of silicon wafer; S2, diffusing phosphorus on the front side of the silicon wafer to form a third semiconductor diffusion region, wherein the phosphorus diffusion process includes: firstly performing low-temperature diffusion, then cooling down and taking out of the furnace, and not heating up to promote diffusion during the process, wherein the temperature of the low-temperature diffusion is 760-790° C.; S3, removing the diffusion layer on the back side of the silicon wafer obtained in S2 and the phosphorus silicon glass layer on the front side; S4, depositing a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer obtained in S3, wherein the first semiconductor layer comprises a tunneling silicon oxide layer and a first doped polysilicon layer, wherein the tunneling silicon oxide layer, the first doped polysilicon layer and the mask layer are all deposited in sequence using a polysilicon deposition furnace, and the deposition temperature is 400-500° C.; Then, high temperature annealing crystallization is performed, and the temperature-increasing diffusion process of the third semiconductor diffusion region and the first doped polysilicon layer is performed together in the high temperature annealing crystallization; wherein the conditions of the high temperature annealing crystallization include: in the presence of a protective gas, controlling the high temperature annealing crystallization temperature to be 880-930° C., the pressure to be 300-1000 Pa, and the time to be 60-120 min; S5, performing a first etching opening on the back surface obtained in S4 to form a second semiconductor opening region; S6, then forming an anti-reflection layer on the front side of the silicon wafer; S7, then cleaning to perform texturing or polishing on the second semiconductor opening area; S8, then forming a second semiconductor layer on the back side obtained in S7, wherein the second semiconductor layer comprises an intrinsic hydrogenated amorphous silicon layer and a second doped silicon layer.

2. The short-process preparation method according to claim 1, characterized in that: The conditions for low-temperature diffusion in S2 include: controlling the volume flow rate of oxygen to be 400 sccm-800 sccm, the total volume flow rate of nitrogen carrying phosphorus oxychloride to be 50 sccm-200 sccm, the gas pressure to be 50 mbar-150 mbar, and the time to be 4-8 minutes.

3. The short-process preparation method according to claim 1, characterized in that: The effective doping concentration of the third semiconductor diffusion region formed by low temperature diffusion in S2 is 5e18-9e18cm -3 ; and / or, the thickness of the third semiconductor diffusion region is 100-300nm.

4. The short-process preparation method according to claim 1, characterized in that: The process of removing the plated diffusion layer on the back side of the silicon wafer obtained in S2 and the phosphosilicate glass layer on the front side described in S3 includes: first single-sided polishing of the back side of the silicon wafer to remove the plated diffusion layer on the back side of the silicon wafer, and then removing the phosphosilicate glass layer on the front side of the silicon wafer through a cleaning process.

5. The short-process preparation method according to claim 1, characterized in that: The protective gas in S4 is nitrogen, and the volume flow rate of the nitrogen is controlled to be 5000-15000 sccm.

6. The short-process preparation method according to claim 1, characterized in that: The deposition conditions of the tunneling silicon oxide layer in S4 include: controlling the volume flow rate of the laughing gas to be 800-1200 sccm, the pressure to be 100-200 Pa, the power to be 10-20 kW, and the time to be 60-120 s; and / or, The deposition conditions of the first doped polysilicon layer in S4 include: adopting a one-step deposition process of directly introducing gases including silane, doping element gas source and hydrogen, and controlling the volume flow rate of the introduced silane to 2000-3000sccm, the volume flow rate of the doping element gas source to 1000-2500sccm, the volume flow rate of hydrogen to 7000-9000sccm, the pressure to 400-500Pa, the power supply to 10-20kW, and the deposition time to 800-1300s.

7. The short-process preparation method according to claim 1, characterized in that: In S4, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the first doped polysilicon layer is 70-120 nm, and the effective doping concentration of the first doped polysilicon layer is 1e19-9e20 cm -3 , the thickness of the mask layer is 30-90nm; and / or, In S8, the thickness of the intrinsic hydrogenated amorphous silicon layer is 4-8 nm, the thickness of the second doped silicon layer is 6-12 nm, and the effective doping concentration of the second doped silicon layer is 1e19-9e20 cm -3 .

8. The short-process preparation method according to claim 1, characterized in that: In S7, the second semiconductor opening area is polished by the cleaning, and the polishing process includes: first polishing with a strong alkali solution, the etching depth of the second semiconductor opening area is 0.2-1μm, and then cleaning is performed to remove organic matter, metal ions and surface oxide layer; wherein the strong alkali solution is a NaOH solution or a KOH solution and its mass concentration is 1%-5%, the polishing reaction temperature is 60-75°C, and the reaction time is 60-180s.

9. The short-process preparation method according to claim 1, characterized in that: The short-process preparation method also includes: S9, then performing a second etching opening on the back surface obtained in S8 to form a first semiconductor opening region; S10, depositing a conductive film layer on the back surface obtained in S9; S11, performing a third etching opening on the back surface obtained in S10 to form an insulating groove in a region between the first semiconductor opening region and the second semiconductor opening region; S12, forming metal electrodes respectively at the first semiconductor opening region and the second semiconductor opening region on the back side obtained in S11.

10. A short-process preparation method for a combined passivation back contact battery as claimed in any one of claims 1 to 9, and use thereof in the preparation of a back contact battery.

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