Semiconductor light-emitting element and method for manufacturing semiconductor light-emitting element

Abstract

Provided is a semiconductor light-emitting element that has a high reverse voltage (Vr) while a dry etching scheme is used as a mesa formation scheme for a support substrate-bonded type semiconductor light-emitting element. The semiconductor light-emitting element is provided with, on a support substrate in the following order: a reflection layer; an intermediate electrode layer; a first conductivity type layer; an active layer; and a second conductivity type layer. The semiconductor light-emitting element is characterized in that: the intermediate electrode layer comprises a dielectric section and a conductor section, the outer peripheral section of the intermediate electrode layer constituting the dielectric section; the dielectric section is present on the outside of side surfaces extending from the first conductivity type layer to the second conductivity type layer; the angle between the dielectric section and the side surface of the first conductivity type layer is 70 to 85°; and no notches are present on the side surface of a semiconductor laminate.

Description

Semiconductor light emitting device and method for manufacturing the same

[0001] The present invention relates to a semiconductor light-emitting device and a method for manufacturing the same.

[0002] As LED applications become more diverse, there is a growing need for high-output, long-wavelength LEDs (emission wavelength: 1000-2000 nm) to be used as the light-emitting components of blood glucose sensors or moisture sensors. A technology has been established to improve the luminous efficiency of InP-based LED elements with an emission wavelength of 1000-2000 nm by using Al in the active layer.

[0003] For example, Patent Document 1 discloses a surface-emitting semiconductor element including a semiconductor laminate including an n-type InP substrate, an n-type InP layer laminated on the n-type InP substrate, an InGaAlAs active layer laminated on the n-type InP layer, and a p-type InP layer laminated on the InGaAlAs active layer, and a reflective member covering the semiconductor laminate. Similarly, Patent Document 2 discloses a semiconductor light-emitting element including InGaAlAs in the active layer.

[0004] JP 2018-182154 A JP 2021-77885 A JP 2022-101468 A

[0005] However, in support substrate-bonded semiconductor light emitting devices, there is a problem in that dielectric deposition occurs on the side surfaces of the active layer during mesa formation, resulting in poor reverse bias characteristics of the semiconductor light emitting device. Patent Document 3 discloses an infrared device with an inclined mesa, but the emission wavelength is in the infrared region, and the mesa angle is considered, and there has been no disclosure up to now of etching and exposing the dielectric layer in a support substrate-bonded device.

[0006] An object of the present invention is to provide a semiconductor light emitting device with a large reverse voltage (Vr) while using a dry etching method as a mesa formation method for a support substrate bonded semiconductor light emitting device.

[0007] In the case of a support substrate-bonded semiconductor light emitting device, when a mesa is formed by dry etching, SiO ２As a result of extensive research conducted by the present inventors to achieve the above object, it was found that elements with a small Vr tend to be subject to over-etching, which will be described later, and that the dielectric layer such as SiO ２ It was found that even if a protective film is formed by a method such as etching, this effect remains, deteriorating the reverse bias characteristics. Therefore, it was found that by suppressing the over-etching rate and keeping the mesa angle within a specific range under dry etching conditions, leakage current can be suppressed and a semiconductor light-emitting device with a large Vr can be obtained.

[0008] That is, the gist of the present invention is as follows: (1) A semiconductor device comprising a reflective layer formed on a support substrate, an intermediate electrode layer formed on the reflective layer, a first conductivity type layer formed on the intermediate electrode layer, an active layer formed on the first conductivity type layer, and a second conductivity type layer formed on the active layer, wherein the intermediate electrode layer is made of a dielectric portion and a conductor portion, and an outer periphery thereof is the dielectric portion, and the dielectric portion exists outside a side surface of a semiconductor laminate having the first conductivity type layer, the active layer, and the second conductivity type layer, and in a cross section of the semiconductor device, a side surface of the first conductivity type layer in the vicinity of the active layer and the a semiconductor light-emitting element characterized in that, when a first line circumscribing a side surface of a second conductivity type layer and a second line tangent to a side surface of the active layer and parallel to the first line are drawn, the second line is located outside the first line, the distance between the first line and the second line is zero, or the second line is located inside the first line and the distance between the two lines is 10 nm or less, and a third line connecting a junction between the intermediate electrode layer and the side surface of the first conductivity type layer and a junction of the first line on the first conductivity type layer side forms an angle of 70° or more and 85° or less with respect to the side of the upper surface of the intermediate electrode layer on which the first conductivity type layer is placed.

[0009] (2) The semiconductor light-emitting element according to (1) above, wherein the active layer contains one or more of Al, Ga, and In as a group III element, and one or more of As, Sb, and P as a group V element, and the first conductivity type layer contains one or more of Al, Ga, and In as a group III element, and one or more of As, Sb, and P as a group V element.

[0010] (3) The semiconductor light-emitting device according to (1) or (2) above, wherein the reverse voltage when a reverse current of 0.1 μA is applied is 20 V or more.

[0011] (4) The semiconductor light-emitting element according to any one of (1) to (3) above, wherein a curvature of a line along the side surface, connecting the upper end and the lower end of the side surface of the first conductivity type layer, is 0 or more and 0.11 or less.

[0012] (5) The dielectric portion is made of SiO ２ Alternatively, the semiconductor light-emitting element according to any one of (1) to (4) above may be made of SiN.

[0013] (6) A semiconductor light-emitting element according to any one of (1) to (5) above, wherein the weight ratio of Si atoms on the side surface between the interface between the dielectric portion and the first conductive type layer and the center of the thickness of the second conductive type layer is 2.5 wt % or less.

[0014] (7) The dielectric portion is made of SiO ２ and a weight ratio of O atoms on a side surface between an interface between the dielectric portion and the first conductivity type layer and a center of a thickness of the second conductivity type layer is 7.5 wt % or less.

[0015] (8) A method for manufacturing a semiconductor light-emitting element, the method comprising the steps of: forming an etching stop layer on a growth substrate; forming a second conductivity type layer on the etching stop layer; forming an active layer on the second conductivity type layer; forming a first conductivity type layer on the active layer; forming an intermediate electrode layer on the first conductivity type layer, the intermediate electrode layer comprising a dielectric portion and a conductor portion, the outer periphery of which is the dielectric portion; forming a reflective layer on the intermediate electrode layer; forming a metal bonding layer on a support substrate; bonding the reflective layer and the metal bonding layer; and removing the growth substrate, wherein the semiconductor laminate from the second conductivity type layer to the first conductivity type layer is removed by a dry etching method along a planned chip dividing line, thereby forming the semiconductor laminate a mesa formation step of forming a side surface on the active layer, wherein when a first line circumscribing the side surface of the first conductivity type layer and the side surface of the second conductivity type layer in the vicinity of the active layer and a second line tangent to the side surface of the active layer and parallel to the first line are drawn in a cross section of the semiconductor element, the second line is located outside the first line, the distance between the first line and the second line is zero, or the second line is located inside the first line and the distance between the two lines is 10 nm or less, and a third line connecting a contact point between the intermediate electrode layer and the side surface of the first conductivity type layer and a contact point of the first line on the first conductivity type layer side forms an angle of 70° or more and 85° or less with respect to the side of the intermediate electrode layer on which the first conductivity type layer is placed.

[0016] (9) The method for manufacturing a semiconductor light-emitting element according to (8) above, wherein the over-etching rate in the dry etching method is 1% or more and 9% or less.

[0017] (10) A method for manufacturing a semiconductor light-emitting element described in (8) or (9) above, wherein the weight ratio of Si atoms on the side surface between the interface between the dielectric portion and the first conductivity type layer and the center of the thickness of the second conductivity type layer immediately after the mesa formation process is 2.5 weight % or less.

[0018] According to the present invention, a semiconductor light emitting device with a large reverse voltage (Vr) can be provided using dry etching as a mesa formation method for a support substrate-bonded semiconductor light emitting device.

[0019] FIG. 2B is a cross-sectional view illustrating a state before dry etching in the method for manufacturing a semiconductor light-emitting element, subsequent to FIG. 2C. FIG. 2C is a cross-sectional view illustrating a state after dry etching in the method for manufacturing a semiconductor light-emitting element, subsequent to FIG. 2A. FIG. 2C is a cross-sectional view illustrating a state after dry etching in the method for manufacturing a semiconductor light-emitting element, subsequent to FIG. 2C. FIG. 1 is a cross-sectional SEM image of a semiconductor light-emitting element according to Example 1. FIG. 2 is a cross-sectional SEM image of a side surface of a semiconductor laminate of a semiconductor light-emitting element according to Example 1. FIG. 3 is a cross-sectional SEM image of a semiconductor light-emitting element according to Example 2. FIG. 4 is a cross-sectional SEM image of a semiconductor light-emitting element according to Example 3. FIG. 4 is an explanatory diagram of a notch and angle θ using a cross-sectional SEM image of a semiconductor light-emitting element according to Comparative Example 1. FIG. 5 is a cross-sectional SEM image of a semiconductor light-emitting element according to Comparative Example 2. FIG. 6 is a cross-sectional SEM image of a semiconductor light-emitting element according to Comparative Example 2. FIG. 7 is a cross-sectional SEM image of a semiconductor light-emitting element according to Comparative Example 3. FIG. 2 is a second diagram showing an SEM image of a side surface of a semiconductor laminate of a semiconductor light-emitting element according to Comparative Example 4.

[0020] Prior to describing the embodiment of the present invention, the following points will be explained in advance with reference to FIG. 6 relating to a comparative example.

[0021] <Notch> In this embodiment, a notch refers to a recess in the side surface of a semiconductor laminate caused by the active layer being etched faster than other layers. When a first line (A in the figure) circumscribing the side surface of the first conductivity-type layer and the side surface of the second conductivity-type layer near the active layer and a second line (B in the figure) tangent to the side surface of the active layer and parallel to the first line are drawn, a notch is defined as a state in which the second line is located inside the first line (the second line is on the semiconductor laminate side), the distance between the first and second lines is greater than 10 nm, and the side surface of the active layer is significantly recessed relative to the side surfaces of the first and second conductivity-type layers. A notch is defined as a state in which the second line is located outside the first line, the distance between the first and second lines is zero, or the second line is located inside the first line and the distance between the two lines is 10 nm or less. In Figure 6 , which shows a notch, the second line is located inside the first line and the distance between the two lines is approximately 400 nm. The presence of a notch may cause a current shortcut between the first conductivity type layer and the second conductivity type layer, reducing the reverse voltage. The term "vicinity of the active layer" refers to the range from the interface between the active layer and the first conductivity type layer or the interface between the active layer and the second conductivity type layer to three times the thickness of the active layer in the thickness direction. A shape that does not cause a current shortcut between the first conductivity type layer and the second conductivity type layer, in the above-described configuration without a notch, is preferably such that the second line is located outside the first line, or such that the distance between the first line and the second line is zero. When the second line is located outside the first line, the distance between the two lines may be any distance that does not easily damage the active layer, e.g., 400 nm or less.

[0022] <Angle θ> In this embodiment, the angle θ refers to the angle formed by a third line (C in the drawing) connecting the point of contact between the intermediate electrode layer (dielectric portion thereof) and the side surface of the first conductivity type layer and the point of contact between the first line (A in the drawing) and the side surface of the first conductivity type layer, with respect to the side of the upper surface of the intermediate electrode layer (dielectric portion thereof) on which the first conductivity type layer is placed.

[0023] <Curvature> In this embodiment, the curvature is the curvature of a line along the side surface that connects the contact point between (the dielectric portion of) the intermediate electrode layer and the side surface of the first conductivity type layer and the contact point of the first straight line (A in the drawing) on ​​the side surface of the first conductivity type layer (or the contact point between the side surface of the first conductivity type layer and the side surface of the active layer if there is no notch). The curvature is calculated by using image measurement software to find an arc along three points, including the two contact points and a midpoint that is equidistant from the contact points, and then calculating the radius of the circle.

[0024] <Over-etching Rate> In this embodiment, the over-etching rate is calculated by dividing the over-etching time by the etching time, where the endpoint time is defined as the point at which the first conductivity type layer has disappeared in a part of the street region as measured by a plasma emission spectroscopic observation device attached to the dry etching device (the point at which the In plasma emission intensity becomes equal to or less than a specified value, and which is also the timing at which a part of the dielectric portion begins to be exposed), and the over-etching time is defined as the etching time performed after the endpoint time.

[0025] In this embodiment, the angle θ and curvature are evaluated by forming a cross section of the semiconductor light emitting device using a focused ion beam (FIB) or the like, acquiring a cross-sectional SEM (scanning electron microscope) image, and measuring the angle and curvature from the image. The cross-sectional SEM image was acquired using a JEOL FE-SEM_JSM7000F at an acceleration voltage of 5 kV, and the angle θ and curvature were measured using IC Measure image measurement software manufactured by The Imaging Source.

[0026] In this embodiment, the mass % and atomic % of elements in each layer on the side surface of the semiconductor laminate are measured using energy dispersive X-ray spectroscopy (EDS) for the side surface of the semiconductor laminate. This also allows the presence or absence of deposition on the side surface near the active layer to be confirmed. The EDS analysis was performed using the above-mentioned FE-SEM_JSM7000F manufactured by JEOL Ltd. at an accelerating voltage of 10 kV.

[0027] In this embodiment, the reverse voltage Vr was measured using an LED tester manufactured by YAC Garter (model number: LX4730A). The wafer before singulation was set in a probe device, and the probe was placed on the pad electrode on the top of the device to measure the reverse voltage (Vr) by passing a reverse current of 0.1 μA. Approximately 5,000 measurements were taken, and the average value was used.

[0028] In this embodiment, "InGaAlAs" is In, where the composition ratios of In, Ga, and Al are a, b, and 1-a-b, respectively. ａ Ga ｂ Al １－ａ―ｂ In this embodiment, the values ​​of the In composition ratio a and the Ga composition ratio b of the InGaAlAs composition ratio are determined from the wavelength observed in photoluminescence measurements performed on the surface of each layer when the layer is grown. Unless otherwise specified, the In composition ratio a and the Ga composition ratio b are 0 or more and 1 or less, and 0≦1−a−b≦1. EDS, for example, can be used as a method for determining the In composition ratio and the Ga composition ratio from the cross section of the semiconductor light-emitting device.

[0029] In this specification, the term "undoped" refers to a layer to which no specific dopant, such as Si, S, or Zn, has been intentionally added. An undoped layer may contain unavoidable dopants during the manufacturing process.

[0030] An embodiment of the present invention will be described below.

[0031] (Semiconductor Light Emitting Device) The semiconductor light emitting device obtained according to this embodiment will be described.

[0032] 1 , the semiconductor light emitting element 1 according to this embodiment includes a reflective layer 91 formed on a support substrate 190, a metal bonding layer 92 formed on the reflective layer 91, an intermediate electrode layer 80 formed on the metal bonding layer 92, a first conductivity type layer 60 formed on the intermediate electrode layer 80, an active layer 50 formed on the first conductivity type layer 60, and a second conductivity type layer 40 formed on the active layer 50. The intermediate electrode layer 80 is made up of a dielectric portion 82 and a conductor portion 81, and the outer periphery of the intermediate electrode layer 80 is the dielectric portion 82.

[0033] The semiconductor light-emitting device 1 shown in FIG. 1 has the following characteristics. In the semiconductor light-emitting device 1, a dielectric portion 82 exists outside the side surface of a semiconductor laminate 200 having a first conductivity-type layer 60, an active layer 50, and a second conductivity-type layer 40. As a result, in the cross section of the device, the dielectric portion of the intermediate electrode layer exists outside the contact point between the intermediate electrode layer and the side surface of the first conductivity-type layer (on the side where the first conductivity-type layer is not present). When viewed from above, the semiconductor laminate 200 has a shape in which the top surface of the dielectric portion 82 can be seen outside the outer periphery of the semiconductor laminate 200. The angle θ formed by the side surface of the first conductivity-type layer 60 with respect to the dielectric portion 82 is 70° or more and 85° or less. In the present specification, when there is no notch as described above, and a first line circumscribing the side surface of the first conductivity type layer 60 and the side surface of the second conductivity type layer 40 near the active layer and a second line tangent to the side surface of the active layer parallel to the first line are drawn, the second line is located outside the first line, the distance between the first line and the second line is zero, or the second line is located inside the first line and the distance between the two lines is 10 nm or less.

[0034] With the above-described configuration, when a reverse current of 0.1 μA is applied to the semiconductor light emitting element 1, the reverse voltage becomes 20 V or more.

[0035] The first conductivity type layer 60 may include layers such as an electron blocking layer, a cladding layer, or a contact layer. Similarly, the second conductivity type layer 40 may include layers such as a cladding layer or a contact layer. Furthermore, an undoped layer called a spacer layer may be provided between the active layer 50 and the first conductivity type layer 60 or between the active layer 50 and the second conductivity type layer 40. The first conductivity type layer 60 and the second conductivity type layer 40 preferably have a larger bandgap than the active layer 50.

[0036] The active layer 50 preferably contains one or more of Al, Ga, and In as a group III element, and preferably contains one or more of As, Sb, and P as a group V element. The first conductivity type layer 60 preferably contains one or more of Al, Ga, and In as a group III element, and preferably contains one or more of As, Sb, and P as a group V element. It is preferable that the first conductivity type layer 60 be a layer having an emission wavelength of 1000 nm or more.

[0037] The angle θ is preferably 70° or more and 85° or less, more preferably 76° or more and 85° or less, and particularly preferably 77° or more and 84° or less. If the angle θ is less than 70°, the street width will be increased to create an area without the first conductivity type layer 60 of a width that does not affect dicing, thereby reducing the number of chips per wafer, and if the angle θ exceeds 85°, the reverse voltage will be reduced. Furthermore, the curvature of the line along the side surface connecting the upper and lower ends of the side surface of the first conductivity type layer 60 is preferably 0 or more and 0.11 or less, more preferably 0 or more and 0.09 or less, and particularly preferably 0.01 or more and 0.08 or less.

[0038] The dielectric portion 82 is made of SiO ２ Alternatively, SiN is preferred, and SiO ２ It is more preferable that the weight percentage of Si atoms on the side surface between the interface between the dielectric portion 82 and the first conductivity type layer 60 and the center of the thickness of the second conductivity type layer 40 (hereinafter also referred to as the main side surface) is 2.5 wt % or less, and the percentage of the number of Si atoms is 5% or less. The weight percentage of Si atoms is more preferably 0.1 wt % or more and 2.5 wt % or less, and particularly preferably 1.0 wt % or more and 2.5 wt % or less. It is also preferable that the dielectric portion 82 is made of SiO ２ In this case, the weight percentage of O atoms is preferably 0.3 wt % or more and 7.5 wt % or less. Although protective film 70 is shown in Fig. 1, protective film 70 may be omitted. The percentage of the number of Si atoms and the weight percentage of Si or O atoms on the main side surface are preferably measured in a state where protective film 70 is not formed on the side surface.

[0039] Hereinafter, an embodiment of a manufacturing method for obtaining this semiconductor light emitting device 1 and each of the steps therein will be described in detail.

[0040] (Method for Manufacturing Semiconductor Light-Emitting Device) FIGS. 2A to 2D are process diagrams of the method for manufacturing the semiconductor light-emitting device 1 described above. These diagrams are schematic illustrations of a cross section of a portion of a growth substrate. For ease of explanation, the intermediate electrode layer and electrodes are simplified, and the aspect ratios of the substrate and each layer are exaggerated and not based on the actual situation. As shown in FIGS. 2A to 2D , the method for manufacturing the semiconductor light-emitting device 1 according to the present invention first involves epitaxially growing each semiconductor layer on the growth substrate 10, followed by forming the intermediate electrode layer 80. Next, the intermediate electrode layer 80 is bonded to the support substrate 190 via a metal bonding layer 92 and a reflective layer 91 formed on the growth substrate 10 side. Next, the growth substrate is removed. Next, a top ohmic electrode is formed, and then a mesa is formed by dry etching.

[0041] <Semiconductor Layer> The growth substrate 10 can be a compound substrate such as GaAs, InP, or InAs, and can be manufactured according to a conventional method. The growth substrate 10 is preferably n-type doped, and its thickness is preferably 200 μm or more and 900 μm or less. Here, examples of elements doped into the growth substrate 10 include S. Each semiconductor layer will be briefly described below.

[0042] First, a buffer layer 20 may be epitaxially grown on the growth substrate 10. The buffer layer 20 serves to alleviate lattice mismatch between the growth substrate 10 and an etching stop layer 30 (described later). The buffer layer 20 can be formed, for example, by metal organic chemical vapor deposition (MOCVD). The buffer layer 20 preferably has a thickness of 0.01 μm to 0.5 μm and is preferably n-type doped. Examples of elements doped into the buffer layer 20 include Si. Next, an etching stop layer 30 is stacked on the buffer layer 20. The etching stop layer 30 preferably has a composition that is not etched under the etching conditions for the growth substrate 10 and the buffer layer 20 and that is lattice-matched with the second conductivity type layer 40. The thickness of the etching stop layer 30 is preferably 0.01 μm or more and 0.1 μm or less, and more preferably 0.02 μm or more and 0.05 μm or less. The etching stop layer 30 is preferably n-type doped, and examples of the doped element include Si. Next, the second conductivity type layer 40 is laminated on the etching stop layer 30. The thickness of the second conductivity type layer 40 only needs to be thick enough to supply carriers, and is preferably, for example, 2 μm or more and 10 μm or less. The second conductivity type layer 40 is preferably n-type doped, and examples of the doped element include Si.

[0043] Furthermore, an active layer 50 is laminated on the second conductivity type layer 40. As described above, the active layer 50 preferably contains one or more of Al, Ga, and In as a group III element, and one or more of As, Sb, and P as a group V element. The active layer 50 may have a single layer structure, a double heterostructure (DH) structure, or a multiple quantum well structure in which multiple barrier layers and well layers are alternately stacked. The figures of this embodiment show a multiple quantum well structure as an example.

[0044] Next, a first-conductivity-type layer 60 is laminated on the active layer 50. The first-conductivity-type layer 60 may have an electron-blocking layer on the active layer 50 side. As described above, the first-conductivity-type layer 60 preferably contains one or more of Al, Ga, and In as a group III element, and one or more of As, Sb, and P as a group V element. The thickness of the first-conductivity-type layer 60 is preferably 0.4 μm to 5 μm, and more preferably 1 μm to 3 μm. The first-conductivity-type layer 60 is preferably p-doped, and examples of the doped element include Zn. The semiconductor layers (second-conductivity-type layer 40 to first-conductivity-type layer 60) laminated above the etching stop layer 30 on the growth substrate 10 constitute the semiconductor laminate 200.

[0045] <Intermediate Electrode Layer> The intermediate electrode layer 80 is formed on the first conductivity-type layer 60. First, a resist is preferably applied to the entire surface of the first conductivity-type layer 60. The resist is patterned into a predetermined shape by photolithography, exposing the semiconductor layer of the first conductivity-type layer 60 only in the area where the conductor portion 81 (described below) is to be formed. Next, a metal film is preferably vapor-deposited on the first conductivity-type layer 60, including the patterned resist. Examples of metals used here include AuZn. The resist and the metal film on the resist are removed by lift-off, thereby forming the conductor portion 81 in the desired pattern on the first conductivity-type layer 60. The conductor portion 81 is preferably subjected to heat treatment by RTA (high temperature, short time annealing). Note that a highly doped contact layer may be patterned and disposed on the first conductivity-type layer 60 side of the conductor portion 81.

[0046] Next, a dielectric portion 82 is formed on the outer periphery of the conductor portion 81 on the first conductivity type layer 60. It is preferable to deposit an insulating film on the first conductivity type layer 60 including the conductor portion 81. The insulating film used here is a SiO ２Alternatively, SiN is preferable. After the insulating film is formed, the insulating film on the conductor portion 81 is removed by etching using a resist mask pattern, and then the remaining resist is removed by lift-off, thereby forming the dielectric portion 82. Well-known methods such as sputtering or plasma CVD can be used to form the metal film and insulating film. The thickness of the intermediate electrode layer 80 is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm, and even more preferably 430 nm to 640 nm.

[0047] <Formation of Reflective Layer> As shown in FIG. 2B , a reflective layer 91 is formed on the intermediate electrode layer 80. The reflective layer 91 may include multiple metal layers. The metal constituting the reflective layer 91 may be Au, Al, Pt, Ti, Ag, or the like. For example, the reflective layer 91 may be a single layer composed of Au alone, or may include two or more Au metal layers. The reflective layer 91 preferably contains 50 mass % or more of Au in its composition. Furthermore, to ensure bonding with the metal bonding layer 92 in a subsequent process, it is preferable that the outermost layer of the reflective layer 91 (the surface opposite the intermediate electrode layer 80) be an Au metal layer.

[0048] For example, the reflective layer 91 can be formed by depositing metals in the following order on the intermediate electrode layer 80: Al, Au, Pt, and Au. The thickness of the Au on the outermost surface of the reflective layer 91 can be, for example, 400 nm to 2000 nm, and the thickness of the metal layer made of a metal other than Au can be, for example, 5 nm to 200 nm. The reflective layer 91 can be formed by deposition using a common method such as vapor deposition.

[0049] A metal bonding layer 92 is formed on the support substrate 190 by laminating a metal such as Ti, Pt, or Au, or a metal that forms a eutectic alloy with Au (such as Sn), or solder. For example, the metal bonding layer 92 can be formed by laminating, in order from the surface of the support substrate 190, Ti having a thickness of 400 nm to 800 nm, Pt having a thickness of 5 nm to 20 nm, and Au having a thickness of 700 nm to 1200 nm. To ensure reliable bonding with the above-mentioned reflective layer 91, it is preferable that the outermost surface of the metal bonding layer 92 (the surface opposite the support substrate) is also an Au metal layer. In this case, bonding between Au layers can be achieved by Au-Au diffusion.

[0050] <Bonding to Support Substrate> Bonding to the support substrate 190 will be described with reference to Fig. 2B. The semiconductor stack 200 and the intermediate electrode layer 80 are bonded to the support substrate 190 via the reflective layer 91 and the metal bonding layer 92. The metal bonding layer 92 and the reflective layer 91 are placed opposite each other and bonded together, and then heated and compressed to bond them together at 250°C to 500°C with a surface pressure of 5 kN to 15 kN for 20 minutes to 40 minutes, thereby bonding the two together.

[0051] The support substrate 190 will now be described. The support substrate 190 may be a substrate of a different type from the growth substrate 10, and may be a submount substrate based on the semiconductor substrate, metal substrate, or ceramic substrate described above. Since the above-mentioned bonding method is used, the support substrate 190 may be lattice-mismatched with the semiconductor layers formed in this embodiment. Note that the support substrate 190 may be an insulating substrate depending on the application, but is preferably a conductive substrate. By using a Si substrate, the thickness of the support substrate 190 can be significantly reduced compared to conventional substrates, making it suitable for implementation in combination with various semiconductor devices. Si substrates are also advantageous in terms of heat dissipation.

[0052] <Removal of Growth Substrate> Removal of the growth substrate 10 will be described with reference to FIG. 2C . After bonding the support substrate 190, the growth substrate 10 is removed. When the growth substrate 10 is an InP substrate, for example, wet etching can be performed using diluted hydrochloric acid. Alternatively, portions of the growth substrate 10, buffer layer 20, and etching stop layer 30 may be removed by polishing.

[0053] After removing the growth substrate 10, it is preferable to form an ohmic electrode (not shown) on the upper surface of the semiconductor layer (the surface opposite to the support substrate 190). The ohmic electrode can be formed using a metal such as Au, Ge, Ni, or Ti, a metal that forms a eutectic alloy with Au (such as Sn), or solder. The ohmic electrode can be formed by depositing a film using a common method such as vapor deposition. The thickness of the ohmic electrode is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

[0054] After forming the ohmic electrode, it is preferable to form a pad electrode on the ohmic electrode. The pad electrode can be formed using a metal such as Ti or Au, a metal that forms a eutectic alloy with Au (such as Sn), or solder. The pad electrode can be formed by a common method such as vapor deposition.

[0055] After the pad electrode is formed, the surface of the ohmic electrode, excluding the area above the pad electrode, is roughened. This is because roughening improves light extraction efficiency. The ohmic electrode surface can be roughened by a common technique such as selective etching using a mask. The ohmic electrode and pad electrode that are not roughened are combined to form the top ohmic electrode and pad electrode 170.

[0056] <Mesa Formation Step> As shown in FIG. 2D , a portion of the semiconductor laminate 200 is removed by dry etching to form a side surface on the semiconductor laminate 200. Reactive ion etching (RIE) is preferably used as the dry etching method, and an inductively coupled plasma (ICP) can be used as the plasma source. Dry etching is performed on street regions having a certain width along the planned chip division lines when viewed from above. The width of the street region (street width) is the width necessary to perform chip division without adversely affecting the active layer, etc., and is, for example, 40 to 100 μm. The street region may be in a lattice shape, and the pad electrodes formed above or the conductor portions 81 of the intermediate electrode layer 80 are disposed in the regions that are not street regions when viewed from above. A mask (e.g., SiO ) is applied to the semiconductor laminate 200 (on the second conductivity type layer 40) so as to expose the semiconductor laminate 200 in the street regions described above. The mask has an etching rate during dry etching that is smaller than that of the semiconductor laminate 200 and a thickness that does not disappear until the etching of the street regions is completed. ２ After forming a mask (mask), dry etching is performed on the street region. Here, the dry etching is performed until the dielectric portion 82 of the intermediate electrode layer 80 is exposed outside the side surface of the semiconductor laminate 200. Furthermore, the angle θ formed by the dielectric portion 82 and the first conductivity type layer 60 is 70° or more and 85° or less, and the dry etching conditions are optimized so that notches are not formed on the side surface of the active layer 50. The dry etching conditions are a stage temperature of 180° C. or more and 200° C. or less, and a gas type of SiCl ４Preferably, the gas used is a mixed gas of Ar and Ar, with a pressure of 0.2 Pa to 1.0 Pa, a bias power of 50 W to 150 W, and an ICP power of 190 W to 400 W. Furthermore, more preferably, the stage temperature is 190°C to 200°C, a pressure of 0.2 Pa to 0.6 Pa, a bias power of 70 W to 150 W, and an ICP power of 190 W to 250 W. Furthermore, the over-etching rate is preferably 1% to 9%, more preferably 3% to 7%, and even more preferably 6% or less. If the over-etching rate is less than 0% to 1%, it is not possible to create a region free of the first conductivity type layer 60 with a width that does not affect dicing, which may increase the street width and reduce the number of chips per wafer.

[0057] SiO mask ２ and SiO of the dielectric portion 82 ２ Although the etching rate is low, it does not mean that the SiO2 mask is not etched at all. ２ Since Si atoms or oxygen atoms scattered from the dielectric portion 82 hardly reach the side surface of the semiconductor laminate 200, problems caused by Si atoms or oxygen atoms adhering to the side surface of the semiconductor laminate 200 do not occur when the conventional dielectric portion 82 is not provided or when etching is not performed until the dielectric portion 82 is exposed. ２ In this configuration, dry etching is performed until the SiO ２ In this case, a problem occurs in that Si atoms or oxygen atoms scattered from the intermediate electrode layer 80 collide with the side surface of the semiconductor laminate 200. In addition to suppressing the over-etching rate as in the present invention, by setting the angle θ between the intermediate electrode layer 80 (the dielectric portion 82 thereof) and the first conductivity type layer 60 to 70° or more and 85° or less, the SiO ２ It is believed that the amount of particles that collide with the side surface near the active layer of the semiconductor laminate 200 can be reduced based on the relationship between the amount of particles that fly off and the angle of flight.

[0058] By appropriately adjusting the dry etching conditions, it is preferable that the weight percentage of Si atoms in the side (main side) between the interface between the dielectric portion 82 and the first conductivity type layer 60 and the center of the thickness of the second conductivity type layer 40 is 2.5 wt % or less and the percentage of the number of Si atoms is 5% or less, as determined by EDS analysis. The weight percentage of Si atoms is more preferably 0.1 wt % or more and 2.5 wt % or less, and particularly preferably 1.0 wt % or more and 2.5 wt % or less. Furthermore, when the dielectric portion 82 is made of SiO ２ In this case, the weight percentage of O atoms is preferably 0.3 wt % or more and 7.5 wt % or less. The percentage of Si atoms and the weight percentage of Si or O atoms on the main side surface are preferably measured in a state where a protective film 70 (described later) is not formed on the side surface.

[0059] After the mesa formation process, it is preferable to form a protective film 70 by using plasma CVD or the like. ２ The SiO mask used in the mesa formation process is also usable. ２may be part of the protective film 70. It is also preferable that the protective film 70 does not cover the upper surface of the pad electrode. The thickness of the protective film 70 is preferably 50 nm to 500 nm. Next, to adjust the overall thickness of the semiconductor light-emitting device, the support substrate 190 is preferably polished or etched to adjust the thickness. In this embodiment, there is no limit to the overall thickness of the semiconductor light-emitting device, but it is preferably 2.4 μm to 15 μm. Next, a backside ohmic electrode 160 is preferably formed on the backside of the support substrate 190. The backside ohmic electrode 160 can be formed using a metal such as Ti, Pt, or Au, a metal that forms a eutectic alloy with Au (e.g., Sn), or solder. The backside ohmic electrode 160 can be formed by deposition using a common method such as vapor deposition. The thickness of the backside ohmic electrode 160 is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm. The formed backside ohmic electrode 160 is preferably heat-treated by RTA. Finally, it is preferable to perform dicing using a dicer or a scriber to separate the semiconductor light emitting elements.

[0060] The key to this invention is the discovery that optimizing the over-etching time in the etching conditions for mesa formation allows the shape, angle θ, and curvature of the main side surface to fall within a certain range. Setting the angle θ to 85° or less suppresses leakage current. The reason for this is that dry etching under conditions where the angle θ is 85° or less reduces the over-etching rate, reducing deposition on the side surfaces of the active layer. This suppresses leakage current due to deposition, possibly improving reverse bias characteristics.

[0061] Furthermore, it is preferable not to roughen the side surfaces of the semiconductor laminate 200 after the mesa formation step. This is because roughening may result in the formation of notches. It is preferable to roughen the top surface of the semiconductor laminate 200. It is more preferable that the range of the top surface of the semiconductor laminate 200 to be roughened excludes the street region, the top surface ohmic electrode, the pad electrode 170, and their vicinity.

[0062] The present invention will be described in more detail below using examples, but the present invention is not limited to the following examples in any way.

[0063] Example 1: n-type InP growth substrate (thickness: 600 μm, S-doped, dopant concentration: 2.0×10 １８ / cm ３ An n-type InP buffer layer (thickness: 0.1 μm, Si doped, dopant concentration: 5.0×10) was grown on the substrate by MOCVD. １７ / cm ３ ), n-type In ０．５７ Ga ０．４３ As etching stop layer (thickness: 0.02 μm, Si doped, dopant concentration: 5.0×10 １７ / cm ３ ), n-type InP cladding layer (thickness: 3.5 μm, Si doped, dopant concentration: 5.0×10 １７ / cm ３ Next, an undoped In was formed as an active layer. ０．４２ Ga ０．４２ Al ０．１６ As barrier layer and undoped InGa ０．１９５ Al ０．０４ A multi-quantum well structure is formed by an As well layer. ０．４２ Ga ０．４２ Al ０．１６ After forming an As barrier layer, a 10 nm thick InGa ０．１９５ Al ０．０４ As well layer and 8 nm thick In ０．４２ Ga ０．４２ Al ０．１６ The first barrier layer was formed on the first and second barrier layers, and the second barrier layer was formed on the second and third barrier layers. ０．５２２ Al ０．４７８ As electron blocking layer (thickness: 0.02 μm), p-type InP cladding layer (thickness: 2.4 μm, Zn doped, dopant concentration: 7.0×10 １７ / cm ３ The thickness and dopant concentration of each semiconductor layer described here are design values ​​at the time of growth of each layer.

[0064] Next, resist was applied to the entire surface of the p-type InP cladding layer. The resist was patterned into a predetermined shape using photolithography, and the resist was removed from the area where the conductor portion was to be formed, exposing the p-type InP cladding layer. AuZn (thickness: 550 nm) was deposited on the p-type InP cladding layer, including the resist, using a sputtering method. The resist and the AuZn on the resist were then removed by lift-off. Further, heat treatment using RTA (conditions: 300°C) was performed. This resulted in the formation of the conductor portion of the intermediate electrode layer.

[0065] Next, a SiO 2 film is formed on the p-type InP clad layer including the conductive portion by plasma CVD. ２ An insulating film (thickness: 700 nm) made of SiO ２ A resist is applied to the insulating film, and a resist mask pattern is used to form a SiO ２ The dielectric portion can be formed by removing the insulating film by etching and then removing the remaining resist by lift-off. This results in the formation of an intermediate electrode layer composed of a dielectric portion and a conductor portion, with the outer periphery being the dielectric portion. Note that a fixed gap is created between the dielectric portion and the conductor portion, and the thickness of the dielectric portion is thicker than the thickness of the conductor portion.

[0066] A reflective layer (Ti (thickness: 2 nm) / Au (thickness: 650 nm) / Pt (thickness: 100 nm) / Au (thickness: 900 nm)) was formed on the intermediate electrode layer by vapor deposition, and a metal bonding layer (Ti (thickness: 650 nm) / Pt (thickness: 20 nm) / Au (thickness: 900 nm)) was further formed on a support substrate (Si substrate) by vapor deposition. The reflective layer and the metal bonding layer were placed facing each other and subjected to thermal compression bonding at a surface pressure of 10 kN and 350°C for 30 minutes. Although not shown, at this time, because the gap between the dielectric portion and the conductor portion and the thickness of the dielectric portion were thicker than the thickness of the conductor portion, recesses in the reflective layer formed at positions corresponding to the conductor portion and its surroundings created voids at the interface between the reflective layer and the metal bonding layer.

[0067] Next, the growth substrate and buffer layer were removed by wet etching using diluted hydrochloric acid to expose the etching stop layer. The etching stop layer was then masked by photolithography to leave the areas where the top ohmic electrode and pad electrode (described later) would be formed as contact layers, and the remaining areas were removed by wet etching using a tartaric acid-hydrogen peroxide solution mixture.

[0068] The mask was removed to expose the etching stop layer, and a top ohmic electrode was formed using a vapor deposition method with Au (thickness: 10 nm) / Ge (thickness: 30 nm) / Au (thickness: 60 nm) / Ni (thickness: 30 nm) / Au (thickness: 800 nm) / Ti (thickness: 100 nm) / Au (thickness: 1000 nm). Next, a pad electrode (Ti (thickness: 150 nm) / Pt (thickness: 100 nm) / Au (thickness: 2500 nm)) was formed on the top ohmic electrode using a vapor deposition method. The electrode pattern was formed using a lift-off method using a resist.

[0069] Next, a resist mask was formed by photolithography to cover the street regions along the planned chip dividing lines, as well as the top-surface ohmic electrodes and pad electrodes. The light extraction surface of the n-type InP cladding layer other than the masked region was then roughened by wet etching. Because the street regions were not roughened by covering them with the mask, the street regions covered by the mask became bank-shaped, unetched regions surrounding the roughened recessed portions, as seen in FIG. 3A . By forming these unetched regions, exposed mask regions along the planned chip dividing lines (described later) can be formed on the upper flat surface of the unetched regions, which is preferable because they can prevent the mesa shape from meandering or becoming abnormal due to dry etching.

[0070] Next, SiO is deposited on the entire surface by plasma CVD. ２ After forming the SiO2 layer, a mask pattern is formed using a resist and then etched to expose the street areas along the planned chip dividing lines. ２A mask was formed. The width of the street region exposed by the mask pattern was 55 μm. Dry etching (ICP-RIE) was performed to expose the dielectric portion of the periphery of the intermediate electrode layer in the street region, and also to expose the side surfaces from the p-type InP clad layer to the n-type InP clad layer. The etching conditions were dry etching, stage temperature 200° C., pressure 0.2 Pa, bias power 150 W, ICP power 190 W, over-etching rate 5%, and ratio of gas species used SiCl ４ :Ar=4:8.

[0071] After the mesa is formed, the SiO 2 existing on the upper surface ohmic electrode and the pad electrode is ２ After removing the mask, the entire surface (the remaining SiO ２ A SiN film was formed as a protective film on the upper surface of the mask and on the exposed side and street regions of the semiconductor laminate. The SiN on the upper surface of the pad electrode was then removed by etching using a resist mask pattern, and the resist was then removed. The SiN thickness was 190 μm. Next, the rear surface of the support substrate was polished or etched to reduce the overall thickness of the semiconductor light-emitting device to 150 μm. Next, a rear ohmic electrode (Ti (thickness: 10 nm) / Pt (thickness: 50 nm) / Au (thickness: 200 nm)) was formed on the rear surface of the support substrate by vapor deposition, and then heat-treated at 300°C for 60 seconds by RTA. Finally, the semiconductor light-emitting device according to Example 1 was fabricated by laser dicing to separate individual rectangular chips measuring 250 μm x 250 μm.

[0072] (Example 2) The etching conditions for forming the mesa were dry etching, stage temperature 200°C, pressure 0.2 Pa, bias power 150 W, ICP power 190 W, overetching rate 5%, and ratio of gas species used SiCl ４ A semiconductor light emitting device according to Example 2 was obtained in the same manner as in Example 1, except that the ratio of SiO 2 to SiO 2 was changed to SiO 2 :Ar=7:14.

[0073] (Example 3) The etching conditions for forming the mesa were dry etching, stage temperature 200°C, pressure 0.25 Pa, bias power 100 W, ICP power 190 W, overetching rate 5%, and ratio of gas species used SiCl ４ A semiconductor light emitting device according to Example 3 was obtained in the same manner as in Example 1, except that the ratio of SiO 2 to SiO 2 was 9:20.

[0074] Comparative Example 1 A semiconductor light-emitting device according to Comparative Example 1 was obtained in the same manner as in Example 1, except that the etching method for forming the mesa was wet etching, the etching solution was Br-MeOH, the immersion time was 20 minutes, and the upper surface and side surfaces of the semiconductor laminate were roughened by wet etching immediately after the mesa formation without the above-described upper surface roughening.

[0075] (Comparative Example 2) The etching conditions for forming the mesa were dry etching, stage temperature was 200°C, pressure was 0.25 Pa, bias power was 100 W, ICP power was 190 W, overetching rate was 10%, and the ratio of gas species used was SiCl ４ A semiconductor light emitting device according to Comparative Example 2 was obtained in the same manner as in Example 1, except that the ratio of SiO 2 to SiO 2 was 9:20.

[0076] (Comparative Example 3) The etching conditions for forming the mesa were dry etching, stage temperature 200°C, pressure 0.2 Pa, bias power 150 W, ICP power 190 W, overetching rate 15%, and ratio of gas species used SiCl ４ A semiconductor light emitting device according to Comparative Example 3 was obtained in the same manner as in Example 1, except that the ratio of SiO 2 to SiO 2 was 7:14.

[0077] (Comparative Example 4) The etching conditions for forming the mesa were dry etching, stage temperature 200°C, pressure 0.25 Pa, bias power 100 W, ICP power 190 W, overetching rate 15%, and ratio of gas species used SiCl ４ A semiconductor light-emitting device according to Comparative Example 4 was obtained in the same manner as in Example 1, except that the ratio of Ar to Si was 9:20. Table 1 below shows the etching methods and conditions used to form the mesas in Examples 1 to 3 and Comparative Examples 1 to 4.

[0078]

[0079] Cross-sectional SEM images were obtained for Examples 1 to 3 and Comparative Examples 1 to 4, and the shape, angle θ, curvature, presence or absence of a notch on the side surface of the active layer, and the distance between the first and second lines of each major side surface were measured. FIGS. 3A to 5 correspond to Examples 1 to 3, respectively, and FIGS. 6 to 9B correspond to Comparative Examples 1 to 4, respectively. As mentioned above, the cross-sectional SEM images were obtained using a JEOL FE-SEM JSM7000F at an accelerating voltage of 5 kV. FIGS. 3A, 4, 5, 6, 7A, 8, and 9A are cross-sectional SEM images of completed devices. The angle θ and curvature were measured using IC Measure, an image measurement software program manufactured by The Imaging Source, as mentioned above. Furthermore, for the elements of Example 1, Example 3, Comparative Example 2, and Comparative Example 4 after mesa formation but before protective film formation, SEM images of the main side surfaces of the semiconductor stacks were obtained as shown in Figures 3B, 7B, and 9B. EDS analysis of the main side surfaces was then performed using an FE-SEM JSM7000F at an accelerating voltage of 10 kV. In the EDS analysis, measurements were taken at 10 equally spaced locations along the thickness direction of the main side surface. Measurement points within the half-thickness range of the second conductivity-type layer away from the active layer were excluded, and the average wt% values ​​of Si atoms and oxygen atoms were calculated for measurement points ranging from the first conductivity-type layer, including the side surface of the active layer, to half the thickness of the second conductivity-type layer on the active layer side. The amount of deposition on the side surface of the active layer was then evaluated from the weight percentage of Si atoms obtained by EDS analysis. Furthermore, using the LED tester (model number: LX4730A) manufactured by YAC Garter Co., Ltd., the wafer before singulation was set in a probing device, and the probe was applied to the pad electrode on the top of the element to measure the reverse voltage (Vr) by passing a current of 0.1 μA. 5,000 measurements were taken, and the average value was used. Table 2 shows the results.

[0080]

[0081] As shown in Table 2, when a first line circumscribing the side surface of the first conductivity type layer and the side surface of the second conductivity type layer near the active layer and a second line tangent to the side surface of the active layer parallel to the first line were drawn in the cross-sectional SEM images of Examples 1 to 3 and Comparative Examples 1 to 4, the distance between the first line and the second line was checked. In Comparative Example 1 ( FIG. 6 ), the second line was inside the first line and the distance was 430 nm, but in Examples 1 to 3 and Comparative Examples 2 to 4, the second line was outside the first line or the distance was zero. Note that the value of the distance is indicated as a minus sign when the second line is inside the first line and concave, and as a plus sign when the second line is outside the first line and convex.

[0082] From Table 2, it was confirmed that when mesas are formed and roughened by wet etching, the side surfaces of the active layer are largely etched, causing notches, resulting in poor reverse current characteristics of the semiconductor light-emitting device. On the other hand, when mesas are formed by dry etching without roughening the main side surfaces, it was confirmed that notches do not occur, but this alone is not enough to improve the poor reverse current characteristics of the semiconductor light-emitting device. If the over-etching time is short, the exposed SiO ２ If the over-etching time is short, side etching progresses toward the support substrate side, and the angle θ is 70° or more and 85° or less. ２ When the over-etching time is long, side etching on the support substrate side progresses, and the angle θ approaches perpendicular. Table 2 confirms that, under dry etching conditions, increasing the over-etching time brings the angle θ closer to perpendicular and increases the amount of deposition. It was confirmed that by optimizing the over-etching time (rate) and setting the angle θ to 70° or more and 85°, a semiconductor light-emitting device with a large reverse voltage (Vr) can be fabricated.

[0083]

[0084] Table 3 shows the number of chips measured, the average value (V), and the standard deviation (V) of the reverse voltage (Vr) when a reverse current of 0.1 μA was passed through the semiconductor light-emitting devices of Examples 1 to 3 and Comparative Examples 2 to 4. It can be seen that Examples 1 to 3 not only have an average value exceeding 20 V, but also a small standard deviation. This shows that high yields can be achieved by performing etching during mesa formation under the conditions of the present invention.

[0085] REFERENCE SIGNS LIST 1 semiconductor light emitting element 10 growth substrate 20 buffer layer 30 etching stop layer 40 second conductivity type layer 50 active layer 60 first conductivity type layer 70 protective film 80 intermediate electrode layer 81 conductor portion 82 dielectric portion 91 reflective layer 92 metal bonding layer 160 backside ohmic electrode 170 topside ohmic electrode and pad electrode 190 supporting substrate 200 semiconductor laminate

Claims

1. A semiconductor device comprising: a reflective layer formed on a support substrate; an intermediate electrode layer formed on the reflective layer; a first conductive type layer formed on the intermediate electrode layer; an active layer formed on the first conductive type layer; and a second conductive type layer formed on the active layer, wherein the intermediate electrode layer is composed of a dielectric portion and a conductive portion, and has a dielectric portion at its outer periphery; the dielectric portion is present outside a side surface of a semiconductor laminate having the first conductive type layer, the active layer, and the second conductive type layer; in a cross section of the semiconductor device, when a first straight line circumscribing a side surface of the first conductive type layer and a side surface of the second conductive type layer in the vicinity of the active layer and a second straight line tangent to a side surface of the active layer parallel to the first straight line are drawn, the second straight line is outside the first straight line, the distance between the first straight line and the second straight line is zero, or the second straight line is inside the first straight line and the distance between the two straight lines is 10 nm or less; A semiconductor light-emitting element, characterized in that a third line connecting a contact point between the intermediate electrode layer and a side surface of the first conductive type layer and a contact point of the first line on the first conductive type layer side forms an angle of 70° or more and 85° or less with respect to the side of the upper surface of the intermediate electrode layer on which the first conductive type layer is placed.

2. The semiconductor light-emitting element according to claim 1, wherein the active layer contains one or more of Al, Ga and In as a group III element and one or more of As, Sb and P as a group V element, and the first conductivity type layer contains one or more of Al, Ga and In as a group III element and one or more of As, Sb and P as a group V element.

3. The semiconductor light-emitting element according to claim 1, wherein a reverse voltage is 20 V or more when a reverse current of 0.1 μA is applied.

4. The semiconductor light-emitting element according to claim 1, wherein a curvature of a line connecting an upper end and a lower end of the side surface of the first conductive type layer along the side surface is between 0 and 0.

11.

5. The dielectric portion is made of SiO ２ The semiconductor light-emitting element according to claim 1 , wherein the material is selected from the group consisting of silicon nitride and silicon nitride.

6. The semiconductor light-emitting element according to claim 1, wherein the weight percentage of Si atoms on a side surface between the interface between the dielectric portion and the first conductive type layer and the center of the thickness of the second conductive type layer is 2.5 weight % or less.

7. The dielectric portion is made of SiO ２ 2. The semiconductor light emitting element according to claim 1, wherein a weight ratio of O atoms on a side surface between an interface between the dielectric portion and the first conductive type layer and a center of a thickness of the second conductive type layer is 7.5 weight % or less.

8. A method for manufacturing a semiconductor light-emitting element, comprising the steps of: forming an etching stop layer on a growth substrate; forming a second conductive type layer on the etching stop layer; forming an active layer on the second conductive type layer; forming a first conductive type layer on the active layer; forming an intermediate electrode layer on the first conductive type layer, the intermediate electrode layer comprising a dielectric portion and a conductive portion, the outer periphery of which is the dielectric portion; forming a reflective layer on the intermediate electrode layer; forming a metal bonding layer on a support substrate; bonding the reflective layer and the metal bonding layer; and removing the growth substrate, further comprising a mesa formation step of forming side surfaces on the semiconductor laminate by removing the semiconductor laminate from the second conductive type layer to the first conductive type layer by a dry etching method along a planned chip division line, a first line circumscribing a side surface of the first conductivity type layer and a side surface of the second conductivity type layer in the vicinity of the active layer, and a second line tangent to the side surface of the active layer and parallel to the first line are drawn, the second line is outside the first line, a distance between the first line and the second line is zero, or the second line is inside the first line and a distance between the two lines is 10 nm or less, and a third line connecting a junction between the intermediate electrode layer and the side surface of the first conductivity type layer and a junction of the first line on the first conductivity type layer side forms an angle of 70° or more and 85° or less with respect to the side of the intermediate electrode layer on which the first conductivity type layer is placed.

9. The method for producing a semiconductor light-emitting element according to claim 8, wherein an over-etching rate in the dry etching method is set to 1% or more and 9% or less.

10. A method for manufacturing a semiconductor light-emitting element as described in claim 8, wherein the weight percentage of Si atoms on the side surface between the interface between the dielectric portion and the first conductive type layer and the center of the thickness of the second conductive type layer immediately after the mesa formation process is 2.5 weight % or less.

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