Reactor protection system using heterogeneous processor having enhanced diversity

Abstract

The present invention relates to a reactor protection system. A reactor protection system using a heterogeneous processor according to an embodiment of the present invention includes: M channels for equally receiving input signals of N different items, wherein M and N are an integer greater than 1; at least two bistable logic processors which are arranged in each of the M channels and perform bistable logic by receiving the input signals of the N different items; and at least two coincidence logic processors which are arranged in each of the M channels, and receive a processing result of the at least two bistable logic processors to perform coincidence logic and generate a trip signal, wherein the at least two bistable logic processors and the at least two coincidence logic processors are implemented in a single board in each of the M channels.

Description

Reactor protection system using heterogeneous processors with enhanced diversity

[0001] The present invention relates to a nuclear reactor protection system, and more particularly, to a nuclear reactor protection system using heterogeneous processors with enhanced diversity.

[0002] Figure 1 is a drawing for explaining the main configuration of a typical nuclear power plant (100). As illustrated in Figure 1, the primary system of the nuclear power plant (100) includes a reactor (130), a pressurizer (140), a coolant pump (150), and a steam generator (160), and the secondary system may include a turbine (170), a generator (180), a condenser (190), and a feedwater pump (191).

[0003] The reactor (130) generates heat of about 1000 degrees Celsius when the nuclear fuel (120) undergoes nuclear fission, thereby raising the temperature of the coolant to about 300 degrees Celsius. In the pressurizer (140), the coolant water is kept from boiling even at temperatures exceeding 100 degrees Celsius, and in the case of a light water reactor, the coolant is 160 kg / cm 2 Apply pressure of 110 kg / cm for the coolant in the case of heavy water reactors. 2 Apply pressure to it.

[0004] The coolant pump (150) performs the function of circulating the primary system coolant that has passed through the steam generator (160) from the reactor (130) back into the reactor (130). The steam generator (160) performs the boiler function of a thermal power plant, and transfers heat to the feedwater that comes in through the secondary system condenser (190) and feedwater pump (191) by the coolant of the primary system that has become hot, thereby converting the feedwater into steam. The steam generated in this way rotates the turbine (170), and accordingly, the generator (180) converts mechanical energy into electrical energy.

[0005] In order to monitor the health of each system while operating a nuclear power plant like this, various types of sensors are installed in the reactor system and the detection signals from the sensors are monitored to determine the status of the nuclear power plant.

[0006] During nuclear power plant operation, if a system malfunction that threatens reactor safety or a cooling malfunction within the nuclear steam supply system occurs, the reactor protection system detects these abnormalities and activates the reactor shutdown function by dropping the control rods. It also activates the engineering safety equipment operation system to cool the reactor. By performing these reactor protection functions, even if a nuclear power plant accident occurs, the plant remains safe and prevents the leakage of radiation and radioactive materials.

[0007] Therefore, the reactor protection system is a system that plays the most important role in the safety and reliability of nuclear power plants. In order to be applied to the power plant site, it must be a system with high reliability and high precision. In addition, when the reactor must be shut down, the reactor protection system must be able to perform the function of shutting down the reactor in any environment inside or outside the reactor protection system.

[0008] To this end, the reactor protection system is generally composed of multiple channels that perform the same function. In addition, the reactor protection system is composed of a signal input unit that acquires detection signals from sensors that measure various process variables and transmits them to multiple channels, a comparison logic unit that compares the acquired detection signals for each process variable with pre-stored set values, a simultaneous logic unit that generates a trip signal by combining the outputs of the comparison logic units of multiple channels when the sensor detection signals for each process variable in the comparison logic unit exceed the set value, and a stop initiation circuit that operates the reactor stop circuit or the engineering safety equipment operation circuit according to the stop signal output from the simultaneous logic unit.

[0009] Figure 2 is a functional block diagram briefly explaining the concept of a digital reactor protection system having one type of processor on a single board in the same channel.

[0010] As illustrated in Fig. 2, the digital reactor protection system (200) is composed of four channels (Channel A, B, C, D) (211, 212, 213, 214) with a redundancy structure. The number of channels may be four or more, but a four-channel redundancy structure is preferable in consideration of redundancy efficiency and circuit complexity. The remote shutdown room operator module and the main control room operator module (not illustrated) are connected to the four channels (211 to 214) to monitor and control the operating status of the reactor protection system.

[0011] In addition, the digital reactor protection system (200) is composed of a control device and a man-machine interface (MMI: Man-Machine Interface) related to testing / diagnosis, and an engineering workstation (EWS: Engineering Work Station) for initially loading the settings. The EWS is used to input the settings and related constants for each processor or hardware within the reactor protection system. The external system is composed of Tr. CPC, reactor trip device (RTSG), and engineering safety facility-component control system (ESF-CCS). Here, Tr can be expressed as PI (Process Instrument).

[0012] The above four channels (211 to 214) are completely independently driven from the sensor signal input terminal to the output terminal of each channel on the same board, and transmit the trip signals (240) for each process variable of the reactor systems output from the comparative logic processors (231 to 234) of each channel to the simultaneous logic processors (251 to 254) of the other channels through a communication method by the Safety Data Link (SDL) to exchange information between each channel. The sensor detection signals (220) for each process variable measured by the sensor include the pressure, flow rate, and water content of each system, the factor values ​​inside the reactor calculated by the Core Protection Calculator (CPC), and the neutron flux output values ​​measured by the Ex-core Neutron Flux Monitoring System (ENFMS), and these values ​​are input independently for each channel.

[0013] Sensor detection signals (220) input to the input terminals of each channel (211 to 214) are transmitted to comparison logic processors (231 to 234) and compared with trip setpoints stored within the comparison logic processors (231 to 234). When a specific signal value exceeds the corresponding trip setpoint, the comparison logic processors (231 to 234) generate trip signals (240) for the corresponding variable. The generated trip signals (240) are transmitted to the respective simultaneous logic processors (251 to 254) in the four channels (211 to 214) via a safety data link.

[0014] The simultaneous logic processors (251 to 254) perform a 2 / 4 logic combination on the trip signals 240) for each process variable output from the comparison logic processors (231 to 234) in the 4 channels (211 to 214) and, if the logic is satisfied, that is, if the corresponding logic values ​​from 2 out of the 4 channels are the same (Voting), the simultaneous logic processors (251 to 254) generate a final trip signal (not shown) and transmit it to the initiation circuit (not shown). When the initiation circuit receives the final trip signal (not shown), it cuts off the control rod power through the reactor trip switch gear (RTSG) to stop the reactor due to the control rod dropping, and operates the engineered safety features-device control system (ESF-CCS) to cool the reactor.

[0015] As illustrated in FIG. 2, for the diversity of the reactor protection system (200), channel A (311) may be configured with a type A comparison logic processor (331) and a type A simultaneous logic processor (351) on a single board, channel B (311) may be configured with a type B comparison logic processor (332) and a type B simultaneous logic processor (352) on a single board, channel C (313) may be configured with a type A comparison logic processor (333) and a type A simultaneous logic processor (353) on a single board, and channel D (314) may be configured with a type B comparison logic processor (334) and a type B simultaneous logic processor (354) on a single board.

[0016] As shown in Fig. 2, the type A comparison logic processors (331, 333) of channel A (311) and channel C (313) equally receive all sensor detection signals (220) from the sensor signal input terminal and perform comparison logic.

[0017] In this case, if the type A comparison logic processors (231, 233) of channel A (211) and channel C (213) fail, channel A (211) and channel B (213) will not operate. Of course, channel B (212) and channel D (214), which are composed of type B processors, receive the same sensor detection signals (220) and perform protection logic, but since two channels are used, the range of protection logic is limited. That is, since the 2oo4 logic is changed to 2oo2 or 2oo3 logic, there is a problem that the reliability of the logic is reduced.

[0018] [Prior Art Literature]

[0019] [Patent Document]

[0020] (Patent Document 1) Korean Patent Publication No. 10-2016-0052861 (Reactor protection system including heterogeneous control devices, Korea Atomic Energy Research Institute)

[0021] (Patent Document 2) Korean Patent Publication No. 10-0848881 (Digital Reactor Protection System, Samchang Enterprise)

[0022] An object of the present invention to solve the above-mentioned problems is to provide a reactor protection system with enhanced diversity to prepare for common cause failure modes that may occur in a reactor protection system.

[0023] However, the problem to be solved by the present invention is not limited to this, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0024] According to one embodiment of the present invention, a nuclear reactor protection system using heterogeneous processors comprises: M channels that equally receive input signals of N different items, where M and N are integers greater than 1; at least two comparison logic processors arranged in each of the M channels and receiving input signals of the N different items to perform comparison logic (Bistable); and at least two concurrent logic processors arranged in each of the M channels and receiving processing results of the at least two comparison logic processors to perform coincidence logic (Coincidence) to generate a trip signal, wherein the at least two comparison logic processors and the at least two concurrent logic processors can be implemented within a single board in each of the M channels.

[0025] The input signals of the N different items may include at least one of pressure, temperature, flow rate and radioactivity measured in the reactor.

[0026] Each of the comparison logic processors, each of which is implemented within a single board of each of the M channels, may be assigned input signals of the N different items without duplication.

[0027] Each of the at least two comparison logic processors implemented within a single board of each of the above M channels may be implemented heterogeneously.

[0028] Each of the above M channels, each consisting of at least two simultaneous logical processors within a single board, may be implemented heterogeneously.

[0029] The comparison logic processor and the concurrent logic processor that process the input signal of the same item within each of the above M channels may be of the same type.

[0030] Among the input signals of the above N different items, the same item can be input to at least two identical and at least two heterogeneous comparison logic processors.

[0031] The above comparison and concurrent logic processor can be implemented in either SRAM or FLASH.

[0032] The disclosed technology may have the following effects. However, this does not mean that a particular embodiment must include all or only the following effects, and thus the scope of the disclosed technology should not be construed as being limited thereby.

[0033] First, by maintaining the protection logic capability in the normal state in the event of a common-cause failure of the reactor protection system, the immunity to common-cause failures can be improved compared to the heterogeneous design of simple controllers.

[0034] Second, by reducing the number of sensor detection signals input to the comparison logic of the reactor protection system, the complexity of the hardware can be reduced, thereby reducing the number of causes of failure and improving the reliability of the reactor protection system.

[0035] Figure 1 is a drawing to explain the main components of a typical nuclear power plant.

[0036] Figure 2 is a functional diagram briefly explaining the concept of a digital reactor protection system having one type of processor on the same channel.

[0037] FIGS. 3A and 3B are functional diagrams for briefly explaining a single channel configuration of a digital reactor protection system according to one embodiment of the present invention.

[0038] FIG. 4 is a functional configuration diagram briefly explaining some configurations for diversity of a digital reactor protection system according to one embodiment of the present invention.

[0039] FIG. 5 is a functional diagram briefly explaining the operation when a common cause failure occurs in a digital reactor protection system according to one embodiment of the present invention.

[0040] FIG. 6 is a flowchart showing a process of acquiring an intermediate value performed within a comparison logic processor according to one embodiment of the present invention.

[0041] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and it is to be understood that all modifications, equivalents, and alternatives included within the technical spirit and scope of the present invention are included. In describing the present invention, if a detailed description of a related known technology is judged to obscure the gist of the present invention, the detailed description will be omitted.

[0042] Terms like "first" and "second" may be used to describe various components, but these terms do not limit the components themselves. These terms are used solely to distinguish one component from another.

[0043] The terminology used in this invention is solely for the purpose of describing specific embodiments and is not intended to limit the invention. The terminology used in this invention has been selected from widely used, current terms, taking into account the functions of the invention. However, this may vary depending on the intentions of those skilled in the art, precedents, or the emergence of new technologies. Furthermore, in certain cases, the applicant may arbitrarily select terms, in which case their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should not be defined simply as names of terms, but rather based on their meanings and the overall content of the invention.

[0044] Singular expressions include plural expressions unless the context clearly dictates otherwise. In the present invention, terms such as "comprise" or "have" are intended to indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood not to preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In describing with reference to the attached drawings, identical or corresponding components are assigned the same drawing numbers, and redundant descriptions thereof will be omitted.

[0046] FIGS. 3A and 3B are functional diagrams for briefly explaining a single channel configuration of a digital reactor protection system according to one embodiment of the present invention.

[0047] Referring to FIG. 3a, a board implementing the channel of the present invention has a heterogeneous-based comparison logic processor (Bistable Processor) (330, 331) and a coincidence logic processor (Coincidence Processor) (350, 351).

[0048] That is, channel A (310) includes a comparison logic processor (330) and a simultaneous logic processor (350) based on the same type within a single board, and at the same time, a comparison logic processor (331) and a simultaneous logic processor (351) implemented as the same type and a different type. In addition, each of the heterogeneous comparison logic processors (330, 331) within channel A (310) receives a portion of the entire sensor detection signals (320) input to the input terminal of channel A (310) without duplication.

[0049] For example, if the sensor detection signals (320) are pressure (P), temperature (T), flow rate (F), and radiation (N), the pressure (P) and temperature (T) (321) are assigned to the SRAM-based comparison logic processor (330) of channel A (310), and the flow rate (F) and radiation (N) (322) are assigned to the FLASH-based comparison logic processor (331). The SRAM-based comparison logic processor (330) compares the assigned sensor detection signals (P, T) (321) with the corresponding trip setpoint, and if the sensor detection signal (P, T) (321) value exceeds the pre-stored trip setpoint, the SRAM-based comparison logic processor (330) generates trip signals (340) for the corresponding process variable. The generated trip signal (340) is transmitted to the SRAM-based simultaneous logic processor (350).

[0050] The SRAM-based simultaneous logic processor (350) performs a 2 / 4 logic combination on the process variable-specific trip signal (340) transmitted from the SRAM-based comparison logic processor (330) in channel A (310) and the SRAM-based comparison logic processors (not shown) in other channels, and when the logic is satisfied, i.e., when the corresponding logic values ​​from two channels out of four channels are the same (Voting), the SRAM-based simultaneous logic processor (350) generates a first channel trip (360) and transmits it to the initiation circuit (not shown).

[0051] Meanwhile, the FLASH-based comparison logic processor (331) compares the assigned sensor detection signal (F, N) (322) with a pre-stored trip setting value, and when the sensor detection signal (F, N) (322) value exceeds the trip setting value, the FLASH-based comparison logic processor (331) generates trip signals (341) for the corresponding process variable.

[0052] The generated trip signal (341) is transmitted to a FLASH-based simultaneous logic processor (351). The FLASH-based simultaneous logic processor (351) performs a 2 / 4 logic combination on the process variable-specific trip signal (341) transmitted from the SRAM-based comparison logic processor (331) within the same channel and the SRAM-based comparison logic processors (not shown) within other channels. If the logic is satisfied, that is, if the corresponding logic values ​​are the same (Voting) from two channels out of four channels, the FLASH-based simultaneous logic processor (351) generates a second channel trip (361) and transmits it to an initiation circuit (not shown).

[0053] Referring to FIG. 3b, channel A (311) constituting the nuclear reactor protection system of the present invention is provided with four comparison logic processors (332 to 335) of different types and four simultaneous logic processors (352 to 355) of different types. Each of the different heterogeneous comparison logic processors (332 to 335) receives, without duplication, one of the entire sensor detection signals (320) input to the input terminal of channel A (310).

[0054] For example, if the sensor detection signals (320) are pressure (P), temperature (T), flow rate (F), and radiation (N), pressure (P) (323) is assigned to the first heterogeneous-based comparison logic processor (332) of channel A (311), temperature (T) (324) is assigned to the second heterogeneous-based comparison logic processor (333), flow rate (F) (325) is assigned to the third heterogeneous-based comparison logic processor (334), and radiation (N) (326) is assigned to the fourth heterogeneous-based comparison logic processor (335). The first to fourth heterogeneous-based comparison logic processors (332 to 335) compare each assigned sensor detection signal (323 to 326) with a pre-stored trip setpoint, and when the value of each sensor detection signal (323 to 326) exceeds the corresponding trip setpoint, each of the first to fourth heterogeneous-based comparison logic processors (332 to 335) generates trip signals (342) for the corresponding variable.

[0055] The first heterogeneous-based simultaneous logic processor (352) performs a 2 / 4 logic combination on the process variable-specific trip signals (342) output from the first heterogeneous-based comparison logic processor (332) of the same channel and the first heterogeneous-based comparison logic processors (not shown) in other channels, and when the logic is satisfied, i.e., when the corresponding logic values ​​are the same (Voting) from two channels out of four channels, the first channel trip (361) is generated and transmitted to the initiation circuit (not shown).

[0056] The first heterogeneous-based simultaneous logic processor (352) causes the remaining comparison logic and simultaneous logic processors, excluding the first heterogeneous-based comparison logic processor (332) of the same channel, to perform the same operation.

[0057] FIG. 4 is a functional configuration diagram briefly explaining some configurations for diversity of a digital reactor protection system according to one embodiment of the present invention.

[0058] As illustrated in FIG. 4, channel A (410), which is one of the channels constituting the nuclear reactor protection system of the present invention, is equipped with heterogeneous comparison logic processors (430, 431) and heterogeneous simultaneous logic processors (450, 451), and each of the heterogeneous comparison logic processors (430, 431) receives, without duplication, some of the sensor detection signals (P, T, F, N) (420) input to channel A (410). Meanwhile, channel B (411), which is one of the channels constituting the nuclear reactor protection system of the present invention, is equipped with heterogeneous comparison logic processors (432, 433) and heterogeneous simultaneous logic processors (452, 453), and each of the heterogeneous comparison logic processors (432, 433) receives, without duplication, some of the sensor detection signals (P, T, F, N) (423) input to channel B (411).

[0059] As an example of a configuration in which sensor detection signals (P, T, F, N) (420, 423) are assigned to comparison logic processors (430, 431, 432, 433) in each channel (channel A, channel B) (410, 411), as illustrated in FIG. 4, pressure (P) and temperature (T) (421) are assigned to the SRAM-based comparison logic processor (430) of channel A (410), and the same pressure (P) and temperature (T) (421) assigned to the SRAM-based comparison logic processor (430) of channel A (410) are assigned to the FLASH-based comparison logic processor (432) of channel B (411). As a result, the FASH-based comparison logic processor (431) of channel A (410) is assigned the flow rate (F) and radiation (N) (422), and the SRAM-based comparison logic processor (433) of channel B (411) is assigned the same flow rate (F) and radiation (N) (422) assigned to the FLASH-based comparison logic processor (431) of channel A (410).

[0060] That is, the same sensor detection signal (422) is assigned to the FLASH-based comparison logic processor (431) of channel A (410) and the SRAM-based comparison logic processor (433) of channel B (411), and the same sensor detection signal (421) is assigned to the SRAM-based comparison logic processor (430) of channel A (410) and the FLASH-based comparison logic processor (432) of channel B (411), but the sensor detection signal (421) and the sensor detection signal (422) are process variable values ​​of different items that do not overlap with each other.

[0061] FIG. 5 is a functional diagram briefly explaining the operation when a common cause failure occurs in a digital reactor protection system according to one embodiment of the present invention.

[0062] In Fig. 5, the trip signal (not shown) of channel A is generated through the OR logic of the first channel trip and the second channel trip, and for channels B, C, and D, a trip signal for each channel is generated through the same OR logic.

[0063] As illustrated in FIG. 5, if a common cause failure occurs in FLASH, the SRAM-based concurrent logic processor (550) receives trip signals for P and T from the SRAM-based comparison logic processors (520, 524), and trip signals for F and N from the SRAM-based comparison logic processors (523, 527), and generates a final trip decision value.

[0064] Similarly, the SRAM-based concurrent logic processors (553, 554, 557) receive trip signals for P, T, F, and N from the SRAM-based comparison logic processors (520, 523, 524, 527) and generate final trip decision values.

[0065] [Explanation of symbols]

[0066] 310, 311, 410, 411, 510 to 513: Channels

[0067] 320 to 326, 420 to 422: Sensor detection signals

[0068] 330 to 335, 430 to 433, 520 to 527: comparison logic processor

[0069] 350 to 355, 450 to 453, 550 to 557: concurrent logical processors

[0070] 360, 361, 460 to 462, 560: Channel Trip

Claims

1. A nuclear reactor protection system using heterogeneous processors, M channels receiving identical input signals of N different items, where M and N are integers greater than 1; At least two comparison logic processors arranged in each of the M channels and receiving input signals of the N different items and performing comparison logic (Bistable); At least two concurrent logic processors are disposed on each of the above M channels and receive the processing results of the at least two comparison logic processors and perform concurrent logic to generate a trip signal, A nuclear protection system using heterogeneous processors, wherein the at least two comparison logic processors and the at least two simultaneous logic processors are implemented within a single board in each of the M channels.

2. In paragraph 1, A nuclear reactor protection system using heterogeneous processors, wherein the input signals of the N different items include at least one of pressure, temperature, flow rate, and radioactivity measured in the nuclear reactor.

3. In paragraph 1, A nuclear protection system using heterogeneous processors, wherein each of the at least two comparison logic processors implemented within a single board for each of the M channels receives input signals of the N different items without duplication.

4. In paragraph 1, A nuclear protection system using heterogeneous processors, wherein each of the comparison logic processors, each of which is implemented within a single board of each of the above M channels, is implemented heterogeneously.

5. In paragraph 1, A nuclear reactor protection system using heterogeneous processors, wherein each of the M channels, each of which consists of at least two simultaneous logical processors within a single board, is implemented heterogeneously.

6. In paragraph 5, A nuclear reactor protection system using heterogeneous processors, wherein the comparison logic processor and the simultaneous logic processor, which process the input signals of the same item within a single board of each of the above M channels, are of the same type.

7. In paragraph 6, A nuclear reactor protection system using heterogeneous processors, wherein among the input signals of the above N different items, the same item is input to at least two identical and at least two heterogeneous comparison logic processors.

8. In paragraph 7, A nuclear protection system using heterogeneous processors, wherein the above comparison and concurrent logic processors are implemented as either SRAM or FLASH.

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