Reactor protection system using heterogeneous bistable / coincidence logic integrated processor

Abstract

The present invention relates to a reactor protection system. The reactor protection system using a heterogeneous bistable / coincidence logic integrated processor according to an embodiment of the present invention comprises: M channels that equally receive input signals of N different items; M signal separators that are disposed in the M channels, respectively, and receive the input signals of the N different items to physically separate and transmit each of the input signals of the N different items, wherein M and N are integers greater than 1; and coincidence logic / bistable integration processors that are disposed in the M channels respectively, receive all the input signals of the N different items separated from each other from the M signal separators, and integrate the coincidence logic / bistable.

Description

Reactor protection system using heterogeneous non-concurrent logic integrated processors

[0001] The present invention relates to a nuclear reactor protection system, and more specifically, to a nuclear reactor protection system using a heterogeneous non-simultaneous logic integrated processor.

[0002] Figure 1 is a drawing for explaining the main configuration of a typical nuclear power plant (100). As illustrated in Figure 1, the primary system of the nuclear power plant (100) includes a reactor (130), a pressurizer (140), a coolant pump (150), and a steam generator (160), and the secondary system may include a turbine (170), a generator (180), a condenser (190), and a feedwater pump (191).

[0003] The reactor (130) generates heat of about 1000 degrees Celsius when the nuclear fuel (120) undergoes nuclear fission, thereby raising the temperature of the coolant to about 300 degrees Celsius. In the pressurizer (140), the coolant water is kept from boiling even at temperatures exceeding 100 degrees Celsius, and in the case of a light water reactor, the coolant is 160 kg / cm 2 Apply pressure of 110 kg / cm for the coolant in the case of heavy water reactors. 2 Apply pressure to it.

[0004] The coolant pump (150) performs the function of circulating the primary system coolant that has passed through the steam generator (160) from the reactor (130) back into the reactor (130). The steam generator (160) performs the boiler function of a thermal power plant, and transfers heat to the feedwater that comes in through the secondary system condenser (190) and feedwater pump (191) by the coolant of the primary system that has become hot, thereby converting the feedwater into steam. The steam generated in this way rotates the turbine (170), and accordingly, the generator (180) converts mechanical energy into electrical energy.

[0005] In order to monitor the health of each system while operating a nuclear power plant like this, various types of sensors are installed in the reactor system and the detection signals from the sensors are monitored to determine the status of the nuclear power plant.

[0006] During nuclear power plant operation, if a system malfunction that threatens reactor safety or a cooling malfunction within the nuclear steam supply system occurs, the reactor protection system detects these abnormalities and activates the reactor shutdown function by dropping the control rods. It also activates the engineering safety equipment operation system to cool the reactor. By performing these reactor protection functions, even if a nuclear power plant accident occurs, the plant remains safe and prevents the leakage of radiation and radioactive materials.

[0007] Therefore, the reactor protection system is a system that plays the most important role in the safety and reliability of nuclear power plants. In order to be applied to the power plant site, it must be a system with high reliability and high precision. In addition, when the reactor must be shut down, the reactor protection system must be able to perform the function of shutting down the reactor in any environment inside or outside the reactor protection system.

[0008] To this end, the reactor protection system is generally composed of multiple channels that perform the same function. In addition, the reactor protection system is composed of a signal input unit that acquires detection signals from sensors that measure various process variables and transmits them to multiple channels, a comparison logic unit that compares the acquired detection signals for each process variable with pre-stored set values, a simultaneous logic unit that generates a trip signal by combining the outputs of the comparison logic units of multiple channels when the sensor detection signals for each process variable in the comparison logic unit exceed the set value, and a stop initiation circuit that operates the reactor stop circuit or the engineering safety equipment operation circuit according to the stop signal output from the simultaneous logic unit.

[0009] Figure 2 is a schematic diagram illustrating a configuration for securing diversity in an existing digital reactor protection system.

[0010] As illustrated in FIG. 2, the digital reactor protection system (200) is composed of four channels (210, Channel A, B, C, D) with a redundancy structure. The number of channels may be four or more, but a four-channel redundancy structure is preferable in consideration of redundancy efficiency and circuit complexity, and the four channels (210) are configured so that physical and electrical independence between the channels is maintained. The remote shutdown room operator module and the main control room operator module (not illustrated) are connected to the four channels (201) to monitor and control the operating status of the reactor protection system.

[0011] In addition, the digital reactor protection system (200) is composed of a control device and a man-machine interface (MMI: Man-Machine Interface) related to testing / diagnosis, and an engineering workstation (EWS: Engineering Work Station) for initially loading the settings. The EWS is used to input the settings and related constants for each processor or hardware within the reactor protection system. The external system is composed of Tr. CPC, reactor trip device (RTSG), and engineering safety facility-component control system (ESF-CCS). Here, Tr can be expressed as PI (Process Instrument).

[0012] The above four channels (201, Channel A, Channel B, Channel C, Channel D) are operated completely independently from the sensor signal input terminal to the output terminal of each channel, and the trip signals (240) for each process variable of the reactor systems output from the comparative logic processors (230, BP: Bistable Processor) of each channel are transmitted to the simultaneous logic processors (250, CP: Coincidence Processor) of the other channels through a communication method by the Safety Data Link (SDL), thereby exchanging information between each channel. The detection signals for each process variable measured by the sensor include the pressure, flow rate, and water content of each system, the internal factor values ​​of the reactor calculated by the Core Protection Calculator (CPC), and the neutron flux output values ​​measured by the Ex-core Neutron Flux Monitoring System (ENFMS), and these values ​​are input independently for each channel.

[0013] Sensor detection signals (220) input to the input terminal of each channel (210) are transmitted to comparison logic processors (230, BP) and compared with trip setpoints stored within the comparison logic processors (230, BP), and when a specific signal value exceeds the corresponding trip setpoint, the comparison logic processors (230, BP) generate trip signals (240) for the corresponding variable.

[0014] The generated trip signals (240) are transmitted to the respective simultaneous logic processors (250, CP of channel A, CP of channel B, CP of channel C, CP of channel D) in the 4 channels (210) via the safety data link. The simultaneous logic processors (250, CP) perform a 2 / 4 logic combination on the trip signals 240) for each process variable output from the comparison logic processors (230, BP) in the 4 channels (210) and, if the logic is satisfied, that is, if the corresponding logic values ​​from 2 of the 4 channels are the same (Voting), the final trip signal (not shown) is generated and transmitted to the initiation circuit (not shown).

[0015] When the above-described initiation circuit receives the final trip signal (not shown), it cuts off the control rod power through the reactor trip switch gear (RTSG) to drive the reactor to stop due to the control rod falling, and drives the engineered safety features-equipment control system (ESF-CCS) to cool the reactor.

[0016] The existing digital reactor protection system as described above has a structure in which the result of the comparison logic processor, i.e., the channel trip, is transmitted to the simultaneous logic processor, and the simultaneous logic processor votes to determine the final trip, requiring multiple processors for a single channel and the entire protection system, which increases the number of failure factors and, in particular, increases the probability of occurrence of a common cause failure mode.

[0017] Patent Document 1 presents an integrated structure of comparative logic and simultaneous logic in a digital reactor protection system. However, although the number of fault elements can be reduced, it has the problem of lowering the reliability of the entire system because it is impossible to respond to common cause faults by using the same type of controller for all channels. In addition, a specific method for obtaining an intermediate value required for a final trip decision when integrating comparative logic and simultaneous logic is not disclosed.

[0018] Additionally, sensor detection signals measuring various process variables may be lost in the electrical path transmitted to the reactor protection system or may experience interference between signal inputs, resulting in inaccurate trip signals.

[0019] [Prior Art Literature]

[0020] [Patent Document]

[0021] (Patent Document 1) Korean Patent Publication No. 10-2010-0093414 (Power Plant Protection System Integrating Comparative Logic and Simultaneous Logic, Korea Electric Power Corporation)

[0022] (Patent Document 2) Korean Patent Publication No. 10-0408493 (Digital reactor protection system and control method thereof that self-excludes common software failures, Korea Electric Power Corporation)

[0023] The purpose of the present invention to solve the above-mentioned problems is to provide a reactor protection system that can reduce the number of failure factors that may occur in a reactor protection system, secure diversity in preparation for common cause failure modes, and provide loss-free and interference-free input of sensor detection signals measuring various process variables to the reactor protection system.

[0024] However, the problem to be solved by the present invention is not limited to this, and may be expanded in various ways without departing from the spirit and scope of the present invention.

[0025] According to one embodiment of the present invention, a nuclear reactor protection system using a heterogeneous simultaneous comparison logic integration processor may include: M channels that equally receive input signals of N different items; M signal separators arranged in each of the M channels and physically isolating and transmitting the input signals of the N different items; wherein M and N are integers greater than 1; and a simultaneous comparison logic integration processor arranged in each of the M channels and receiving all of the input signals of the N different items that are isolated from each other from the M signal separators to integrate and perform simultaneous and comparison logic.

[0026] The input signals of the N different items may include at least one of pressure, temperature, flow rate and radioactivity measured in the reactor.

[0027] Each of the simultaneous comparison logic integration processors arranged in each of the above M channels can receive M × N signals.

[0028] Each of the simultaneous comparison logic integration processors arranged in each of the M channels can receive the M input signals for each of the N different items.

[0029] The above simultaneous comparison logic integrated processor can generate intermediate values ​​for input signals of the same item and perform comparison and simultaneous logic using the intermediate values.

[0030] The generation of the median may include sequentially sorting the values ​​of the input signals of the same item, and if two or more of the values ​​of the input signals of the same item sorted in the sequence are the same, finding a median from the values ​​of the input signals of the same item sorted in the sequence, and obtaining a conservative value from the median, and if two or more of the values ​​of the input signals of the same item sorted in the sequence are not the same, determining whether the number of channels is even, and if the number of channels is even, finding a median from the values ​​of the input signals of the same item sorted in the sequence excluding the maximum and minimum values, and obtaining a conservative value from the median, and if the number of channels is odd, obtaining a median from the values ​​of the input signals of the same item sorted in the sequence excluding the maximum and minimum values.

[0031] Finding a median in the values ​​of the input signals of the same item sorted in the above sequence, and obtaining a conservative value from the median may include removing the maximum and minimum values ​​from the values ​​of the input signals of the same item sorted in the above sequence, if there are duplicate maximum and minimum values, removing only one of the sorted values ​​first, and if there are values ​​with the same median value after removing the maximum and minimum values, selecting the one of the sorted values ​​first as the median.

[0032] At least some of the simultaneous comparison logic integrated processors arranged in each of the M channels may be implemented heterogeneously.

[0033] The same item input values ​​of at least two channels among the above M (M>2) channels can be input to at least one same type and at least one different type simultaneous comparison logic integration processor.

[0034] The above simultaneous comparison logic integrated processor can be configured with a combination of heterogeneous FPGAs (Field Programmable Gate Arrays) and heterogeneous CPUs.

[0035] The above simultaneous comparison logic integrated processor is implemented as either a first type implemented as an SRAM (Static RAM)-based FPGA and a RISC (Reduced Instruction Set Computer)-based CPU or a second type implemented as an FLSH-based FPGA and a CISC (Complex Instruction Set Computer)-based CPU, and the M channels can be configured with at least one of the first type and at least one of the second type simultaneous comparison logic integrated processors.

[0036] The disclosed technology may have the following effects. However, this does not mean that a particular embodiment must include all or only the following effects, and therefore the scope of the disclosed technology should not be construed as being limited thereby.

[0037] First, the reliability of the reactor protection system can be improved by reducing the complexity of the hardware and software that make up the system, thereby reducing the number of causes of failure.

[0038] Second, by using heterogeneous integrated controllers, even if a common cause failure occurs in one type of controller, the other types of controllers can perform safety functions, thereby improving the safety of the reactor.

[0039] Third, by ensuring the integrity of various sensor detection signals input to the reactor protection system, the reliability and safety of the reactor protection system can be maximized.

[0040] Fourth, by deriving the trip setting value to be input into the simultaneous logic applied in the reactor protection system with reliable logic, the reliability of the reactor shutdown / non-shutdown judgment can be improved.

[0041] Figure 1 is a drawing to explain the main components of a typical nuclear power plant.

[0042] Figure 2 is a schematic diagram illustrating a configuration for securing diversity in an existing digital reactor protection system.

[0043] FIG. 3 is a functional configuration diagram briefly explaining a single channel configuration of a digital reactor protection system according to one embodiment of the present invention.

[0044] FIG. 4 is a functional diagram briefly explaining the concept of the overall operation of a digital reactor protection system according to one embodiment of the present invention.

[0045] FIG. 5 is a functional diagram briefly explaining the concept of a digital reactor protection system using a heterogeneous simultaneous comparison logic integration processor according to one embodiment of the present invention.

[0046] FIG. 6 is a flowchart showing a process of acquiring an intermediate value performed within a simultaneous comparison logic integration processor according to one embodiment of the present invention.

[0047] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, and it is to be understood that all modifications, equivalents, and alternatives included within the technical spirit and scope of the present invention are included. In describing the present invention, if a detailed description of a related known technology is judged to obscure the gist of the present invention, the detailed description will be omitted.

[0048] Terms like "first" and "second" may be used to describe various components, but these terms do not limit the components themselves. These terms are used solely to distinguish one component from another.

[0049] The terminology used in this invention is solely for the purpose of describing specific embodiments and is not intended to limit the invention. The terminology used in this invention has been selected from widely used, current terms, taking into account the functions of the invention. However, this may vary depending on the intentions of those skilled in the art, precedents, or the emergence of new technologies. Furthermore, in certain cases, the applicant may arbitrarily select terms, in which case their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should not be defined simply as names of terms, but rather based on their meanings and the overall content of the invention.

[0050] Singular expressions include plural expressions unless the context clearly dictates otherwise. In the present invention, terms such as "comprise" or "have" are intended to indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood not to preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0051] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In describing with reference to the attached drawings, identical or corresponding components are assigned the same drawing numbers, and redundant descriptions thereof will be omitted.

[0052] FIG. 3 is a functional configuration diagram briefly explaining a single channel configuration of a digital reactor protection system according to one embodiment of the present invention.

[0053] As illustrated in FIG. 3, channel A (310) constituting the nuclear reactor protection system of the present invention includes a single simultaneous comparison logic integrated processor (350) that integrates the comparison logic processor (230) and the simultaneous logic processor (250) in the single channel of FIG. 2.

[0054] As illustrated in FIG. 3, sensor detection signals (P, T, F, N) (320) input to channel A (310) are isolated from each other by a signal separator (330) and transmitted to a simultaneous comparison logic integrated processor (350). The signal separator (330) can perform physical isolation through a signal separator (e.g., an optical converter) to ensure the independence of the sensor detection signals (320) input equally to each channel (310, 311, 312, 313). In addition, the signal separator (330) of channel A (310) is identically provided in other channels (channel B, channel C, channel C) (311, 312, 313) except for channel A (31).

[0055] The simultaneous comparison logic integrated processor (350) of channel A (310) simultaneously receives not only the signal value (340) from the signal separator (330) of channel A (310), but also signal values ​​(341, 342, 342) from the signal separators (not shown) of each of other channels, i.e., channel B, channel C, and channel D (311, 312, 313). Here, each of the signal values ​​(340, 341, 342, 342) includes all of the sensor detection signals (320).

[0056] That is, the simultaneous comparison logic integration processor (350) of channel A (310) performs simultaneous and comparison logic on the same items among the signal values ​​(340, 341, 342, 342) input from the signal separators of each of channel A (310), channel B (311), channel C (312), and channel D (313) to determine the channel trip (360). For example, the simultaneous comparison logic integration processor (350) of channel A performs simultaneous and comparison logic on values ​​corresponding to the pressure item (P) among the input items received from channel A (310), channel B (311), channel C (312), and channel D (313).

[0057] FIG. 4 is a functional diagram briefly explaining the concept of the overall operation of a digital reactor protection system according to one embodiment of the present invention.

[0058] As illustrated in FIG. 4, each channel (410, 411, 412, 413) of the nuclear protection system (400) of the present invention includes a signal separator (430) and simultaneous comparison logic integrated processors (450), and the entire protection logic of the nuclear protection system is performed.

[0059] As illustrated in FIG. 4, the sensor detection signals (P, T, F, N) (420) input to each channel (410, 411, 412, 413) are isolated from each other by the signal separator (430) of each channel (410, 411, 412, 413) and transmitted to the simultaneous comparison logic integration processor (450) of each channel (410, 411, 412, 413). Here, the signal separator (430) of each channel (410, 411, 412, 413) simultaneously transmits the isolated sensor detection signals (420) to the simultaneous comparison logic integration processor (450) of the other channel. The signal separator (430) may perform physical isolation through a signal separation device (e.g., an optical converter) to ensure the independence of the sensor detection signals (420) input to the channel. A simultaneous comparison logic integrated processor of a specific channel can perform simultaneous and comparison logic on signal values ​​transmitted by signal separators of a specific channel and signal separators of other channels. Here, each signal (440) transmitted from each signal separator (430) includes all sensor detection signals (420).

[0060] FIG. 5 is a functional diagram briefly explaining the concept of a digital reactor protection system using a heterogeneous simultaneous comparison logic integration processor according to one embodiment of the present invention.

[0061] As illustrated in FIG. 5, each channel (510, 511, 512, 513) of the nuclear protection system (500) of the present invention includes a signal separator (530) and simultaneous comparison logic integrated processors (550), and the entire protection logic of the nuclear protection system is performed.

[0062] As illustrated in FIG. 5, sensor detection signals (P, T, F, N) (520) input to each channel (511, 512, 513, 514) are isolated from each other by signal separators (530, 531, 532, 533) of each channel (511, 512, 513, 514) and transmitted to a simultaneous comparison logic integration processor (551, 552, 553, 554).

[0063] Here, the sensor detection signals (540) isolated from each other by the signal separators (530, 531, 532, 533) of each channel (511, 512, 513, 514) are simultaneously transmitted to the simultaneous comparison logic integration processors in the same channel and different channels. The signal separators (530 to 533) may perform physical isolation through a signal separator (e.g., an optical converter) to ensure the independence of the sensor detection signals (520) input to each channel. For example, the simultaneous comparison logic integration processor (551) of channel A (511) performs simultaneous and comparison logic on the signal values ​​(540) input from the signal separator (530) of channel A (511) and the respective signal separators (531, 532, 533, 544) of channel B (512), channel C (513), and channel D (514). Here, each signal (540) transmitted from each signal separator (530) includes all sensor detection signals (520).

[0064] As illustrated in FIG. 5, the simultaneous comparison logic integrated processor (551) of channel A (511) and the simultaneous comparison logic integrated processor (552) of channel B (512) are implemented based on FPGAs of different types and CPUs of different types, not of the same type, and similarly, the simultaneous comparison logic integrated processor (553) of channel C (513) and the simultaneous comparison logic integrated processor (554) of channel D (514) are also implemented based on FPGAs of different types and CPUs of different types, not of the same type.

[0065] Here, the simultaneous comparison logic integration processor (551) of channel A (511), the simultaneous comparison logic integration processor (553) of channel C (513), the simultaneous comparison logic integration processor (552) of channel B (512) and the simultaneous comparison logic integration processor (554) of channel D (515) can be implemented based on the same type of FPGA and the same type of CPU.

[0066] For example, the A-type can be implemented with an SRAM-based FPGA and a RISC-based CPU, while the B-type can be implemented with a FLASH-based FPGA and a CISC-based CPU. Consequently, even if a failure occurs in the A-type, the B-type will not experience the same failure as the A-type, preventing common-cause failures.

[0067] That is, even if channel A (511) and channel C (513) using simultaneous comparison logic integration processors based on FPGAs and CPUs of the same type fail, channel B (512) and channel D (514) using simultaneous comparison logic integration processors based on heterogeneous FPGAs and CPUs can operate normally, thereby satisfying the diversity required in the reactor protection system. However, in addition to the method disclosed above, a structure for allocating heterogeneous FPGAs to each channel for diversity can be implemented in various ways.

[0068] For example, channel A (511) and channel B (512) may use a simultaneous comparison logic integrated processor using an SRAM-based FPGA and a RISC-based CPU, and channel C (513) and channel D (514) may use a simultaneous comparison logic integrated processor using a FLASH-based FPGA and a CISC-based CPU.

[0069] In another example, channel A (511) and channel D (514) may use a concurrent comparison logic integrated processor using an SRAM-based FPGA and a RISC-based CPU, and channel B (512) and channel C (513) may use a concurrent comparison logic integrated processor using a FLASH-based FPGA and a CISC-based CPU.

[0070] FIG. 6 is a flowchart showing a process of acquiring an intermediate value performed within a simultaneous comparison logic integration processor according to one embodiment of the present invention.

[0071] As illustrated in Figure 6, first, the simultaneous comparison logic integration processor sequentially sorts the values ​​input from multiple channels by process variable (S610). That is, the pressure (P), temperature (T), flow rate (F), and radiation (N) received from each channel are sequentially sorted.

[0072] Next, it is determined whether two or more of the same process variable values ​​input from multiple channels are the same (S620). In other words, it is determined whether two or more of the pressure (P) values ​​transmitted from multiple channels are the same.

[0073] If two or more identical values ​​exist, and if duplicate maximum and minimum values ​​exist when removing the maximum and minimum values ​​after sequential sorting, only one of the sorted values ​​is removed first, and if the median value exists after removing the maximum and minimum values, the one that was sorted first is selected as the median value (S630).

[0074] If there are no two or more identical process variable values ​​input from multiple channels, it is determined whether the number of channels is an even number (S640).

[0075] In case there are an even number of channels, in step S610, the median value is found by excluding the maximum and minimum values ​​from the values ​​sequentially sorted by process variable, and a conservative value is obtained from the median value (S650).

[0076] In step S640, if the number of channels is odd, the median value excluding the maximum and minimum values ​​is obtained from the values ​​sequentially sorted by process variable in step S610 (S660).

[0077] [Explanation of symbols]

[0078] 320, 420: Detection signals

[0079] 330, 430, 530: Signal separator

[0080] 350, 450, 550: Simultaneous Comparison Logic Integrated Processor

Claims

1. A nuclear reactor protection system using a heterogeneous simultaneous comparison logic integration processor, M channels receiving identical input signals of N different items; M signal separators arranged in each of the M channels and receiving input signals of the N different items and physically isolating and transmitting each of the input signals of the N different items, where M and N are integers greater than 1; and A nuclear reactor protection system using a heterogeneous simultaneous comparison logic integration processor, comprising a simultaneous comparison logic integration processor that receives all input signals of the N different items that are arranged in each of the M channels and are isolated from each other from the M signal separators and performs simultaneous and comparison logic.

2. In paragraph 1, A reactor protection system using a heterogeneous simultaneous comparison logic integration processor, wherein the input signals of the N different items include at least one of pressure, temperature, flow rate and radioactivity measured in the reactor.

3. In paragraph 1, A nuclear reactor protection system using heterogeneous simultaneous comparison logic integration processors, each of which is arranged on each of the above M channels and receives M × N input signals.

4. In paragraph 1, A nuclear reactor protection system using heterogeneous simultaneous comparison logic integration processors, wherein each of the simultaneous comparison logic integration processors arranged in each of the M channels receives the M input signals for each of the N different items.

5. In paragraph 1, A nuclear reactor protection system using a heterogeneous simultaneous comparison logic integration processor, wherein the simultaneous comparison logic integration processor includes generating an intermediate value for input signals of the same item.

6. In paragraph 5, The generation of the above median is The values of the input signals of the same item are arranged sequentially, and if two or more of the values of the input signals of the same item arranged sequentially are the same value, the median value is found among the values of the input signals of the same item arranged sequentially, and a conservative value is obtained from the median value. If two or more values of the input signals of the same item are not the same, it is determined whether the number of channels is even, and if the number of channels is even, the median value is found excluding the maximum and minimum values from the values of the input signals of the same item sorted in the above sequence, and a conservative value is obtained from the median value. A nuclear reactor protection system using a heterogeneous simultaneous comparison logic integrated processor, which comprises obtaining a median value excluding the maximum and minimum values from the values of the input signals of the same items sorted in the above sequence when the number of channels is odd.

7. In paragraph 6, Finding the median value among the values of the input signals of the same item sorted in the above sequence and obtaining a conservative value from the median value A nuclear protection system using a heterogeneous simultaneous comparison logic integrated processor, wherein when removing maximum and minimum values from the values of the input signals of the same item sorted in the above sequence, if there are duplicate maximum and minimum values, only one sorted value is removed first, and if there is a value with the same intermediate value after removing the maximum and minimum values, the first sorted one is selected as the intermediate value.

8. In paragraph 1, A nuclear reactor protection system using heterogeneous simultaneous comparison logic integration processors, wherein at least some of the simultaneous comparison logic integration processors arranged in each of the M channels are implemented heterogeneously.

9. In paragraph 8, A nuclear reactor protection system using a heterogeneous simultaneous comparison logic integration processor, wherein the same item input values of at least two channels among the above M channels are input to at least one same type and at least one different type simultaneous comparison logic integration processor.

10. In paragraph 9, The above simultaneous comparison logic integrated processor is a nuclear reactor protection system using a heterogeneous simultaneous comparison logic integrated processor composed of a combination of an FPGA (Field Programmable Gate Array) and a CPU.

11. In paragraph 9, The above simultaneous comparison logic integration processor is implemented as either a first type implemented with a SRAM (Static RAM)-based FPGA and a RISC (Reduced Instruction Set Computer)-based CPU or a second type implemented with a FLSH-based FPGA and a CISC (Complex Instruction Set Computer)-based CPU, and the M channels are composed of at least one of the first type and at least one of the second type simultaneous comparison logic integration processors, a nuclear reactor protection system using heterogeneous simultaneous comparison logic integration processors.

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