Arithmetic unit and computing device
WO2025185479A8 Publication Date: 2025-10-02CANAAN CREATIVE CO LTD
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Patent Information
- Application Number
- PCT/CN2025/078991
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-03-05
- Filing Date
- 2025-02-25
- Publication Date
- 2025-10-02
AI Technical Summary
Technical Problem
When multiple chips are powered in series, in signal communication scenarios across voltage domains, the signal duty cycle is easily offset. Existing technical solutions are complex and increase chip power consumption and area.
Method used
Sequential logic devices such as triggers are used to adjust the signal duty cycle, and the duty cycle offset during cross-voltage domain signal transmission is corrected through clock sampling to simplify the logic circuit structure.
Benefits of technology
Effectively correct duty cycle offset, reduce chip area and power consumption, simplify logic circuit design, and keep signal period unchanged.
✦ Generated by Eureka AI based on patent content.
Abstract
The present application discloses an arithmetic unit and a computing device. The arithmetic unit comprises: a plurality of processing modules connected in series; at least one communication link arranged on the processing modules; and a signal duty cycle adjusting circuit arranged on the communication link and used to perform duty cycle adjustment on transmission signals on the communication link, wherein the signal duty cycle adjusting circuit comprises a timing logic device used to solve the problem of signal duty cycle distortion during cross-voltage domain transmission.
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