Pressure sensor and preparation method therefor and air conditioning device

Abstract

A pressure sensor (1000) and a preparation method therefor and an air conditioning device. The pressure sensor (1000) comprises: a silicon substrate (100), the silicon substrate (100) comprising a first surface (101) and a second surface (102) opposite to each other, and the second surface (102) being provided with a cavity (150); a plurality of doped leads (120), the plurality of doped leads (120) being arranged in the silicon substrate (100); a plurality of varistor (130), the plurality of varistors (130) being electrically connected to the plurality of doped leads (120), respectively; a plurality of contact plugs (140), the plurality of contact plugs (140) being electrically connected to the plurality of doped leads (120), respectively; and a sealing cover (200), the sealing cover (200) being fastened on the silicon substrate (100) and forming a closed cavity (300) with the silicon substrate (100); the sealing cover (200) comprises a bonding portion (201); the sealing cover (200) is bonded and connected to the silicon substrate (100) by means of the bonding portion (201); the orthographic projection of the bonding portion (201) on the silicon substrate (100) is located between the orthographic projections of the varistors (130) and the contact plugs (140) on the silicon substrate (100); the surface of each varistor (130) facing the sealing cover (200) is exposed to the closed cavity (300); and in a first direction (Z), the distance between a third surface (121) of each doped lead (120) and the first surface (101) is greater than the distance between the surface of each varistor (130) facing the sealing cover (200) and the first surface (101).

Description

Pressure sensor, manufacturing method thereof, and air conditioning device

[0001] This application claims the benefit of Chinese patent application No. 202410288513.0 filed with the Patent Office of China on March 13, 2024, and all disclosed contents of that application are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of sensor technology, and in particular to a pressure sensor, a manufacturing method thereof, and an air conditioning device. Background Art

[0003] With the development of new energy vehicle technology and the general trend toward energy conservation and environmental protection, the market penetration of new energy vehicles has gradually increased, becoming a major trend in the automotive industry. Since new energy vehicles lack engine heat, they require additional electricity for heating, resulting in low conversion efficiency. Therefore, air conditioning and heating have become the largest non-power loss in new energy vehicles. Limited by the difficulty and long cycle of improving battery and fast-charging technologies, optimizing energy consumption in vehicle thermal management systems has become a key development direction for new energy vehicles. In vehicle thermal management systems, pressure sensors are placed in the refrigerant pipes. By sensing the pressure in the pipes, they adjust the operating power of the compressor and evaporator to achieve temperature control and energy conservation. Consequently, the requirements for pressure sensors are becoming increasingly stringent.

[0004] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the Invention

[0005] In one aspect, a pressure sensor is provided, comprising:

[0006] A silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the second surface being provided with a cavity, and the first surface being provided with a plurality of first grooves;

[0007] a plurality of doped leads, the plurality of doped leads being disposed in the silicon substrate, the doped leads comprising a third surface close to the first surface, at least a portion of the third surface being exposed to the first groove;

[0008] a plurality of varistors, wherein the plurality of varistors are disposed in the silicon substrate and are electrically connected to the plurality of doped leads respectively;

[0009] a plurality of contact plugs, each of which is disposed in each of the first grooves and electrically connected to each of the doped leads; and

[0010] A sealing cover, the sealing cover is buckled on the silicon substrate and forms a closed cavity between the sealing cover and the silicon substrate, the sealing cover includes a bonding portion, and the sealing cover is bonded to the silicon substrate through the bonding portion,

[0011] The orthographic projection of the bonding portion on the silicon substrate is located between the orthographic projections of the varistor and the contact plug on the silicon substrate;

[0012] The surface of the varistor facing the sealing cover is exposed to the sealed cavity; and

[0013] The distance between the third surface and the first surface in the first direction is greater than the distance between the surface of the varistor facing the sealing cover and the first surface in the first direction, and the first direction is parallel to the direction from the silicon substrate toward the sealing cover;

[0014] The orthographic projection of the varistor on the silicon substrate at least partially overlaps with the orthographic projection of the doped lead on the silicon substrate.

[0015] According to an exemplary embodiment of the present disclosure, a surface of the varistor facing away from the doping lead, a surface of the contact plug facing away from the doping lead, and the first surface form a planarized surface.

[0016] According to an exemplary embodiment of the present disclosure, an orthographic projection of the sealing cover on the silicon substrate does not overlap with an orthographic projection of the contact plug on the silicon substrate.

[0017] According to an exemplary embodiment of the present disclosure, an orthographic projection of the contact plug on the silicon substrate at least partially overlaps with an orthographic projection of the doped lead on the silicon substrate; and / or,

[0018] The orthographic projection of the piezoresistor on the silicon substrate falls within the orthographic projection of the cavity on the silicon substrate.

[0019] According to an exemplary embodiment of the present disclosure, the pressure sensor further includes a conductive portion located on a side of the contact plug away from the silicon substrate, wherein a material of the conductive portion is different from a material of the sealing cover.

[0020] According to an exemplary embodiment of the present disclosure, the pressure sensor further includes a packaging portion surrounding a plurality of side walls of the conductive portion, wherein a material of at least a portion of the packaging portion is different from a material of the sealing cover and a material of the conductive portion.

[0021] According to an exemplary embodiment of the present disclosure, the sealing cover is made of glass or silicon, the conductive portion is made of copper, and at least a portion of the packaging portion is made of a molding material.

[0022] According to an exemplary embodiment of the present disclosure, the packaging portion includes a first sub-packaging portion and a second sub-packaging portion, wherein the first sub-packaging portion is located at the periphery of the sealing cover, and the second sub-packaging portion is located at the periphery of the first sub-packaging portion.

[0023] Wherein, the material of the second sub-encapsulation part is the same as the material of the sealing cover; the material of the first sub-encapsulation part includes a plastic packaging material; and

[0024] The conductive portion is in direct contact with the first sub-package portion.

[0025] According to an exemplary embodiment of the present disclosure, the first sub-package portion includes a first via hole, and the conductive portion fills the first via hole; or,

[0026] A second via is formed between the sealing cover and the second sub-package; the conductive portion includes a first portion and a second portion, the first portion is electrically connected to the contact plug,

[0027] The first portion is located in the second via hole, covers sidewalls of the sealing cover and the second sub-package portion close to the second via hole, and covers at least a portion of a surface of the contact plug facing away from the doped lead; the second portion extends from the first portion and covers at least a portion of a surface of the sealing cover facing away from the silicon substrate; and

[0028] The second via hole includes a third via hole not filled by the first portion, and the first sub-package portion fills the third via hole.

[0029] According to an exemplary embodiment of the present disclosure, the pressure sensor further includes a conductive portion and a packaging portion, wherein the conductive portion is located on a side of the contact plug away from the silicon substrate, and the packaging portion surrounds multiple sidewalls of the conductive portion and multiple sidewalls of the sealing cover.

[0030] The sealing cover is made of silicon, the conductive portion is made of conductive silicon, and the packaging portion is made of a plastic material.

[0031] According to an exemplary embodiment of the present disclosure, the pressure sensor further includes a conductive portion and a packaging portion, wherein the conductive portion is located on a side of the contact plug away from the silicon substrate, the packaging portion surrounds multiple sidewalls of the conductive portion, and the conductive portion contacts multiple sidewalls of the sealing cover.

[0032] The sealing cover is made of glass, the conductive portion is made of glass conductive paste, and the packaging portion is made of glass.

[0033] According to an exemplary embodiment of the present disclosure, the pressure sensor further includes:

[0034] a metal transition portion, the metal transition portion being located on a side of the conductive portion facing away from the silicon substrate and being electrically connected to the conductive portion; and

[0035] A contact terminal is located on a side of the metal transition portion facing away from the silicon substrate and is electrically connected to the metal transition portion.

[0036] According to an exemplary embodiment of the present disclosure, the conductive portion includes a second seed layer, the second seed layer is located on a side of the conductive portion close to the contact plug, and a material of the second seed layer includes titanium, copper, or a metal alloy.

[0037] According to an exemplary embodiment of the present disclosure, the encapsulation part includes a plurality of via holes, and the second seed layer covers at least a portion of a sidewall and a bottom of at least one via hole of the encapsulation part.

[0038] According to an exemplary embodiment of the present disclosure, the contact plug includes a first seed layer, the first seed layer is located on a side of the contact plug close to the doped wire, and a material of the first seed layer includes titanium, copper, or a metal alloy.

[0039] According to an exemplary embodiment of the present disclosure, the pressure sensor further includes a first transition layer located between the contact plug and the conductive portion, wherein an orthographic projection of the first transition layer on the silicon substrate at least partially overlaps with an orthographic projection of the contact plug on the silicon substrate.

[0040] According to an exemplary embodiment of the present disclosure, the pressure sensor further includes a second transition layer located between the conductive portion and the metal transition portion, wherein an orthographic projection of the second transition layer on the silicon substrate at least partially overlaps with an orthographic projection of the conductive portion on the silicon substrate.

[0041] In another aspect, a method for preparing a pressure sensor is provided, comprising:

[0042] Providing a silicon substrate, the silicon substrate comprising a first side and a second side opposite to each other;

[0043] forming a plurality of doped leads in the silicon substrate close to the first surface and spaced apart from each other, wherein the doped leads include a third surface close to the first surface, and a distance between the first surface and the third surface is greater than 0;

[0044] forming a plurality of varistors on the first surface of the silicon substrate, the plurality of varistors being electrically connected to the plurality of doped leads respectively, and the orthographic projections of the varistors on the silicon substrate at least partially overlapping with the orthographic projections of the doped leads on the silicon substrate;

[0045] forming a plurality of first grooves on the first surface of the silicon substrate, wherein the first grooves expose at least a portion of the third surface of the doped lead;

[0046] forming a plurality of contact plugs in the first groove, wherein the plurality of contact plugs are electrically connected to the plurality of doped leads respectively, and a surface of the varistor facing away from the doped leads, a surface of the contact plug facing away from the doped leads, and the first surface form a planarized surface;

[0047] forming a sealing cover on the first surface of the silicon substrate, wherein the sealing cover is buckled onto the silicon substrate and forms a sealed cavity between the sealing cover and the silicon substrate, the sealing cover including a bonding portion, the sealing cover being bonded to the silicon substrate via the bonding portion, and an orthographic projection of the bonding portion on the silicon substrate being located between the orthographic projections of the varistor and the contact plug on the silicon substrate; and

[0048] A cavity is formed on the second surface of the silicon substrate.

[0049] According to an exemplary embodiment of the present disclosure, the preparation method further includes:

[0050] forming a packaging portion and a conductive portion on the first surface of the silicon substrate;

[0051] The packaging part is located on the silicon substrate and the contact plug, and is located on the periphery of the sealing cover; at least a portion of the conductive part is located in the via hole of the packaging part and is electrically connected to the contact plug, and the via hole of the packaging part exposes at least a portion of the conductive part.

[0052] According to an exemplary embodiment of the present disclosure, the preparation method further includes:

[0053] Before forming the plurality of doped leads, forming a first protective layer on the first surface of the silicon substrate using a high temperature oxidation technique; and

[0054] After forming the plurality of varistors and before forming the plurality of first grooves, the first protection layer is removed.

[0055] According to an exemplary embodiment of the present disclosure, forming a plurality of contact plugs in the first groove includes:

[0056] forming a first seed layer in the first groove by using a physical vapor deposition technique;

[0057] Filling the first groove with a contact plug material layer using electroplating technology;

[0058] Removing excess contact plug material layer using chemical mechanical polishing technology; and

[0059] Annealing is performed to form a plurality of contact plugs.

[0060] According to an exemplary embodiment of the present disclosure, forming the conductive portion on the first surface of the silicon substrate includes:

[0061] forming a second seed layer on the first surface of the silicon substrate by using a physical vapor deposition technique;

[0062] Using photolithography technology, forming a photoresist deep hole above the contact plug;

[0063] Filling the photoresist deep holes with conductive material using electroplating technology;

[0064] removing the photoresist; and

[0065] The redundant second seed layer is removed by wet etching technology to form the conductive portion.

[0066] According to an exemplary embodiment of the present disclosure, forming a sealing cover on the first surface of the silicon substrate includes:

[0067] Provide glass sheets;

[0068] Using laser induction on a glass sheet to modify a designated area of ​​the glass sheet;

[0069] Etching the glass sheet using an HF solution to form a first recessed portion and a second recessed portion on a rear surface of the glass sheet, thereby forming a bonding portion surrounding the first recessed portion on the rear surface of the glass sheet, wherein the rear surface of the glass sheet is a side facing the silicon substrate during bonding, and the depth of the second recessed portion is greater than the height of the conductive portion;

[0070] Using bonding technology, bonding the bonding portion of the glass sheet to the first surface of the silicon substrate to obtain a bonding sheet; and

[0071] The front surface of the glass sheet is thinned to expose the conductive portion, thereby forming the sealing cover.

[0072] According to an exemplary embodiment of the present disclosure, forming an encapsulation portion on the first surface of the silicon substrate includes:

[0073] Using vacuum technology, covering the front surface of the bonding wafer with a packaging material to form a packaging material layer, wherein the front surface of the bonding wafer is a surface of the bonding wafer away from the second surface of the silicon substrate; and

[0074] The bonding sheet and the packaging material layer are thinned to a target thickness by using a grinding technique, while exposing the conductive portion and the sealing cover.

[0075] According to an exemplary embodiment of the present disclosure, the preparation method further includes:

[0076] A second protection layer is formed on the first surface of the silicon substrate by using chemical vapor deposition technology, wherein the second protection layer covers the surface of the contact plug facing away from the doped lead.

[0077] According to an exemplary embodiment of the present disclosure, forming a sealing cover on the first surface of the silicon substrate includes:

[0078] Provide silicon wafers;

[0079] Using photolithography and deep silicon etching technology, a groove of a specified shape is etched on the reverse side of the silicon wafer to form a bonding portion surrounding the groove on the reverse side of the silicon wafer, wherein the reverse side of the silicon wafer is the side facing the silicon substrate during bonding;

[0080] Using bonding technology, bonding the bonding portion of the silicon wafer and the first surface of the silicon substrate to obtain a bonding wafer;

[0081] Thinning the front side of the silicon wafer to a certain thickness; and

[0082] The silicon wafer is etched using photolithography technology and deep silicon etching technology, until the second protection layer and the bonding portion intersect to form the sealing cover.

[0083] According to an exemplary embodiment of the present disclosure, forming a packaging portion on the first surface of the silicon substrate includes:

[0084] removing the second protective layer;

[0085] Using vacuum technology, covering the front surface of the bonding wafer with a packaging material to form a packaging material layer, wherein the front surface of the bonding wafer is a surface of the bonding wafer away from the second surface of the silicon substrate; and

[0086] Using a grinding technique, the bonding wafer and the packaging material layer are thinned to a target thickness, exposing the front side of the silicon wafer to form a packaging portion;

[0087] Forming a conductive portion on the first surface of the silicon substrate includes:

[0088] forming a via hole in the packaging portion by using photolithography and etching techniques;

[0089] forming a second seed layer on the sidewalls and bottom of the via hole of the packaging part by using a physical vapor deposition technique;

[0090] Filling the via holes of the packaging portion with conductive material using electroplating technology; and

[0091] The excess conductive material is removed by using a chemical mechanical polishing technique to form a conductive portion filling the via hole of the packaging portion.

[0092] According to an exemplary embodiment of the present disclosure, the preparation method further includes:

[0093] A first transition layer is formed on the first surface of the silicon substrate using physical vapor deposition technology. The first transition layer is electrically connected to the contact plug, and the orthographic projection of the first transition layer on the silicon substrate at least partially overlaps with the orthographic projection of the contact plug on the silicon substrate.

[0094] According to an exemplary embodiment of the present disclosure, forming a sealing cover and a conductive portion on the first surface of the silicon substrate includes:

[0095] Provide silicon wafers;

[0096] Using photolithography and deep silicon etching technology, a first recess and a silicon pillar are formed on the reverse side of the silicon wafer to form a bonding portion surrounding the first recess on the reverse side of the silicon wafer, wherein the reverse side of the silicon wafer is the side facing the silicon substrate during bonding;

[0097] Aligning and bonding the bonding portion and silicon pillar of the silicon wafer to the first surface of the silicon substrate to obtain a bonding wafer, wherein the bonding portion is aligned and bonded to a region of the silicon substrate between the varistor and the contact plug, and the silicon pillar is aligned and bonded to the first transition layer; and

[0098] The front side of the silicon wafer is thinned to expose the surface of the silicon pillar away from the silicon substrate, so as to form the sealing cover and the conductive portion.

[0099] According to an exemplary embodiment of the present disclosure, forming a packaging portion on the first surface of the silicon substrate includes:

[0100] Using vacuum technology, covering the front surface of the bonding wafer with a packaging material to form a packaging material layer, wherein the front surface of the bonding wafer is a surface of the bonding wafer away from the second surface of the silicon substrate; and

[0101] The bonding sheet and the packaging material layer are thinned to a target thickness by using a grinding technique, exposing the front surfaces of the silicon pillar and the sealing cover to form a packaging portion.

[0102] According to an exemplary embodiment of the present disclosure, the preparation method further includes:

[0103] A second transition layer is formed on the surface of the silicon pillar away from the silicon substrate by using physical vapor deposition technology and electroplating technology.

[0104] According to an exemplary embodiment of the present disclosure, the packaging portion includes a second sub-packaging portion, and forming the sealing cover and the second sub-packaging portion on the first surface of the silicon substrate includes:

[0105] Provide glass sheets;

[0106] Using laser modification and HF etching technology, a first recessed portion and a second recessed portion are formed on the reverse side of the glass sheet, where the reverse side of the glass sheet is the side facing the silicon substrate during bonding;

[0107] Performing a two-side thinning process on the glass sheet to form a glass sheet comprising a first recessed portion, a bonding portion, and a through hole, wherein the bonding portion surrounds the first recessed portion;

[0108] The glass sheet including the first recessed portion, the bonding portion and the through hole is aligned and bonded to the first surface of the silicon substrate, wherein the bonding portion is aligned and bonded to the area of ​​the silicon substrate between the varistor and the contact plug, and the through hole exposes the contact plug to form the sealing cover and the second sub-packaging portion.

[0109] According to an exemplary embodiment of the present disclosure, the packaging portion further includes a first sub-packaging portion, and forming the first sub-packaging portion on the first surface of the silicon substrate includes:

[0110] Injecting the encapsulation material into the through holes of the glass sheet using vacuum technology and hole filling technology; and

[0111] forming a via hole in the packaging material by using an etching technique to form a first sub-packaging portion;

[0112] Forming a conductive portion on the first surface of the silicon substrate includes:

[0113] forming a second seed layer on the sidewalls and bottom of the via hole of the first sub-package part by using a physical vapor deposition technique;

[0114] Filling the via holes of the first sub-package with conductive material using electroplating technology; and

[0115] The excess conductive material is removed by using a chemical mechanical polishing technique to form a conductive portion filling the via hole of the first sub-package portion.

[0116] According to an exemplary embodiment of the present disclosure, forming a conductive portion on the first surface of the silicon substrate includes:

[0117] A conductive portion is formed on the sidewalls of the through-hole of the glass sheet including the first recess, the bonding portion, and the through-hole, and on the surface of the glass sheet including the first recess, the bonding portion, and the through-hole, using physical vapor deposition and electroplating techniques. The conductive portion includes a first portion and a second portion. The first portion covers the sidewalls of the through-hole of both the sealing cover and the second sub-package portion close to the glass sheet, and the first portion covers at least a portion of a surface of the contact plug facing away from the doped lead. The second portion extends from the first portion and covers at least a portion of a surface of the sealing cover facing away from the silicon substrate. The through-hole of the glass sheet includes a third via hole not filled by the first portion.

[0118] The packaging portion further includes a first sub-packaging portion, and forming the first sub-packaging portion on the first surface of the silicon substrate includes:

[0119] Injecting packaging material into the third via hole using vacuum technology and hole filling technology; and

[0120] The packaging material in the area outside the third via hole is removed by using an etching technology to form the first sub-packaging portion.

[0121] According to an exemplary embodiment of the present disclosure, forming a sealing cover and an encapsulation portion on a first surface of the silicon substrate includes:

[0122] Provide glass sheets;

[0123] Using laser modification and HF etching technology, a first recessed portion and a second recessed portion are formed on the reverse side of the glass sheet, where the reverse side of the glass sheet is the side facing the silicon substrate during bonding;

[0124] Performing a two-side thinning process on the glass sheet to form a glass sheet comprising a first recessed portion, a bonding portion, and a through hole, wherein the bonding portion surrounds the first recessed portion;

[0125] The glass sheet including the first recessed portion, the bonding portion and the through hole is aligned and bonded to the first surface of the silicon substrate to obtain a bonding sheet, wherein the bonding portion is aligned and bonded to the area of ​​the silicon substrate between the varistor and the contact plug, and the through hole exposes the contact plug to form the sealing cover and the packaging layer.

[0126] According to an exemplary embodiment of the present disclosure, forming the conductive portion on the first surface of the silicon substrate includes: injecting a conductive paste into the through hole of the glass sheet, and heating and curing the paste to form the conductive portion.

[0127] According to an exemplary embodiment of the present disclosure, the preparation method further includes:

[0128] forming a metal transition portion on a side of the conductive portion facing away from the silicon substrate, the metal transition portion being electrically connected to the conductive portion; and

[0129] A contact terminal is formed on a side of the metal transition portion facing away from the silicon substrate, and the contact terminal is electrically connected to the metal transition portion.

[0130] In yet another aspect, an air conditioning device is provided, comprising the pressure sensor as described in any one of the above items.

[0131] In yet another aspect, a vehicle is provided, comprising the air conditioning device as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0132] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0133] FIG1 is a schematic diagram of an equivalent circuit of a pressure sensor according to an exemplary embodiment of the present disclosure;

[0134] FIG2 is a schematic diagram of a pressure sensor according to an exemplary embodiment of the present disclosure;

[0135] FIG3 is a schematic diagram of a pressure sensor according to an exemplary embodiment of the present disclosure;

[0136] FIG4 is a schematic diagram of a pressure sensor according to an exemplary embodiment of the present disclosure;

[0137] FIG5A is a schematic diagram of a pressure sensor according to an exemplary embodiment of the present disclosure, FIG5B is a schematic diagram of pressure sensors according to other exemplary embodiments of the present disclosure, and FIG5C is a schematic diagram of pressure sensors according to other exemplary embodiments of the present disclosure;

[0138] FIG6A is a partially enlarged schematic diagram of the S1 region in FIG2 according to some embodiments of the present disclosure, FIG6B is a partially enlarged schematic diagram of the S1 region in FIG2 according to other embodiments of the present disclosure, and FIG6C is a partially enlarged schematic diagram of the S2 region in FIG2 according to some embodiments of the present disclosure; FIG7 is a flow chart of a method for manufacturing a pressure sensor according to an exemplary embodiment of the present disclosure;

[0139] 8A-8M are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor;

[0140] 9A-9O are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor;

[0141] 10A-10L are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor;

[0142] 11A-11J are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor;

[0143] 12A-12J are schematic diagrams of the structures of some membrane layers during the preparation process of the pressure sensor; and

[0144] 13A-13J are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor.

[0145] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0146] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0147] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0148] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. The terms "include," "comprising," and similar words mean that the element or object preceding the word encompasses the elements or objects listed after the word, and their equivalents, without excluding other elements or objects.

[0149] In this document, unless otherwise specifically stated, directional terms such as "upper", "lower", "left", "right", "inside", "outside", etc. are used to indicate the orientation or positional relationship based on the drawings, and are only for the convenience of describing the present disclosure, and are not intended to indicate or imply that the device, element or component referred to must have a specific orientation, be constructed or operate in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationship they represent may also change accordingly. Therefore, these directional terms cannot be understood as limiting the present disclosure. When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0150] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0151] It should be noted that, in this article, the term "same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are made of the same material and are formed through the same composition process. These specific patterns may also be at different heights or have different thicknesses.

[0152] In this document, unless otherwise specified, the expression "electrically connected" may mean that two components or elements are directly electrically connected, for example, component or element A is in direct contact with component or element B, and electrical signals can be transmitted between the two components; it may also mean that two components or elements are electrically connected through a conductive medium such as a conductive wire, for example, component or element A is electrically connected to component or element B through a conductive wire to transmit electrical signals between the two components or elements; it may also mean that two components or elements are electrically connected through at least one electronic component, for example, component or element A is electrically connected to component or element B through at least one thin-film transistor to transmit electrical signals between the two components or elements.

[0153] Those skilled in the art should understand that, herein, unless otherwise specified, the expression “height” or “thickness” refers to the dimension along the surface of each film layer disposed perpendicular to the substrate.

[0154] The following is a brief explanation of some technical terms in this disclosure.

[0155] MEMS (Micro-Electro-Mechanical systems): micro-electromechanical systems;

[0156] TGV (Through Glass Vias): through glass via;

[0157] TSV (Through Silicon Vias): through silicon via;

[0158] RDL (Re-distributed layer): redistribution layer;

[0159] CTE (Coefficient of Thermal Expansion): coefficient of thermal expansion;

[0160] CMP (Chemical Mechanical Polishing): Chemical Mechanical Polishing;

[0161] ICP (Inductively Couple Plasma): Inductively coupled plasma;

[0162] DRIE (Deep Reactive Ion Etching): deep silicon etching;

[0163] PVD (Physical Vapor Deposition): physical vapor deposition.

[0164] MEMS pressure sensors utilize the principle of piezoresistive effect and adopt integrated process technology to dope and diffuse along specific crystal directions on single-crystal silicon wafers to create strain resistors, forming a Wheatstone bridge. By utilizing the elastic mechanical properties of silicon materials, anisotropic micromachining is performed on the same silicon material to create a diffused silicon sensor that integrates force sensitivity and force-to-electricity conversion detection.

[0165] FIG. 1 is a schematic diagram of an equivalent circuit of a pressure sensor according to an exemplary embodiment of the present disclosure.

[0166] MEMS pressure sensors typically have four piezoresistors fabricated on the silicon diaphragm. As shown in Figure 1, R1, R2, R3, and R4 are four piezoresistors of equal resistance (R1 = R2 = R3 = R4), forming a Wheatstone bridge on the silicon diaphragm. When no external force is applied, the bridge is balanced, and the output voltage U0 is zero. When the diaphragm is subjected to external pressure, the bridge becomes unbalanced. For example, the changes in R1, R2, R3, and R4, ΔR1, ΔR2, ΔR3, and ΔR4, can be different. For example, if the resistances R1 and R4 increase by ΔR, while the resistances R2 and R3 decrease by ΔR, then ΔR1 = ΔR4 = +ΔR, and ΔR2 = ΔR3 = -ΔR. Alternatively, if the resistances R1 and R4 decrease by ΔR, while the resistances R2 and R3 increase by ΔR, then ΔR1 = ΔR4 = -ΔR, and ΔR2 = ΔR3 = +ΔR.

[0167] By adding an excitation power supply U to the bridge, an output voltage U0 that is proportional to the measured pressure can be obtained, thereby achieving the purpose of measuring pressure.

[0168] FIG. 2 is a schematic diagram of a pressure sensor according to an exemplary embodiment of the present disclosure.

[0169] The embodiment of the present disclosure provides a pressure sensor 1000. As shown in FIG2 , the pressure sensor 1000 includes a silicon substrate 100, a plurality of doped wires 120, a plurality of piezoresistors 130, a plurality of contact plugs 140, and a sealing cover 200.

[0170] The silicon substrate 100 includes a first surface 101 and a second surface 102 opposite to each other, wherein a cavity 150 is formed on the second surface 102. A plurality of first grooves 180 are formed on the first surface.

[0171] A plurality of doped wires 120 are disposed in the silicon substrate 100 near the first surface 101. The doped wires 120 include a third surface 121 near the first surface 101. At least a portion of the third surface 121 is exposed to the first groove 180. For example, the plurality of doped wires 120 can be formed by ion implantation in a portion of the silicon substrate.

[0172] Multiple varistors 130 are formed on the first surface of silicon substrate 100 and are located within silicon substrate 100. The varistors 130 are electrically connected to the doped leads 120. The varistors 130 correspond to the cavities 150. For example, the varistors 130 can be formed by ion implantation in a portion of the silicon substrate.

[0173] For example, the orthographic projection of the varistor 130 on the silicon substrate 100 at least partially overlaps with the orthographic projection of the doped lead 120 on the silicon substrate 100. This design increases the contact area between the varistor and the doped lead, making the connection between the varistor and the doped lead more stable and improving the electrical connection, thereby improving the stability of the pressure sensor.

[0174] In some embodiments, the varistor 130 and the doped lead 120 may also be connected in a termination manner. For example, one end of the varistor 130 close to the doped lead is connected to the other end of the doped lead 120 close to the varistor in a termination manner.

[0175] It should be noted that the expression "the orthographic projection of the varistor on the silicon substrate at least partially overlaps with the orthographic projection of the doped lead on the silicon substrate" here includes at least the following situations: (1) the overlapping portion of the orthographic projection of the varistor on the silicon substrate and the orthographic projection of the doped lead on the silicon substrate is a region with a certain area, that is, the varistor and the doped lead are in surface contact; (2) the overlapping portion of the orthographic projection of the varistor on the silicon substrate and the orthographic projection of the doped lead on the silicon substrate is a point or a line, that is, the varistor and the doped lead are in endpoint contact or sidewall contact.

[0176] A plurality of contact plugs 140 are formed on the first surface of the silicon substrate 100, and the plurality of contact plugs 140 are respectively located in the plurality of first recesses 180. The plurality of contact plugs 140 are electrically connected to the plurality of doped leads 120. For example, the plurality of contact plugs 140 can be formed by filling the plurality of first recesses 180 with a conductive material using electroplating technology, such as copper electroplating to form the plurality of contact plugs 140.

[0177] The sealing cover 200 is fastened to the silicon substrate 100 to form a sealed cavity 300 between the sealing cover 200 and the silicon substrate 100. The plurality of piezoresistors 130 are located in the sealed cavity 300. That is, the surfaces 131 of the piezoresistors 130 facing the sealing cover 200 are exposed to the sealed cavity 300.

[0178] Through such a design, the sensitivity of the piezoresistor 130 to the pressure change in the sealed cavity 300 can be improved, and the pressure change on the pressure sensor can be detected more accurately.

[0179] At least a portion of the sealing cover 200 is connected to a region of the first surface 101 between the varistor 130 and the contact plug 140. For example, the sealing cover 200 includes a bonding portion 201, through which the sealing cover 200 is bonded to the silicon substrate 100. The orthographic projection of the bonding portion 201 on the silicon substrate 100 is located between the orthographic projections of the varistor 130 and the contact plug 140 on the silicon substrate 100.

[0180] In the first direction Z, the distance between the third surface 121 of the doped lead 120 and the first surface 101 of the silicon substrate 100 is d1, and d1 is greater than 0. The distance between the surface 131 of the varistor 130 facing the sealing cover and the first surface 101 of the silicon substrate 100 is approximately 0. In other words, the surface 131 of the varistor 130 facing the sealing cover and the first surface 101 of the silicon substrate 100 can form a common surface. The first direction Z is parallel to the direction from the silicon substrate 100 toward the sealing cover 200.

[0181] Exemplarily, the distance between the third surface 121 of the doped lead 120 and the first surface 101 of the silicon substrate 100 is greater than the distance between the surface 131 of the varistor 130 facing the sealing cover and the first surface 101 of the silicon substrate 100 .

[0182] In the embodiments of the present disclosure, the bonding area can be reduced by designing the bonding portion 201 of the sealing cover 200 as an annular bonding ring. By controlling the shape and position of the bonding ring, the area of ​​the silicon substrate 100 bonded to the bonding ring can be adjusted. For example, the bonding ring can be bonded to the silicon material in the silicon substrate, avoiding bonding of the bonding ring to the varistor 130 or the contact plug 140, which is beneficial for improving the bonding yield and enhancing the airtightness.

[0183] The sealed cavity 300 formed between the sealing cover 200 and the silicon substrate 100 of the MEMS pressure sensor is required to be airtight. The sealed cavity 300 is achieved by bonding the sealing cover 200 to the silicon substrate 100. When metal traces or metal pads are higher than the surface of the silicon substrate 100, for example, after bonding, the electrical signal of the varistor 130 in the sealed cavity 300 needs to be led out by metal traces, and the bonding area covers the metal traces. Direct bonding of the metal traces to the silicon / glass sealing cover 200 can result in incomplete bonding or even gaps, causing poor bonding, which in turn leads to poor airtightness in the sealed cavity 300, ultimately affecting the accuracy of the measurement results.

[0184] Multiple varistors 130 are connected via multiple doped wires 120 to form a Wheatstone bridge. The doped wires 120 can be extended through contact plugs 140 to connect to external circuits. The doped wires 120 connecting the varistors 130 and the contact plugs 140 are located within the silicon substrate 100, i.e., they are not directly exposed from the surface of the silicon substrate 100. Because the varistors 130 are located within the area covered by the sealing cover 200 on the silicon substrate 100, and the contact plugs 140 are located outside the area covered by the sealing cover 200 on the silicon substrate 100, the varistors 130 and contact plugs 140 are electrically connected via the doped wires 120. Therefore, the orthographic projections of the sealing cover 200 and the doped wires 120 on the silicon substrate 100 intersect. In the embodiment of the present disclosure, multiple doped leads 120 are located in the silicon substrate 100, that is, the doped leads 120 are not directly exposed from the surface of the silicon substrate 100, which can avoid bonding between the bonding portion 201 and the doped leads 120, and is beneficial to improving the bonding yield between the sealing cover 200 and the silicon substrate 100, thereby improving the airtightness of the sealed cavity 300 and improving the accuracy of the measurement results.

[0185] As shown in Figure 2, a cavity 150 is formed on the side of the silicon substrate 100 facing away from the sealing cover 200. The positions of the multiple piezoresistors 130 correspond to the positions of the cavities 150. When the silicon substrate 100 is subjected to external pressure, the resistance of the piezoresistors 130 changes, causing the bridge to lose balance. By applying an excitation power supply to the bridge, an output voltage proportional to the measured pressure is generated, thereby achieving the purpose of pressure measurement.

[0186] For example, the orthographic projection of the piezoresistor 130 on the silicon substrate 100 falls within the orthographic projection of the cavity 150 on the silicon substrate 100. For example, the piezoresistor 130 may be located between the sealed cavity 300 and the cavity 150, with the orthographic projection of the piezoresistor 130 on the silicon substrate 100 falling within the overlapping region of the orthographic projections of the sealed cavity 300 and the cavity 150 on the silicon substrate 100. With this design, the piezoresistor 130 can more sensitively sense pressure changes in the sealed cavity 300, thereby improving the sensitivity of the pressure sensor.

[0187] Exemplarily, the orthographic projection of the sealing cap 200 on the silicon substrate 100 does not overlap with the orthographic projection of the contact plug 140 on the silicon substrate 100 .

[0188] For example, the material of the sealing cover 200 includes silicon or glass, and the material of the contact plug 140 includes a metal conductive material. The bonding effect between silicon or glass and metal materials is worse than the bonding effect of silicon / silicon bonding and silicon / glass bonding. By arranging the contact plug 140 in the first groove 180 and being located on the periphery of the sealing cover 200, direct contact between the bonding portion 201 and the contact plug 140 can be avoided, thereby reducing the influence of the metal wiring on the bonding process, which is conducive to improving the bonding yield between the sealing cover 200 and the silicon substrate 100, thereby improving the airtightness of the closed cavity 300 and improving the accuracy of the measurement results.

[0189] For example, in the embodiment of the present disclosure, the surface 131 of the varistor 130 facing away from the doped lead, the surface 141 of the contact plug 140 facing away from the doped lead, and the first surface 101 form a planarized surface. For example, the varistor 130, the contact plug 140, and the first surface 101 can be planarized, such as by polishing using a CMP process, to form a planarized surface, thereby eliminating protruding metal traces on the bonding surface of the silicon substrate 100 (i.e., the first surface 101).

[0190] Through such a design, the bonding surface of the silicon substrate 100 has a flat surface, which is beneficial to improving the bonding effect between the sealing cover 200 and the silicon substrate 100, improving the airtightness of the sealed cavity 300, and improving the accuracy of the measurement results.

[0191] For example, four varistors 130 may be formed on the silicon substrate 100, and the four varistors 130 may be connected together through a doped lead 120 located in the silicon substrate 100; alternatively, the portion of the lead connecting the four varistors 130 that overlaps with the bonding area of ​​the sealing cover 200 may use the doped lead 120 located in the silicon substrate 100, and the portion that does not overlap with the bonding area of ​​the sealing cover 200 may use a conductive lead located on the silicon substrate 100.

[0192] For example, the doped leads 120 may be formed in the silicon substrate 100 by ion implantation technology, and the depth of the doped leads 120 is sufficient to not affect the bonding of the sealing cover 200 to the surface of the silicon substrate 100 . This is not limited in the embodiments of the present disclosure.

[0193] For example, the orthographic projection of the contact plug 140 on the silicon substrate 100 at least partially overlaps with the orthographic projection of the doped lead 120 on the silicon substrate 100. For example, the orthographic projection of the contact plug 140 on the silicon substrate 100 falls within the orthographic projection of the doped lead 120 on the silicon substrate 100. This design increases the contact area between the contact plug 140 and the doped lead 120, improving the electrical connection between the contact plug 140 and the doped lead 120. It also reduces the space occupied by the contact plug 140, facilitating the preparation of the packaging portion and the conductive portion in subsequent processes.

[0194] For example, pressure sensor 1000 may further include: an encapsulation portion 420 and a conductive portion 410. Conductive portion 410 is located on the side of contact plug 140 facing away from silicon substrate 100. Encapsulation portion 420 surrounds multiple sidewalls of conductive portion 410. For example, referring again to FIG. 2 , encapsulation portion 420 is located on silicon substrate 100 and contact plug 140 and is positioned outside sealing cover 200. Conductive portion 410 is located in via 429 of encapsulation portion 420, with one end connected to contact plug 140 and the other end exposed through via 429 of encapsulation portion 420.

[0195] The packaging part 420 is arranged around the sealing cover 200 and replaces a part of the original sealing cover structure. When the conductive part 410 is arranged, a via 429 can be formed in the packaging part 420 to avoid forming a via on the sealing cover 200.

[0196] For example, the sealing cover 200 and the packaging part 420 are integrally formed using the same cover material (such as silicon or glass), and then a via is formed on the cover material, and a conductive part 410 is formed in the via. When the sealing cover 200 is made of glass, the efficiency of deep glass groove processing is low. Traditional glass processing of deep grooves uses ICP etching (Inductively Coupled Plasma, inductively coupled plasma etching), but the etching rate of glass material is slow, less than 1μm / min, which is very inefficient, and the etching process continues to heat up, and excessively high temperature can easily damage the glass; when the sealing cover 200 is a silicon wafer, when the via 429 is formed on the silicon wafer, because the depth of deep silicon etching is uncontrollable and the thickness inside the silicon wafer fluctuates, deep silicon etching must use over-etching, which can easily cause damage to the silicon substrate and metal traces. The silicon substrate is easily etched without a protective layer. Furthermore, TGVs (through glass vias) / TSVs (through silicon vias) and silicon substrates 100 are prone to delamination and cracking. The CTE (coefficient of thermal expansion) of TGV / TSV metal differs significantly from that of materials such as silicon wafers, glass sheets, and PI (polyimide). MEMS device manufacturing involves multiple thermal processes, such as PI adhesive curing and Cu pillar reflow. During these processes, materials expand and contract as they heat up and cool down. This difference in CTE leads to different thermal stresses and expansion / contraction, causing tension or compression between materials, leading to delamination and cracking. Thermal issues between TGV / TSV metal and silicon wafers and glass sheets are particularly severe.

[0197] In an embodiment of the present disclosure, a packaging portion 420 is formed on the periphery of the sealing cover 200, and a conductive portion 410 connected to the contact plug 140 is formed in the via hole of the packaging portion 420. The material of the conductive portion 410 is different from the material of the sealing cover 200, and the material of at least a portion of the packaging portion 420 is different from the material of the sealing cover 200 and the material of the conductive portion 410. For example, the material of the sealing cover 200 includes glass or silicon, the material of the conductive portion 410 includes copper, and the material of at least a portion of the packaging portion 420 includes a molding material. In some exemplary embodiments, the molding material may include a mixture. For example, the molding material may include a mixture formed by epoxy resin, silicon filler, phenolic resin, and solvent.

[0198] Through such a design, a plastic encapsulation material is used to replace part of the silicon or glass sealing cover 200, that is, TMV (molded through hole) replaces TSV / TGV, which can reduce the difficulty of the electroplating filling process, improve the thermal stress problems caused by CTE mismatch, such as material cracks and warping, and improve the yield and reliability of the pressure sensor. In particular, when the conductive part expands due to heat, the material properties of the plastic encapsulation material give it a certain elasticity. In addition, when preparing the plastic encapsulation material, the components of the plastic encapsulation material can be adjusted so that the CTE of the plastic encapsulation material is close to the CTE of the conductive part. As a result, the thermal expansion of the conductive part is absorbed by the plastic encapsulation material, which avoids the occurrence of cracks in the plastic encapsulation material and improves the production yield of the pressure sensor.

[0199] 2 , the pressure sensor 1000 may further include a metal transition portion 430 and a contact terminal 440. The metal transition portion 430 is located on a side of the conductive portion 410 facing away from the silicon substrate 100 and is electrically connected to the conductive portion 410. The contact terminal 440 is located on a side of the metal transition portion 430 facing away from the silicon substrate 100 and is electrically connected to the metal transition portion 430.

[0200] For example, a groove can be formed at the end of the conductive part 410 by a process such as corrosion, and then a metal transition part 430 is formed on the groove of the conductive part 410 by a deposition process. The metal transition part 430 is formed conformally on the end of the conductive part 410, that is, a groove is also formed on the surface of the metal transition part 430.

[0201] For example, the metal transition portion may include a nickel-palladium-gold protective layer. For example, a seed layer may be formed using PVD (Physical Vapor Deposition) technology; patterning may be achieved using photolithography to form photoresist grooves; the seed layer may be thickened using electroplating; the adhesive may be removed and cleaned using a degumming solution; excess seed layer may be removed using etching technology; and a nickel-palladium-gold protective layer may be formed on the copper layer using chemical plating technology.

[0202] For example, the contact terminal 440 may be formed on the metal transfer portion 430 by applying flux, placing solder balls, reflowing, cleaning, etc. The contact terminal 440 may be a solder ball.

[0203] In the embodiment of the present disclosure, the material and / or structure of the conductive portion 410 and the packaging portion 420 may be further optimized to improve the adaptability of the pressure sensor while ensuring the performance of the pressure sensor.

[0204] FIG. 3 is a schematic diagram of a pressure sensor according to an exemplary embodiment of the present disclosure.

[0205] For example, in an embodiment of the present disclosure, a pressure sensor 1000 may include a silicon substrate 100, a plurality of doped leads 120, a plurality of piezoresistors 130, a plurality of contact plugs 140, a sealing cover 200, a conductive portion 410, and an encapsulation portion 420. The silicon substrate 100, the plurality of doped leads 120, the plurality of piezoresistors 130, the plurality of contact plugs 140, and the sealing cover 200 may have the same structure as that of the embodiment shown in FIG. 2 , and thus will not be described in detail herein.

[0206] Unlike the embodiment shown in FIG. 2 , the encapsulation portion 420 in the embodiment shown in FIG. 3 is not formed of a single material. For example, referring to FIG. 3 , the encapsulation portion 420 may include a first sub-encapsulation portion 421 and a second sub-encapsulation portion 422. The first sub-encapsulation portion 421 is located outside the sealing cover 200, and the second sub-encapsulation portion 422 is located outside the first sub-encapsulation portion 422.

[0207] Exemplarily, the material of the second sub-packaging portion 422 is the same as the material of the sealing cover 200. For example, the material of both the second sub-packaging portion 422 and the sealing cover 200 is glass.

[0208] Exemplarily, the material of the first sub-package portion 421 includes a molding material. The conductive portion 410 is in direct contact with the first sub-package portion 421 .

[0209] Exemplarily, the first sub-package portion 421 includes a first via hole VH1 , and the conductive portion 410 fills the first via hole VH1 .

[0210] The use of plastic encapsulation material to replace part of the glass sealing cover 200, that is, TMV (molded through hole) to replace TGV (glass through hole), can reduce the difficulty of the electroplating filling process, improve the thermal stress problem caused by CTE mismatch, such as material cracks, warping, etc., and improve the yield of the pressure sensor. In particular, when the conductive part expands due to heat, the material properties of the plastic encapsulation material give it a certain elasticity. And when preparing the plastic encapsulation material, the composition of the plastic encapsulation material can be adjusted so that the CTE of the plastic encapsulation material is close to the CTE of the conductive part. As a result, the thermal expansion of the conductive part is absorbed by the plastic encapsulation material, which avoids the plastic encapsulation material from breaking and improves the preparation yield of the pressure sensor. At the same time, the periphery of the plastic encapsulation material is wrapped by the second sub-encapsulation part of the glass material, which can improve the mechanical properties of the pressure sensor, such as the surface scratch resistance, which is conducive to improving the reliability of the pressure sensor.

[0211] FIG. 4 is a schematic diagram of a pressure sensor according to an exemplary embodiment of the present disclosure.

[0212] For example, in an embodiment of the present disclosure, a pressure sensor 1000 may include a silicon substrate 100, a plurality of doped leads 120, a plurality of piezoresistors 130, a plurality of contact plugs 140, a sealing cover 200, a conductive portion 410, and an encapsulation portion 420. The silicon substrate 100, the plurality of doped leads 120, the plurality of piezoresistors 130, the plurality of contact plugs 140, and the sealing cover 200 may have the same structure as that of the embodiment shown in FIG. 3 , and thus will not be described in detail herein.

[0213] 3 , the conductive portion 410 in the embodiment shown in FIG4 is not designed as a columnar structure, but as an RDL pattern. The shape of the packaging portion is also different.

[0214] For example, referring to FIG4 , a second via VH2 is formed between the sealing cover 200 and the second sub-package portion 422. The conductive portion 410 includes a first portion 411 and a second portion 412. The first portion 411 is electrically connected to the contact plug 140. The first portion 411 is located in the second via VH2, covers the sidewalls of both the sealing cover 200 and the second sub-package portion 422 near the second via VH2, and covers at least a portion of the surface 141 of the contact plug 140 that faces away from the doped lead. The second portion 412 extends from the first portion 411 and covers at least a portion of the surface 2001 of the sealing cover 200 that faces away from the silicon substrate. The first portion 411 and the second portion 412 are used to transmit the input and output electrical signals of the Wheatstone bridge.

[0215] The second via hole VH2 includes a third via hole VH3 that is not filled by the first portion 411 , and the first sub-package portion 421 fills the third via hole VH3 .

[0216] Filling the third via VH3 with plastic encapsulation material protects the first portion 411 in the second via VH2 from external environmental influences. For example, moisture in the external environment could corrode the first portion 411, potentially adversely affecting the input and output of electrical signals. This improves the long-term stability of the sensor. Furthermore, the RDL pattern design of the conductive portion 410 allows for flexible adjustment of the lead position of the conductive portion 410, enabling more flexible design matching with external circuits.

[0217] In the embodiments of the present disclosure, the conductive portion can be made of other conductive materials besides metallic conductive materials. For example, the conductive portion can be made of the same material as the sealing cover, thereby reducing thermal stress issues caused by CTE mismatch, such as material cracking and warping, and improving the yield of the pressure sensor.

[0218] 5A is a schematic diagram of a pressure sensor according to an exemplary embodiment of the present disclosure, FIG. 5B is a schematic diagram of pressure sensors according to other exemplary embodiments of the present disclosure, and FIG. 5C is a schematic diagram of pressure sensors according to other exemplary embodiments of the present disclosure.

[0219] For example, in an embodiment of the present disclosure, a pressure sensor 1000 may include a silicon substrate 100, a plurality of doped leads 120, a plurality of piezoresistors 130, a plurality of contact plugs 140, a sealing cover 200, a conductive portion 410, and an encapsulation portion 420. The silicon substrate 100, the plurality of doped leads 120, the plurality of piezoresistors 130, the plurality of contact plugs 140, and the sealing cover 200 may have the same structure as that of the embodiment shown in FIG. 2 , and thus will not be described in detail herein.

[0220] Different from the embodiment shown in FIG. 2 , the conductive portion 410 and the sealing cover 200 in the embodiment shown in FIG. 5A are formed of the same material.

[0221] For example, referring to FIG5A , the conductive portion 410 is located on a side of the contact plug 140 away from the silicon substrate 100, and the encapsulation portion 420 surrounds multiple sidewalls of the conductive portion 410 and multiple sidewalls of the sealing cover 200. The sealing cover 200 is made of silicon, the conductive portion 410 is made of conductive silicon, and the encapsulation portion 420 is made of a molding compound. For example, the conductive portion 410 may be doped with a high concentration of silicon to form conductive silicon.

[0222] Using plastic encapsulation material to replace part of the silicon sealing cover 200—that is, TMVs (Through Silicon Vias) instead of TSVs (Through Silicon Vias)—and using the same material for the sealing cover 200 and the conductive portion 410, can mitigate thermal stress issues caused by CTE mismatch, such as material cracking and warping, thereby improving the yield of the pressure sensor. The sealing cover 200 and the conductive portion 410 can be integrally molded, simplifying the process and reducing costs.

[0223] In some embodiments, a transition layer may be provided between the contact plug 140 and the conductive portion 410 to improve the bonding effect between the contact plug 140 and the conductive portion 410. Alternatively, a transition layer may be provided between the conductive portion 410 and the metal transition portion 430 to improve the ohmic contact characteristics between the conductive portion 410 and the metal transition portion 430.

[0224] For example, referring to FIG. 5B , the pressure sensor may further include a first transition layer 170 positioned between the contact plug 140 and the conductive portion 410. The orthographic projection of the first transition layer 170 on the silicon substrate 100 at least partially overlaps with the orthographic projection of the contact plug 140 on the silicon substrate 100. For example, the material of the first transition layer 170 may include gold, the material of the contact plug 140 may include copper, and the material of the conductive portion 410 may include conductive silicon. The bonding effect between gold and silicon materials is better than that between copper and silicon materials. This design can improve the bonding effect between the contact plug 140 and the conductive portion 410, thereby enhancing the stability of the pressure sensor.

[0225] For example, referring again to FIG. 5B , the pressure sensor may further include a second transition layer 190 positioned between the conductive portion 410 and the metal transition portion 430. The orthographic projection of the second transition layer 190 on the silicon substrate 100 at least partially overlaps with the orthographic projection of the conductive portion 410 on the silicon substrate 100. For example, the material of the second transition layer 190 may include copper, the material of the conductive portion 410 may include conductive silicon, and the material of the metal transition portion 430 may include a nickel-palladium-gold alloy or a metal stack. This design improves the ohmic contact characteristics between the conductive portion 410 and the metal transition portion 430.

[0226] For example, in an embodiment of the present disclosure, referring to FIG. 5C , a pressure sensor 1000 may include a silicon substrate 100, a plurality of doped leads 120, a plurality of piezoresistors 130, a plurality of contact plugs 140, a sealing cover 200, a conductive portion 410, and an encapsulation portion 420. The silicon substrate 100, the plurality of doped leads 120, the plurality of piezoresistors 130, the plurality of contact plugs 140, and the sealing cover 200 may have the same structure as that of the embodiment shown in FIG. 2 , and thus will not be described in detail herein.

[0227] Different from the embodiment shown in FIG. 2 , the conductive portion 410 and the packaging portion 420 in the embodiment shown in FIG. 5C are made of different materials and have different structures.

[0228] 5C , the conductive portion 410 is located on a side of the contact plug 140 away from the silicon substrate 100, the encapsulation portion 420 surrounds multiple sidewalls of the conductive portion 410, and the conductive portion 410 contacts multiple sidewalls of the sealing cover 200. The conductive portion 410 may directly contact the sealing cover 200. The encapsulation portion 420 does not contact the sealing cover 200.

[0229] Exemplarily, the material of the sealing cover 200 includes glass, the material of the conductive part 410 includes glass conductive paste, and the material of the packaging part 420 includes glass. That is, the sealing cover 200 and the packaging part 420 can be made of glass material, and the conductive part 410 can be made of glass conductive paste. In the related art, the conductive part 410 can be made of metal material. Due to the large difference in CTE between the metal and the glass sheet, when the pressure sensor chip is heated or cooled after heating, squeezing or pulling occurs between the metal and the glass sheet. Furthermore, the metal may break the silicon wafer or glass sheet, or delamination may occur between the metal and the glass sheet, resulting in quality problems in the pressure sensor chip. In this embodiment, the CTE of the glass conductive paste is close to that of the glass, which can improve thermal stress problems caused by CTE mismatch, such as material cracks, warping, etc., and improve the yield of the pressure sensor.

[0230] Figure 6A is a partially enlarged schematic diagram of the S1 area in Figure 2 according to some embodiments of the present disclosure, Figure 6B is a partially enlarged schematic diagram of the S1 area in Figure 2 according to other embodiments of the present disclosure, and Figure 6C is a partially enlarged schematic diagram of the S2 area in Figure 2 according to some embodiments of the present disclosure.

[0231] By way of example, referring to FIG6A , the conductive portion 410 may include a second seed layer 4101 and a main body 4102. The second seed layer 4101 is located on a side of the conductive portion 410 near the contact plug 140. The material of the second seed layer 4101 includes titanium, copper, or a metal alloy. The material of the main body 4102 includes copper. The provision of the second seed layer can enhance the ohmic contact between the conductive portion 410 and the contact plug 140, thereby improving the performance of the pressure sensor.

[0232] In some embodiments, the second seed layer 4101 may cover at least a portion of the surface of the contact plug 140 close to the conductive portion.

[0233] In other embodiments, the second seed layer 4101 may also cover at least a portion of the sidewall of the via hole of the encapsulation layer.

[0234] 2 and 6B , the package portion 420 may include a plurality of vias 429, and the conductive portion 410 may be located in the vias 429 of the package portion. The conductive portion 410 may include a second seed layer 4101 and a main body portion 4102. The second seed layer 4101 may cover at least a portion of the sidewalls and bottom of at least one via 429 of the package portion.

[0235] Through such a design, the ohmic contact characteristics between the conductive part 410 and the contact plug 140 can be improved, and the film quality of the conductive part 410 can be improved, so that the conductive part 410 can better fill the via hole of the packaging part 420, which is beneficial to improving the stability of the device.

[0236] For example, referring to FIG6C , the contact plug 140 may include a first seed layer 1401 and a contact plug body 1402. The first seed layer 1401 is located on a side of the contact plug 140 that is adjacent to the doped lead 120. The material of the first seed layer 1401 includes titanium, copper, or a metal alloy. This design improves the ohmic contact characteristics between the contact plug 140 and the doped lead 120, thereby improving device performance.

[0237] FIG. 7 is a flowchart of a method for preparing a pressure sensor according to an exemplary embodiment of the present disclosure.

[0238] An embodiment of the present disclosure further provides a method for preparing a pressure sensor. As shown in FIG7 , the method for preparing the pressure sensor may include the following steps S100 - S600 .

[0239] Step S100: providing a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface opposite to each other.

[0240] Step S200: forming a plurality of doped leads in the silicon substrate close to the first surface and spaced apart.

[0241] Exemplarily, the doped lead includes a third surface close to the first surface, and a distance between the first surface and the third surface is greater than zero.

[0242] Step S300: forming a plurality of varistors on a first surface of a silicon substrate, wherein the plurality of varistors are connected to a plurality of doped wires, wherein the orthographic projections of the varistors on the silicon substrate at least partially overlap with the orthographic projections of the doped wires on the silicon substrate.

[0243] Step S400: A plurality of first grooves are formed on the first surface of the silicon substrate, the first grooves exposing at least a portion of the third surface of the doped leads. A plurality of contact plugs are formed in the first grooves, the plurality of contact plugs being connected to the plurality of doped leads, wherein the surfaces of the varistor facing away from the doped leads, the surfaces of the contact plugs facing away from the doped leads, and the first surface form a planarized surface.

[0244] Step S500: Form a sealing cover on the first surface of the silicon substrate. The sealing cover is fastened to the substrate to form a sealed cavity between the substrate and the plurality of varistors. The plurality of varistors are located in the sealed cavity, and at least a portion of the sealing cover is bonded to an area on the first surface between the varistors and the contact plugs. For example, the sealing cover includes a bonding portion, the sealing cover is bonded to the silicon substrate via the bonding portion, and the orthographic projection of the bonding portion on the silicon substrate is located between the orthographic projections of the varistors and the contact plugs on the silicon substrate.

[0245] Step S600: forming a cavity on the second surface of the silicon substrate, wherein the position of the cavity corresponds to the position of the varistor.

[0246] The embodiment of the present disclosure provides a method for preparing a pressure sensor, wherein a plurality of piezoresistors are connected through a plurality of doped leads to form a Wheatstone bridge, and the doped leads can be led out through contact plugs to connect to an external circuit. The doped leads connecting the piezoresistors and the contact plugs are formed in the silicon substrate, that is, they are not directly exposed from the surface of the silicon substrate. Since the piezoresistors are located in the area covered by the sealing cover on the silicon substrate, and the contact plugs are located outside the area covered by the sealing cover on the silicon substrate, the orthographic projections of the sealing cover and the doped leads on the silicon substrate inevitably have an intersecting portion. Since the doped leads are located in the silicon substrate and are not directly exposed from the surface of the silicon substrate, there are no raised metal traces on the bonding surface, which can avoid the sealing cover being located on the metal traces. In other words, the materials in the silicon substrate that are bonded to the sealing cover can all be silicon materials. Through such a design, a good bonding effect can be achieved between the sealing cover and the silicon substrate, avoiding the influence of the metal traces on the bonding yield, improving the airtightness of the sealed cavity, and improving the accuracy of the measurement results.

[0247] Illustratively, the method for preparing the pressure sensor provided in an embodiment of the present disclosure also includes: forming a packaging part and a conductive part on the first surface of the silicon substrate, wherein the packaging part is located on the silicon substrate and the contact plug, and is located on the periphery of the sealing cover; at least a portion of the conductive part is located in the via of the packaging part and is electrically connected to the contact plug, and the via of the packaging part exposes at least a portion of the conductive part to facilitate electrical connection between the conductive part and other conductive components (such as a metal transition part).

[0248] For example, at least a portion of the encapsulation portion can be formed by laminating a plastic encapsulation material. Using plastic encapsulation material to replace a portion of a silicon or glass sealing cover, that is, replacing TSVs / TGVs with TMVs, can reduce the difficulty of the electroplating filling process, improve thermal stress issues caused by CTE mismatch, such as material cracking and warping, and improve the yield of the pressure sensor.

[0249] 8A-8M are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor.

[0250] Illustratively, in an embodiment of the present disclosure, with reference to FIG. 8A to FIG. 8M , a detailed description of each step in the method for preparing a pressure sensor is described below.

[0251] In step S100 , a silicon substrate 100 is provided. The silicon substrate 100 includes a first surface 101 and a second surface 102 opposite to each other.

[0252] Specifically, as shown in FIG8A , a silicon wafer is provided, and the silicon wafer is ultrasonically cleaned using acetone + isopropyl alcohol (IPA) organic matter, and then RCA standard cleaning (wet chemical cleaning method) is performed. After cleaning, the silicon wafer is oven-baked to ensure that the silicon wafer is clean and dry, thereby forming a silicon substrate 100 .

[0253] First alignment marks 110 are formed on silicon substrate 100. For example, patterning is accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. DRIE (deep silicon etch) technology is then used to etch silicon substrate 100 to obtain grooves of a predetermined shape, serving as first alignment marks 110. Finally, a desizing solution is used to remove and clean the substrate.

[0254] In step S200 , a plurality of doped leads are formed in the silicon substrate close to the first surface and spaced apart.

[0255] Specifically, as shown in FIG8B , a patterned photoresist layer is formed on the bonding surface (i.e., the first surface 101) of the silicon substrate 100 using photolithography technology. The steps include photoresist coating, pre-baking, exposure, and development. The patterned photoresist layer exposes the area on the silicon substrate 100 where the doped leads 120 are to be formed. Then, ion implantation technology is used to complete the doping of the silicon substrate 100 to form a plurality of doped leads 120 in the silicon substrate 100. After the doped leads 120 are formed, the photoresist can be removed by debonding with a debonding solution, and then annealing can be performed.

[0256] The area where the doped lead 120 needs to be formed can be preset in advance, that is, the pattern formed on the photoresist layer can be preset.

[0257] Exemplarily, the pressure sensor fabrication method further includes forming a first protective layer on the first surface 101 of the silicon substrate 100 using a high-temperature oxidation technique before forming the plurality of doped leads 120. For example, a silicon oxide layer approximately 50 nm thick can be formed on the surface of the silicon wafer to serve as a protective layer for subsequent ion implantation. Providing silicon oxide as the first protective layer reduces the probability of dopant ions being implanted into other areas, thereby improving the doping effect and enhancing the conductivity of the doped leads 120.

[0258] In step S300, a plurality of varistors are formed on a first surface of a silicon substrate, and the plurality of varistors are connected to a plurality of doped wires, wherein the orthographic projections of the varistors on the silicon substrate at least partially overlap with the orthographic projections of the doped wires on the silicon substrate.

[0259] Specifically, as shown in FIG8C , a patterned photoresist layer is formed on the bonding surface (i.e., the first surface 101) of the silicon substrate 100 using photolithography technology, and the steps include photoresist coating, pre-baking, exposure, and development; the patterned photoresist layer exposes the area on the silicon substrate 100 where the varistor 130 needs to be formed, and then the ion implantation technology is used to complete the doping of the silicon substrate 100 to form a plurality of varistors 130 in the silicon substrate 100; after the varistor 130 is formed, the photoresist can be removed by degumming with a degumming solution, and then annealing treatment is performed.

[0260] For example, integrated process technology can be used to dope and diffuse along a specific crystal direction on a single-crystal silicon substrate 100 to produce strain resistors to form a Wheatstone bridge. By utilizing the elastic mechanical properties of silicon materials, anisotropic micromachining can be performed on the same silicon material to produce a diffused silicon sensor that integrates force sensitivity and force-to-electricity conversion detection.

[0261] The area where the varistor 130 needs to be formed can be preset in advance, that is, the pattern formed on the photoresist layer can be preset.

[0262] Exemplarily, the method for manufacturing the pressure sensor further includes: removing the first protective layer after forming the plurality of piezoresistors and before forming the plurality of first grooves. For example, a wet etching process may be used to remove a thin layer of silicon oxide on the surface of the silicon substrate.

[0263] In step S400, a plurality of contact plugs are formed on the first surface of the silicon substrate, and the plurality of contact plugs are connected to the plurality of doped leads. For example, a plurality of first grooves are formed on the first surface of the silicon substrate, the first grooves exposing at least a portion of the third surface of the doped leads; and a plurality of contact plugs are formed in the first grooves, wherein the plurality of contact plugs are electrically connected to the plurality of doped leads, respectively.

[0264] Exemplarily, forming the plurality of contact plugs in the first recess includes: forming a first seed layer in the first recess using physical vapor deposition; filling the first recess with a contact plug material layer using electroplating; removing excess contact plug material layer using chemical mechanical polishing; and annealing to form the plurality of contact plugs. The surfaces of the varistor facing away from the doped leads, the surfaces of the contact plugs facing away from the doped leads, and the first surface form a planarized surface.

[0265] Specifically, as shown in FIG8D , a photoresist material layer is formed on the first surface 101 of the silicon substrate 100 and patterned using photolithography to form a patterned photoresist layer. Dry etching or wet etching is used to remove silicon above the doped layer in the silicon substrate 100, forming a plurality of first recesses 180. A degumming solution is then used to remove and clean the photoresist layer. A deposition process, such as PVD, is then used to form a first seed layer of Ti or Cu. The first recesses 180 are then filled with a contact plug material layer using electroplating, such as copper electroplating. Excess contact plug material is then removed using a chemical mechanical polishing (CMP) process to form a plurality of contact plugs 140 corresponding to the plurality of doped leads 120. Finally, an annealing process is performed to ensure stable ohmic contact between the contact plugs 140 and the doped leads 120.

[0266] By chemical mechanical polishing, the surface 131 of the varistor away from the doped lead, the surface 141 of the contact plug away from the doped lead, and the first surface 101 can be flattened, which is beneficial to improving the airtightness of the closed cavity formed by subsequent bonding and improving the accuracy of the measurement results.

[0267] As shown in FIG. 8E , after the contact plug 140 is formed, a conductive portion 410 is formed on the contact plug 140 .

[0268] Illustratively, forming a conductive portion on the first surface of the silicon substrate includes: forming a second seed layer on the first surface of the silicon substrate using physical vapor deposition technology; forming a photoresist deep hole above the contact plug using photolithography technology; filling the photoresist deep hole with conductive material using electroplating technology; removing the photoresist; and removing excess second seed layer using wet etching technology to form the conductive portion.

[0269] For example, the second seed layer may include a Cu metal layer or a Ti / Cu metal stack. Electroplating techniques are used to fill the photoresist deep holes with a conductive material, including electroplating copper to fill the photoresist deep holes. The photoresist is then removed using a degumming solution. Wet etching techniques are used to remove the thinner second seed layer outside the conductive pillars, forming isolated conductive portions 410. Conductive portions 410 may be copper pillars.

[0270] In step S500, a sealing cover is formed on the first surface of the silicon substrate. The sealing cover is buckled on the substrate to form a closed cavity between the substrate. A plurality of varistors are located in the closed cavity, and at least a portion of the sealing cover is connected to the area of ​​the first surface between the varistor and the contact plug.

[0271] Exemplarily, forming a sealing cover on the first surface of a silicon substrate includes: providing a glass sheet; modifying a designated area of ​​the glass sheet using laser induction; etching the glass sheet using an HF solution to form a first recess and a second recess on the back surface of the glass sheet, thereby forming a bonding portion surrounding the first recess on the back surface of the glass sheet, wherein the back surface of the glass sheet is the side facing the silicon substrate during bonding, and the depth of the second recess is greater than the height of the conductive portion; bonding the bonding portion of the glass sheet to the first surface of the silicon substrate using a bonding technique to obtain a bonding sheet; and thinning the front surface of the glass sheet to expose the conductive portion to form the sealing cover. For example, referring to FIG8H , the depth h2 of the second recess is greater than the height h1 of the conductive portion 410, ensuring that the conductive portion 410 does not adversely affect the bonding process during bonding.

[0272] For example, the sealing cover 200 may be a glass cover. As shown in FIG8F , a glass substrate is provided. As shown in FIG8G , shallow grooves and deep grooves are formed on the glass substrate to form a first recessed portion 231 and a second recessed portion 232 , thereby forming a glass substrate including a sealing portion 221 and a clamping portion 222 .

[0273] The formation of the first recessed portion 231 and the second recessed portion 232 forms a bonding portion 201 on the glass cover. The bonding portion 201 can be annular and surround the first recessed portion 231. The bonding ring in the glass cover participates in the bonding process, which can reduce the bonding area and thus the bonding pressure, preventing damage to the silicon substrate 100 caused by excessive pressure, while also improving the bonding yield and enhancing airtightness.

[0274] For example, a laser-induced glass substrate can be used to modify a predetermined region of the glass substrate. Subsequently, the glass substrate is etched with an etching solution to form a first recessed portion 231 in the center region of the glass substrate and a second recessed portion 232 in the edge region. The portion of the glass substrate forming the first recessed portion 231 is the sealing portion 221, and the portion forming the second recessed portion 232 is the clamping portion 222. The etching solution can be, for example, an acidic solution such as hydrofluoric acid (HF) or an alkaline solution such as sodium hydroxide (NaOH).

[0275] By using laser induction and wet etching to process glass blind grooves, two depth blind grooves can be etched at the same time. The processing process is short and the efficiency is high, which is conducive to shortening the processing time and reducing production costs.

[0276] As shown in Figure 8H, the sealing cover 200 is then buckled onto the silicon substrate 100 so that the sealing cover 200 and the silicon substrate 100 are bonded together, forming a closed cavity 300 between the sealing portion 221 of the sealing cover 200 and the silicon substrate 100, and the clamping portion 222 is located on the side of the sealing portion 221 facing away from the silicon substrate 100.

[0277] A second positioning mark 210 may also be formed on the sealing cover 200. The first positioning mark 110 and the second positioning mark 210 form a buckling position between the sealing cover 200 and the silicon substrate 100, that is, a position during bonding.

[0278] When forming the second alignment mark 210 on the sealing cover 200, the glass substrate is ultrasonically cleaned using acetone and isopropyl alcohol, using RCA standard cleaning. After cleaning, the glass substrate is oven-baked to ensure it is clean and dry. Patterning is accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. Wet etching is used to create a groove of the specified shape on the bottom of the glass substrate, serving as the second alignment mark 210. Finally, a desmearing solution is used for desmearing and cleaning.

[0279] Referring to Figures 8H and 8I , a glass thinning process may be used to thin the sealing cover 200 to a certain thickness so as to remove the clamping portion 222 .

[0280] As shown in FIG8J , a packaging material is applied to the front surface of the bonding wafer using vacuum technology to form a packaging material layer. The bonding wafer includes a silicon substrate 100 and a sealing cover 200. The front surface of the bonding wafer is the surface of the bonding wafer that is away from the second surface of the silicon substrate. For example, a plastic encapsulation material is applied to the silicon substrate 100 and the sealing cover 200. Then, a grinding and thinning technique is used to thin the bonding wafer and the packaging material layer to a target thickness, exposing the conductive portion 410 and the sealing cover 200, thereby forming the packaging portion 420.

[0281] The packaging portion 420 surrounds the sealing cover 200 and replaces part of the original structure of the sealing cover 200. When the conductive portion 410 is provided, a via hole can be formed in the packaging portion 420, thereby avoiding forming a via hole in the sealing cover 200.

[0282] When the sealing cover 200 is made of glass, the TGV / TSV is prone to delamination and cracking from the wafer. The CTE of the TGV / TSV metal differs significantly from that of materials such as silicon wafers, glass sheets, and PI. The MEMS device manufacturing process involves multiple thermal processes, such as PI glue curing and Cu Pillar reflow. During the process, the materials expand and contract as they heat up and cool down. The different CTEs of the materials lead to different thermal stresses and different amounts of expansion and contraction, which can cause pulling or squeezing, leading to delamination and cracking between materials. The thermal problems between the TGV / TSV metal and silicon wafers and glass sheets are even more serious.

[0283] In the embodiments of the present disclosure, the material of the encapsulation portion 420 is typically a plastic encapsulation material mixed with multiple materials. For example, the encapsulation portion 420 may include a mixture of epoxy resin, silicone filler, phenolic resin, and solvent. This mixture has a thermal expansion coefficient that is more compatible with metals such as copper, and has better elasticity than silicon and glass, effectively reducing metal delamination and substrate peeling after heating.

[0284] By forming a packaging portion 420 on the periphery of the sealing cover 200 and forming a conductive portion 410 connected to the contact plug 140 in the packaging portion 420, that is, using a plastic packaging material to replace the sealing cover 200 made of silicon or glass, that is, TMV replaces TGV / TSV, the difficulty of the electroplating filling process can be reduced, and the thermal stress problems caused by CTE mismatch, such as material cracks and warping, can be improved, which is conducive to improving the preparation yield of the pressure sensor.

[0285] For example, referring to FIG8K , the method for preparing the pressure sensor may further include: forming a metal transition portion 430 on the side of the conductive portion 410 facing away from the silicon substrate 100, the metal transition portion 430 being electrically connected to the conductive portion 410. For example, a nickel-palladium-gold protective layer may be formed on the surface of the conductive portion 410 using electroless plating technology (ENIG). For example, a groove may be formed at the end of the conductive portion 410 by etching or other processes, and then a metal transition portion 430 may be formed on the groove of the conductive portion 410 by a deposition process. The metal transition portion 430 is formed conformally on the end of the conductive portion 410, that is, a groove is also formed on the surface of the metal transition portion 430. For example, a seed layer may be made using PVD technology; patterning may be achieved using photolithography technology to obtain a photoresist groove; the seed layer may be thickened using electroplating technology; degumming and cleaning may be performed using a degumming solution; the surface seed layer may be removed using etching technology; and a nickel-palladium-gold protective layer may be made on the copper column using electroless plating technology as the metal transition portion 430.

[0286] For example, the metal transfer portion 430 may include an adhesive layer, a barrier layer, a wetting layer, and an anti-oxidation layer covering the conductive portion 410 .

[0287] In step S600 , a cavity is formed on the second surface of the silicon substrate 100 , and the position of the cavity corresponds to the position of the varistor 130 .

[0288] 8L , a cavity 150 is formed on the second surface of the silicon substrate 100, and the positions of the plurality of piezoresistors 130 correspond to the positions of the cavity 150. For example, patterning can be achieved using photolithography, and the silicon substrate 100 can be etched using DRIE technology to obtain a deep cavity, and then the photoresist can be removed.

[0289] When the silicon substrate 100 is subjected to external pressure, the resistance of the piezoresistor 130 changes, causing the bridge to lose balance. By adding an excitation power supply to the bridge, an output voltage proportional to the measured pressure can be obtained, thereby achieving the purpose of measuring pressure.

[0290] For example, the pressure sensor fabrication method may further include forming a contact terminal on a side of the metal transition portion facing away from the silicon substrate, the contact terminal being electrically connected to the metal transition portion. For example, referring to FIG8 , contact terminal 440 may be formed on metal transition portion 430 by applying flux, placing a solder ball, reflowing, and cleaning. Contact terminal 440 may be a solder ball.

[0291] For example, in the embodiment of the present disclosure, after the cavity 150 is formed on the second surface of the silicon substrate 100 , the metal transfer portion 430 may be formed at the end of the conductive portion 410 , which is not limited in the present disclosure.

[0292] 9A-9O are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor.

[0293] In another embodiment, the detailed description of each step in the method for preparing a pressure sensor provided by the present disclosure is as follows.

[0294] In step S100 , a silicon substrate 100 is provided. The silicon substrate 100 includes a first surface 101 and a second surface 102 opposite to each other.

[0295] Specifically, as shown in FIG9A , a silicon wafer is provided, and ultrasonic cleaning is performed on the silicon wafer using acetone + isopropyl alcohol (IPA) organic matter, and RCA standard cleaning (wet chemical cleaning method) is performed. After cleaning, the silicon wafer is baked in an oven to ensure that the silicon wafer is clean and dry, thereby forming a silicon substrate 100 .

[0296] First alignment marks 110 are formed on silicon substrate 100. For example, patterning is accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. DRIE (deep silicon etch) technology is then used to etch silicon substrate 100 to obtain grooves of a predetermined shape, serving as first alignment marks 110. Finally, a desizing solution is used to remove and clean the substrate.

[0297] In step S200 , a plurality of doped leads are formed in the silicon substrate close to the first surface and spaced apart.

[0298] Specifically, as shown in FIG9B , a patterned photoresist layer is formed on the bonding surface (i.e., the first surface 101) of the silicon substrate 100 using photolithography technology. The steps include photoresist coating, pre-baking, exposure, and development. The patterned photoresist layer exposes the area on the silicon substrate 100 where the doped leads 120 are to be formed. Then, ion implantation technology is used to complete the doping of the silicon substrate 100 to form a plurality of doped leads 120 in the silicon substrate 100. After the doped leads 120 are formed, the photoresist can be removed by debonding with a debonding solution, and then annealing can be performed.

[0299] The area where the doped lead 120 needs to be formed can be preset in advance, that is, the pattern formed on the photoresist layer can be preset.

[0300] Exemplarily, the pressure sensor fabrication method further includes forming a first protective layer on the first surface 101 of the silicon substrate 100 using a high-temperature oxidation technique before forming the plurality of doped leads 120. For example, a silicon oxide layer approximately 50 nm thick can be formed on the surface of the silicon wafer to serve as a protective layer for subsequent ion implantation. Providing silicon oxide as the first protective layer reduces the probability of dopant ions being implanted into other areas, thereby improving the doping effect and enhancing the conductivity of the doped leads 120.

[0301] In step S300, a plurality of varistors are formed on a first surface of a silicon substrate, and the plurality of varistors are connected to a plurality of doped wires, wherein the orthographic projections of the varistors on the silicon substrate at least partially overlap with the orthographic projections of the doped wires on the silicon substrate.

[0302] Specifically, as shown in FIG9C , a patterned photoresist layer is formed on the bonding surface (i.e., the first surface 101) of the silicon substrate 100 using photolithography technology, and the steps include photoresist coating, pre-baking, exposure, and development; the patterned photoresist layer exposes the area on the silicon substrate 100 where the varistor 130 needs to be formed, and then the ion implantation technology is used to complete the doping of the silicon substrate 100 to form a plurality of varistors 130 in the silicon substrate 100; after the varistor 130 is formed, the photoresist can be removed by degumming with a degumming solution, and then annealing treatment is performed.

[0303] For example, integrated process technology can be used to dope and diffuse along a specific crystal direction on a single-crystal silicon substrate 100 to produce strain resistors to form a Wheatstone bridge. By utilizing the elastic mechanical properties of silicon materials, anisotropic micromachining can be performed on the same silicon material to produce a diffused silicon sensor that integrates force sensitivity and force-to-electricity conversion detection.

[0304] The area where the varistor 130 needs to be formed can be preset in advance, that is, the pattern formed on the photoresist layer can be preset.

[0305] Exemplarily, the method for manufacturing the pressure sensor further includes: removing the first protective layer after forming the plurality of piezoresistors and before forming the plurality of first grooves. For example, a wet etching process may be used to remove a thin layer of silicon oxide on the surface of the silicon substrate.

[0306] In step S400, a plurality of contact plugs are formed on the first surface of the silicon substrate, and the plurality of contact plugs are connected to the plurality of doped leads. For example, a plurality of first grooves are formed on the first surface of the silicon substrate, the first grooves exposing at least a portion of the third surface of the doped leads; and a plurality of contact plugs are formed in the first grooves, wherein the plurality of contact plugs are electrically connected to the plurality of doped leads, respectively.

[0307] Exemplarily, forming the plurality of contact plugs in the first recess includes: forming a first seed layer in the first recess using physical vapor deposition; filling the first recess with a contact plug material layer using electroplating; removing excess contact plug material layer using chemical mechanical polishing; and annealing to form the plurality of contact plugs. The surface 131 of the varistor 130 facing away from the doped lead, the surface 141 of the contact plug 140 facing away from the doped lead, and the first surface 101 form a planarized surface.

[0308] Specifically, as shown in FIG9D , a photoresist layer is formed on the first surface of the silicon substrate 100 and patterned using photolithography to form a patterned photoresist layer. Dry or wet etching is used to remove silicon from a portion of the silicon substrate 100 above the doped leads, forming a first recess 180. A stripping solution is then used to remove and clean the photoresist layer. A deposition process, such as PVD, is then used to form a first seed layer of Ti or Cu. Electroplating is then used to fill the first recess 180 with a contact plug material layer, such as copper electroplating. Chemical mechanical polishing (CMP) is then used to remove excess contact plug material, forming a plurality of contact plugs 140 corresponding to the plurality of doped leads 120. Finally, an annealing process is performed to ensure stable ohmic contact between the contact plugs 140 and the doped leads 120.

[0309] By chemical mechanical polishing, the surface 131 of the varistor away from the doped lead, the surface 141 of the contact plug away from the doped lead, and the first surface 101 can be flattened, thereby improving the airtightness of the closed cavity 300 formed by bonding and improving the accuracy of the measurement results.

[0310] For example, referring to FIG. 9E , the pressure sensor fabrication method further includes: after forming the contact plug 140, forming a second protective layer 160 on the first surface of the silicon substrate using chemical vapor deposition technology, wherein the second protective layer 160 covers the surface 141 of the contact plug 140 facing away from the doped lead. For example, silicon oxide can be formed on the first surface of the silicon substrate using chemical vapor deposition technology, patterned using photolithography and etching techniques, and then stripped and cleaned to obtain the second protective layer 160 covering the contact plug 140. The second protective layer 160 can also cover a portion of the silicon substrate 100. The second protective layer 160 can protect the silicon substrate 100 and the contact plug 140 during subsequent processes (such as wafer dicing and etching processes), thereby preventing damage to the silicon substrate 100 and the contact plug 140.

[0311] In step S500, a sealing cover is formed on the first surface of the silicon substrate, and the sealing cover is buckled on the substrate to form a closed cavity between the substrate, a plurality of varistors are located in the closed cavity, and at least a portion of the sealing cover is connected to the area on the first surface between the varistor and the contact plug.

[0312] Exemplarily, forming a sealing cover on the first surface of a silicon substrate includes: providing a silicon wafer; etching a groove of a specified shape on the reverse side of the silicon wafer using photolithography and deep silicon etching techniques to form a bonding portion surrounding the groove on the reverse side of the silicon wafer, wherein the reverse side of the silicon wafer faces the silicon substrate during bonding; bonding the bonding portion of the silicon wafer to the first surface of the silicon substrate using bonding techniques to obtain a bonding wafer; thinning the front side of the silicon wafer to a certain thickness; and etching the silicon wafer using photolithography and deep silicon etching techniques to the intersection of the second protective layer and the bonding portion to form the sealing cover. The bonding wafer includes a silicon substrate and a sealing cover.

[0313] Specifically, as shown in FIG9F , a silicon wafer is provided and ultrasonically cleaned using acetone and isopropyl alcohol, followed by RCA standard cleaning. After cleaning, the wafer is oven-baked to ensure it is clean and dry. A second alignment mark 210 can be formed on the wafer. For example, patterning can be accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. Using DRIE technology, the wafer is etched to obtain a groove of a specified shape, serving as the second alignment mark 210. Finally, a debonding solution is used for debonding and cleaning.

[0314] As shown in FIG9G , a bonding portion 201 connected to the silicon substrate 100 is formed on one side of the silicon wafer. For example, patterning can be accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. DRIE technology is then used to etch the silicon wafer into grooves of a specified shape, which are then removed and cleaned using a debonding solution.

[0315] As shown in Figure 9H, the silicon wafer is buckled on the silicon substrate 100, and the bonding part 201 is connected to the silicon substrate 100, so that the sealing cover 200 and the silicon substrate 100 are bonded together, and a closed cavity 300 is formed between the sealing part 221 of the sealing cover 200 and the silicon substrate 100, and the clamping part 222 is located on the side of the sealing part 221 away from the silicon substrate 100.

[0316] The sealing cover 200 has a second positioning mark 210 , and the first positioning mark 110 and the second positioning mark 210 form a buckling positioning between the sealing cover 200 and the silicon substrate 100 , that is, a positioning during bonding.

[0317] 9H and 9I , a thinning process may be used to thin the silicon wafer to a certain thickness.

[0318] As shown in FIG9J , patterning can be completed by photolithography technology, and the steps include photoresist coating, pre-baking, exposure, and development; using DRIE technology, the silicon wafer is etched to remove the portion of the silicon wafer near the periphery of the bonding portion 201, namely the clamping portion 222, and finally a debonding solution is used for debonding and cleaning.

[0319] Exemplarily, as shown in FIG9K , forming a packaging portion on the first surface of the silicon substrate includes: removing the second protective layer 160, for example, by using a wet etching process to remove the second protective layer 160 on the bonding surface of the silicon wafer. Using vacuum technology, the packaging material is covered on the front of the bonding wafer, for example, the plastic packaging material is covered on the silicon substrate 100 and the sealing cover 200 to form a packaging material layer. The bonding wafer includes the silicon substrate 100 and the sealing cover 200. The front of the bonding wafer is the surface of the bonding wafer away from the second surface of the silicon substrate. Using grinding technology, the bonding wafer and the packaging material layer are thinned to the target thickness to expose the front of the silicon wafer to form the packaging portion 420.

[0320] After forming the encapsulation portion 420, the conductive portion 410 can then be formed on the first surface of the silicon substrate. Forming the conductive portion may include forming a via hole in the encapsulation portion using photolithography and etching techniques; forming a second seed layer on the sidewalls and bottom of the via hole in the encapsulation portion using physical vapor deposition techniques; filling the via hole in the encapsulation portion with a conductive material using electroplating techniques; and removing excess conductive material using chemical mechanical polishing techniques to form the conductive portion filling the via hole in the encapsulation portion.

[0321] For example, as shown in FIG9L , the packaging portion 420 is etched using photolithography and etching processes to form multiple vias 429 that expose the contact plugs 140. In each via 429, a second seed layer is formed using PVD. For example, the second seed layer may include a Ti / Cu metal stack. The second seed layer is relatively thin, which can enhance the bonding strength between the subsequent electroplated metal and the packaging portion 420 and the contact plugs 140. Electroplating technology is used to fill each via 429 of the packaging portion 420. For example, copper is electroplated to fill each via 429 of the packaging portion 420. Finally, CMP or wet etching is used to remove excess metal, forming multiple conductive portions 410 that are connected to the multiple contact plugs 140 in a one-to-one manner. The conductive portions 410 may be copper pillars.

[0322] The packaging part 420 is arranged around the sealing cover 200. The packaging part 420 replaces part of the structure of the original sealing cover 200. When the conductive part 410 is set, a via hole can be formed in the packaging part 420, thereby avoiding the formation of a via hole on the sealing cover 200, reducing the processing difficulty and improving the yield.

[0323] When the sealing cover 200 is a silicon wafer and a via is formed on the wafer, the deep silicon etching must be performed using overetching because the depth of the deep silicon etching is uncontrollable and the thickness of the silicon wafer fluctuates. However, overetching can easily damage the structural silicon wafer and metal traces, and the silicon substrate is easily etched without the second protective layer 160.

[0324] In the embodiment of the present disclosure, a packaging portion 420 is formed on the periphery of the sealing cover 200, and a conductive portion 410 connected to the contact plug 140 is formed in the packaging portion 420, that is, a plastic packaging material is used to replace the sealing cover 200 made of silicon, that is, TMV replaces TSV, which is beneficial to reducing the difficulty of the electroplating filling process, improving the thermal stress problems caused by CTE mismatch, such as material cracks, warping, etc., and improving the yield of the pressure sensor.

[0325] In step S600 , a cavity is formed on the second surface of the silicon substrate, and the position of the cavity corresponds to the position of the varistor.

[0326] Specifically, as shown in FIG9N , a cavity 150 is formed on the second surface of silicon substrate 100, and the positions of multiple piezoresistors 130 correspond to the positions of cavities 150. When silicon substrate 100 is subjected to external pressure, the resistance of piezoresistors 130 changes, causing the bridge to lose balance. By applying an excitation power supply to the bridge, an output voltage proportional to the measured pressure can be obtained, thereby achieving the purpose of pressure measurement.

[0327] As shown in FIG9M , before forming the cavity 150 on the second surface of the silicon substrate 100, a metal transition portion 430 may be formed at the end of the conductive portion 410. For example, a groove may be formed at the end of the conductive portion 410 by etching or other processes, and then the metal transition portion 430 may be formed on the groove of the conductive portion 410 by a deposition process. The metal transition portion 430 is conformally formed on the end of the conductive portion 410, that is, a groove is also formed on the surface of the metal transition portion 430. A seed layer is formed using PVD technology; patterning is achieved using photolithography technology to obtain a photoresist groove; the seed layer is thickened using electroplating technology; a degumming solution is used for degumming and cleaning; the surface seed layer is removed using etching technology; and a nickel-palladium-gold protective layer is formed on the copper pillar using chemical plating technology to serve as the metal transition portion 430.

[0328] For example, the metal transfer portion 430 may include an adhesive layer, a barrier layer, a wetting layer, and an anti-oxidation layer covering the conductive portion 410 .

[0329] As shown in FIG. 9O , contact terminals 440 may be formed on the metal transfer portion 430 through processes such as applying flux, placing solder balls, reflowing, and cleaning. The contact terminals 440 may be solder balls.

[0330] 10A-10L are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor.

[0331] In another embodiment, the detailed description of each step in the method for preparing a pressure sensor provided by the embodiment of the present disclosure is as follows.

[0332] By way of example, with reference to Figures 10A-10D , a method for fabricating a pressure sensor includes providing a silicon substrate 100, forming a first alignment mark 110 on the silicon substrate, and sequentially forming a doped lead 120, a piezoresistor 130, and a contact plug 140 on the silicon substrate 100. The process steps corresponding to Figures 10A-10D may be the same as the corresponding process steps of Figures 8A-8D in the aforementioned embodiment, and are not further described herein.

[0333] Exemplarily, the method for preparing the pressure sensor also includes: after forming the contact plug, using physical vapor deposition technology to form a first transition layer on the first surface of the silicon substrate, the first transition layer is electrically connected to the contact plug, and the orthographic projection of the first transition layer on the silicon substrate covers the orthographic projection of the contact plug on the silicon substrate.

[0334] For example, as shown in FIG10E , a first transition layer 170 can be formed on the first surface of the silicon substrate 100 using physical vapor deposition technology. For example, the first transition layer 170 includes metal Au. Patterning is performed using photolithography and etching techniques, followed by stripping and cleaning to obtain the first transition layer 170. The orthographic projection of the first transition layer 170 on the silicon substrate 100 at least partially overlaps with the orthographic projection of the contact plug 140 on the silicon substrate 100. The first transition layer 170 can be used for bonding to the conductive pillar in subsequent processes, thereby improving bonding yield.

[0335] In step S500, a sealing cover is formed on the first surface of the silicon substrate, and the sealing cover is buckled on the substrate to form a closed cavity between the substrate, a plurality of varistors are located in the closed cavity, and at least a portion of the sealing cover is connected to the area on the first surface between the varistor and the contact plug.

[0336] In some embodiments, the sealing cover and the conductive portion can be prepared in the same layer, that is, the sealing cover and the conductive portion can be formed of the same material. For example, the sealing cover includes a silicon wafer, and the conductive portion includes conductive silicon.

[0337] Exemplarily, forming a sealing cover and a conductive portion on the first surface of a silicon substrate may include: providing a silicon wafer; using photolithography and deep silicon etching techniques to form a first recess and a silicon pillar on the back surface of the silicon wafer, thereby forming a bonding portion surrounding the first recess on the back surface of the silicon wafer, wherein the back surface of the silicon wafer faces the silicon substrate during bonding; aligning and bonding the bonding portion and the silicon pillar of the silicon wafer to the first surface of the silicon substrate to obtain a bonding sheet, wherein the bonding portion is aligned and bonded to a region of the silicon substrate between the varistor and the contact plug, and the silicon pillar is aligned and bonded to the first transition layer; and thinning the front surface of the silicon wafer to expose the surface of the silicon pillar away from the silicon substrate, thereby forming the sealing cover and the conductive portion. The bonding sheet includes a silicon substrate, a sealing cover, and a silicon pillar.

[0338] For example, as shown in FIG10F , a silicon wafer is provided and ultrasonically cleaned using acetone and isopropyl alcohol, followed by RCA standard cleaning. After cleaning, the wafer is oven-baked to ensure it is clean and dry. A second alignment mark 210 can be formed on the wafer. For example, patterning can be accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. DRIE technology is then used to etch the wafer to obtain a groove of a specified shape, serving as the second alignment mark 210. Finally, a debonding solution is used for debonding and cleaning.

[0339] As shown in FIG10G , a shallow groove (e.g., the first recessed portion 231) and a silicon pillar 236 are formed on one side of the silicon wafer. For example, two photolithography + DRIE processes can be used to successively complete the shallow groove and the silicon pillar. Exemplarily, the silicon pillar region can be formed into conductive silicon using an ion implantation process. When forming the shallow groove (e.g., the first recessed portion 231) and the silicon pillar 236, a sealing portion 221, a clamping portion 222, and a bonding portion 201 can be formed on the silicon wafer. After the subsequent bonding process is completed, the silicon pillar 236 can be used as the conductive portion 410 of the pressure sensor.

[0340] As shown in Figure 10H , a silicon wafer is mounted on a silicon substrate 100, and the bonding portion 201 and silicon pillars are connected to the silicon substrate 100 via a hybrid bonding process. The sealing cover 200 is bonded to the silicon substrate 100, forming a sealed cavity 300 between the sealing portion 221 of the sealing cover 200 and the silicon substrate 100. The clamping portion 222 is located on the side of the sealing portion 221 facing away from the silicon substrate 100. The silicon pillars 236 are electrically connected to the contact plugs 140 via a first transition layer 170. Providing a first transition layer 170, for example, a thin layer of metal Au, can improve the bonding yield between the silicon pillars 236 and the contact plugs 140, thereby enhancing the reliability of the pressure sensor.

[0341] Exemplarily, the sealing cover 200 has a second positioning mark 210 , and the first positioning mark 110 and the second positioning mark 210 form a snap-fitting positioning between the sealing cover 200 and the silicon substrate 100 , that is, positioning during bonding.

[0342] As shown in FIG. 10I , a thinning process may be used to thin the silicon wafer to a certain thickness, exposing the silicon pillars 236 .

[0343] As shown in Figure 10J, forming a packaging part on the first side of the silicon substrate includes: using vacuum technology to cover the front side of the bonding sheet with packaging material to form a packaging material layer, wherein the front side of the bonding sheet is the surface of the bonding sheet away from the second side of the silicon substrate; and using grinding technology to thin the bonding sheet and the packaging material layer to a target thickness, exposing the front side of the silicon column and the sealing cover to form a packaging part 420.

[0344] For example, the packaging part 420 is arranged around the sealing cover 200, and the packaging part 420 replaces part of the structure of the original sealing cover 200, that is, the plastic packaging material is used to replace part of the silicon material of the sealing cover 200, that is, TMV replaces TSV, which can reduce the difficulty of the electroplating filling process and improve the thermal stress problems caused by CTE mismatch, such as material cracks and warping, which is conducive to improving the yield of preparing pressure sensors.

[0345] In step S600 , a cavity is formed on the second surface of the silicon substrate, and the position of the cavity corresponds to the position of the varistor.

[0346] Specifically, as shown in FIG10K , a cavity 150 is formed on the second surface of silicon substrate 100, and the positions of multiple piezoresistors 130 correspond to the positions of cavity 150. When silicon substrate 100 is subjected to external pressure, the resistance of piezoresistors 130 changes, causing the bridge to lose balance. By applying an excitation power supply to the bridge, an output voltage proportional to the measured pressure can be generated, thereby achieving the purpose of pressure measurement.

[0347] Continuing with FIG10K , before forming the cavity 150 on the second surface of the silicon substrate 100, a metal transition portion 430 may be formed at the end of the conductive portion 410. For example, a groove may be formed at the end of the conductive portion 410 by etching or other processes, and then the metal transition portion 430 may be formed on the groove of the conductive portion 410 by deposition. The metal transition portion 430 is conformally formed on the end of the conductive portion 410, i.e., a groove is also formed on the surface of the metal transition portion 430.

[0348] For example, the seed layer can be made using PVD technology; patterning can be achieved using photolithography technology to obtain photoresist grooves; the seed layer can be thickened using electroplating technology; degumming liquid can be used for degumming and cleaning; excess seed layer on the surface can be removed using corrosion technology; and a nickel-palladium-gold protective layer can be made using chemical plating technology as the metal transfer part 430.

[0349] For example, the metal transfer portion 430 may include an adhesive layer, a barrier layer, a wetting layer, and an anti-oxidation layer covering the conductive portion 410 .

[0350] Exemplarily, the pressure sensor fabrication method further includes forming a copper metal layer as a second transition layer on the surface of the silicon pillar (i.e., conductive portion 410) away from the silicon substrate, using physical vapor deposition and electroplating techniques before forming the nickel-palladium-gold protective layer. The copper metal layer enables ohmic contact between the silicon pillar and the nickel-palladium-gold protective layer, thereby improving the electrical performance of the pressure sensor.

[0351] As shown in FIG. 10L , a contact terminal 440 may be formed on the metal transfer portion 430 through processes such as applying flux, placing solder balls, reflowing, and cleaning. The contact terminal 440 may be a solder ball.

[0352] 11A-11J are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor.

[0353] In another embodiment, the detailed description of each step in the method for preparing a pressure sensor provided by an embodiment of the present disclosure is as follows.

[0354] By way of example, with reference to Figures 11A-11D , a method for fabricating a pressure sensor includes providing a silicon substrate 100, forming a first alignment mark 110 on the silicon substrate, and sequentially forming a doped lead 120, a piezoresistor 130, and a contact plug 140 on the silicon substrate 100. The process steps corresponding to Figures 11A-11D may be the same as the corresponding process steps in Figures 8A-8D in the aforementioned embodiment, and are not further described here.

[0355] In step S500, a sealing cover is formed on the first surface of the silicon substrate, and the sealing cover is buckled on the substrate to form a closed cavity between the substrate, a plurality of varistors are located in the closed cavity, and at least a portion of the sealing cover is connected to the area on the first surface between the varistor and the contact plug.

[0356] In some embodiments, the sealing cover and a portion of the packaging portion may be made of the same layer, that is, the sealing cover and a portion of the packaging portion may be formed of the same material. For example, the sealing cover and a portion of the packaging portion may both be made of glass.

[0357] Exemplarily, the packaging part includes a second sub-packaging part, and forming a sealing cover and the second sub-packaging part on the first surface of the silicon substrate includes: providing a glass sheet; using laser modification and HF etching technology to make a first recessed portion and a second recessed portion on the back surface of the glass sheet, and the back surface of the glass sheet is the side facing the silicon substrate during bonding; thinning the glass sheet on both sides to form a glass sheet including a first recessed portion, a bonding portion and a through hole, and the bonding portion surrounds the first recessed portion; aligning and bonding the glass sheet including the first recessed portion, the bonding portion and the through hole to the first surface of the silicon substrate, wherein the bonding portion is aligned and bonded to the area in the silicon substrate between the varistor and the contact plug, and the through hole exposes the contact plug to form the sealing cover and the second sub-packaging part.

[0358] For example, the sealing cover 200 may be a glass cover. As shown in FIG11E , a glass substrate is provided. As shown in FIG11F , shallow grooves and deep grooves are formed on the glass substrate to form a first recessed portion 231 and a second recessed portion 232 , thereby forming the sealing cover 200 including a sealing portion 221 and a clamping portion 222 .

[0359] The formation of the first recessed portion 231 and the second recessed portion 232 forms a bonding portion 201 on the glass cover. The bonding portion 201 can be annular and surround the first recessed portion 231. The bonding ring in the glass cover participates in the bonding process, which can reduce the bonding area and thus the bonding pressure, preventing damage to the silicon substrate 100 caused by excessive pressure, while also improving the bonding yield and enhancing airtightness.

[0360] For example, a laser-induced glass substrate can be used to modify a predetermined region of the glass substrate. Subsequently, the glass substrate is etched with an etching solution to form a first recessed portion 231 in the middle region of the glass substrate and a second recessed portion 232 near an edge region. The portion of the glass substrate where the first recessed portion 231 is formed serves as the sealing portion 221, and the portion where the second recessed portion 232 is formed serves as the clamping portion 222. The etching solution can be, for example, an acidic solution such as hydrofluoric acid (HF) or an alkaline solution such as sodium hydroxide (NaOH).

[0361] By using laser induction and wet etching to process glass blind grooves, two depth blind grooves can be etched at the same time. The processing process is short and the efficiency is high, which is conducive to shortening the processing time and reducing production costs.

[0362] As shown in FIG11G , the glass sheet is double-sided thinned and polished to form a glass sheet including a first recessed portion 231, a bonding portion 201, and a through hole VH, with the bonding portion 201 surrounding the first recessed portion 231. After the double-sided thinning process, the clamping portion 222 can also be removed to form an independent second sub-encapsulation portion 422.

[0363] As shown in FIG11H , a glass sheet including the sealing cover 200 and the second sub-package portion 422 is then placed on the silicon substrate 100, so that the sealing cover 200 and the silicon substrate 100 are bonded together, forming a sealed cavity 300 between the sealing cover 200 and the silicon substrate 100. The second sub-package portion 422 is bonded to the edge region of the silicon substrate 100, so that the through hole VH between the sealing cover 200 and the second sub-package portion 422 can expose the contact plug 140, facilitating the subsequent design of connecting the contact plug 140 to the conductive portion.

[0364] For example, a second positioning mark 210 may be further formed on the sealing cover 200 , and the first positioning mark 110 and the second positioning mark 210 are used to form a snap-fitting positioning between the sealing cover 200 and the silicon substrate 100 , that is, positioning during bonding.

[0365] When forming the second alignment mark 210 on the sealing cover 200, the glass substrate is ultrasonically cleaned using acetone and isopropyl alcohol, using RCA standard cleaning. After cleaning, the glass substrate is oven-baked to ensure it is clean and dry. Patterning is accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. Wet etching is used to create a groove of the specified shape on the bottom of the glass substrate, serving as the second alignment mark 210. Finally, a desmearing solution is used for desmearing and cleaning.

[0366] Exemplarily, the pressure sensor fabrication method may further include forming a first sub-package portion on the first surface of the silicon substrate. The first sub-package portion and the second sub-package portion may be made of different materials. For example, the first sub-package portion may be made of a molding compound, and the second sub-package portion may be made of glass. The two different materials together form the package portion.

[0367] Replacing part of the glass sealing cover 200 with a plastic encapsulation material—that is, replacing TGVs (through glass vias) with TMVs—reduces the difficulty of the electroplating filling process and mitigates thermal stress issues caused by CTE mismatch, such as material cracking and warping, thereby improving the yield of the pressure sensor. Furthermore, the plastic encapsulation material is surrounded by a second sub-encapsulation made of glass, which improves the mechanical properties of the pressure sensor, such as surface scratch resistance, and contributes to increased reliability.

[0368] Exemplarily, the packaging part may also include a first sub-packaging part, and forming the first sub-packaging part on the first surface of the silicon substrate includes: using vacuum technology and hole filling technology to inject packaging material into the through hole of the glass sheet; and using etching technology to form a via in the packaging material to form the first sub-packaging part.

[0369] For example, referring to Figures 11H and 11I, the through hole VH between the sealing cover 200 and the second sub-package part 422 can be filled with molding material through vacuum lamination and hole filling technology, and the first sub-package part 421 can be etched using photolithography and etching processes to obtain multiple vias 429 exposing the contact plugs 140.

[0370] Exemplarily, forming a conductive portion on the first surface of the silicon substrate includes: forming a second seed layer on the sidewalls and bottom of the via of the first sub-package portion using a physical vapor deposition technique; filling the via of the first sub-package portion with a conductive material using an electroplating technique; and removing excess conductive material using a chemical mechanical polishing technique to form a conductive portion filling the via of the first sub-package portion.

[0371] For example, as shown in FIG11I , photolithography and etching processes are used to etch the first sub-package 421 to form multiple vias 429 that expose the contact plugs 140. In each via 429, a second seed layer is formed using PVD. The second seed layer may include a Ti / Cu metal stack. The thin second seed layer can enhance the bonding strength between the subsequently electroplated metal and the first sub-package and the contact plugs. Electroplating technology is used to fill each via 429 in the first sub-package 421. Finally, CMP or wet etching is used to remove excess metal, forming a plurality of conductive portions 410 that are connected to the plurality of contact plugs 140 in a one-to-one manner. For example, the conductive portions 410 may be copper pillars.

[0372] The first sub-package portion 421 is disposed around the sealing cover 200. By forming the first sub-package portion 421 on the periphery of the sealing cover 200 and forming the conductive portion 410 connected to the contact plug 140 in the first sub-package portion 421, that is, using a plastic encapsulation material to replace part of the glass sealing cover 200, that is, using TMV instead of TGV, the difficulty of the electroplating filling process can be reduced, and thermal stress problems caused by CTE mismatch, such as material cracking and warping, can be improved, which is conducive to improving the yield of the pressure sensor.

[0373] In step S600 , a cavity is formed on the second surface of the silicon substrate, and the position of the cavity corresponds to the position of the varistor.

[0374] Specifically, as shown in FIG11J , a cavity 150 is formed on the second surface of the silicon substrate 100, and the positions of the plurality of piezoresistors 130 correspond to the positions of the cavities 150. When the silicon substrate 100 is subjected to external pressure, the resistance of the piezoresistors 130 changes, causing the bridge to lose balance. By applying an excitation power supply to the bridge, an output voltage proportional to the measured pressure can be obtained, thereby achieving the purpose of pressure measurement.

[0375] As shown in FIG11J , before forming the cavity 150 on the second surface of the silicon substrate 100, a metal transition portion 430 may be formed at the end of the conductive portion 410. For example, a groove may be formed at the end of the conductive portion 410 by etching or other processes, and then the metal transition portion 430 may be formed on the groove of the conductive portion 410 by a deposition process. The metal transition portion 430 is conformally formed on the end of the conductive portion 410, that is, a groove is also formed on the surface of the metal transition portion 430. A seed layer is formed using PVD technology; patterning is achieved using photolithography technology to obtain a photoresist groove; the seed layer is thickened using electroplating technology; a degumming solution is used for degumming and cleaning; the surface seed layer is removed using etching technology; and a nickel-palladium-gold protective layer is formed on the copper layer using chemical plating technology to serve as the metal transition portion 430.

[0376] For example, the metal transfer portion 430 may include an adhesive layer, a barrier layer, a wetting layer, and an anti-oxidation layer covering the conductive portion 410 .

[0377] As shown in FIG. 11J , contact terminals 440 may be formed on the metal transfer portion 430 by applying flux, placing solder balls, reflowing, cleaning, and other processes. The contact terminals 440 may be solder balls.

[0378] 12A-12J are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor.

[0379] In another embodiment, the detailed description of each step in the method for preparing a pressure sensor provided by an embodiment of the present disclosure is as follows.

[0380] By way of example, with reference to Figures 12A-12D , a method for fabricating a pressure sensor includes providing a silicon substrate 100, forming a first alignment mark 110 on the silicon substrate, and sequentially forming a doped lead 120, a piezoresistor 130, and a contact plug 140 on the silicon substrate 100. The process steps corresponding to Figures 12A-12D may be the same as the corresponding process steps of Figures 8A-8D in the aforementioned embodiment, and are not further described here.

[0381] In step S500, a sealing cover is formed on the first surface of the silicon substrate, and the sealing cover is buckled on the substrate to form a closed cavity between the substrate, a plurality of varistors are located in the closed cavity, and at least a portion of the sealing cover is connected to the area on the first surface between the varistor and the contact plug.

[0382] In some embodiments, the sealing cover and a portion of the packaging portion can be made of the same layer, that is, the sealing cover and a portion of the packaging portion can be formed of the same material. For example, the sealing cover and a portion of the packaging portion can both be made of glass.

[0383] Illustratively, forming a sealing cover and a second sub-package on the first surface of a silicon substrate includes: providing a glass sheet; using laser modification and HF etching technology to make a first recessed portion and a second recessed portion on the reverse side of the glass sheet, wherein the reverse side of the glass sheet is the side facing the silicon substrate during bonding; thinning the glass sheet on both sides to form a glass sheet comprising a first recessed portion, a bonding portion and a through hole, wherein the bonding portion surrounds the first recessed portion; aligning and bonding the glass sheet comprising the first recessed portion, the bonding portion and the through hole to the first surface of the silicon substrate, wherein the bonding portion is aligned and bonded to an area in the silicon substrate between the varistor and the contact plug, and the through hole exposes the contact plug to form a sealing cover and a second sub-package.

[0384] For example, the sealing cover 200 can be a glass cover. As shown in FIG12E , a glass substrate is provided. As shown in FIG12F , shallow grooves and deep grooves are formed on the glass substrate to form shallow grooves and deep grooves, namely, first recessed portions 231 and second recessed portions 232 , thereby forming a glass cover including a sealing portion 221 and a clamping portion 222 .

[0385] The formation of the first recessed portion 231 and the second recessed portion 232 forms a bonding portion 201 on the glass cover. The bonding portion 201 can be annular and surround the first recessed portion 231. The bonding ring in the glass cover participates in the bonding process, which can reduce the bonding area and thus the bonding pressure, preventing damage to the silicon substrate 100 caused by excessive pressure, while also improving the bonding yield and enhancing airtightness.

[0386] For example, a laser-induced glass substrate can be used to modify a predetermined region of the glass substrate. Subsequently, the glass substrate is etched with an etching solution to form a first recessed portion 231 in the middle region of the glass substrate and a second recessed portion 232 near an edge region. The portion of the glass substrate where the first recessed portion 231 is formed serves as the sealing portion 221, and the portion where the second recessed portion 232 is formed serves as the clamping portion 222. The etching solution can be, for example, an acidic solution such as hydrofluoric acid (HF) or an alkaline solution such as sodium hydroxide (NaOH).

[0387] By using laser induction and wet etching to process glass blind grooves, two depth blind grooves can be etched at the same time. The processing process is short and the efficiency is high, which is conducive to shortening the processing time and reducing production costs.

[0388] As shown in FIG12G , the glass sheet is double-sided thinned and polished to form a glass sheet including a first recessed portion 231, a bonding portion 201, and a through hole VH, with the bonding portion 201 surrounding the first recessed portion 231. After the double-sided thinning process, the clamping portion 222 can also be removed to form an independent second sub-encapsulation portion 422.

[0389] As shown in FIG12H , a glass sheet including the sealing cover 200 and the second sub-package portion 422 is then placed on the silicon substrate 100, so that the sealing cover 200 and the silicon substrate 100 are bonded together, forming a sealed cavity 300 between the sealing cover 200 and the silicon substrate 100. The second sub-package portion 422 is bonded to the edge region of the silicon substrate 100, so that the through hole VH (also referred to as the second via VH2) between the sealing cover 200 and the second sub-package portion 422 can expose the contact plug 140.

[0390] For example, a second positioning mark 210 may be further formed on the sealing cover 200 , and the first positioning mark 110 and the second positioning mark 210 are used to form a snap-fitting positioning between the sealing cover 200 and the silicon substrate 100 , that is, positioning during bonding.

[0391] When forming the second alignment mark 210 on the sealing cover 200, the glass substrate is ultrasonically cleaned using acetone and isopropyl alcohol, using RCA standard cleaning. After cleaning, the glass substrate is oven-baked to ensure it is clean and dry. Patterning is accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. Wet etching is used to create a groove of the specified shape on the bottom of the glass substrate, serving as the second alignment mark 210. Finally, a desmearing solution is used for desmearing and cleaning.

[0392] Exemplarily, the pressure sensor fabrication method may further include forming a first sub-package portion on the first surface of the silicon substrate. The first sub-package portion and the second sub-package portion may be made of different materials. For example, the first sub-package portion may be made of a molding compound, and the second sub-package portion may be made of glass. The two different materials together form the package portion.

[0393] Replacing part of the glass sealing cover 200 with a plastic encapsulation material—that is, replacing TGVs (through glass vias) with TMVs—reduces the difficulty of the electroplating filling process and mitigates thermal stress issues caused by CTE mismatch, such as material cracking and warping, thereby improving the yield of the pressure sensor. Furthermore, the plastic encapsulation material is surrounded by a second sub-encapsulation made of glass, which improves the mechanical properties of the pressure sensor, such as surface scratch resistance, and contributes to increased reliability.

[0394] Illustratively, forming a conductive portion on the first surface of the silicon substrate includes: using physical vapor deposition technology and electroplating technology to form a conductive portion on the sidewalls of the through hole of the glass sheet and the surface of the glass sheet, wherein the conductive portion includes a first part and a second part, the first part covers at least part of the sidewalls of the through hole of the glass sheet close to the sealing cover and the second sub-package part and the surface of the contact plug away from the doped lead; the second part is extended from the first part and covers at least part of the surface of the sealing cover away from the silicon substrate.

[0395] Exemplarily, the through-hole of the glass sheet includes a third via hole not filled by the first portion. Forming the first sub-encapsulation portion on the first surface of the silicon substrate includes: injecting an encapsulation material into the third via hole using a vacuum technique and a hole-filling technique; and removing the encapsulation material from an area outside the third via hole using an etching technique to form the first sub-encapsulation portion.

[0396] For example, referring to Figures 12H and 12I , a Ti / Cu seed layer is formed on the sidewalls and surface of the through hole VH between the sealing cover 200 and the second sub-package 422 using physical vapor deposition. A thick Cu metal layer is then formed on the seed layer using electroplating. The Cu metal layer is then patterned through processes such as resist coating, exposure, etching, and resist stripping to form the conductive portion 410. The conductive portion 410 includes a first portion 411 and a second portion 412. The first portion 411 covers at least a portion of the sidewalls of the through hole VH near the glass sheet in both the sealing cover 200 and the second sub-package 422, as well as the surface of the contact plug 140 facing away from the doped lead, thereby electrically connecting the first portion 411 to the contact plug 140. The second portion 412 extends from the first portion 411 and covers at least a portion of the surface of the sealing cover 200 facing away from the silicon substrate. The second portion 412 can be used to connect to an external circuit.

[0397] The conductive portion 410 adopts an RDL graphic design, so that the position of the lead end of the conductive portion 410 can be flexibly adjusted, and can be more flexibly matched with the external circuit design.

[0398] After forming the conductive portion 410, the through hole VH of the glass sheet may further include a third via hole VH3 not filled by the first portion 411. Molding material is injected into the third via hole VH3 using vacuum lamination and hole filling techniques, and the molding material in areas other than the third via hole VH3 is removed using etching techniques to form a first sub-encapsulation portion 421.

[0399] The first portion 411 of the conductive portion 410 is disposed around the first sub-encapsulation portion 421. Using a plastic encapsulation material to replace part of the glass sealing cover 200 can improve thermal stress problems caused by CTE mismatch, such as material cracks and warping, and improve the yield of the pressure sensor.

[0400] In step S600 , a cavity is formed on the second surface of the silicon substrate, and the position of the cavity corresponds to the position of the varistor.

[0401] Specifically, as shown in FIG12J , a cavity 150 is formed on the second surface of silicon substrate 100, and the positions of multiple piezoresistors 130 correspond to the positions of cavity 150. When silicon substrate 100 is subjected to external pressure, the resistance of piezoresistors 130 changes, causing the bridge to lose balance. By applying an excitation power supply to the bridge, an output voltage proportional to the measured pressure can be obtained, thereby achieving the purpose of pressure measurement.

[0402] As shown in FIG12J , before forming the cavity 150 on the second surface of the silicon substrate 100, a metal transition portion 430 may be formed at the end of the conductive portion 410. For example, a groove may be formed at the end of the conductive portion 410 by etching or other processes, and then the metal transition portion 430 may be formed on the groove of the conductive portion 410 by a deposition process. The metal transition portion 430 is conformally formed on the end of the conductive portion 410, that is, a groove is also formed on the surface of the metal transition portion 430. A seed layer is formed using PVD technology; patterning is achieved using photolithography technology to obtain a photoresist groove; the seed layer is thickened using electroplating technology; a degumming solution is used for degumming and cleaning; the surface seed layer is removed using etching technology; and a nickel-palladium-gold protective layer is formed on the copper layer using chemical plating technology to serve as the metal transition portion 430.

[0403] As shown in FIG. 12J , contact terminals 440 may be formed on the metal transfer portion 430 by applying flux, placing solder balls, reflowing, cleaning, and other processes. The contact terminals 440 may be solder balls.

[0404] In the embodiments of the present disclosure, the sealing cover, the conductive portion, and the packaging portion can also be made of the same type of material. For example, the sealing cover and the packaging portion can both be made of glass material, and the conductive portion can be made of glass conductive paste. Through such a design, thermal stress problems caused by CTE mismatch, such as material cracks and warping, can be improved, which is beneficial to improving the yield of the pressure sensor. At the same time, the periphery of the plastic encapsulation material is wrapped by the packaging portion of the glass material, which can improve the mechanical properties of the pressure sensor, such as surface scratch resistance, and is beneficial to improving the reliability of the pressure sensor.

[0405] 13A-13J are schematic structural diagrams of some membrane layers during the preparation process of the pressure sensor.

[0406] In another embodiment, a detailed description of each step in a method for preparing a pressure sensor provided by an embodiment of the present disclosure is discussed below.

[0407] By way of example, with reference to Figures 13A-13D , a method for fabricating a pressure sensor includes providing a silicon substrate 100, forming a first alignment mark 110 on the silicon substrate, and sequentially forming a doped lead 120, a piezoresistor 130, and a contact plug 140 on the silicon substrate 100. The process steps corresponding to Figures 13A-13D may be the same as the corresponding process steps in Figures 8A-8D in the aforementioned embodiment, and are not further described here.

[0408] In step S500, a sealing cover is formed on the first surface of the silicon substrate, and the sealing cover is buckled on the substrate to form a closed cavity between the substrate, a plurality of varistors are located in the closed cavity, and at least a portion of the sealing cover is connected to the area on the first surface between the varistor and the contact plug.

[0409] In some embodiments, the sealing cover and the packaging portion can be made of the same layer, that is, the sealing cover and the packaging portion can be formed of the same material. For example, the sealing cover and the packaging portion can both be made of glass.

[0410] Illustratively, forming a sealing cover and a packaging portion on the first surface of a silicon substrate includes: providing a glass sheet; using laser modification and HF etching technology to make a first recessed portion and a second recessed portion on the reverse side of the glass sheet, wherein the reverse side of the glass sheet is the side facing the silicon substrate during bonding; thinning the glass sheet on both sides to form a glass sheet comprising a first recessed portion, a bonding portion, and a through hole, wherein the bonding portion surrounds the first recessed portion; aligning and bonding the glass sheet comprising the first recessed portion, the bonding portion, and the through hole to the first surface of the silicon substrate to obtain a bonding sheet, wherein the bonding portion is aligned and bonded to an area in the silicon substrate between the varistor and the contact plug, and the through hole exposes the contact plug to form a sealing cover and a packaging layer.

[0411] For example, the sealing cover 200 can be a glass cover. As shown in FIG13E , a glass substrate is provided. As shown in FIG13F , shallow grooves and deep grooves are formed on the glass substrate to form shallow grooves and deep grooves, namely, first recessed portions 231 and second recessed portions 232 , thereby forming a glass cover including a sealing portion 221 and a clamping portion 222 .

[0412] The formation of the first recessed portion 231 and the second recessed portion 232 forms a bonding portion 201 on the glass cover. The bonding portion 201 can be annular and surround the first recessed portion 231. The bonding ring in the glass cover participates in the bonding process, which can reduce the bonding area and thus the bonding pressure, preventing damage to the silicon substrate 100 caused by excessive pressure, while also improving the bonding yield and enhancing airtightness.

[0413] For example, a laser-induced glass substrate can be used to modify a predetermined region of the glass substrate. Subsequently, the glass substrate is etched with an etching solution to form a first recessed portion 231 in the middle region of the glass substrate and a second recessed portion 232 near an edge region. The portion of the glass substrate where the first recessed portion 231 is formed serves as the sealing portion 221, and the portion where the second recessed portion 232 is formed serves as the clamping portion 222. The etching solution can be, for example, an acidic solution such as hydrofluoric acid (HF) or an alkaline solution such as sodium hydroxide (NaOH).

[0414] By using laser induction and wet etching to process glass blind grooves, two depth blind grooves can be etched at the same time. The processing process is short and the efficiency is high, which is conducive to shortening the processing time and reducing production costs.

[0415] 13F and 13G , the glass sheet is double-sided thinned and polished to form a glass sheet including a first recessed portion 231, a bonding portion 201, and a through hole VH, with the bonding portion 201 surrounding the first recessed portion 231. After the double-sided thinning process, the clamping portion 222 can be removed to form an independent packaging portion 420.

[0416] As shown in FIG13H , the glass sheet including the sealing cover 200 and the encapsulation portion 420 is then placed on the silicon substrate 100, so that the sealing cover 200 and the silicon substrate 100 are bonded together, forming a sealed cavity 300 between the sealing cover 200 and the silicon substrate 100. The encapsulation portion 420 is bonded to the edge region of the silicon substrate 100, so that the through hole VH between the sealing cover 200 and the encapsulation portion 420 can expose the contact plug 140.

[0417] For example, a second positioning mark 210 may be further formed on the sealing cover 200 , and the first positioning mark 110 and the second positioning mark 210 are used to form a snap-fitting positioning between the sealing cover 200 and the silicon substrate 100 , that is, positioning during bonding.

[0418] When forming the second alignment mark 210 on the sealing cover 200, the glass substrate is ultrasonically cleaned using acetone and isopropyl alcohol, using RCA standard cleaning. After cleaning, the glass substrate is oven-baked to ensure it is clean and dry. Patterning is accomplished using photolithography, which includes photoresist coating, pre-baking, exposure, and development. Wet etching is used to create a groove of the specified shape on the bottom of the glass substrate, serving as the second alignment mark 210. Finally, a desmearing solution is used for desmearing and cleaning.

[0419] Exemplarily, forming the conductive portion on the first surface of the silicon substrate includes: injecting a conductive paste into a through hole of a glass sheet, and heating and curing the paste to form the conductive portion.

[0420] For example, as shown in Figure 13I, a conductive paste is injected into the through hole VH between the sealing cover 200 and the packaging part 420, and heated and cured to form the conductive part 410. The conductive paste may include glass conductive paste.

[0421] This design mitigates thermal stress issues caused by CTE mismatch, such as material cracking and warping, and improves the yield of the pressure sensor. Furthermore, the glass encapsulation surrounding the plastic package enhances the mechanical properties of the pressure sensor, such as surface scratch resistance, and contributes to increased reliability.

[0422] In step S600 , a cavity is formed on the second surface of the silicon substrate, and the position of the cavity corresponds to the position of the varistor.

[0423] Specifically, as shown in FIG13I , a cavity 150 is formed on the second surface of the silicon substrate 100, and the positions of the plurality of piezoresistors 130 correspond to the positions of the cavities 150. When the silicon substrate 100 is subjected to external pressure, the resistance of the piezoresistors 130 changes, causing the bridge to lose balance. By applying an excitation power supply to the bridge, an output voltage proportional to the measured pressure is generated, thereby achieving the purpose of pressure measurement.

[0424] As shown in FIG13J , before forming cavity 150 on the second surface of silicon substrate 100, a metal transition portion 430 may be formed at the end of conductive portion 410. For example, a seed layer may be formed using PVD technology; patterning may be achieved using photolithography to form photoresist grooves; the seed layer may be thickened using electroplating; the surface of the seed layer may be removed using a debonding solution; and a nickel-palladium-gold protective layer may be formed on the copper layer using chemical plating to serve as metal transition portion 430.

[0425] For example, the metal transfer portion 430 may include an adhesive layer, a barrier layer, a wetting layer, and an anti-oxidation layer covering the conductive portion 410 .

[0426] For example, before preparing the nickel palladium gold protective layer, PVD technology, electroplating technology, photolithography technology and etching technology can be used to form a Cu metal layer on the surface of the conductive part 410 to improve the conductivity between the glass conductive paste and the nickel palladium gold protective layer.

[0427] As shown in FIG. 13J , contact terminals 440 may be formed on the metal transfer portion 430 by applying flux, placing solder balls, reflowing, cleaning, and other processes. The contact terminals 440 may be solder balls.

[0428] The method for preparing the pressure sensor provided in the embodiments of the present disclosure can be used to manufacture the pressure sensor provided in the embodiments of the present disclosure.

[0429] An embodiment of the present disclosure further provides an air conditioning device equipped with the pressure sensor provided in the above-mentioned embodiment. This air conditioning device may be, for example, a vehicle air conditioner, a household wall-mounted air conditioner, a floor-standing air conditioner, or a central air conditioner. The pressure sensor can be arranged in the refrigerant piping of the air conditioning device. By sensing the pressure in the piping, it can adjust the operating power of the compressor and evaporator, achieving temperature control and energy conservation. For more beneficial effects of the air conditioning device provided by the present disclosure, please refer to the discussion in the above-mentioned device embodiment and preparation method embodiment of the pressure sensor, which will not be repeated here.

[0430] Embodiments of the present disclosure also provide a vehicle including the aforementioned air conditioning device. Examples of the vehicle include automobiles, trucks, trains, high-speed trains, and construction vehicles. The beneficial effects of the vehicle provided by the present disclosure are discussed in the aforementioned pressure sensor device and preparation method embodiments, and are not further elaborated here.

[0431] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A pressure sensor, characterized in that: include: A silicon substrate, the silicon substrate comprising a first surface and a second surface opposite to each other, the second surface being provided with a cavity, and the first surface being provided with a plurality of first grooves; a plurality of doped leads, the plurality of doped leads being disposed in the silicon substrate, the doped leads comprising a third surface close to the first surface, at least a portion of the third surface being exposed to the first groove; a plurality of varistors, wherein the plurality of varistors are disposed in the silicon substrate and are electrically connected to the plurality of doped leads respectively; a plurality of contact plugs, each of which is disposed in each of the first grooves and electrically connected to each of the doped leads; and A sealing cover, the sealing cover is buckled on the silicon substrate and forms a closed cavity between the sealing cover and the silicon substrate, the sealing cover includes a bonding portion, and the sealing cover is bonded to the silicon substrate through the bonding portion, The orthographic projection of the bonding portion on the silicon substrate is located between the orthographic projections of the varistor and the contact plug on the silicon substrate; The surface of the varistor facing the sealing cover is exposed to the sealed cavity; A distance between the third surface and the first surface in a first direction is greater than a distance between a surface of the varistor facing the sealing cover and the first surface in the first direction, and the first direction is parallel to a direction from the silicon substrate toward the sealing cover; and The orthographic projection of the varistor on the silicon substrate at least partially overlaps with the orthographic projection of the doped lead on the silicon substrate.

2. The pressure sensor according to claim 1, wherein The surface of the varistor facing away from the doped lead, the surface of the contact plug facing away from the doped lead, and the first surface form a planarized surface.

3. The pressure sensor according to claim 1 or 2, wherein: An orthographic projection of the sealing cover on the silicon substrate does not overlap with an orthographic projection of the contact plug on the silicon substrate.

4. The pressure sensor according to claim 3, wherein: The orthographic projection of the contact plug on the silicon substrate at least partially overlaps with the orthographic projection of the doped lead on the silicon substrate; and / or, The orthographic projection of the piezoresistor on the silicon substrate falls within the orthographic projection of the cavity on the silicon substrate.

5. The pressure sensor according to any one of claims 1 to 4, wherein: The pressure sensor further includes a conductive portion, which is disposed on a side of the contact plug away from the silicon substrate. The material of the conductive portion is different from that of the sealing cover. The pressure sensor according to claim 5 , wherein: The pressure sensor further includes a packaging portion surrounding a plurality of side walls of the conductive portion, wherein a material of at least a portion of the packaging portion is different from a material of the sealing cover and a material of the conductive portion.

7. The pressure sensor according to claim 6, wherein: The packaging part includes a first sub-packaging part and a second sub-packaging part, the first sub-packaging part is arranged on the periphery of the sealing cover, and the second sub-packaging part is arranged on the periphery of the first sub-packaging part; The material of the second sub-encapsulation part is the same as the material of the sealing cover; the material of the first sub-encapsulation part includes a plastic packaging material; and The conductive portion is in direct contact with the first sub-package portion.

8. The pressure sensor according to claim 7, wherein: The first sub-package portion includes a first via hole, and the conductive portion fills the first via hole; or, A second via is formed between the sealing cover and the second sub-package part, the conductive part includes a first part and a second part, the first part is electrically connected to the contact plug, wherein the first part is arranged in the second via, the first part covers the side walls of both the sealing cover and the second sub-package part close to the second via, and the first part covers at least a part of the surface of the contact plug away from the doped lead; the second part is led out from the first part and covers at least a part of the surface of the sealing cover away from the silicon substrate; and the second via includes a third via not filled by the first part, and the first sub-package part fills the third via.

9. A method for preparing a pressure sensor, characterized in that: include: Providing a silicon substrate, the silicon substrate comprising a first side and a second side opposite to each other; forming a plurality of doped leads in the silicon substrate close to the first surface and spaced apart from each other, wherein the doped leads include a third surface close to the first surface, and a distance between the first surface and the third surface is greater than 0; forming a plurality of varistors on the first surface of the silicon substrate, the plurality of varistors being electrically connected to the plurality of doped leads respectively, and the orthographic projections of the varistors on the silicon substrate at least partially overlapping with the orthographic projections of the doped leads on the silicon substrate; forming a plurality of first grooves on the first surface of the silicon substrate, wherein the first grooves expose at least a portion of the third surface of the doped lead; forming a plurality of contact plugs in the first groove, wherein the plurality of contact plugs are electrically connected to the plurality of doped leads respectively, and a surface of the varistor facing away from the doped leads, a surface of the contact plug facing away from the doped leads, and the first surface form a planarized surface; forming a sealing cover on the first surface of the silicon substrate, wherein the sealing cover is buckled onto the silicon substrate and forms a sealed cavity between the sealing cover and the silicon substrate, the sealing cover including a bonding portion, the sealing cover being bonded to the silicon substrate via the bonding portion, and an orthographic projection of the bonding portion on the silicon substrate being located between the orthographic projections of the varistor and the contact plug on the silicon substrate; and A cavity is formed on the second surface of the silicon substrate.

10. The preparation method according to claim 9, wherein The preparation method further comprises: forming a packaging portion and a conductive portion on the first surface of the silicon substrate; The packaging part is located on the silicon substrate and the contact plug, and is located on the periphery of the sealing cover; at least a portion of the conductive part is located in the via hole of the packaging part and is electrically connected to the contact plug, and the via hole of the packaging part exposes at least a portion of the conductive part.

11. The preparation method according to claim 10, wherein Forming the conductive portion on the first surface of the silicon substrate includes: forming a second seed layer on the first surface of the silicon substrate by using a physical vapor deposition technique; Using photolithography technology, forming a photoresist deep hole above the contact plug; Filling the photoresist deep holes with conductive material using electroplating technology; removing the photoresist; and Using a wet etching technique, removing excess second seed layer to form the conductive portion; Forming a sealing cover on the first surface of the silicon substrate comprises: Provide glass sheets; Using laser induction on a glass sheet to modify a designated area of ​​the glass sheet; Etching the glass sheet using an HF solution to form a first recessed portion and a second recessed portion on a rear surface of the glass sheet, thereby forming a bonding portion surrounding the first recessed portion on the rear surface of the glass sheet, wherein the rear surface of the glass sheet is a side facing the silicon substrate during bonding, and the depth of the second recessed portion is greater than the height of the conductive portion; Using bonding technology, bonding the bonding portion of the glass sheet to the first surface of the silicon substrate to obtain a bonding sheet; and Thinning the front surface of the glass sheet to expose the conductive portion to form the sealing cover; Forming a packaging portion on the first surface of the silicon substrate includes: Using vacuum technology, covering the front surface of the bonding wafer with a packaging material to form a packaging material layer, wherein the front surface of the bonding wafer is a surface of the bonding wafer away from the second surface of the silicon substrate; and The bonding sheet and the packaging material layer are thinned to a target thickness by using a grinding technique, while exposing the conductive portion and the sealing cover.

12. The preparation method according to claim 10, wherein The preparation method further comprises: forming a second protective layer on the first surface of the silicon substrate by using a chemical vapor deposition technique, wherein the second protective layer covers a surface of the contact plug facing away from the doped lead; Forming a sealing cover on the first surface of the silicon substrate comprises: Provide silicon wafers; Using photolithography and deep silicon etching technology, a groove of a specified shape is etched on the reverse side of the silicon wafer to form a bonding portion surrounding the groove on the reverse side of the silicon wafer, wherein the reverse side of the silicon wafer is the side facing the silicon substrate during bonding; Using bonding technology, bonding the bonding portion of the silicon wafer and the first surface of the silicon substrate to obtain a bonding wafer; Thinning the front side of the silicon wafer to a certain thickness; and The silicon wafer is etched using photolithography technology and deep silicon etching technology, until the second protection layer and the bonding portion intersect to form the sealing cover.

13. The preparation method according to claim 12, wherein Forming a packaging portion on the first surface of the silicon substrate includes: removing the second protective layer; Using vacuum technology, covering the front surface of the bonding wafer with a packaging material to form a packaging material layer, wherein the front surface of the bonding wafer is a surface of the bonding wafer away from the second surface of the silicon substrate; and Using a grinding technique, the bonding wafer and the packaging material layer are thinned to a target thickness, exposing the front side of the silicon wafer to form a packaging portion; Forming a conductive portion on the first surface of the silicon substrate includes: forming a via hole in the packaging portion by using photolithography and etching techniques; forming a second seed layer on the sidewalls and bottom of the via hole of the packaging part by using a physical vapor deposition technique; Filling the via holes of the packaging portion with conductive material using electroplating technology; and The excess conductive material is removed by using a chemical mechanical polishing technique to form a conductive portion filling the via hole of the packaging portion.

14. The preparation method according to claim 10, wherein The preparation method further comprises: forming a first transition layer on the first surface of the silicon substrate using a physical vapor deposition technique, wherein the first transition layer is electrically connected to the contact plug, and an orthographic projection of the first transition layer on the silicon substrate at least partially overlaps with an orthographic projection of the contact plug on the silicon substrate; Forming a sealing cover and a conductive portion on the first surface of the silicon substrate includes: Provide silicon wafers; Using photolithography and deep silicon etching technology, a first recess and a silicon pillar are formed on the reverse side of the silicon wafer to form a bonding portion surrounding the first recess on the reverse side of the silicon wafer, wherein the reverse side of the silicon wafer is the side facing the silicon substrate during bonding; Aligning and bonding the bonding portion and silicon pillar of the silicon wafer to the first surface of the silicon substrate to obtain a bonding wafer, wherein the bonding portion is aligned and bonded to a region of the silicon substrate between the varistor and the contact plug, and the silicon pillar is aligned and bonded to the first transition layer; and The front side of the silicon wafer is thinned to expose the surface of the silicon pillar away from the silicon substrate, so as to form the sealing cover and the conductive portion.

15. The preparation method according to claim 14, wherein Forming a packaging portion on the first surface of the silicon substrate includes: Using vacuum technology, covering the front surface of the bonding wafer with a packaging material to form a packaging material layer, wherein the front surface of the bonding wafer is a surface of the bonding wafer away from the second surface of the silicon substrate; and The bonding sheet and the packaging material layer are thinned to a target thickness by using a grinding technique, exposing the front surfaces of the silicon pillar and the sealing cover to form a packaging portion.

16. The preparation method according to claim 10, wherein The packaging portion includes a second sub-packaging portion, and forming the sealing cover and the second sub-packaging portion on the first surface of the silicon substrate includes: Provide glass sheets; Using laser modification and HF etching technology, a first recessed portion and a second recessed portion are formed on the reverse side of the glass sheet, where the reverse side of the glass sheet is the side facing the silicon substrate during bonding; Performing a two-side thinning process on the glass sheet to form a glass sheet comprising a first recessed portion, a bonding portion, and a through hole, wherein the bonding portion surrounds the first recessed portion; The glass sheet including the first recessed portion, the bonding portion and the through hole is aligned and bonded to the first surface of the silicon substrate, wherein the bonding portion is aligned and bonded to the area of ​​the silicon substrate between the varistor and the contact plug, and the through hole exposes the contact plug to form the sealing cover and the second sub-packaging portion.

17. The preparation method according to claim 16, wherein The packaging portion further includes a first sub-packaging portion, and forming the first sub-packaging portion on the first surface of the silicon substrate includes: Injecting the encapsulation material into the through holes of the glass sheet using vacuum technology and hole filling technology; and forming a via hole in the packaging material by using an etching technique to form a first sub-packaging portion; Forming a conductive portion on the first surface of the silicon substrate includes: forming a second seed layer on the sidewalls and bottom of the via hole of the first sub-package part by using a physical vapor deposition technique; Filling the via holes of the first sub-package with conductive material using electroplating technology; and The excess conductive material is removed by using a chemical mechanical polishing technique to form a conductive portion filling the via hole of the first sub-package portion.

18. The preparation method according to claim 16, wherein Forming a conductive portion on the first surface of the silicon substrate includes: A conductive portion is formed on the sidewalls of the through-hole of the glass sheet including the first recess, the bonding portion, and the through-hole, and on the surface of the glass sheet including the first recess, the bonding portion, and the through-hole, using physical vapor deposition and electroplating techniques. The conductive portion includes a first portion and a second portion. The first portion covers the sidewalls of the through-hole of both the sealing cover and the second sub-package portion close to the glass sheet, and the first portion covers at least a portion of a surface of the contact plug facing away from the doped lead. The second portion extends from the first portion and covers at least a portion of a surface of the sealing cover facing away from the silicon substrate. The through-hole of the glass sheet includes a third via hole not filled by the first portion. The packaging portion further includes a first sub-packaging portion, and forming the first sub-packaging portion on the first surface of the silicon substrate includes: Injecting packaging material into the third via hole using vacuum technology and hole filling technology; and The packaging material in the area outside the third via hole is removed by using an etching technology to form the first sub-packaging portion.

19. The preparation method according to claim 10, wherein Forming a sealing cover and a packaging portion on the first surface of the silicon substrate includes: Provide glass sheets; Using laser modification and HF etching technology, a first recessed portion and a second recessed portion are formed on the reverse side of the glass sheet, where the reverse side of the glass sheet is the side facing the silicon substrate during bonding; Performing a two-side thinning process on the glass sheet to form a glass sheet comprising a first recessed portion, a bonding portion, and a through hole, wherein the bonding portion surrounds the first recessed portion; Aligning and bonding the glass sheet comprising the first recess, the bonding portion, and the through hole to the first surface of the silicon substrate to obtain a bonding sheet, wherein the bonding portion is aligned and bonded to a region of the silicon substrate between the varistor and the contact plug, and the through hole exposes the contact plug, thereby forming the sealing cover and the encapsulation layer; Forming the conductive portion on the first surface of the silicon substrate includes: injecting conductive paste into the through hole of the glass sheet, heating and curing, so as to form the conductive portion.

20. An air conditioning device, characterized in that: The pressure sensor comprises the pressure sensor according to any one of claims 1 to 8.

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