Storage chip and preparation method therefor, and electronic device

Abstract

The present application relates to the technical field of storage. Provided are a storage chip and a preparation method therefor, and an electronic device, which make the effective area of a first storage unit to be 4F2, thereby increasing the storage density of a first storage chain and increasing the number of first storage units in the first storage chain. The storage chip comprises a first storage chain, first bit line gating tubes, first board line gating tubes and a routing layer, which are stacked in sequence, wherein the routing layer comprises a first bit line and first board lines; the first storage chain comprises a plurality of first storage sub-chains connected in series, each first storage sub-chain comprising a plurality of first storage units connected in series, and the first storage sub-chains being connected in series between the first bit line gating tubes and the first board line gating tubes; the first bit line gating tubes are connected in series between the first bit line and the first storage sub-chains, and the plurality of first storage sub-chains are electrically connected to the same first bit line by means of the plurality of first bit line gating tubes; and the first board line gating tubes are connected in series between the first board lines and the first storage sub-chains, and the plurality of first board line gating tubes are electrically connected to the plurality of first board lines on a one-to-one basis.

Description

Memory chip, preparation method thereof and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410331837.8, filed on March 21, 2024, and entitled "Memory chip, preparation method thereof and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of storage, and in particular to a memory chip, a preparation method thereof and an electronic device. BACKGROUND

[0003] With the rapid development of the chip industry, the performance and storage density of the memory gradually become an important factor limiting the performance of the chip. Under the background of the demand for large capacity and large bandwidth storage today, the storage unit needs to be continuously miniaturized and stacked to achieve high-density storage.

[0004] The current chain ferroelectric random access memory (FeRAM) is a very popular new storage technology. One of the advantages of chain FeRam as a ferroelectric memory is that the area occupied by its storage unit is 4F 2 , which is 33% smaller than the area occupied by the 1T1C (one transistor and one capacitor) storage unit, so higher density can be achieved.

[0005] However, due to the existence of the bit line selection tube and / or the plate line selection tube, the area occupied by the storage unit of the traditional ferroelectric chain FeRam is not strictly 4F 2 Therefore, there is still room for improvement in the storage density of the traditional ferroelectric chain FeRam. SUMMARY

[0006] To solve the above technical problems, the present application provides a memory chip, a preparation method thereof and an electronic device, which can avoid the first bit line selection tube and the first plate line selection tube from occupying the area of the memory chip in the plane, so that the effective area of the first storage unit on the first storage chain becomes a standard 4F 2 , so as to improve the storage density of the first storage chain, and at the same time, the number of first storage units in the first storage chain can also be increased.

[0007] In a first aspect, the present application provides a memory chip, which comprises a substrate, a first memory chain arranged on the substrate, a first bit line pass transistor and a first plate line pass transistor stacked on a side of the first memory chain away from the substrate, and a wiring layer arranged on a side of the first bit line pass transistor and the first plate line pass transistor away from the substrate. The wiring layer comprises a first bit line and a plurality of first plate lines. The first memory chain comprises a plurality of first sub-memory chains connected in series, each first sub-memory chain comprising a plurality of first memory cells connected in series, and each first sub-memory chain being connected in series between the first bit line pass transistor and the first plate line pass transistor. The first bit line pass transistor is connected in series between the first bit line and the first sub-memory chain, and the plurality of first sub-memory chains are electrically connected to the same first bit line through the plurality of first bit line pass transistors. The first plate line pass transistor is connected in series between the first plate line and the first sub-memory chain, and the plurality of first plate line pass transistors are electrically connected to the plurality of first plate lines one by one.

[0008] In the present application, the first bit line pass transistor and the first plate line pass transistor are stacked with the first memory chain. In this way, the first bit line pass transistor and the first plate line pass transistor can be arranged to overlap the first memory chain, i.e., the orthographic projection of the first bit line pass transistor and the first plate line pass transistor on the X-Y plane falls within the orthographic projection range of the layer on which the first memory chain is located on the X-Y plane, thereby avoiding the first bit line pass transistor and the first plate line pass transistor occupying the area of the memory chip on the X-Y plane, and making the effective area of the first memory cells on the first memory chain become a standard 4F 2 . Thus, the storage density of the first memory chain is improved. Furthermore, even if the storage array contains more first memory chains due to the limitation of the on-state current of the transistors in the first memory cells, the plurality of first bit line pass transistors and the plurality of first plate line pass transistors electrically connected to the plurality of first memory chains can be stacked with the first memory chain in the Z direction, thereby improving the storage density of the storage array. Moreover, because all the first bit line pass transistors and all the first plate line pass transistors electrically connected to the first memory chain can be stacked with the first memory chain in the Z direction, the number of first memory cells in the first memory chain can be increased indefinitely, i.e., the length of the first memory chain can be infinite, if the size of the memory chip allows. The Z direction is the direction in which the first memory chain points to the first bit line pass transistor and the first plate line pass transistor, and the X-Y plane is perpendicular to the Z direction.

[0009] In some possible implementation manners, the first plate line pass transistor and the first bit line pass transistor can be arranged on the same layer or on different layers. When the first plate line pass transistor and the first bit line pass transistor are arranged on different layers, the first plate line pass transistor can be arranged between the substrate and the first bit line pass transistor, or the first bit line pass transistor can be arranged between the substrate and the first plate line pass transistor.

[0010] Compared with the scheme that the first plate line pass transistor and the first bit line pass transistor are arranged in different layers, the scheme that the first plate line pass transistor and the first bit line pass transistor are arranged in the same layer can realize that the first plate line pass transistor and the first bit line pass transistor are prepared by the same semiconductor process, thereby simplifying the preparation process of the storage chip. Moreover, in the case that the first plate line pass transistor and the first bit line pass transistor are arranged in the same layer, the first plate line pass transistor and the first bit line pass transistor are respectively electrically connected with the first storage chain and the trace layer.

[0011] In some possible implementation manners, the first storage chain is prepared by a front-end process, and the first bit line pass transistor, the first plate line pass transistor, and the trace layer are prepared by a back-end process. In this way, the high-temperature processing during preparation of the first bit line pass transistor, the first plate line pass transistor, and the trace layer can be avoided, and the performance of the transistor in the first storage chain can be affected.

[0012] In some possible implementation manners, the first bit line pass transistor includes a first sub-bit line pass transistor and a second sub-bit line pass transistor, the first plate line pass transistor includes a first sub-plate line pass transistor and a second sub-plate line pass transistor, and the first sub-storage chain is connected in series between the first sub-bit line pass transistor and the first sub-plate line pass transistor. The first sub-storage chain includes at least three segment storage chains connected in series, one segment storage chain is connected in series between the first sub-bit line pass transistor and the second sub-plate line pass transistor, one segment storage chain is connected in series between the first sub-plate line pass transistor and the second sub-bit line pass transistor, and the other segment storage chains are connected in series between the second sub-bit line pass transistor and the second sub-plate line pass transistor.

[0013] In this way, the first sub-storage chain or the segment storage chain can also be dynamically adjusted according to the service life of the first storage chain, so as to ensure the performance of the first storage chain within the service life.

[0014] Considering that the on-state current of the transistor is high and the performance is good at the initial stage of the service life of the first storage chain (for example, the use time of the first storage chain is less than a preset time), the selected first sub-storage chain can be relatively long, and in the read-write stage, the first sub-bit line pass transistor and the first sub-plate line pass transistor connected in series with the selected storage unit work, and the second sub-bit line pass transistor and the second sub-plate line pass transistor do not work, so that the first sub-storage chain in which the first selected storage unit is located is selected, and only the other storage units in the selected first sub-storage chain except the first selected storage unit are not read-write signals.

[0015] For example, the first sub storage chain includes five segment storage chains connected in series, and each segment storage chain includes two first storage units. If the use time of the first storage chain is less than a preset time, in the read-write stage, the first sub bit line pass gate connected with the first first storage unit of the first sub storage chain and the first sub plate line pass gate connected with the tenth first storage unit of the first sub storage chain are turned on, and other second sub bit line pass gates and second sub plate line pass gates connected with the first sub storage chain are turned off.

[0016] With the increase of use time, the performance of the transistor gradually decreases, and the on-state current decreases. For example, in the case where the use time of the first storage chain is greater than or equal to the preset time, in the read-write stage, one segment storage chain in one first sub storage chain can be selected, and other segment storage chains in the first sub storage chain are not selected.

[0017] For example, in the read-write stage, if the first / two first storage units on the first sub storage chain are the first selected storage unit, the first sub bit line pass gate and the second sub plate line pass gate connected in series with the first selected storage unit are turned on, and other second sub bit line pass gates and first sub plate line pass gates are turned off; if one of the third to eighth first storage units on the first sub storage chain is the first selected storage unit, the second sub bit line pass gate and the second sub plate line pass gate connected in series with the first selected storage unit are turned on, and other first sub bit line pass gates and first sub plate line pass gates are turned off; if the ninth / tenth first storage unit on the first sub storage chain is the first selected storage unit, the second sub bit line pass gate and the first sub plate line pass gate connected in series with the first selected storage unit are turned on, and other first sub bit line pass gates and second sub plate line pass gates are turned off.

[0018] In some possible implementation manners, the memory chip further includes a comparison circuit, and the wiring layer further includes a second bit line, and input ends of the comparison circuit are respectively connected with the second bit line and the first bit line. In the read stage, the first bit line is used to input a storage signal to the comparison circuit, and the second bit line is used to input a reference voltage to the comparison circuit; and the comparison circuit is used to determine whether the storage signal is a digital signal 0 or a digital signal 1 according to the reference voltage.

[0019] On this basis, the comparison circuit can be prepared by a post-process. On the one hand, the high-temperature processing during preparation of the comparison circuit can be avoided, and the performance of the transistor in the first storage chain is affected. On the other hand, when the comparison circuit is prepared by the post-process, the comparison circuit and the first storage chain can also be stacked in the Z direction, that is, the orthographic projection of the comparison circuit on the X-Y plane falls within the orthographic projection range of the first storage chain on the X-Y plane, so that the comparison circuit occupies the area of the memory chip on the X-Y plane.

[0020] In some possible implementation manners, the memory chip further includes a second memory chain, a second bit line pass transistor, and a second plate line pass transistor, and the wiring layer further includes a plurality of second plate lines. The second bit line pass transistor and the second plate line pass transistor are stacked on a side of the wiring layer away from the first memory chain, and the second memory chain is stacked on a side of the second bit line pass transistor and the second plate line pass transistor away from the first memory chain. In this way, the memory density can be further improved.

[0021] The second memory chain includes a plurality of second sub-memory chains connected in series, and each second sub-memory chain includes a plurality of second memory cells connected in series. The second sub-memory chain is connected in series between the second bit line pass transistor and the second plate line pass transistor. The second bit line pass transistor is connected in series between the first bit line and the second sub-memory chain, and the plurality of second sub-memory chains are electrically connected to the same first bit line through the plurality of second bit line pass transistors. The second plate line pass transistor is connected in series between the second plate line and the second sub-memory chain, and the plurality of second plate line pass transistors are electrically connected to the plurality of second plate lines one by one.

[0022] In some possible implementation manners, the memory chip further includes a third memory chain, a third bit line pass transistor, a third plate line pass transistor, a fourth memory chain, a fourth bit line pass transistor, and a fourth plate line pass transistor, and the wiring layer further includes a second bit line, a plurality of third plate lines, and a plurality of fourth plate lines. The third memory chain is arranged on the same layer as the first memory chain, and includes a plurality of third sub-memory chains connected in series, and each third sub-memory chain includes a plurality of third memory cells connected in series. The third bit line pass transistor and the third plate line pass transistor are arranged on the same layer as the first bit line pass transistor and the first plate line pass transistor, and the third sub-memory chain is connected in series between the third bit line pass transistor and the third plate line pass transistor. The fourth memory chain is arranged on the same layer as the second memory chain, and includes a plurality of fourth sub-memory chains connected in series, and each fourth sub-memory chain includes a plurality of fourth memory cells connected in series. The fourth bit line pass transistor and the fourth plate line pass transistor are arranged on the same layer as the second bit line pass transistor and the second plate line pass transistor, and the fourth sub-memory chain is connected in series between the fourth bit line pass transistor and the fourth plate line pass transistor.

[0023] The third bit line pass transistor is connected in series between the second bit line and the third sub-storage chain, and the plurality of third sub-storage chains are electrically connected to the same second bit line through the plurality of third bit line pass transistors; the third plate line pass transistor is connected in series between the third plate line and the third sub-storage chain, and the plurality of third plate line pass transistors are electrically connected to the plurality of third plate lines one by one; the fourth bit line pass transistor is connected in series between the second bit line and the fourth sub-storage chain, and the plurality of fourth sub-storage chains are electrically connected to the same second bit line through the plurality of fourth bit line pass transistors; and the fourth plate line pass transistor is connected in series between the fourth plate line and the fourth sub-storage chain, and the plurality of fourth plate line pass transistors are electrically connected to the plurality of fourth plate lines one by one. The first storage chain and the second storage chain are stacked in the Z direction, and the third storage chain and the fourth storage chain are stacked in the Z direction, which can improve the storage density. Moreover, in the X-Y plane, the first storage chain and the third storage chain are arranged in an array, and the second storage chain and the fourth storage chain are arranged in an array.

[0024] The working of the first storage chain, the second storage chain, the third storage chain, and the fourth storage chain in the storage chip can be divided into the following three cases:

[0025] In the first case, the first storage unit in the first storage chain and the third storage unit in the third storage chain are used for read-write signals. For example, in the read stage, the plurality of first storage units in the first storage chain include a first selected storage unit, and the first selected storage unit is used to input a first read signal to the comparison circuit through the first bit line, and the second bit line is used to input a first reference voltage to the comparison circuit; or in the read stage, the plurality of third storage units in the third storage chain include a third selected storage unit, and the third selected storage unit is used to input a second read signal to the comparison circuit through the second bit line, and the first bit line is used to input a second reference voltage to the comparison circuit.

[0026] In the case where the first bit line transmits the first read signal, the second bit line is used to provide the first reference signal; in the case where the second bit line is used to provide the second read signal, the first bit line is used to provide the second reference signal. That is, the functions of the first bit line and the second bit line can be interchanged to realize time-sharing use of the first bit line and the second bit line to read signals.

[0027] In the second case, the first storage unit in the first storage chain and the second storage unit in the second storage chain are used for read-write signals. For example, in the read stage, the plurality of first storage units in the first storage chain include a first selected storage unit, and the first selected storage unit is used to input a first read signal to the comparison circuit through the first bit line, and the second bit line is used to input a first reference voltage to the comparison circuit. Or in the read stage, the plurality of second storage units in the second storage chain include a second selected storage unit, and the second selected storage unit is used to input a second read signal to the comparison circuit through the first bit line BL1, and the second bit line is used to input a second reference voltage to the comparison circuit.

[0028] The first bit line is electrically connected with the first storage chain and the second storage chain respectively. When the first storage chain includes the first selected storage unit, the first read signal output by the first selected storage unit can be transmitted by using the first bit line, and at this time the second bit line is used to transmit the first reference voltage. When the second storage chain includes the second selected storage unit, the second read signal output by the second selected storage unit can be transmitted by using the first bit line, and at this time the second bit line is still used to transmit the first reference voltage.

[0029] Similarly to the second case, the third storage unit in the third storage chain and the fourth storage unit in the fourth storage chain can also be used to read and write signals, which will not be described herein again.

[0030] In the third case, the second storage unit in the second storage chain and the fourth storage unit in the fourth storage chain are used to read and write signals. For example, in the read stage, the plurality of second storage units in the second storage chain include a second selected storage unit, the second selected storage unit is used to input the first read signal to the comparison circuit through the first bit line, and the second bit line is used to input the first reference voltage to the comparison circuit. Alternatively, in the read stage, the plurality of fourth storage units in the fourth storage chain include a fourth selected storage unit, the fourth selected storage unit is used to input the second read signal to the comparison circuit through the second bit line, and the first bit line is used to input the second reference voltage to the comparison circuit.

[0031] In the case that the first bit line transmits the first read signal, the second bit line is used to provide the first reference signal; in the case that the second bit line is used to provide the second read signal, the first bit line is used to provide the second reference signal. That is, the functions of the first bit line and the second bit line can be interchanged to realize the time-sharing use of the first bit line and the second bit line to read signals.

[0032] In some possible implementation manners, the first storage unit includes a transistor and a capacitor connected in parallel, and the storage chip further includes a word line, a first gate line and a second gate line. The word line is electrically connected with the gate of the transistor, the first pole of the transistor is electrically connected with the first plate line pass transistor, and the second pole of the transistor is electrically connected with the first bit line pass transistor; the first gate line is electrically connected with the gate of the first bit line pass transistor, and the second gate line is electrically connected with the gate of the first plate line pass transistor.

[0033] The word line is used to transmit a signal to the gate of the transistor to control the transistor to be turned on or turned off; the first gate line is used to transmit a signal to the gate of the first bit line pass transistor to control the first bit line pass transistor to be turned on or turned off; and the second gate line is used to transmit a signal to the gate of the second bit line pass transistor to control the first plate line pass transistor to be turned on or turned off.

[0034] In a second aspect, the present application provides an electronic device, which includes a processor and the storage chip of the first aspect, and the processor is used to read and write data of the storage chip.

[0035] The second aspect and any kind of implementation manner of the second aspect correspond to the first aspect and any kind of implementation manner of the first aspect respectively. The technical effects corresponding to the second aspect and any kind of implementation manner of the second aspect can refer to the technical effects corresponding to the first aspect and any kind of implementation manner of the first aspect described above, and will not be described here again.

[0036] In a third aspect, the present application provides a preparation method of a storage chip, comprising: forming a first storage chain on a substrate, the first storage chain comprising a plurality of first sub-storage chains connected in series, and each first sub-storage chain comprising a plurality of first storage units connected in series; forming a first bit line pass transistor and a first plate line pass transistor on the first storage chain, the first sub-storage chain being connected in series between the first bit line pass transistor and the first plate line pass transistor; forming a wiring layer on a side of the first bit line pass transistor and the first plate line pass transistor away from the substrate, the wiring layer comprising a first bit line and a plurality of first plate lines, the first bit line pass transistor being connected in series between the first bit line and the first sub-storage chain, and the plurality of first sub-storage chains being electrically connected to the same first bit line through the plurality of first bit line pass transistors; and the first plate line pass transistor being connected in series between the first plate line and the first sub-storage chain, and the plurality of first plate line pass transistors being electrically connected to the plurality of first plate lines one by one.

[0037] In some possible implementation manners, the wiring layer further comprises a plurality of second plate lines. After the wiring layer is formed on the side of the first bit line pass transistor and the first plate line pass transistor away from the substrate, the preparation method of the chip further comprises: forming a second bit line pass transistor and a second plate line pass transistor on a side of the plurality of second plate lines away from the substrate; forming a second storage chain on a side of the second bit line pass transistor and the second plate line pass transistor away from the substrate; the second storage chain comprising a plurality of second sub-storage chains connected in series, and each second sub-storage chain comprising a plurality of second storage units connected in series; the second sub-storage chain being connected in series between the second bit line pass transistor and the second plate line pass transistor; the second bit line pass transistor being connected in series between the first bit line and the second sub-storage chain, and the plurality of second sub-storage chains being electrically connected to the same first bit line through the plurality of second bit line pass transistors; and the second plate line pass transistor being connected in series between the second plate line and the second sub-storage chain, and the plurality of second plate line pass transistors being electrically connected to the plurality of second plate lines one by one.

[0038] The third aspect and any kind of implementation manner of the third aspect correspond to the first aspect and any kind of implementation manner of the first aspect respectively. The technical effects corresponding to the third aspect and any kind of implementation manner of the third aspect can refer to the technical effects corresponding to the first aspect and any kind of implementation manner of the first aspect described above, and will not be described here again. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1 is an interaction diagram of various modules in a memory provided by an embodiment of the present application;

[0040] Figure 2 is a diagram of arrangement of multiple memory cells according to an embodiment of the present application;

[0041] Figure 3a is a diagram of structure of a memory chip according to an embodiment of the present application;

[0042] Figure 3b is a diagram of structure of a memory chip according to an embodiment of the present application;

[0043] Figure 3c is a diagram of structure of a memory chip according to an embodiment of the present application;

[0044] Figure 4 is a diagram of circuit connection of various electronic devices on a memory chip according to an embodiment of the present application;

[0045] Figure 5 is a timing diagram of operation of the circuit shown in Figure 4;

[0046] Figure 6 is a diagram of circuit connection of various electronic devices on a memory chip according to an embodiment of the present application;

[0047] Figure 7a is a diagram of operation of a portion of first bit line pass gates and a portion of first plate line pass gates according to an embodiment of the present application;

[0048] Figure 7b is a diagram of operation of first bit line pass gates and first plate line pass gates according to an embodiment of the present application;

[0049] Figure 8 is a diagram of circuit connection of various electronic devices on a memory chip according to an embodiment of the present application;

[0050] Figure 9 is a diagram of structure of a memory chip according to an embodiment of the present application;

[0051] Figure 10 is a diagram of circuit connection of various electronic devices on a memory chip according to an embodiment of the present application;

[0052] Figure 11a is a diagram of operation of first bit lines and second bit lines according to an embodiment of the present application;

[0053] Figure 11b is a diagram of operation of first bit lines and second bit lines according to an embodiment of the present application;

[0054] Figure 12a is a diagram of operation of first bit lines and second bit lines according to an embodiment of the present application;

[0055] Figure 12b is a diagram of operation of first bit lines and second bit lines according to an embodiment of the present application;

[0056] Figure 13a is a diagram of operation of first bit lines and second bit lines according to an embodiment of the present application;

[0057] Figure 13b is a diagram of operation of first bit lines and second bit lines according to an embodiment of the present application;

[0058] FIG. 14 is a flowchart of a preparation process of a memory chip according to an embodiment of the present application;

[0059] FIG. 15a is a flowchart of a preparation process of a memory chip according to an embodiment of the present application;

[0060] FIG. 15b is a flowchart of a preparation process of a memory chip according to an embodiment of the present application;

[0061] FIG. 16 is a flowchart of a preparation process of a memory chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0062] The technical solutions in the embodiments of the present application will be clearly and completely described with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0063] The term "and / or" in the present application is only used to describe an association relationship of associated objects, and can represent three relationships, for example, A and / or B can represent three cases of existence of A alone, existence of A and B simultaneously, and existence of B alone.

[0064] The terms "first" and "second" and the like in the description and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe a specific order of the target objects.

[0065] In the embodiments of the present application, the words such as "exemplary" or "for example" are used to mean serving as an example, illustration, or description. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design solutions. Rather, the words such as "exemplary" or "for example" are used in the specific manner to present the relevant concept.

[0066] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0067] The embodiments of the present application provide an electronic device, which can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like containing a memory.

[0068] Consumer electronic products such as mobile phones, tablet computers, notebook computers, personal computers (PCs), personal digital assistants (PDAs), smart wearables (e.g., smart watches, smart bands, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products such as smart door locks, televisions, smart speakers, refrigerators, robotic vacuum cleaners, etc. Vehicle-mounted electronic products such as vehicle-mounted navigation devices, vehicle-mounted displays, etc. Financial terminal products such as automated teller machines (ATMs), self-service terminals, etc. Communication electronic products such as servers, memories, radars, base stations, etc. Communication equipment containing memory chips.

[0069] For the convenience of description, the following takes a mobile phone as an example of an electronic device. The mobile phone can include a processor and a memory, as shown in FIG. 1, the memory includes a memory array, a controller, a row decoder, a column decoder, etc. The processor can send an address of a selected memory cell to the row decoder and the column decoder through the controller. The row decoder and the column decoder determine the memory cell in the memory array after decoding the received address, and then make the selected memory cell perform a read / write operation.

[0070] As mentioned in the background, in order to achieve high-density storage, the area occupied by a memory cell in a chain ferroelectric memory can reach 4F 2 . That is, as shown in FIG. 2, assuming that the pitch between adjacent memory cells is the same, the sum of the single-side size of any memory cell and the pitch between the memory cell and the adjacent memory cell is 2F, then the area occupied by the memory cell is 4F 2 .

[0071] The chain ferroelectric memory includes a memory chip, the memory chip includes a memory array, the memory array includes a plurality of memory chains, each memory chain includes a plurality of memory cells, and a bit line selector (BLS) is further electrically connected between the plurality of memory cells on a memory chain and a bit line. A plate line selector (PLS) is further electrically connected between the plurality of memory cells on a memory chain and a plate line. Moreover, the bit line selector and / or the plate line selector also occupy a part of the area in the memory chip, for example, the area occupied by the bit line selector and the plate line selector ranges from 20nm*20nm to 300nm*300nm. Therefore, although the area occupied by the memory cell is 4F 2But the effective area of the storage unit in a storage chain is not a standard 4F 2 .

[0072] In addition, the number of storage units connected in series in a storage chain is limited by the on-state current of the transistor in the storage unit, and the number of storage units cannot generally exceed 32, so the number of storage chains in a traditional storage array is not small, and the number of bit line pass transistors and plate line pass transistors also increases accordingly. Therefore, the storage density of the traditional storage chain still has room for improvement. In the present application, the on-state current of the transistor can range from 100 nA to 1000 uA, and the off-state leakage current of the transistor can range from 0.1 fA to 1000 pA.

[0073] Based on this, the embodiments of the present application provide a storage chip which can be applied to chain ferroelectric memory, chain dynamic random access memory (DRAM) and other chain memories. The embodiments of the present application avoid the occupation of the area of the storage chip by the bit line pass transistor and the plate line pass transistor by manufacturing the storage chain, the bit line pass transistor and the plate line pass transistor in different layers of the storage chip

[0074] The structure of the storage chip will be described in detail below with reference to the accompanying drawings.

[0075] As shown in FIGS. 3a and 4, the storage chip includes a substrate 10, a first storage chain, a first bit line pass transistor BLS1, a first plate line pass transistor PLS1, and a wiring layer. The first storage chain includes a plurality of first sub-storage chains connected in series, and each first sub-storage chain includes a plurality of first storage units connected in series. The first storage unit includes a transistor and a capacitor, and the wiring layer includes a first bit line BL1 and a plurality of first plate lines PL1.

[0076] For example, the first storage chain includes 100 first sub-storage chains connected in series, and each first sub-storage chain includes 10 first storage units connected in series, that is, the first storage chain includes 1000 first storage units connected in series. Of course, the number of first storage units included in the plurality of first sub-storage chains can also be different, which will not be described here.

[0077] In the Z direction, the first storage chain, the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1, and the wiring layer are sequentially stacked. The first storage chain can be prepared by a front-end process, and the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 and the wiring layer can be prepared by a back-end process. In this way, the high-temperature processing during the preparation of the first bit line pass transistor BLS1, the first plate line pass transistor PLS1 and the wiring layer can be avoided, and the performance of the transistor in the first storage chain can be affected.

[0078] Optionally, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 can be disposed on the same layer (alternatively, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 can be formed by the same semiconductor process), and the first bit line BL1 and the plurality of first plate lines PL1 can be disposed on the same routing layer (alternatively, the first bit line BL1 and the plurality of first plate lines PL1 can be formed by the same semiconductor process).

[0079] For example, as shown in FIG. 3a, the first storage chain includes one transistor and one capacitor, and the capacitor includes a first electrode and a second electrode. The transistor is located on a metal 0 (M0) layer, the first electrode is located on an M1 layer, and the second electrode is located on an M2 layer. The first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 are located on an M3 layer to an Mn layer, where n > 3. The first bit line BL1 and the plurality of first plate lines PL1 are located on an M(n+1) layer.

[0080] Further, an insulating layer is further disposed between the first electrode and the second electrode; a first dielectric layer should be further disposed between the M2 layer and the M3 layer, and the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 can be connected in series through a first via hole in the first dielectric layer; a second dielectric layer is further disposed between the Mn layer and the M(n+1) layer, the first bit line BL1 can be electrically connected to the plurality of first plate line selection transistors PLS1 on the first storage chain through a second via hole in the second dielectric layer, and the plurality of first plate lines PL1 can be respectively and one-to-one electrically connected to the plurality of first plate line selection transistors PLS1 through the second via hole in the second dielectric layer.

[0081] Of course, the transistor and the capacitor of the first storage chain, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1, the first bit line BL1 and the plurality of first plate lines PL1 can be stacked in other manners in addition to the above-mentioned manner of stacking on the M0 layer to the M(n+1) layer, and the embodiments of the present application do not limit this.

[0082] For example, the foregoing introduces that the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 are disposed on the same layer and are located on the M3 layer to the Mn layer, and in other possible implementation manners, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 can also be disposed on different layers. For example, as shown in FIG. 3b, the first bit line selection transistor BLS1 is disposed between the substrate 10 and the first plate line selection transistor PLS1; or as shown in FIG. 3c, the first bit line selection transistor BLS1 is disposed between the substrate 10 and the first plate line selection transistor PLS1.

[0083] Compared with the scheme that the first plate line pass transistor PLS1 and the first bit line pass transistor BLS1 are arranged in different layers, the scheme that the first plate line pass transistor PLS1 and the first bit line pass transistor BLS1 are arranged in the same layer can realize that the first plate line pass transistor PLS1 and the first bit line pass transistor BLS1 are prepared by the same semiconductor process, thereby simplifying the preparation process of the memory chip. Moreover, in the case that the first plate line pass transistor PLS1 and the first bit line pass transistor BLS1 are arranged in the same layer, the first plate line pass transistor PLS1 and the first bit line pass transistor BLS1 are respectively electrically connected with the first storage chain and the wire layer.

[0084] In the present application, by stacking the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 with the first storage chain, the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 can be arranged overlapping the first storage chain, that is, the orthographic projection of the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 on the X-Y plane falls within the orthographic projection range of the layer where the first storage chain is located on the X-Y plane, thereby avoiding the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 occupying the area of the memory chip on the X-Y plane, so that the effective area of the first storage unit on the first storage chain becomes a standard 4F 2 , so as to improve the storage density of the first storage chain. Further, even if the limitation of the on-state current of the transistor in the first storage unit causes the storage array to contain more first storage chains, the plurality of first bit line pass transistors BLS1 and the plurality of first plate line pass transistors PLS1 electrically connected with the plurality of first storage chains can be stacked with the first storage chain in the Z direction, thereby improving the storage density of the storage array. Moreover, because all the first bit line pass transistors and all the first plate line pass transistors electrically connected with the first storage chain can be stacked with the first storage chain in the Z direction, the number of first storage units in the first storage chain can be increased infinitely, that is, the length of the first storage chain can be infinitely long, under the condition that the size of the memory chip is allowed.

[0085] , wherein the X-Y plane is perpendicular to the Z direction. The orthographic projection of the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 on the X-Y plane means that the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 are vertically projected on the X-Y plane along the Z direction. The orthographic projection of the layer where the first storage chain is located on the X-Y plane means that the layer where the first storage chain is located is vertically projected on the X-Y plane along the Z direction.

[0086] As shown in FIG. 4, the first sub-memory chain is connected in series between the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1, and the first bit line selection transistor BLS1 is connected in series between the first bit line BL1 and the first sub-memory chain, and the plurality of first sub-memory chains are electrically connected to the same first bit line BL1 through the plurality of first bit line selection transistors BLS1. The first plate line selection transistor PLS1 is connected in series between the first plate line PL1 and the first sub-memory chain, and the plurality of first plate line selection transistors PLS1 are electrically connected to the plurality of first plate lines PL1 one by one, that is, different first plate line selection transistors PLS1 are respectively electrically connected to different first plate lines PL1.

[0087] The transistor in the first memory cell, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 each include a gate, a first pole and a second pole, the first pole being a source, and the second pole being a drain; or the first pole being a drain, and the second pole being a source. The material of the gate, the first pole and the second pole includes but is not limited to at least one of tungsten (W), titanium nitride (TiN) and molybdenum (Mo). In addition, the transistor in the first memory cell, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 each further include a channel layer and a gate dielectric layer, the material of the channel layer including but not limited to single crystal silicon / germanium, polycrystalline silicon / germanium, oxide semiconductor (IGZO, IWO, etc.), organic semiconductor (pentacene, P3HT, etc.), two-dimensional material semiconductor (MoS2, WSe2, etc.), one-dimensional semiconductor (CNT, etc.) and the like, and the material of the gate dielectric layer including but not limited to SiO2, SiN x , high dielectric constant High-K material (HfO2, ZrO2, etc.) and the like. The first sub-memory chain connected in series between the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 means that the first sub-memory chain is electrically connected to the second pole of the first bit line selection transistor BLS1 and the first pole of the first plate line selection transistor PLS1 respectively.

[0088] The first bit line selection transistor BLS1 connected in series between the first bit line BL1 and the first sub-memory chain means that the first pole of the first bit line selection transistor BLS1 is electrically connected to the first bit line BL1, and the second pole of the first bit line selection transistor BLS1 is electrically connected to the first sub-memory chain.

[0089] The first plate line selection transistor PLS1 connected in series between the first plate line PL1 and the first sub-memory chain means that the first pole of the first plate line selection transistor PLS1 is electrically connected to the first sub-memory chain, and the second pole of the first plate line selection transistor PLS1 is electrically connected to the first plate line PL1.

[0090] In some possible implementations, the present application does not limit the connection mode of the transistor and the capacitor in the first memory cell.

[0091] Optionally, as shown in FIG. 4, in the first storage unit, the transistor can be connected in parallel with the capacitor, i.e., the first electrode of the capacitor is electrically connected with the first pole of the transistor, and the second electrode of the capacitor is electrically connected with the second pole of the transistor. Further, the first pole of the transistor and the first electrode of the capacitor are electrically connected with the first pole of the first plate line selection transistor PLS1, and the second pole of the transistor and the second electrode of the capacitor are electrically connected with the second pole of the first bit line selection transistor BLS1.

[0092] Thus, the first plate line PL1, the second pole of the first plate line selection transistor PLS1, the first pole of the first plate line selection transistor PLS1, the first pole of the transistor / the first electrode of the capacitor, the second pole of the transistor / the second electrode of the capacitor, the second pole of the first bit line selection transistor BLS1, the first pole of the first bit line selection transistor BLS1, and the first bit line BL1 constitute a path.

[0093] Optionally, in the first storage unit, the transistor can be connected in series with the capacitor, i.e., the first electrode of the capacitor is electrically connected with the first pole of the transistor.

[0094] Optionally, in the first storage unit, the first electrode of the capacitor is electrically connected with the gate of the transistor.

[0095] Hereinafter, the transistor and the capacitor are connected in parallel as shown in FIG. 4, and the transistor in the first storage unit, the first bit line selection transistor BLS1, and the first plate line selection transistor PLS1 are all N-type transistors, and the reading and writing principles of the storage unit on the first storage chain are described.

[0096] As shown in FIG. 4, on the basis of the foregoing, the storage chip can further include a plurality of word lines WL, a plurality of first gate lines GL1, and a plurality of second gate lines GL2, and the plurality of word lines WL, the plurality of first gate lines GL1, and the plurality of second gate lines GL2 can be arranged in the same layer as the first bit line BL1 and the first plate line PL1. Among them, the plurality of word lines WL are one-to-one electrically connected with the gates of the transistors in the plurality of first storage units, for controlling the transistors to be turned on or turned off; the plurality of first gate lines GL1 are one-to-one electrically connected with the plurality of first bit line selection transistors BLS1, for controlling the first bit line selection transistors BLS1 to be turned on or turned off; and the plurality of second gate lines GL2 are one-to-one electrically connected with the gates of the plurality of first plate line selection transistors PLS1, for controlling the first plate line selection transistors PLS1 to be turned on or turned off.

[0097] As shown in FIG. 5, in the standby stage, the first bit line BL1 and the plurality of first plate lines PL1 are at low level (e.g. 0V); the plurality of first gate lines GL1 and the plurality of second gate lines GL2 are at low level (e.g. 0V), the first bit line select transistor BLS1 and the first plate line select transistor PLS1 are both off, the first bit line BL1 cannot transmit signals to the first storage chain through the first bit line select transistor BLS1, and the first plate line PL1 cannot transmit signals to the first storage chain through the first plate line select transistor PLS1; the plurality of word lines WL are at high level, and the transistors in the plurality of first storage units are turned on.

[0098] Next, as shown in FIG. 5, in the pre-charge stage, the plurality of word lines WL are still controlled to be at high level, and the transistors in the plurality of first storage units are turned on. The first selected storage unit is connected in series with one first bit line select transistor BLS1 and one first plate line select transistor PLS1, the first gate line GL1 electrically connected with the first bit line select transistor BLS1 and the second gate line GL2 electrically connected with the first plate line select transistor PLS1 are controlled to be at high level, so that the first bit line select transistor BLS1 and the first plate line select transistor PLS1 are turned on, and thus the first bit line BL1 and the first plate line PL1 electrically connected with the first bit line select transistor BLS1 and the first plate line select transistor PLS1 can be electrically connected with the first sub-storage chain in which the first selected storage unit is located through the first bit line select transistor BLS1 and the first plate line select transistor PLS1, so that the first sub-storage chain in which the first selected storage unit is located is selected. The first bit line select transistor BLS1 and the first plate line select transistor PLS1 connected in series with other first sub-storage chains in the first storage chain are both off, and thus the other first sub-storage chains cannot be electrically connected with the first bit line BL1 and the first plate line PL1 through the first bit line select transistor BLS1 and the first plate line select transistor PLS1, and thus the other first sub-storage chains are not selected.

[0099] Those skilled in the art should understand that the first selected storage unit is one of the plurality of first storage units, and the first selected storage unit is different from other first storage units in the plurality of first storage units in that the first selected storage unit can be selected to read the stored signals in the read stage, and the first selected storage unit can be selected to write the stored signals in the write-back stage. The roles of the second selected storage unit in the plurality of second storage units, the third selected storage unit in the plurality of third storage units, and the fourth selected storage unit in the plurality of fourth storage units are the same as the role of the first selected storage unit in the plurality of first storage units, and thus will not be described again.

[0100] Then, as shown in FIG. 5, in the reading stage, the first selected storage cell in the plurality of first storage cells is confirmed, the first bit line BL1 electrically connected with the first selected storage cell is pre-charged to 0V, and the first bit line BL1 is in a float state, so that when a signal is read, the potential on the first bit line BL1 changes.

[0101] Further, the selected first sub-storage chain includes the first selected storage cell and the unselected storage cell, the word line WL electrically connected with the first selected storage cell is controlled to be at a low level, and the transistor in the first selected storage cell is turned off; the word line WL electrically connected with the unselected storage cell is controlled to be at a high level, and the transistor in the unselected storage cell is turned on. In this way, the first bit line BL1, the first bit line selection transistor BLS1 electrically connected with the selected first sub-storage chain, the capacitor in the first selected storage cell, the transistor in the unselected storage cell, the first plate line selection transistor PLS1 electrically connected with the selected first sub-storage chain, and the first plate line PL1 electrically connected with the selected first sub-storage chain form a path.

[0102] The first plate line PL1 electrically connected with the selected first sub-storage chain is controlled to be at a high level (for example, an operating voltage of 0.5V-3V), and the storage signal in the capacitor of the first selected storage cell is read.

[0103] On this basis, as shown in FIG. 6, the storage chip can further include a second bit line BL2 and a comparison circuit, which can be a sense amplifier (SA) for example. The first bit line BL1 is electrically connected with a first input end of the sense amplifier SA, for inputting a storage signal to the sense amplifier SA; and the second bit line BL2 is electrically connected with a second input end of the sense amplifier SA, for inputting a reference voltage Vref to the sense amplifier SA.

[0104] Taking the selected first storage chain as a ferroelectric storage chain as an example, the reading stage is divided into a destroy stage and a sense stage. In the destroy stage, the capacitor (ferroelectric capacitor) in the first selected storage cell undergoes ferroelectric flipping, and the charge is transmitted to the first bit line BL1. Then, in the sense stage, the comparison circuit works, and differentially amplifies the received storage signal, to determine whether the storage signal is a digital signal 0 or a digital signal 1 according to the reference voltage Vref.

[0105] Specifically, if the storage signal in the first selected storage unit is digital signal 0, the potential of the first bit line BL1 will be raised a little (the denser dotted line in FIG. 5), but the potential of the first bit line BL1 is still lower than the reference voltage Vref; if the storage signal in the first selected storage unit is digital signal 1, the potential of the first bit line BL1 will be raised to a higher potential, and the potential of the first bit line BL1 exceeds the reference voltage Vref. The sense amplifier SA differentially amplifies the received storage signal according to the different potentials on the first bit line BL1, and lowers the potential of the storage signal to 0V when the storage signal is digital signal 0, and raises the potential of the storage signal to Vdd when the storage signal is digital signal 1. At this point, the read operation is completed.

[0106] In addition, as shown in FIG. 6, in addition to including the second bit line BL2, the storage chip can also include a second storage chain, a second bit line selection transistor BLS2, a second plate line selection transistor PLS2, and a plurality of second plate lines PL2. The second storage chain can be prepared by the same semiconductor process as the first storage chain, the second bit line selection transistor BLS2 and the second plate line selection transistor PLS2 can be prepared by the same semiconductor process as the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1, and the plurality of second plate lines PL2 and the second bit line BL2 can be prepared by the same semiconductor process as the plurality of first plate lines PL1 and the first bit line BL1. The second storage chain includes a plurality of second sub-storage chains connected in series, and each second sub-storage chain includes a plurality of second storage units connected in series. The second bit line selection transistor BLS2 is connected in series between the second bit line BL2 and the second sub-storage chain, and the plurality of second sub-storage chains are electrically connected to the same second bit line BL2 through the plurality of second bit line selection transistors BLS2; the second plate line selection transistor PLS2 is connected in series between the second plate line PL2 and the second sub-storage chain, and the plurality of second plate line selection transistors PLS2 are electrically connected to the plurality of second plate lines PL2 one by one.

[0107] Referring to FIG. 6, the word line WL, the first bit line BL1, the first plate line PL1, the first gate line GL1, and the second gate line GL2 electrically connected to the first storage chain, and the word line WL, the second bit line BL2, the second plate line PL2, the first gate line GL1, and the second gate line GL2 electrically connected to the second storage chain can be prepared by the same semiconductor process. However, it should be understood that the word line WL, the first bit line BL1, the first plate line PL1, the first gate line GL1, and the second gate line GL2 electrically connected to the first storage chain, and the word line WL, the second bit line BL2, the second plate line PL2, the first gate line GL1, and the second gate line GL2 electrically connected to the second storage chain are not shared.

[0108] In the read stage, the first bit line BL1 inputs the storage signal to the sense amplifier SA, and the second bit line BL2 inputs the reference signal Vref to the sense amplifier SA. In some embodiments, the first bit line BL1 and the second bit line BL2 can input the storage signal to the sense amplifier SA in time division, that is, when the first bit line BL1 inputs the storage signal to the sense amplifier SA, the second bit line BL2 inputs the reference signal Vref to the sense amplifier SA; when the second bit line BL2 inputs the storage signal to the sense amplifier SA, the first bit line BL1 inputs the reference signal Vref to the sense amplifier SA.

[0109] In some possible implementation manners, the comparison circuit can be prepared by a back-end process. On the one hand, high-temperature processing during preparation of the comparison circuit can be avoided, and the performance of the transistor in the first storage chain is affected; on the other hand, when the comparison circuit is prepared by the back-end process, the comparison circuit and the first storage chain can also be stacked in the Z direction, that is, the orthogonal projection of the comparison circuit on the X-Y plane falls within the orthogonal projection range of the first storage chain on the X-Y plane, so that the comparison circuit occupies the area of the storage chip on the X-Y plane.

[0110] Then, as shown in FIG. 5, in the write recovery stage, the first plate line PL1 electrically connected with the selected first sub-storage chain is maintained at a high potential for a period of time, and then is lowered to a low level (for example, 0 V) and is maintained at the low level for a period of time. During this period, the word line WL electrically connected with the transistor of the first selected storage unit is kept at a low potential, so that the transistor of the first selected storage unit is turned off, and the capacitor of the first selected storage unit is still selected. When the signal read in the read stage is a digital signal 0, the voltage on the first bit line BL1 is 0 V, and the digital signal 0 can be written into the capacitor of the first selected storage unit again in the period when the first plate line PL1 electrically connected with the selected first sub-storage chain is at a high potential. When the signal read in the read stage is a digital signal 1, the voltage on the first bit line BL1 is a high potential VDD, and the digital signal 0 can be written into the capacitor of the first selected storage unit again in the period when the first plate line PL1 electrically connected with the selected first sub-storage chain is at a low potential.

[0111] Then, as shown in FIG. 5, in the post-charge stage, the first bit line BL1 and the plurality of first plate lines PL1 are at a low level, and then the potential of the plurality of word lines WL is kept at a low level for a period of time and is then raised, and the transistors of the plurality of first storage units are all turned on. Then, the first gate line GL1 electrically connected with the first bit line pass transistor BLS1 and the second gate line GL2 electrically connected with the first plate line pass transistor PLS1 become low, and the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 are turned off. At this time, one read-write cycle is completed.

[0112] The above example takes the transistor of the first storage unit, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 as N-type transistors, and the transistor in the first storage unit is connected in parallel with the capacitor as an example to simply introduce the read-write process of the first storage unit. Of course, at least one of the transistor of the first storage unit, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 can be an N-type transistor, and the others can be P-type transistors; or the transistor of the first storage unit, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 can all be P-type transistors. In addition, the transistor in the first storage unit can also be connected in other ways, and the embodiments of the present application do not limit this.

[0113] In some possible implementations, taking the storage chip applied to the chain ferroelectric memory as an example, the capacitor can be a ferroelectric capacitor, and the material of the ferroelectric layer between the first electrode and the second electrode in the ferroelectric capacitor can include hafnium-based, zirconium-based oxide, hafnium-based, zirconium-based oxide containing a doping element (such as Hf, Zr, Si, Y, La, Ce, etc.). The ferroelectric layer can be one layer, or a plurality of layers of ferroelectric / anti-ferroelectric materials with different components. The thickness of the ferroelectric layer can range from 2 nm to 15 nm, and the area of the ferroelectric layer in the X-Y plane can range from 0.04 um 2 to 0.25 um 2 .

[0114] In some embodiments, as shown in FIG. 7a, the first bit line selection transistor BLS1 includes a first sub-bit line selection transistor BLS1_1 and a second sub-bit line selection transistor BLS1_2, the first plate line selection transistor includes a first sub-plate line selection transistor PLS1_1 and a second sub-plate line selection transistor PLS1_2, and the first sub-storage chain is connected in series between the first sub-bit line selection transistor BLS1_1 and the first sub-plate line selection transistor PLS1_1.

[0115] The first sub-storage chain includes at least three sub-storage chains connected in series, one sub-storage chain is connected in series between the first sub-bit line selection transistor BLS1_1 and the second sub-plate line selection transistor PLS1_2, one sub-storage chain is connected in series between the first sub-plate line selection transistor PLS1_1 and the second sub-bit line selection transistor BLS1_2, and the other sub-storage chains are connected in series between the second sub-bit line selection transistor BLS1_2 and the second sub-plate line selection transistor PLS1_2. In this way, the first sub-storage chain or the sub-storage chain can also be dynamically adjusted to be selected according to the service life of the first storage chain, so as to ensure the performance of the first storage chain within the service life.

[0116] As shown in FIG. 7a, in the early stage of the life of the first storage chain (for example, the usage time of the first storage chain is less than the preset time), the on-state current of the transistor is high, and the performance is good. Therefore, the selected first sub-storage chain can be relatively long. In the read / write stage, the first sub-bit line pass transistor and the first sub-plate line pass transistor connected in series with the selected storage unit are turned on, and the second sub-bit line pass transistor and the second sub-plate line pass transistor are not turned on, so that the first sub-storage chain where the first selected storage unit is located is selected, and only the storage units other than the first selected storage unit in the selected first sub-storage chain are not read / write signals. The usage time of the first storage chain refers to the actual usage time after the first storage chain is put into use. The preset time refers to the usage time of the first storage chain designed by the person skilled in the art in advance.

[0117] For example, as shown in FIG. 7a, the first sub-storage chain includes five segmented storage chains connected in series, and each segmented storage chain includes two first storage units. If the usage time of the first storage chain is less than the preset time, in the read / write stage, the first sub-bit line pass transistor BLS1_1 connected in series with the first first storage unit of the first sub-storage chain and the first sub-plate line pass transistor PLS1_1 connected in series with the tenth first storage unit of the first sub-storage chain are turned on (black in the figure), and the other second sub-bit line pass transistor BLS1_2 and the second sub-plate line pass transistor PLS1_2 connected in series with the first sub-storage chain are turned off (gray in the figure).

[0118] With the increase of the usage time, the performance of the transistor gradually decays, and the on-state current decreases. For example, in the case where the usage time of the first storage chain is greater than or equal to the preset time, in the read / write stage, one segmented storage chain in one first sub-storage chain can be selected, and the other segmented storage chains in the first sub-storage chain are not selected.

[0119] For example, as shown in FIG. 7b, in the read / write stage, if the first / two first storage units on the first sub-storage chain are the first selected storage unit, the first sub-bit line pass transistor BLS1_1 and the second sub-plate line pass transistor PLS1_2 connected in series with the first selected storage unit are turned on, and the other second sub-bit line pass transistor BLS1_2 and the first sub-plate line pass transistor PLS1_1 are turned off; if one of the third to eighth first storage units on the first sub-storage chain is the first selected storage unit, the second sub-bit line pass transistor BLS1_2 and the second sub-plate line pass transistor PLS1_2 connected in series with the first selected storage unit are turned on, and the other first sub-bit line pass transistor BLS1_1 and the first sub-plate line pass transistor PLS1_1 are turned off; if the ninth / tenth first storage unit on the first sub-storage chain is the first selected storage unit, the second sub-bit line pass transistor BLS1_2 and the first sub-plate line pass transistor PLS1_1 connected in series with the first selected storage unit are turned on, and the other first sub-bit line pass transistor BLS1_1 and the second sub-plate line pass transistor PLS1_2 are turned off.

[0120] In some possible implementation manners, the preset time length is not limited to a specific time, and can be designed according to the specific situation of the storage chip, for example, the preset time length can be 10 years.

[0121] The structure corresponding to the foregoing FIG. 6 introduces a scheme in which the second storage chain and the first storage chain are arranged in the same layer, the second bit line pass gate BLS2 and the second plate line pass gate PLS2 are electrically connected with the second bit line BL2 and arranged in the same layer with the first bit line pass gate BLS1 and the first plate line pass gate PLS1, and the plurality of second plate lines PL2 and the second bit line BL2 are arranged in the same layer with the first bit line BL1 and the plurality of first plate lines PL1. In another embodiment, as shown in FIG. 8, the second storage chain, the second bit line pass gate BLS2 and the second plate line pass gate PLS2 can also be arranged in a stacked manner with the first storage chain, the first bit line pass gate BLS1 and the first plate line pass gate PLS1, and the second storage chain and the second storage chain share the same first bit line BL1. The scheme of the stacked arrangement is described in detail below with reference to FIGS. 8 and 9.

[0122] As shown in FIG. 9, the second plate line PL2 is arranged in the same layer with the first bit line BL1 and the first plate line PL1, and is located in the wiring layer. The second bit line pass gate BLS2 and the second plate line pass gate PLS2 are stacked on the side of the first bit line BL1 and the first plate line PL1 away from the first storage chain, and the second storage chain is stacked on the side of the second bit line pass gate BLS2 and the second plate line pass gate PLS2 away from the first storage chain. That is, on the basis of the first bit line pass gate BLS1 and the first plate line pass gate PLS1 being stacked with the first storage chain in the Z direction, the second bit line pass gate BLS2 and the second plate line pass gate PLS2 and the second storage chain are also stacked with the first storage chain in the Z direction. In this way, the storage density can be further improved.

[0123] For example, as shown in FIG. 9, the plurality of second plate lines PL2 are located in the M(n+1) layer; the second bit line pass gate BLS2 and the second plate line pass gate PLS2 are located in the M(n+2) layer to the Mm layer, where m>n+2; the second electrode of the capacitor in the second storage chain is located in the M(m+1) layer, the first electrode of the capacitor in the second storage chain is located in the M(m+2) layer, the transistor in the second storage chain is located in the M(m+3) layer to the Mx layer, and x>m+3.

[0124] Further, the third dielectric layer is arranged between the M(n+1) layer and the M(n+2) layer, and the fourth dielectric layer is arranged between the Mm layer and the second storage chain.

[0125] Of course, the plurality of second plate lines PL2, the second bit line pass transistor BLS2 and the second plate line pass transistor PLS2, the transistors and the capacitors of the second storage chain can be stacked in other manners in addition to the above-mentioned manner of being stacked in the M(n+2) layer to the Mx layer, and the embodiments of the present application do not limit this.

[0126] For example, the foregoing introduces that the second bit line pass transistor BLS2 and the second plate line pass transistor PLS2 are arranged in the same layer and are located in the M(n+2) layer to the Mm layer, and in other possible implementation manners, the second bit line pass transistor BLS2 and the second plate line pass transistor PLS2 can also be arranged in different layers. For example, the second bit line pass transistor BLS2 is arranged between the substrate 10 and the second plate line pass transistor PLS2; or the second bit line pass transistor BLS2 is arranged between the substrate 10 and the second plate line pass transistor PLS2.

[0127] Compared with the scheme of the second bit line pass transistor BLS2 and the second plate line pass transistor PLS2 being arranged in different layers, the scheme of the second plate line pass transistor PLS2 and the second bit line pass transistor BLS2 being arranged in the same layer can realize that the second bit line pass transistor BLS2 and the second plate line pass transistor PLS2 are prepared by the same semiconductor process, thereby simplifying the preparation process of the storage chip. Moreover, in the case of the second bit line pass transistor BLS2 and the second plate line pass transistor PLS2 being arranged in the same layer, the second bit line pass transistor BLS2 and the second plate line pass transistor PLS2 are facilitated to be electrically connected with the first storage chain and the traces of the trace layer, respectively.

[0128] On this basis, as shown in FIG. 8, the second storage chain includes a plurality of second sub-storage chains connected in series, the second sub-storage chain includes a plurality of second storage units connected in series, and the second storage chain is connected in series between the second bit line pass transistor BLS2 and the second plate line pass transistor PLS2. The second bit line pass transistor BLS2 is connected in series between the first bit line BL1 and the second sub-storage chain, and the plurality of second sub-storage chains are electrically connected with the same first bit line BL1 through the plurality of second bit line pass transistors BLS2, that is, on the same first bit line BL1, the plurality of first bit line pass transistors BLS1 are electrically connected, and the plurality of second bit line pass transistors BLS2 are also electrically connected. The second plate line pass transistor BLS2 is connected in series between the second plate line PL2 and the second sub-storage chain, and the plurality of second plate line pass transistors PLS2 are electrically connected with the plurality of second plate lines PL2 one by one.

[0129] By making the plurality of first bit line pass transistors BLS1 and the plurality of second bit line pass transistors BLS2 share the same first bit line BL1, any first storage unit on the first storage chain can be selected as the first selected storage unit, or any second storage unit on the second storage chain can be selected as the second selected storage unit, thereby realizing reading and writing of the first selected storage unit and the second selected storage unit in time. Moreover, the number of traces in the trace layer is also reduced.

[0130] Further, as shown in FIG. 10, the storage chip further comprises a third storage chain, a third bit line selection transistor BLS3, a third plate line selection transistor PLS3, a fourth storage chain, a fourth bit line selection transistor BLS4, a fourth plate line selection transistor PLS4, a second bit line BL2, a plurality of third plate lines PL3, and a plurality of fourth plate lines PL4.

[0131] The third storage chain is arranged in the same layer as the first storage chain, and the third storage chain comprises a plurality of third sub-storage chains connected in series, and each third sub-storage chain comprises a plurality of third storage units connected in series. The fourth storage chain is arranged in the same layer as the second storage chain, and the fourth storage chain comprises a plurality of fourth sub-storage chains connected in series, and each fourth sub-storage chain comprises a plurality of fourth storage units connected in series.

[0132] The third bit line selection transistor BLS3 and the third plate line selection transistor PLS3 are arranged in the same layer as the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1, and the third sub-storage chain is connected in series between the third bit line selection transistor BLS3 and the third plate line selection transistor PLS3. The fourth bit line selection transistor BLS4 and the fourth plate line selection transistor PLS4 are arranged in the same layer as the second bit line selection transistor BLS2 and the second plate line selection transistor PLS2, and the fourth sub-storage chain is connected in series between the fourth bit line selection transistor BLS4 and the fourth plate line selection transistor PLS4.

[0133] The second bit line BL2, the plurality of third plate lines PL3, and the plurality of fourth plate lines PL4 are arranged in the same layer as the first bit line BL1 and the plurality of second plate lines PL2, and are located in the wiring layer. The third bit line selection transistor BLS3 is connected in series between the second bit line BL2 and the third sub-storage chain, and the plurality of third sub-storage chains are electrically connected to the same second bit line BL2 through the plurality of third bit line selection transistors BLS3. The third plate line selection transistor PLS3 is connected in series between the third plate line PL3 and the third sub-storage chain, and the plurality of third plate line selection transistors PLS3 are electrically connected to the plurality of third plate lines PL3 one by one. The fourth bit line selection transistor BLS4 is connected in series between the second bit line BL2 and the fourth sub-storage chain, and the plurality of fourth sub-storage chains are electrically connected to the same second bit line BL2 through the plurality of fourth bit line selection transistors BLS4. The fourth plate line selection transistor PLS4 is connected in series between the fourth plate line PL4 and the fourth sub-storage chain, and the plurality of fourth plate line selection transistors PLS4 are electrically connected to the plurality of fourth plate lines PL4 one by one.

[0134] That is, the first storage chain and the second storage chain sharing the same first bit line BL1 are stacked in the Z direction, and the third storage chain and the fourth storage chain sharing the same second bit line BL2 are stacked in the Z direction. Moreover, the first storage chain and the third storage chain are prepared by the same semiconductor process, and the second storage chain and the fourth storage chain are prepared by the same semiconductor process.

[0135] And since the first storage chain and the second storage chain share the same first bit line BL1, the third storage chain and the fourth storage chain share the same second bit line BL2, and in the case that the first bit line BL1 inputs the storage signal to the comparison circuit, the second bit line BL2 can be used to input the reference voltage Vref to the comparison circuit; in the case that the second bit line BL2 inputs the storage signal to the comparison circuit, the first bit line BL1 can be used to input the reference voltage Vref to the comparison circuit.

[0136] Based on this, the operation of the first storage chain, the second storage chain, the third storage chain, and the fourth storage chain in the storage chip can be divided into the following three cases:

[0137] The first case is that the first storage unit in the first storage chain and the third storage unit in the third storage chain are used for read-write signals. For example, as shown in FIG. 11a, in the read stage, the plurality of first storage units in the first storage chain includes a first selected storage unit, and the first selected storage unit is used to input a first read signal data1 to the comparison circuit through the first bit line BL1, and the second bit line BL2 is used to input a first reference voltage Vref1 to the comparison circuit. Alternatively, as shown in FIG. 11b, in the read stage, the plurality of third storage units in the third storage chain includes a third selected storage unit, and the third selected storage unit is used to input a second read signal data2 to the comparison circuit through the second bit line BL2, and the first bit line BL1 is used to input a second reference voltage Vref2 to the comparison circuit.

[0138] The second case is that the first storage unit in the first storage chain and the second storage unit in the second storage chain are used for read-write signals. For example, as shown in FIG. 12a, in the read stage, the plurality of first storage units in the first storage chain includes a first selected storage unit, and the first selected storage unit is used to input a first read signal data1 to the comparison circuit through the first bit line BL1, and the second bit line BL2 is used to input a first reference voltage Vref1 to the comparison circuit. Alternatively, as shown in FIG. 12b, in the read stage, the plurality of second storage units in the second storage chain includes a second selected storage unit, and the second selected storage unit is used to input a second read signal data2 to the comparison circuit through the first bit line BL1, and the second bit line BL2 is used to input a second reference voltage Vref2 to the comparison circuit.

[0139] Similar to the second case, the third storage unit in the third storage chain and the fourth storage unit in the fourth storage chain can also be used to read-write signals, which will not be described here.

[0140] In the third case, the second storage unit in the second storage chain and the fourth storage unit in the fourth storage chain are used for reading and writing signals. For example, as shown in FIG. 13a, in the reading stage, the plurality of second storage units in the second storage chain include a second selected storage unit, the second selected storage unit is used for inputting a first reading signal data1 to the comparison circuit through the first bit line BL1, and the second bit line BL2 is used for inputting a first reference voltage Vref1 to the comparison circuit. Alternatively, as shown in FIG. 13b, in the reading stage, the plurality of fourth storage units in the fourth storage chain include a fourth selected storage unit, the fourth selected storage unit is used for inputting a second reading signal data2 to the comparison circuit through the second bit line BL2, and the first bit line BL1 is used for inputting a second reference voltage Vref2 to the comparison circuit.

[0141] The embodiment of the present application further provides a preparation method of the storage chip, as shown in FIG. 14, which can be realized by the following steps:

[0142] S110, as shown in FIG. 15a, forming the first storage chain on the substrate 10, the first storage chain includes a plurality of first sub-storage chains connected in series, and the first sub-storage chain includes a plurality of first storage units connected in series.

[0143] For example, as shown in FIG. 15a, the first storage chain includes a transistor and a capacitor, and the capacitor includes a first electrode and a second electrode. The transistor is located at the metal 0 (M0) layer, the first electrode is located at the M1 layer, and the second electrode is located at the M2 layer.

[0144] S120, as shown in FIG. 15b, forming the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 on the first storage chain, and the first sub-storage chain is connected in series between the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1.

[0145] For example, as shown in FIG. 15b, the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 are located at the M3 layer to the Mn layer, where n>3.

[0146] In some possible implementation manners, after the step S110 and before the step S120, a first dielectric layer can be further formed on the first storage chain, and the first storage chain is electrically isolated from the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 by using the first dielectric layer. Further, in order to realize that the first sub-storage chain of the first storage chain is connected in series between the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1, a first via hole can be further formed in the first dielectric layer, so that the first bit line pass transistor BLS1 and the first plate line pass transistor PLS1 formed after the first dielectric layer can be connected in series with the first sub-storage chain through the first via hole.

[0147] S130, as shown in FIG. 3a, a wiring layer is formed on the side of the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 away from the substrate 10, the wiring layer includes the first bit line BL1 and a plurality of first plate lines PL1, the first bit line selection transistor BLS1 is connected in series between the first bit line BL1 and the first sub-memory chain, and the plurality of first sub-memory chains are electrically connected to the same first bit line BL1 through the plurality of first bit line selection transistors BLS1; the first plate line selection transistor PLS1 is connected in series between the first plate line PL1 and the first sub-memory chain, and the plurality of first plate line selection transistors PLS1 are electrically connected to the plurality of first plate lines PL1 one by one.

[0148] For example, as shown in FIG. 3a, the first bit line BL1 and the plurality of first plate lines PL1 are located at the M(n+1) layer.

[0149] In some possible implementation manners, after step S120 and before step S130, a second dielectric layer can also be formed on the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1, and the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 are electrically isolated from the first bit line BL1 and the plurality of first plate lines PL1 by using the second dielectric layer. Further, in order to realize that the first bit line selection transistor BLS1 is connected in series between the first bit line BL1 and the first sub-memory chain, and the first plate line selection transistor PLS1 is connected in series between the first plate line PL1 and the first sub-memory chain, a second via hole can also be formed in the second dielectric layer, so that the first bit line BL1 formed after the second dielectric layer can be electrically connected to the plurality of first plate line selection transistors PLS1 through the second via hole, and the plurality of first plate lines PL1 can be respectively electrically connected to the first plate line selection transistors PLS1 through the second via hole.

[0150] In the present application, by stacking the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 with the first memory chain, the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 can be overlapped with the first memory chain, that is, the orthographic projection of the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 on the X-Y plane falls within the orthographic projection range of the layer where the first memory chain is located on the X-Y plane, thereby avoiding the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1 occupying the area of the memory chip on the X-Y plane, and making the effective area of the first memory cell on the first memory chain become a standard 4F 2 , so as to improve the storage density of the first memory chain. Further, even if the limitation of the on-state current of the transistor in the first memory cell results in that the storage array contains more first memory chains, the plurality of first bit line selection transistors BLS1 and the first plate line selection transistors PLS1 electrically connected to the plurality of first memory chains can also be stacked with the first memory chain in the Z direction, thereby improving the storage density of the storage array.

[0151] In some embodiments, the wiring layer further comprises a plurality of second plate lines PL2. After step S130, the method for manufacturing the chip further comprises:

[0152] S140, as shown in FIG. 16, forming second bit line pass gates BLS2 and second plate line pass gates PLS2 on the side of the plurality of second plate lines PL2 away from the substrate 10.

[0153] In some possible implementations, after step S130 and before step S140, a third dielectric layer can be formed on the plurality of second plate lines PL2, and the plurality of first plate lines PL1, the first bit line BL1, the plurality of second plate lines PL2, the second bit line pass gates BLS2 and the second plate line pass gates PLS2 are electrically isolated by the third dielectric layer. Further, as mentioned in step S150, in order to realize that the second bit line pass gates BLS2 are connected in series between the first bit line BL1 and the second sub-memory chain, and the second plate line pass gates PLS2 are connected in series between the second plate line PL2 and the second sub-memory chain, a third via hole can be formed in the third dielectric layer, so that the second bit line pass gates BLS2 formed after the third dielectric layer can be electrically connected to the plurality of second plate lines PL2 through the third via hole, and the second plate line pass gates PLS2 can be electrically connected to the plurality of second plate lines PL2 respectively through the third via hole.

[0154] S150, as shown in FIG. 9, forming a second memory chain on the side of the second bit line pass gates BLS2 and the second plate line pass gates PLS2 away from the substrate 10; the second memory chain comprises a plurality of second sub-memory chains connected in series, the second sub-memory chain comprises a plurality of second memory cells connected in series, and the second sub-memory chain is connected in series between the second bit line pass gate BLS2 and the second plate line pass gate PLS2. The second bit line pass gate BLS2 is connected in series between the first bit line BL1 and the second sub-memory chain, and the plurality of second sub-memory chains are electrically connected to the same first bit line BL1 through the plurality of second bit line pass gates BLS2; the second plate line pass gate PLS2 is connected in series between the second plate line PL2 and the second sub-memory chain, and the plurality of second plate line pass gates PLS2 are electrically connected to the plurality of second plate lines PL2 one by one.

[0155] In some possible implementations, after step S140 and before step S150, a fourth dielectric layer can be formed on the second bit line pass gates BLS2 and the second plate line pass gates PLS2, and the second bit line pass gates BLS2 and the second plate line pass gates PLS2 are electrically isolated from the second memory chain by the fourth dielectric layer. Further, in order to realize that the second sub-memory chain of the second memory chain is connected in series between the second bit line pass gate BLS2 and the second plate line pass gate PLS2, a fourth via hole can be formed in the fourth dielectric layer, so that the second bit line pass gate BLS2 and the second plate line pass gate PLS2 formed after the fourth dielectric layer can be connected in series with the second sub-memory chain through the fourth via hole.

[0156] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative, but not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims.

Claims

1. A memory chip, characterized in that, include: Substrate; A first memory chain disposed on the substrate, the first memory chain including a plurality of first sub-memory chains connected in series, the first sub-memory chains including a plurality of first memory cells connected in series; A first bit line selector and a first plate line selector are stacked on the side of the first memory chain away from the substrate, and the first sub-memory chain is connected in series between the first bit line selector and the first plate line selector. A wiring layer is disposed on the side of the first bit line selector and the first board line selector facing away from the substrate. The wiring layer includes a first bit line and multiple first board lines. The first bit line selector is connected in series between the first bit line and the first sub-memory chain, and the multiple first sub-memory chains are electrically connected to the same first bit line through multiple first bit line selectors. The first board line selector is connected in series between the first board line and the first sub-memory chain, and the multiple first board line selectors are electrically connected to the multiple first board lines one-to-one.

2. The memory chip according to claim 1, characterized in that, The first memory chain is fabricated through a front-end process, while the first bit line selector, the first board line selector, and the wiring layer are all fabricated through a back-end process.

3. The memory chip according to claim 1 or 2, characterized in that, The first bit line selector includes a first sub-bit line selector and a second sub-bit line selector; the first board line selector includes a first sub-board line selector and a second sub-board line selector; and the first sub-memory chain is connected in series between the first sub-bit line selector and the first sub-board line selector. The first sub-memory chain includes at least three serially connected segmented memory chains. One segmented memory chain is connected in series between the first sub-bit line selector and the second sub-board line selector. Another segmented memory chain is connected in series between the first sub-board line selector and the second sub-bit line selector. The other segmented memory chains are connected in series between the second sub-bit line selector and the second sub-board line selector.

4. The memory chip according to claim 3, characterized in that, During the read / write phase, the plurality of first storage units in the first storage chain include a selected storage unit; If the usage time of the first storage chain is less than the preset time, then during the read / write phase, the first sub-bit line selector and the first sub-board line selector connected in series with the selected storage cell will work, while the second sub-bit line selector and the second sub-board line selector will not work. If the usage duration of the first storage chain is greater than or equal to the preset duration, then during the read / write phase, the first sub-bit line selector and the second sub-board line selector connected in series with the selected storage unit will operate, or the second sub-bit line selector and the first sub-board line selector connected in series with the selected storage unit will operate, or the second sub-bit line selector and the second sub-board line selector connected in series with the selected storage unit will operate.

5. The memory chip according to any one of claims 1-4, characterized in that, The memory chip also includes a comparator circuit, and the wiring layer also includes a second bit line. The comparator circuit is fabricated by a subsequent process. The input terminals of the comparison circuit are electrically connected to the second bit line and the first bit line, respectively; wherein, during the reading phase, the first bit line is used to input a storage signal to the comparison circuit, and the second bit line is used to input a reference voltage to the comparison circuit; the comparison circuit is used to determine whether the storage signal is a digital signal 0 or a digital signal 1 based on the reference voltage.

6. The memory chip according to any one of claims 1-4, characterized in that, The memory chip also includes a second memory chain, a second bit line selector, and a second board line selector; the wiring layer also includes multiple second board lines. The second bit line selector and the second board line selector are stacked on the side of the routing layer away from the first memory chain, and the second memory chain is stacked on the side of the second bit line selector and the second board line selector away from the first memory chain. The second memory chain includes a plurality of second sub-memory chains connected in series, and the second sub-memory chain includes a plurality of second memory cells connected in series; the second sub-memory chain is connected in series between the second bit line selector and the second board line selector; The second bit line selector is connected in series between the first bit line and the second sub-memory chain, and the plurality of second sub-memory chains are electrically connected to the same first bit line through the plurality of second bit line selectors; the second board line selector is connected in series between the second board line and the second sub-memory chain, and the plurality of second board line selectors are electrically connected to the plurality of second board lines one-to-one.

7. The memory chip according to claim 6, characterized in that, The memory chip also includes a third memory chain, a third bit line selector, a third board line selector, a fourth memory chain, a fourth bit line selector, and a fourth board line selector. The wiring layer also includes a second bit line, multiple third board lines, and multiple fourth board lines. The third storage chain is configured at the same layer as the first storage chain. The third storage chain includes multiple third sub-storage chains connected in series, and each third sub-storage chain includes multiple third storage units connected in series. The third bit line selector and the third board line selector are disposed on the same layer as the first bit line selector and the first board line selector, and the third sub-memory chain is connected in series between the third bit line selector and the third board line selector. The fourth storage chain is configured at the same layer as the second storage chain. The fourth storage chain includes multiple fourth sub-storage chains connected in series, and each fourth sub-storage chain includes multiple fourth storage units connected in series. The fourth bit line selector and the fourth board line selector are disposed on the same layer as the second bit line selector and the second board line selector, and the fourth sub-memory chain is connected in series between the fourth bit line selector and the fourth board line selector. The third bit line selector is connected in series between the second bit line and the third sub-memory chain, and the plurality of third sub-memory chains are electrically connected to the same second bit line through the plurality of third bit line selectors; the third board line selector is connected in series between the third board line and the third sub-memory chain, and the plurality of third board line selectors are electrically connected to the plurality of third board lines in a one-to-one correspondence; the fourth bit line selector is connected in series between the second bit line and the fourth sub-memory chain, and the plurality of fourth sub-memory chains are electrically connected to the same second bit line through the plurality of fourth bit line selectors; the fourth board line selector is connected in series between the fourth board line and the fourth sub-memory chain, and the plurality of fourth board line selectors are electrically connected to the plurality of fourth board lines in a one-to-one correspondence.

8. The memory chip according to claim 7, characterized in that, During the read phase, the plurality of first memory cells in the first memory chain include a first selected memory cell, which is used to input a first read signal to the comparator circuit via the first bit line, and the second bit line is used to input a first reference voltage to the comparator circuit; or... During the read phase, the plurality of third memory cells in the third memory chain include a third selected memory cell, which is used to input a second read signal to the comparator circuit via the second bit line, and the first bit line is used to input a second reference voltage to the comparator circuit.

9. The memory chip according to claim 7, characterized in that, During the read phase, the plurality of first memory cells in the first memory chain include a first selected memory cell, which is used to input a first read signal to the comparator circuit via the first bit line, and the second bit line is used to input a first reference voltage to the comparator circuit; or... During the read phase, the plurality of second memory cells in the second memory chain include a second selected memory cell, which is used to input a second read signal to the comparator circuit through the first bit line, and the second bit line is used to input a second reference voltage to the comparator circuit.

10. The memory chip according to claim 7, characterized in that, During the read phase, the plurality of second memory cells in the second memory chain include a second selected memory cell, which is used to input a first read signal to the comparator circuit via the first bit line, and the second bit line is used to input a first reference voltage to the comparator circuit; or... During the read phase, the plurality of fourth memory cells in the fourth memory chain include a fourth selected memory cell, which is used to input a second read signal to the comparator circuit via the second bit line, and the first bit line is used to input a second reference voltage to the comparator circuit.

11. The memory chip according to any one of claims 1-10, characterized in that, The first memory cell includes transistors and capacitors connected in parallel, and the wiring layer further includes word lines, a first gate line, and a second gate line; The word line is electrically connected to the gate of the transistor, the first terminal of the transistor is electrically connected to the first board line selector, and the second terminal of the transistor is electrically connected to the first bit line selector. The first gate line is electrically connected to the gate of the first bit line selector, and the second gate line is electrically connected to the gate of the first plate line selector.

12. A memory, characterized in that, It includes a controller and a memory chip as described in any one of claims 1-11, wherein the controller is used to control the memory chip to read and write data.

13. An electronic device, characterized in that, It includes a processor and the memory of claim 12, wherein the processor is configured to read and write data to the memory chip via a controller in the memory.

14. A method for fabricating a memory chip, characterized in that, include: A first memory chain is formed on a substrate, the first memory chain including a plurality of first sub-memory chains connected in series, the first sub-memory chains including a plurality of first memory cells connected in series; A first bit line selector and a first board line selector are formed on the first memory chain, and the first sub-memory chain is connected in series between the first bit line selector and the first board line selector. A wiring layer is formed on the side of the first bit line selector and the first board line selector away from the substrate. The wiring layer includes a first bit line and multiple first board lines. The first bit line selector is connected in series between the first bit line and the first sub-memory chain, and the multiple first sub-memory chains are electrically connected to the same first bit line through multiple first bit line selectors. The first board line selector is connected in series between the first board line and the first sub-memory chain, and the multiple first board line selectors are electrically connected to multiple first board lines one-to-one.

15. The method for fabricating a memory chip according to claim 14, characterized in that, The wiring layer also includes multiple second board lines; After forming a wiring layer on the side of the first line selector and the first board line selector away from the substrate, the chip fabrication method further includes: A second bit line selector and a second plate line selector are formed on the side of the plurality of second plate lines opposite to the substrate; A second memory chain is formed on the side of the second bit line selector and the second board line selector away from the substrate; the second memory chain includes a plurality of second sub-memory chains connected in series, and the second sub-memory chains include a plurality of second memory cells connected in series; the second sub-memory chains are connected in series between the second bit line selector and the second board line selector; the second bit line selector is connected in series between the first bit line and the second sub-memory chain, and the plurality of second sub-memory chains are electrically connected to the same first bit line through the plurality of second bit line selectors; the second board line selector is connected in series between the second board line and the second sub-memory chain, and the plurality of second board line selectors are electrically connected to the plurality of second board lines one-to-one.

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