Device for equalising attenuation of a signal by a transmission line and system for testing electronic devices

Abstract

A device for equalising attenuation of a signal by a radio-frequency, RF, chain, includes an input port (18;39;57), an output port (19;40;58), at least one series path interconnecting the input port (18;39;57) and the output port (19;40;58), and at least one shunt path (35;50,53;62,65) having an impedance of which the magnitude increases with frequency. At least one of the series paths and the shunt paths (35;50,53;62,65) includes at least one variable resistor (28,32,36;47,51,54;63,66). The device includes a device (13) for adjusting the respective resistance values of the variable resistors (28,32,36;47,51,54;63,66). Each series path interconnecting the input port (18;39;57) and the output port (19;40;58;70) is a series path including all nodes (20;41,42;59,60) connecting the respective at least one shunt paths (35;50,53;62,65) to the at least one series paths.

Description

[0001]M / ADVA-015-PC DEVICE FOR EQUALISING ATTENUATION OF A SIGNAL BY A TRANS- MISSION LINE AND SYSTEM FOR TESTING ELECTRONIC DEVICES The invention relates to a device for equalising attenuation of a signal by a ra- dio-frequency, RF, chain, including: an input port; an output port; at least one series path interconnecting the input port and the output port; at least one shunt path having an impedance of which the magnitude in- creases with frequency, wherein at least one of the series paths and the shunt paths includes at least one variable resistor; and a device for adjusting the respective resistance values of the variable resistors. The invention also relates to a system for testing electronic devices. There exist many use cases in which equipment arranged to process a signal is supplied with the signal by a radio-frequency chain (RF chain), i.e. a cascade of electronic components and sub-units which may include amplifiers, filters, mixers, attenuators and detectors, but generally includes at least one trans- mission line. Such chains contain elements of which the gain curves (in case of active elements) or ohmic loss curves (in case of passive elements) have a negative slope over frequency, also referred to as roll-off. These act cumula- tively to shape the overall gain or loss curve of the RF chain. The resulting negative roll-off can have detrimental effects on parameters important to theoverall system comprising the RF chain and the equipment. In case of a mod-ulated signal, the Error Vector Magnitude (EVM), also referred to as relative constellation error, may be larger than desired. Too much gain at low fre- quencies can generate parasitic coupling, leading to undesired oscillations. M / ADVA-015-PC Too much gain at lower frequencies can give rise to noise that mixers or other non-linear components can transfer into the frequency band at which the equipment operates. A designer of the equipment can provide the equipment with one or more equalisers to compensate for the negative roll-off. However, the designer of the equipment cannot be sure of the extent to which practical components of e.g. transmission lines supplying the signal to the equipment conform to specifications used to design the equaliser. In any event, custom- ers operating the equipment may not be using components, e.g. cables, withthe properties forming the basis for the equaliser design.US 2012 / 0043968 A1 discloses a test apparatus including a variable equaliser circuit. The test apparatus is connected to a Device Under Test (DUT) via a transmission line. The test apparatus judges the quality of the DUT or identi- fies defective portions based upon a signal output from the DUT. The variableequaliser circuit includes an equalising unit and a level sh ifter. The equalisingunit includes a first resistor R1, a second resistor R2, a first capacitor C1, asecond capacitor C2 and at least one shunt resistor Rs. The first resistor R1 isconfigured as a variable resistor, the resistance value of which is changeable. The first resistor R1 is arrange between an output terminal P2 of the variable equaliser circuit and a fixed voltage terminal (ground terminal). The first ca- pacitor C1 is arranged between the output terminal P2 and the ground termi- nal in parallel with the first resistor R1. The first capacitor C1 is configured as a variable capacitor, the capacitance of which is changeable. The second re-sistor R2 is arranged between an input terminal P1 of the equalising circuitand the output terminal P2. The second capacitor C2 is arranged between the input terminal P1 and the output terminal P2, in parallel with the second resis- tor R2. A third resistor R3 functioning as the shunt resistor Rs is arranged be- tween the input terminal P1 and a connection node N1 that connects one ter- minal of the second resistor R2 and one terminal of the second capacitor C2. The third resistor is preferably configured to have a resistance on the order offive to ten times the characteristic impedance of the transmission line to re-duce the effect of the variable equaliser circuit on impedance matching be- M / ADVA-015-PC tween a terminator of the test apparatus and the DUT. Before a test opera- tion, a user of the test apparatus can measure or calculate the amount of dis- tortion or the frequency characteristics of such distortion that occurs in the signal output from the DUT due to the effects of the transmission line or the like. Accordingly, the user can determine the circuit constants of the first re- sistor R1 and the first capacitor C1 so as to cancel out distortion that occurs due to the transmission line or the like. The variable equaliser circuit includes no inductor, which is stated to have the advantage that unintended oscillation does not occur. The known circuit is more properly to be regarded as a circuit comprising a tuneable filter, rather than as a tuneable equaliser. This is be- cause only the resistance in the shunt path is variable. A problem of theequalising unit is that, at high frequencies, the first and second capacitors C1,C2 determine the degree of attenuation. The attenuation profile of the equal- ising unit cannot therefore compensate for the roll-off of the chain comprising the transmission line. US 5,363,069 discloses an electronically tuneable equaliser circuit for RF appli- cations which can be fabricated either as a hybrid of microstrip transmission lines and surface-mounted resistors or as part of a completely monotlithic de- vice which includes microstrip transmission lines. The equaliser circuit com- prises a microstrip transmission line having at least one stub tuner extending transversely therefrom and further having a voltage-variable resistive means coupled to at least one stub tuner to de-Q that subtuner, thereby selectively determining an attenuation profile for the equaliser circuit. The disclosed em- bodiments have three lossy stub tuners which are connected to a main trans- mission line comprised of a plurality of microstrip lines coupled in series. It isstated that the dimensions and values of the microstrip lines and the resistorswere arrived at after optimising for a parabolic attenuation curve and In / Out voltage standing wave ratio (VSWR). In an embodiment, open-ended mi- crostrip lines providing the shunt paths with an open-circuit configuration are replaced with a short-circuit configuration. For this purpose, artificial transmis- sion lines are connected to microstrip lines that are in the other embodiment open-ended. Each artificial transmission line comprises inductive elements M / ADVA-015-PC that are coupled together in series to the microstrip line. Adjacent inductive elements are coupled together at a T-junction. To the remaining leg of each respective T-junction is coupled a corresponding Field Effect Transistor (FET). The sources of the FETs are grounded. By choosing how much of the artificial transmission line to short, the centre frequency of the attenuation profile can be shifted to accommodate a variety of attenuation profiles. It appears that the purpose of the voltage-variable resistive means is to compensate for the parabolic gain shapes of travelling-wave tubes over a very broad frequencyrange by providing an equaliser circuit that also has a parabolic attenuationprofile. Thus, this equaliser circuit is unsuitable for compensating for the typi- cal roll-off in an RF chain in at least the lower half of the frequency range for which the known equaliser circuit is designed. Furthermore, insofar as the re- sistors in each of the three stub tuners would be variable, they would be inde- pendently variable, making implementation relatively difficult. US 6,549,087 B1 discloses a variable equaliser. The variable equaliser is atwo-port bridge “T” network with variable top and bottom branches. The vari-able equaliser includes a main path that includes a signal in port that receives, for example, RF signals from a cable or network amplifier. The variable equal- iser also includes a signal out port that provides equalised RF signals to a ca- ble or amplifier. The main path is represented as two resistors that are cou- pled in series between the signal in port and the signal out port. The main path also includes DC blocking capacitors that are coupled in series in the main path. The variable equaliser further includes top and bottom resonator branches. The top resonator branch is coupled in parallel with the main path. The bottom resonator branch is coupled to a node of the main path. The vari- able equaliser includes variable top and bottom branches. The variable top branch includes parallel-coupled RC networks. The number of RC networks in the equaliser can be varied as necessary for a particular implementation and can include as few as one independently controlled branch or RC network. Each RC network independently controls one break point for the frequency re- sponse of the variable equaliser. In the embodiment, the resistors of the RC networks are implemented by PIN diodes that are each connected in series M / ADVA-015-PCwith capacitors. The resistance of these PIN diodes is selectively adjusted byvarying the current through the diodes. A problem of having multiple series paths, the main path and top resonator branch including one or more top reso- nator branches, is that the conductive traces forming the branches are not ideal, so that a practical implementation either deviates from an idealised de- sign or the design process becomes relatively complicated. There is in any event an increased risk of signal interference between branches. It is an object of the invention to provide a device and system of the typesmentioned above in the opening paragraph with which roll -off of an RF trans-mission chain is compensated for and that conforms to a relatively easily ob-tainable design with a low r isk of interference.The object is achieved according to a first aspect by a device that is character- ised in that each series path interconnecting the input port and the output port is a series path including all nodes connecting the respective at least one shunt paths to the at least one series paths. Nodes connecting the respective at least one shunt paths to the at least one series paths will be referred to hereinafter as main nodes, whereas other nodes on the series paths will be referred to as secondary nodes. At least one of the series paths and shunt paths includes at least one variable resistor. This means that at least one of the set of paths formed by the seriespaths and the shunt paths includes at least one variable resistor. It is possiblefor none of the series paths to include a variable resistor or none of the shunt paths to include a variable resistor or for both one or more series paths and one or more shunt paths to include a variable resistor. Variable in this case means that the resistance value is adjustable. This is to be distinguished from small variations due to changing environmental conditions. M / ADVA-015-PC The device includes an input port. The input port is for receiving the signal that has passed through the RF chain. The output port is for providing a sig- nal upon attenuation and filtering by the device. At least one series path in- terconnecting the input port and the output port. At least one of these seriespaths includes at least one main node. The device further includes at l eastone shunt path having an impedance of which the magnitude increases withfrequency. Thus, it is possible to compensate for roll -off by the RF chain.Equalisation and attenuation are provided by one device. The signal attenua- tion curves are curves increasing steadily with frequency. The curves can be scaled by the adjusting the respective resistance values of the at least one variable resistors. The device provided for adjusting the respective resistance values may do so automatically or in response to an external signal received from a signal interface or a signal received from a user interface, for example. This device may select the respective resistance values from a limited number of sets of values or adjust the values on a continuous or quasi-continuous scale, e.g. independently of one another. Because each series path interconnecting the input port and the output port is a series path including all nodes connecting the respective at least one shunt paths to the at least one series paths, there are no series paths bypassing oneor more main nodes. This makes the device according to the first aspect well -suited to high-frequency applications. The number of series paths betweennodes and between the input port and the output port is kept low. There arerelatively few, in embodiments no, nodes where signal interference among dif- ferent series paths can arise. The object is achieved according to a second aspect by a device that is char- acterised in that any series path interconnecting the input port and the output port and including at least one of the variable resistors is also a series path in- cluding all nodes connecting the respective at least one shunt paths to the at least one series paths. M / ADVA-015-PC The device according to the second aspect may also be an example of a device according to the first aspect. In devices according to the second aspect, there is a relatively low number of series paths connecting the same two nodes or the same two ports, and there are relatively few internal connections to ground. Because any series path interconnecting the input port and the out- put port and including at least one of the variable resistors is also a series path including all nodes connecting the respective at least one shunt paths to the at least one series paths, there are no series paths bypassing one or more main nodes that include a variable resistor. Thus, at least the characteristics of any such paths have properties that do not vary and can be accounted for in the design process. In an embodiment of the device according to the second aspect, the at least one series path and the at least one shunt path form a bridged-T network. The T-network includes a main node where the shunt path connects to the two branches forming the T-shape. A further path bypasses, i.e. bridges, that main node. This path will generally include an impedance having a reactive component, e.g. one or more components having a capacitance. The path will not, however, include any of the variable resistors. In an example of this embodiment, the bridged-T network is a symmetrical bridged-T network. Symmetry is defined with respect to the main node and the shunt path, through which the line of symmetry extends, with components in paths by- passing the main node being centred schematically on the line of symmetry. The network part to the left is the mirror image of that to the right in a sche- matic circuit diagram of the network. The symmetry may in particular be sym-metry both in terms of structure and in terms of nomina l component values.An effect of the symmetry is that predictable results are obtained . Further-more, simultaneous impedance matching at input and output is made possible. M / ADVA-015-PC Simultaneous impedance matching at both input and output makes the opera- tion of the device more predictable. This is because the resulting transmission coefficient depends on the source and load impedance, of which the value is known only nominally. The actual value may deviate. In an example of any of the embodiments in which the at least one series path and the at least one shunt path form a bridged-T network, the bridged-T net- work includes: a series path interconnecting the input port and the output port and in- cluding at least one of the variable resistors and the node connecting the shunt path to that series path; and at least one, e.g. only one, path interconnecting the input port and the output port and including a bypass path section bypassing the node, wherein the bypass path section of at least one of the paths including a bypass path section includes a capacitive component. As the frequency increases, the impedance of the series path bypassing thenode will decrease. Thus, the roll -off of the RF chain will be compensated forup to high frequencies. There will be almost no filtering, but in effect athrough-path for the signal. In this embodiment, there is at least one series path that interconnects the input port and the output port and includes at least one of the variable resistors and the node connecting the shunt path to that series path, i.e. a main node. There is at least one further series path that branches off from a secondary node to form a bypass path section, the bypass path section being a path section bypassing the main node and option- ally also the variable resistors, which bypass path section returns to a further secondary node. Further path sections may be shared with the series path in- cluding the variable resistors and extend from the secondary nodes to the in- put port and output port, respectively. It is noted that, where there is more than one path interconnecting the input port and the output port and including a bypass path section bypassing the node, there may be one or more such M / ADVA-015-PC path of which the bypass path section does not include a capacitive compo- nent. Hence, at least one, but not necessarily all, of the paths including a by- pass path section includes a capacitive component. In an embodiment of the device according to the first aspect or the device ac- cording to the second aspect, the at least one series path and the at least one shunt path form one of: a T-network and a Pi-network. The two types are essentially equivalent. The main nodes are at the intersec- tions of the (vertical) leg or legs – these are defined by the shunt paths - and the (horizontal) branches extending from the main node or nodes to the input and output port.In an example of this embodiment, the network is a symmetrical network.Again, symmetry is defined with respect to the main node and the shunt path, through which the line of symmetry extends. In a schematic representation ofthe network, the line of symmetry extends vertically – this is the direction par-allel to the shunt path or paths - through a central one of the main nodes where the number of main nodes is odd and between the central two main nodes where the number of main nodes is even. The network part to the leftis the mirror image of that to the right in the schematic representation of thenetwork. The symmetry may in particular be symmetry both in terms of struc- ture and in terms of nominal component values. An effect of the symmetry is that predictable results are obtained. Furthermore, simultaneous impedance matching is made possible. In an example of any of the embodiments in which the at least one series path and the at least one shunt path form one of: a bridged-T network; a T-network; and M / ADVA-015-PC a Pi-network, the network includes only passive components. Thus, there are no amplifiers in the network. This improves the suitability for use in radio frequency signal processing, since non-linear effects are limited. In an example of any of the embodiments in which the at least one series path and the at least one shunt path form one of: a bridged-T network; a T-network; and a Pi-network, the network forms an integrated filter and variable attenu- ator. In an example of this embodiment, the filter is an all-poles filter, e.g. a sym- metrical all-poles filter. Examples include Butterworth and Chebyshev filters.In an example of any embodiment in which the filter is an all -poles filter, e.g.a symmetrical all-poles filter, the filter is a Chebyshev filter.This type of filter is relatively well -suited to high-frequency applications.In an example of any of the embodiments in which the at least one series path and the at least one shunt path form one of: a bridged-T network; a T-network; and a Pi-network, and the network forms an integrated filter and variable at- tenuator, the filter is a fixed filter. This means that the filter coefficients are fixed in value. The process of de- signing the filter and thus the network is relatively simple for this embodi- ment. M / ADVA-015-PC In an example of any of the embodiments in which the at least one series path and the at least one shunt path form one of: a bridged-T network; a T-network; and a Pi-network, and the network forms an integrated filter and vari- able attenuator, the filter is a third-order filter. Because the order of the filter determines the number of branches of the net- work, this filter is relatively simple to implement. The number of branches is kept relatively low. In an embodiment of the device according to the first aspect or the device ac- cording to the second aspect, the shunt paths are at most two in number. This embodiment allows the desired filter characteristics to be achieved at minimal complexity. In an embodiment of the device according to the first aspect or the device ac- cording to the second aspect, the or each shunt path includes a series connec- tion of at least one of the variable resistors and at least one reactive compo- nent having an inductance. The impedance of the shunt path increases with frequency, providing the re- quired filter characteristic. An embodiment of the device according to the first aspect or the device ac- cording to the second aspect comprises at least one arrangement of a first branch and a second branch, connected in parallel to the first branch, wherein the first branch includes at least one of the variable resistors and the second branch includes at least one component having a capacitance, each of the first and second branches being included in at least one respective one of the se- ries paths. M / ADVA-015-PC At low signal frequencies, the impedance of the first branch, including at least one of the variable resistors, is lower, and the network becomes an attenua- tor. At high frequencies, the first branch is effectively short-circuited by the second branch. This provides the required equalisation. In the simplest im- plementation, the or each arrangement of a first branch and a second branch that is connected in parallel to the first branch forms an RC network. According to a third aspect, the system for testing electronic devices according to the invention comprises: a test device arranged to receive and evaluate a signal originating from a Device Under Test, DUT; a transmission line for transmitting the signal between the DUT and the test device; and a device according to at least one of the first and second aspects, ar- ranged to compensate for attenuation of the signal by at least the transmis- sion line. The transmission line need not be connected directly to the DUT and the test device, but forms part of the RF chain between the two. The invention will be explained in further detail with reference to the accom- panying drawings, in which: Fig. 1 is a very schematic diagram of a system for testing electronic devices;Fig. 2 is a diagram showing attenuation and gain curves of components of anRF chain and of the complete RF chain without equalisation or attenua- tion; Fig. 3 is a diagram showing equalising curves of an adjustable device for equalising attenuation of a signal by the RF chain at various attenuation values; Fig. 4 is a diagram of a network comprised in a first device for equalising at- tenuation of a signal by the RF chain; M / ADVA-015-PC Fig. 5 is a diagram of an equivalent network comprised in a second device for equalising attenuation of a signal by the RF chain; Fig. 6 is a diagram of a network comprised in a third device for equalising at- tenuation of a signal by the RF chain; and Fig. 7 is a diagram of a network comprised in a fourth device for equalising at- tenuation of a signal by the RF chain A system 1 (Fig. 1) for testing a Device Under Test (DUT 2) comprises an Auto- mated Test Equipment unit (ATE unit 3) and a cable 4 for transmitting signals between the ATE unit 3 and the DUT 2. The cable 4 may be a co-axial cable,e.g. having an impedance of which the magnitude has a nominal value of 50 ^.The DUT 2 may comprise a Very Large-Scale Integrated (VLSI) circuit device, for example. The ATE unit 3 comprises a cable interface 5, switch 6 and amplifier 7. The cable 4 and cable interface , switch 6 and amplifier 7 form an RF chain. The amplifier 7 has an amplifier gain curve 8 (Fig. 2). The switch 6 has a switch attenuation curve 9. The cable 4 has a cable attenuation curve 10. The RF chain has an RF chain gain curve 11, where, for simplicity, it has been assumed that the cable interface 5 has a negligible influence on the signal. It will be appreciated that the RF chain gain curve 11 has a downward slope, the gaindecreasing with increasing signal frequency. This is referred to as roll -off.The ATE unit 3 comprises a device for equalis ing attenuation of a signal by theRF chain so as to compensate for the roll -off. The device for equalising atten-uation of a signal by the RF chain comprises an equaliser unit 12 and a control device 13 for adjusting resistance values of variable resistors comprised in anetwork comprised in the equaliser unit 12. The control device 13 may be con-figured to fulfil further functions in the ATE unit 3 that are unrelated to theequaliser function. M / ADVA-015-PCUpon being processed by the equaliser unit 12 the signal originating from theDUT 2 is passed to a test device 14 configured to receive and evaluate the sig- nal. In the illustrated embodiment, the result is communicated via an output interface 15, which may be a user interface or a signal interface for providing a signal to an external data processing device such as an industrial Personal Com- puter (PC), for example. The test device 14 of the illustrated embodiment is configured to generate test signals, the switch 6 determining which signal is carried by the cable 4. As mentioned, the control device 13 is configured to adjust resistance values ofvariable resistors comprised in a network comprised in the equaliser unit 12. Inthis manner, one of several attenuation settings can be selected. Resulting equalising curves are shown in Fig. 3. It can be seen that the attenuation curves scale according to the attenuation settings. On a logarithmic scale, as depicted, the negative gain increases (approaches zero) continuously with increasing fre- quency, such that the signal is attenuated less at higher frequencies. This com- pensates for the roll-off of the RF chain (Fig. 2).In the illustrated embodiment, an input interface 16 in communication with thecontrol device 13 is provided for selecting the attenuation settings. The input interface 16 may comprise a user interface, for example. The equaliser unit 12 comprises a network of only passive components that forms an integrated filter and variable attenuator. The filter is in each case an all-poles filter, e.g. a Butterworth or Chebyshev filter. The filter may in partic- ular be designed as a third-order Chebyshev filter. To produce the equalising curves shown in Fig. 3, it suffices that the filter is a fixed filter, i.e. the filter coefficients are not variable. This in turn means that the reactive components of the network have fixed nominal capacitance or inductance values as the case may be. The networks only comprise variable resistors having variable nominal resistance values. M / ADVA-015-PC In an alternative embodiment (not shown or described in more detail here), at least one component or group of components of the network has a variable reactance and the device for equalising attenuation of a signal by the RF chain also comprises a device, such as the control device 13, for adjusting the respec- tive reactance values. A first device for equalising attenuation of a signal by the RF chain comprises a first network 17 (Fig. 4). The first network 17 is a T-network. The first net- work 17 comprises an input port 18, an output port 19. Series paths intercon- necting the input port 18 and the output port 19 include one main node 20 and four secondary nodes 21,22,23,24. The first network 17 includes a first RC network 25 and a second RC network 26. The first RC network 25 extends between first and second secondary nodes 21,22. A first RC network branch 27 extending between the first and second secondary nodes 21,22 includes a first variable resistor 28 having a nom- inal resistance R1. A second RC network branch 29 extending between the first and second secondary nodes 21,22 includes a first capacitor 30 having a nomi- nal capacitance C1. The first and second RC network branches 27,29 are ar- ranged in parallel. The second RC network 26 extends between third and fourth secondary nodes 23,24. A third RC network branch 31 extending between the third and fourth secondary nodes 23,24 includes a second variable resistor 32 having anominal resistance R1 equal to that of the first variable resistor 28. A fourth RCnetwork branch 33 extending between the third and fourth secondary nodes 23,24 includes a second capacitor 34 having a nominal capacitance C1 equal to that of the first capacitor 30. The third and fourth RC network branches 31,33 are arranged in parallel. M / ADVA-015-PC A shunt path 35 branches off from the main node 20 and includes a series con- nection of a variable shunt resistor 36 having a resistance R2 and an inductor 37 having an inductance L1. Because there are two paths between the first and second secondary nodes 21,22 and two paths between the third and fourth secondary nodes 23,24,there are four series paths interconnecting the input port 18 and the outputport 19. They all include the main node 20 connecting the shunt path 35 to the series paths. Conversely, each and any series path that interconnects the input port 18 and the output port 19 also includes all main nodes 20, i.e. all nodes connecting a respective one of the shunt paths 35 comprised in the first net- work 17 to at least one of the series paths interconnecting the input port 18 and the output port 19. This helps to minimise interference between signals con- veyed along different series paths. The series paths can have approximately equal lengths, simplifying the design process. The first network 17 has an odd number of main nodes 20 between the input port 18 and the output port 19 and is symmetrical in structure with respect to the central main node 20. Because of this, and because the first and second variable resistors 28,32 have the same nominal resistance value R1and the first and second capacitors 30,34 have the same nominal capacitance C1, the first network 17 is a symmetrical network and integrates a symmetrical filter. It is noted that the control device 13 is configured to adjust the nominal resistance value R1, so as to keep both the first and second variable resistors 28,32 at the same nominal resistance value R1. Although other types of filter such as Butterworth or Bessel filters could be used, the filter used here as an example is designed as a third-order Chebyshev filter. The number of filter coefficients gxis therefore three, first two g0,g1being equal in value. The values follow from an amount of ripple chosen as a starting point for the design, typically corresponding to a desired amount of ripple. The values of the inductance L1 and the capacitance C1 follow from the filter coefficients, a M / ADVA-015-PC cut-off frequency f0 of the filter and the fact that the network and the compo- nents of the RF chain are impedance-matched at a nominal impedance R0 e.g. with a magnitude of 50 ^^ The resistance values R1,R2 set by the control device 13 follow from a particulardesired linear attenuation A, shown next to the equalising curves in Fig. 3, andthe value R0. The values for the first network 17 are obtainable analytically as follows: A second network 38 (Fig. 5) is equivalent to the first network 17, being the equivalent ^-network. The second network 38 comprises an input port 39 and an output port 40. Se- ries paths interconnecting the input port 39 and the output port 40 include a first and second main node 41,42 and two secondary nodes 43,44. The second network 38 includes one RC network 45. M / ADVA-015-PC The RC network 45 extends between the first and second secondary nodes 43,44. A first RC network branch 46 extending between the first and second secondary nodes 43,44 includes a first variable resistor 47 having a nom- inal resistance R3. A second RC network branch 48 extending between the first and second secondary nodes 43,44 includes a capacitor 49 having a nominal capacitance C2. The first and second RC network branches 46,48 are arranged in parallel. A first shunt path 50 branches off from a first main node 41 and includes a series connection of a first variable shunt resistor 51 having a nominal re- sistance R4 and a first inductor 52 having a nominal inductance L2. A second shunt path 53 branches off from a second main node 42 and includesa series connection of a second variable shunt resistor 54 having a nominalresistance R4and a second inductor 55 having a nominal inductance L2. That is to say, the first and second variable shunt resistors 51,54 have the same nomi- nal resistance R4, which the control device 13 is arranged to adjust so as to keep them the same. The first and second inductors 52,55 have the same nom- inal inductance L2, which in this embodiment is invariable. An alternative em- bodiment in which this value is variable in tandem is conceivable. Because there are two paths between the first and second secondary nodes 43,44, there are two series paths interconnecting the input port 39 and the output port 40. They all include the first and second main node 41,42 re- spectively connecting the first and second shunt paths 50,53 to the series paths.Conversely, each and any series path that interconnects the input port 39 andthe output port 40 also includes all main nodes 41,42 i.e. all nodes connecting a respective one of the shunt paths 50,53 comprised in the second network 38to at least one of the series paths interconnecting the input port 39 and theoutput port 40. This helps to minimise interference between signals conveyed along different series paths. The series paths can have approximately equal lengths, simplifying the design process. M / ADVA-015-PC The second network 38 has an even number of main nodes 41,42 between the input port 39 and the output port 40 and is symmetrical in structure with respect to the network part located between the central main nodes 41,42. Because of this, and because the first and second variable shunt resistors 51,54 have the same nominal resistance value R4and the first and second inductors 52,55 have the same nominal inductance L2, the second network 38 is a symmetrical net- work and integrates a symmetrical filter. The filter is designed as a third-order Chebyshev filter. The number of filter coefficients gxis therefore three, first two g0,g1being equal in value. The valuesfollow from the desired amount of ripple. The values of the inductance L2 andthe capacitance C3 follow from the filter coefficients, a cut-off frequency f0 of the filter and the fact that the network and the components of the RF chain are impedance-matched at a nominal impedance R0e.g. with a magnitude of 50 ^^ One way of calculating these values R3,R4,L2,C2is to convert the val- ues R1,R2,L1,C1obtained for the first network 17 as follows: ^ ^^^ ^ ^ (6) ^^(7) ^ ^^^^ ^^^(8)^^ ^ ^ ^^ ^ ^^ (9).A third network 56 (Fig. 6) is slightly different from the first and second net- works 17,38. The third network 56 is also a symmetrical ^-network. M / ADVA-015-PC The third network 56 comprises an input port 57 and an output port 58. Oneseries path interconnects the input port 57 and the output port 58 and includesfirst and second main nodes 59,60, but no secondary nodes. The third network 56 includes one quarter-wave transformer 61. The quarter-wave transformer 61 extends between the first and second main nodes 59,60. A first shunt path 62 branches off from a first main node 59 and includes a series connection of a first variable shunt resistor 63 having a nominal re- sistance R5and a first inductor 64 having a nominal inductance L3. A second shunt path 65 branches off from a second main node 60 and includesa series connection of a second variable shunt resistor 66 having a nominalresistance R5and a second inductor 67 having a nominal inductance L3. That is to say, the first and second variable shunt resistors 63,66 have the same nomi- nal resistance R5, which the control device 13 is arranged to adjust so as to keep them the same. The first and second inductors 64,67 have the same nom- inal inductance L3, which in this embodiment is invariable. An alternative em- bodiment in which this value is variable in tandem is conceivable. There is only one series path interconnecting the input port 57 and the outputport 58. This path includes the first and second main nodes 59,60 respectivelyconnecting the first and second shunt paths 62,65 to the series path. Con-versely, each and any series path that interconnects the input port 57 and theoutput port 58 also includes all main nodes 59,60 i.e. all nodes connecting a respective one of the shunt paths 62,65 comprised in the third network 56 to atleast one of the series paths interconnecting the input port 57 and the outputport 58. The third network 56 has an even number of main nodes 59,60 between the input port 57 and the output port 58 and is symmetrical in structure with respectto the network part located between the central main nodes 59,60. Because of M / ADVA-015-PC this, and because the first and second variable shunt resistors 63,66 have the same nominal resistance value R5 and the first and second inductors 64,67 have the same nominal inductance L3, the third network 56 is a symmetrical network and integrates a symmetrical filter. The filter is designed as a third-order Chebyshev filter. The number of filter coefficients gx is therefore three, the first two g0,g1 being equal in value. The values follow from the desired amount of ripple. For a given linear attenuation A and given filter coefficients, the values of the resistance R5 and inductance L3 can be determined iteratively through simulation. A fourth network 68 (Fig. 7) differs more fundamentally from the net- works 17,38,56 discussed so far. The fourth network 68 comprises an input port 69 and an output port 70. Oneseries path interconnecting the input port 69 and the output port 70 includes amain node 71 and two secondary nodes 72,73. Another series path is a bypass path comprising a bypass path section 74 that bypasses the main node 71, in- cluding only the secondary nodes 72,73. The bypass path that comprises the bypass path section 74 bypassing the main node 71 includes a first impedance 75. The series path including the main node 71 includes a first variable resistor 76 and a second variable resistor 77, both having a nominal resistance value R6. That is to say, the first and second variable resistors 76,77 have the same nominal resistance R6, which the control device 13 is arranged to adjust so as to keep them the same. A shunt path 78 branches off from the main node 71 and includes a second impedance 79. The series paths (including the bypass path that comprises the bypass path section 74) and the shunt path 78 form a bridged T-network. M / ADVA-015-PCIt will be apparent that, in contrast to the other networks 17,38,56, not everyseries path interconnecting the input port 69 and the output port 70 includes all the main nodes 71. However, any series path interconnecting the input port 69 and the output port 70 and including at least one of the variable resistors 76,77 is also a series path including all main nodes 71 interconnecting the respectiveshunt paths to the series paths. This is because the first impedance 75 onlyincludes resistance components having a fixed nominal resistance value. Here, fixed means only that the value is non-adjustable. The value may be fixed but for variations with temperature or other environmental factors. The number of paths is kept relatively low even if the variable resistors 76,77 are implemented as stepped controlled resistors (ladder resistors), i.e. a number of resistors con-nected in series, one or more of which can be selectively short -circuited bymeans of switches, or a parallel circuit of which each branch includes a seriesconnection of a switch and a resistor. There is no need to take account of the various path lengths and how to avoid that they give rise to interference in each of the configurations that the switches implementing the stepped controlled re- sistors can effect. The fourth network 68 has an odd number of main nodes 71 between the input port 69 and the output port 70 and is symmetrical in structure with respect to the central main nodes 71. Because of this, and because the first and second variable resistors 76,77 have the same nominal resistance value R6, the fourth network 68 is a symmetrical network and integrates a symmetrical filter. The filter is an all-poles filter with a symmetrical structure. Here, it will be assumed that the filter is a fixed filter, i.e. the filter coefficients are fixed. This implies that, in addition to the resistance components of the first and second impedances 75,79, the reactive components have fixed nominal values (possibly but for variations due to changing environmental factors such as temperature). In other embodiments, the reactive components may be adjustable like the re- sistance values R6 of the variable resistors 76,77. M / ADVA-015-PC The first impedance 75 includes a capacitive component (not shown), either only a capacitive component or an RC network. In the latter case, there would be two paths interconnecting the secondary nodes 72,73 and bypassing the main node 71. One path includes the capacitor having a capacitance C3. The other includes a resistor having a resistance R7The second impedance 79 includes an inductive component (not shown) having an inductance L4, either on its own or in series with a resistor having a resistance R8 to form an LR network. Values can be obtained from the filter coefficient g0, a cut-off frequency fpof the filter and the fact that the network and the components of the RF chain are impedance-matched at a nominal impedance R0 e.g. with a magnitude of 50 ^: Where the first impedance 75 includes only a capacitive component with a nom- inal capacitance C3and the shunt path 78 includes only an inductive component with a nominal inductance L4, the following equations pertain: M / ADVA-015-PC In each of the four networks 17,38,56,68 described above, any variable resistor can be implemented as at least one of the following: - a rheostat; - a (digital) potentiometer; - a trimmer; - a photoresistor; - a diode, e.g. a PIN diode or a Schottky diode; - a Field Effect Transistor (FET), a Complementary Metal Oxide Semicon- ductor (CMOS) transistor or a similar device that provides a voltage-con- trolled or current controlled electrically conductive channel; or- a stepped controlled resistor (resistor ladder). A first example of the latter comprises a number of resistors connected in series, one or more of which can be selectively short-circuited by means of switches. A second example comprises a parallel circuit of which each branch includes a series connection of a switch and a resistor. The invention is not limited to the embodiments described above, which may be varied within the scope of the accompanying claims. Although the example of a system comprising an ATE unit 3 has been used as a use case of the device for equalising attenuation of an RF chain, other use cases are conceivable, in- cluding for example cable television equipment. In an embodiment, the device for equalising attenuation of a signal by an RF chain is connectable to a selected one of multiple RF chains by a switch and the device for adjusting the respective resistance values of the variable resistors is configured to select a set of resistance values from sets of values associated with settings of the switch. This embodiment can be implemented in the sys- tem 1 described above by use of an appropriate cable interface 5, switch 6 and control device 13 for example. M / ADVA-015-PC Instead of a network forming an integrated fixed filter and variable attenuator, a network of which also the filter coefficients are adjustable may be used. List of reference numerals 1 - System 2 - Device Under Test (DUT) 3 - Automated Test Equipment (ATE) unit 4 - Cable 5 - Cable interface 6 - Switch 7 - Amplifier 8 - Amplifier gain curve 9 - Switch attenuation curve 10 - Cable attenuation curve 11 - RF chain gain curve 12 - Equaliser unit 13 - Control device 14 - Test device 15 - Output interface 16 - Input interface 17 - First network 18 - Input port 19 - Output port 20 - Main node 21 - First secondary node 22 - Second secondary node 23 - Third secondary node 24 - Fourth secondary node 25 - First RC network 26 - Second RC network 27 - First RC network branch 28 - First variable resistor M / ADVA-015-PC 9 - Second RC network branch 0 - First capacitor 1 - Third RC network branch 2 - Second variable resistor 3 - Fourth RC network branch 4 - Second capacitor 5 - Shunt path 6 - Variable shunt resistor 7 - Inductor 8 - Second network 9 - Input port 0 - Output port 1 - First main node 2 - Second main node 3 - First secondary node 4 - Second secondary node 5 - RC network 6 - First RC network branch 7 - First variable resistor 8 - Second RC network branch 9 - Capacitor 0 - First shunt path 1 - First variable shunt resistor 2 - First inductor 3 - Second shunt path 4 - Second variable shunt resistor 5 - Second inductor 6 - Third network 7 - Input port 8 - Output port 9 - First main node 0 - Second main node 1 - Quarter-wave transformer M / ADVA-015-PC 27 2 - First shunt path 3 - First variable shunt resistor 4 - First inductor 5 - Second shunt path 6 - Second variable shunt resistor 7 - Second inductor 8 - Fourth network 9 - Input port 0 - Output port 1 - Main node 2 - First secondary node 3 - Second secondary node 4 - Bypass path section 5 - First impedance 6 - First variable resistor 7 - Second variable resistor 8 - Shunt path 9 - Second impedance

Claims

M / ADVA-015-PC Claims 1. Device for equalising attenuation of a signal by a radio-frequency, RF, chain, including: an input port (18;39;57); an output port (19;40;58); at least one series path interconnecting the input port (18;39;57)and the output port (19;40;58); at least one shunt path (35;50,53;62,65) having an impedance of which the magnitude increases with frequency, wherein at least one of the series paths and the shunt paths (35;50,53;62,65) includes at least one variable resis- tor (28,32,36;47,51,54;63,66); and a device (13) for adjusting the respective resistance values of the variable resistors (28,32,36;47,51,54;63,66), characterised in that each series path interconnecting the input port (18;39;57) andthe output port (19;40;58;70) is a series path including all nodes (20;41,42;59,60) connecting the respective at least one shunt paths (35;50,53;62,65) to the at least one series paths.

2. Device for equalising attenuation of a signal by a radio-frequency, RF, chain, e.g. device according to claim 1, including: an input port (18;39;57;69) an output port (19;40;58;70); at least one series path interconnecting the input port (18;39;57;69) and the output port (19;40;58;70); at least one shunt path (35;50,53;62,65;78) having an impedance of which the magnitude increases with frequency ,wherein at least one of the series paths and the shunt paths (35;50,53;62,65;78) includes at least one variable resis- tor (28,32,36;47,51,54;63,66;76,77); andM / ADVA-015-PC a device (13) for adjusting the respective resistance values of the variable resistors (28,32,36;47,51,54;63,66;76,77), characterised in that any series path interconnecting the input port (18;39;57;69) and the output port (19;40;58;70) and including at least one of the variable resistors (28,32,36;47,51,54;63,66;76,77) is also a series path including all nodes (20;41,42;59,60;71) connecting the respective at least one shunt paths (35;50,53;62,65;78) to the at least one series paths.

3. Device according to claim 2, wherein the at least one series path and the at least one shunt path (78) form a bridged-T network (68).

4. Device according to claim 3, wherein the bridged-T network (68) is a symmetrical bridged-T network (68).

5. Device according to claim 3 or 4, wherein the bridged-T network (68) includes: aseries path interconnecting the input port (69) and the outputport (70) and including at least one of the variable resistors (76,77) and the node (71) connecting the shunt path (78) to that series path; and at least one, e.g. only one, path interconnecting the input port (69) and the output port (70) and including a bypass path sec- tion (74) bypassing the node (71), wherein the bypass path section (74) of at least one of the paths including a bypass path section (74) includes a capacitive compo- nent (75).

6. Device according to claim 1 or 2, wherein the at least one series path and the at least one shunt path (35;50,53;62,65) form one of: a T-network (17) andM / ADVA-015-PC a Pi-network (38;56).

7. Device according to claim 6, wherein the network (17;38;56) is a symmetrical net- work (17;38;56).

8. Device according to any one of claims 3-7, wherein the network (17;38;56;68) includes only passive compo- nents.

9. Device according to any one of claims 3-8, wherein the network (17;38;56;68) forms an integrated filter and variable attenuator.

10. Device according to claim 9, wherein the filter is an all-poles filter, e.g. a symmetrical all-poles filter.

11. Device according to claim 10, wherein the filter is a Chebyshev filter.

12. Device according to any one of claims claim 9-11, wherein the filter is a fixed filter.

13. Device according to any one of claims 9-12. wherein the filter is a third-order filter.

14. Device according to any one of the preceding claims, wherein the shunt paths (35;50,53;62,65;78) are at most two in number.M / ADVA-015-PC 15. Device according to any one of the preceding claims, wherein the or each shunt path (35;50,53;62,65;78) includes a series connection of at least one of the variable resis- tors (28,32,36;47,51,54;63,66;76,77) and at least one reactive compo- nent (37;52,55;64,67;79) having an inductance.

16. Device according to any one of the preceding claims, comprising at least one arrangement (25,26;45) of a first branch (27,31;46) and a second branch (29,33;48), connected in paral- lel to the first branch (27,31;46), wherein the first branch (27,31;46) includes at least one of the variable resistors (28,32,36;47,51,54;63,66;76,77) and the second branch (29,33;48) includes at least one component (30,34;49) having a capacitance, each of the first and second branches (27,29,31,33;46,48) being included in at least one respective one of the series paths.

17. System for testing electronic devices, comprising: atest device (14) arranged to receive and evaluate a signal origi-nating from a Device Under Test, DUT (2); a transmission line (4) for transmitting the signal between the DUT (2) and the test device (14); and a device (12,13) according to any one of the preceding claims, ar- ranged to compensate for attenuation of the signal by at least the trans- mission line (4).

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