Heterojunction back-polished battery and manufacturing method therefor

Abstract

A manufacturing method for a heterojunction back-polished battery, comprising: performing gettering treatment on a silicon wafer; removing a phosphosilicate glass layer from the back surface of the silicon wafer; and performing texturing treatment on the silicon wafer. Further provided is a heterojunction back-polished battery, comprising: a silicon wafer, the front surface of the silicon wafer successively comprising a first amorphous silicon layer and a first TCO film layer in the direction facing away from the back surface of the silicon wafer, and the back surface of the silicon wafer successively comprising a second amorphous silicon layer and a second TCO film layer in the direction facing away from the front surface of the silicon wafer. The front surface of the heterojunction back-polished battery comprises a pyramid-shaped structure, and the back surface of the heterojunction back-polished battery comprises a pit-shaped structure. In the provided manufacturing method for a heterojunction back-polished battery, providing the step of removing the phosphosilicate glass layer can increase optical path lengths on back surfaces of heterojunction batteries so as to promote the secondary absorption of light in the batteries, improving the photoelectric performance of the heterojunction batteries.

Description

Heterojunction back-polished solar cell and its preparation method

[0001] Cross-referencing

[0002] This disclosure claims priority to Chinese Patent Application No. 202410573723.4, filed on May 10, 2024, entitled "Heterojunction Back Polished Battery and Preparation Method Thereof", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of solar cell technology, and in particular to a method for preparing a heterojunction back-polished solar cell, and a heterojunction back-polished solar cell prepared by the method. Background Technology

[0004] Heterojunction (HJT) is a type of N-type solar cell with a bifacial symmetrical structure, generating electricity from both sides with high bifaciality and low light decay rate. N-type monocrystalline silicon wafers are more suitable for thinning. Thinning silicon wafers not only reduces the manufacturing cost of the main material, but also reduces bulk recombination, lowers the saturation current, and increases the turn-on voltage.

[0005] Compared to other existing solar cells, heterojunction (HJT) cells have a simpler fabrication process, higher process stability, and lower fabrication temperature; however, they require higher equipment investment, stricter process requirements, and have higher non-silicon manufacturing costs. Therefore, there is a need to further improve the efficiency of heterojunction cells and reduce their manufacturing costs. Summary of the Invention

[0006] This disclosure provides a method for preparing a heterojunction back-polished solar cell, and a heterojunction back-polished solar cell prepared by the method.

[0007] In a first aspect, embodiments of this disclosure provide a method for preparing a heterojunction back-polished solar cell, comprising: performing a gettering process on a silicon wafer; removing the phosphosilicate glass layer on the front side of the silicon wafer; and performing a texturing process on the silicon wafer.

[0008] In some embodiments, the step of removing the phosphosilicate glass layer on the front side of the silicon wafer includes: spraying a water film onto the back side of the silicon wafer; and removing the phosphosilicate glass layer on the front side of the silicon wafer using an etching solution.

[0009] In some embodiments, the step of removing the phosphosilicate glass layer on the front side of the silicon wafer by means of an etching solution includes: placing the silicon wafer in a mixed solution of HF and HCl to react and remove the phosphosilicate glass layer.

[0010] In some embodiments, in the mixed solution of HF and HCl, the concentration of HF is 5-15 wt% and the concentration of HCl is 1-10 wt%.

[0011] In some embodiments, the silicon wafer is placed in a mixed solution of HF and HCl for reaction for 1-5 minutes.

[0012] In some embodiments, in the step of reacting the silicon wafer in a mixed solution of HF and HCl, the silicon wafer is transported using rollers at a speed of 2-5 m / min.

[0013] In some embodiments, the step of removing the phosphosilicate glass layer on the front side of the silicon wafer further includes: adding the mixed solution of HF and HCl during the reaction of the silicon wafer in a mixed solution of HF and HCl.

[0014] In some embodiments, the step of supplementing the mixed solution of HF and HCl includes: supplementing each 4500-5500 half-wafers with a mixed solution of HF and HCl accounting for 0.03%-0.08% of the total volume.

[0015] In some embodiments, the step of texturing the silicon wafer includes: during the texturing process, placing the silicon wafer in a mixed solution of texturing additive and KOH for reaction at a temperature of 75-90°C; wherein the concentration of the texturing additive is 0.5-1.3 wt% and the concentration of KOH is 0.03-0.08 wt%.

[0016] In a second aspect, this disclosure provides a heterojunction back-polished solar cell, which is prepared by the preparation method described in the first aspect of this disclosure.

[0017] In some embodiments, the heterojunction back-polished solar cell includes: a silicon wafer; the front side of the silicon wafer includes a first amorphous silicon layer and a first TCO film layer in sequence along the direction away from the silicon wafer; the back side of the silicon wafer includes a second amorphous silicon layer and a second TCO film layer in sequence along the direction away from the silicon wafer; the front side of the heterojunction back-polished solar cell includes a pyramid-shaped structure; the back side of the heterojunction back-polished solar cell includes a pit-shaped structure.

[0018] In some embodiments, the depth of the pit-type structure on the back side of the heterojunction back-polished battery is 500-1000 nm.

[0019] In some embodiments, the reflectivity of the back surface of the heterojunction back-polished cell is greater than or equal to 45%.

[0020] In the method for fabricating a heterojunction back-polished solar cell according to the present disclosure, a step of removing the phosphosilicate glass layer is added after the gettering process. The phosphosilicate glass layer on the front side of the silicon wafer is selectively removed, and the back side of the silicon wafer is polished, which improves the reflectivity of the back side of the silicon wafer. It also facilitates the deposition of the amorphous silicon layer and the TCO film layer, improves the passivation effect, and reduces the overall weight of the silicon wafer, thereby improving the efficiency of the heterojunction back-polished solar cell. Attached Figure Description

[0021] Figure 1 is a flowchart of a method for preparing a heterojunction back-polished solar cell according to an embodiment of this disclosure.

[0022] Figure 2A is a schematic diagram of the pre-cleaning of silicon wafers in an embodiment of this disclosure.

[0023] Figure 2B is a schematic diagram of the gettering process on the silicon wafer in an embodiment of this disclosure.

[0024] Figure 2C is a schematic diagram of removing the phosphosilicate glass layer on the front side of the silicon wafer in an embodiment of this disclosure.

[0025] Figure 2D is a schematic diagram of texturing silicon wafers in an embodiment of this disclosure.

[0026] Figure 2E is a schematic diagram of amorphous silicon deposition on a silicon wafer in an embodiment of this disclosure.

[0027] Figure 2F is a schematic diagram of TCO film deposition on a silicon wafer in an embodiment of this disclosure.

[0028] Figure 2G is a schematic diagram of metallization of silicon wafers in an embodiment of this disclosure.

[0029] Figure 3 is a schematic diagram of the structure of a heterojunction back-polished solar cell according to an embodiment of this disclosure.

[0030] Figure 4 is a schematic diagram of a heterojunction cell fabricated according to a comparative example.

[0031] Figure 5 is an enlarged view of the back side of the silicon wafer prepared according to Example 1 of this disclosure.

[0032] Figure 6 is an enlarged view of the back side of the silicon wafer prepared according to Comparative Example 1. Detailed Implementation

[0033] To enable those skilled in the art to better understand the technical solutions of this disclosure, the technical solutions of this disclosure will be described in detail below with reference to the accompanying drawings.

[0034] Exemplary embodiments will be described more fully below with reference to the accompanying drawings; however, these exemplary embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0035] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0036] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0038] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0039] In a first aspect, this disclosure provides a method for fabricating a heterojunction back-polished solar cell, referring to FIG1, comprising: S1, performing a gettering process on a silicon wafer; S2, removing the phosphosilicate glass (PSG) layer on the front side of the silicon wafer; and S3, performing a texturing process on the silicon wafer.

[0040] In the fabrication process of heterojunction solar cells, high-temperature gettering of silicon wafers generates PSG layers on both the front and back sides of the wafer. These PSG layers prevent the reaction between alkali and silicon. In some related technologies, HJT cell fabrication methods include pre-cleaning, gettering, texturing, amorphous silicon deposition, TCO deposition, and electrode printing.

[0041] In this embodiment, before texturing the silicon wafer, a step of removing the PSG layer on the front side of the silicon wafer is added, selectively removing the phosphosilicate glass layer on the front side of the silicon wafer. This results in a pyramidal textured surface on the front side of the silicon wafer after texturing, while the back side is polished, increasing the reflectivity of the back side of the silicon wafer. This promotes secondary light reflection and increases the long-wavelength absorption of the battery. After etching and polishing the back side of the silicon wafer, the surface is smoother, reducing surface dangling bonds and thus reducing surface recombination. This facilitates the subsequent deposition of amorphous silicon layers and TCO films, improving passivation and thereby increasing the efficiency of the HJT battery. By adding the step of removing the PSG layer on the front side of the silicon wafer for single-sided texturing, the overall weight of the silicon wafer can also be reduced.

[0042] In the embodiments of this disclosure, the silicon wafer is subjected to gettering treatment, which is mainly used to reduce contamination during the processing and manufacturing of the silicon wafer, reduce minority carrier recombination centers in the silicon wafer, and thus improve the performance of the silicon wafer.

[0043] In some embodiments, prior to the gettering process, the silicon wafer is further subjected to a pre-cleaning process to remove impurities and damage layers from the surface of the silicon wafer, and to polish the front and back sides of the silicon wafer.

[0044] In some embodiments, after texturing the silicon wafer, the process further includes: depositing an amorphous silicon layer to significantly improve minority carrier lifetime by utilizing the passivation effect of amorphous silicon; depositing a TCO film layer to effectively increase carrier collection; and metallizing the positive and negative electrodes of the battery by screen printing to form ohmic contacts.

[0045] Figures 2A to 2G are schematic diagrams of the process flow for preparing heterojunction back-polished solar cells in the embodiments of this disclosure.

[0046] As shown in Figure 2A, silicon wafer 1 undergoes pre-cleaning treatment; as shown in Figure 2B, silicon wafer 1 undergoes high-temperature gettering treatment, generating PSG layers 2 on the front and back sides of silicon wafer 1; as shown in Figure 2C, the PSG layer on the front side of silicon wafer 1 is removed; as shown in Figure 2D, silicon wafer 1 undergoes texturing treatment, forming a pyramid-shaped structure on the front side of silicon wafer 1, while the back side of silicon wafer 1 is polished; as shown in Figure 2E, a first amorphous silicon layer 31 and a second amorphous silicon layer 32 are deposited on the surface of silicon wafer 1. Specifically, on the front side of silicon wafer 1, an intrinsic amorphous silicon (ia-Si:H) layer 311 and a doped N-type amorphous silicon or N-type nanocrystalline silicon (na-Si:H or n-nc-Si:H) layer 312 are deposited sequentially; on the back side of silicon wafer 1, an intrinsic amorphous silicon (ia-Si:H) layer 321 and a doped P-type amorphous silicon or P-type nanocrystalline silicon (pa-Si:H or p-nc-Si:H) layer 322; as shown in Figure 2F, TCO film layer 4 is deposited on the surface of silicon wafer 1; as shown in Figure 2G, metal electrode 5 is prepared by screen printing.

[0047] In the embodiments disclosed herein, an amorphous silicon layer can be deposited on the surface of a silicon wafer using the PEVD method.

[0048] In the embodiments disclosed herein, a TCO film layer can be deposited on the surface of a silicon wafer using the PVD method.

[0049] This disclosure does not impose any special limitations on how to remove the PSG layer on the front side of the silicon wafer.

[0050] In some embodiments, the step of removing the phosphosilicate glass layer on the front side of the silicon wafer using a chain-type PSG removal process includes: spraying a water film onto the back side of the silicon wafer; and removing the phosphosilicate glass layer on the front side of the silicon wafer using an etching solution.

[0051] In the method described in this disclosure, there are no special limitations on the etching solution used to remove the PSG layer on the front side of the silicon wafer, as long as it can achieve the purpose of removing the PSG layer on the front side.

[0052] In some embodiments, the step of removing the phosphosilicate glass layer on the front side of the silicon wafer by means of an etching solution includes: placing the silicon wafer in a mixed solution of HF and HCl to react and remove the phosphosilicate glass layer.

[0053] In some embodiments, in the mixed solution of HF and HCl, the concentration of HF is 5-15 wt% and the concentration of HCl is 1-10 wt%.

[0054] In some embodiments, in the mixed solution of HF and HCl, the concentration of HF is 7-9 wt% and the concentration of HCl is 2-5 wt%.

[0055] In some embodiments, when removing the PSG layer on the front side of the silicon wafer, the silicon wafer is placed in a mixed solution of HF and HCl and reacted at room temperature.

[0056] In some embodiments, the silicon wafer is placed in a mixed solution of HF and HCl for reaction for 1-5 minutes.

[0057] In some embodiments, the time to remove the PSG layer on the front side of the silicon wafer is 3-4 minutes.

[0058] In some embodiments, in the step of reacting the silicon wafer in a mixed solution of HF and HCl, the silicon wafer is transported using rollers at a speed of 2-5 m / min.

[0059] In some embodiments, when removing the PSG layer on the front side of the silicon wafer, the silicon wafer is transported by rollers at a speed of 3.9 m / min.

[0060] In some embodiments, the step of removing the phosphosilicate glass layer on the front side of the silicon wafer further includes: adding the mixed solution of HF and HCl during the reaction of the silicon wafer in a mixed solution of HF and HCl.

[0061] In this embodiment of the disclosure, the addition of a mixed solution of HF and HCl ensures that the concentrations of HF and HCl in the mixed solution meet the requirements, thereby ensuring the effectiveness of removing the PSG layer on the front side of the silicon wafer.

[0062] In some embodiments, the step of supplementing the mixed solution of HF and HCl includes: supplementing each 4500-5500 half-wafers with 0.03%-0.08% of the total volume of the mixed solution of HF and HCl.

[0063] In some embodiments, for every 5000 half tablets, a mixed solution of 0.05% of the total volume of HF and HCl is added, and the concentration ratio of HF and HCl in the added mixed solution is consistent with the initial concentration ratio.

[0064] In some embodiments, the step of texturing the silicon wafer includes: during the texturing process, placing the silicon wafer in a mixed solution of texturing additive and KOH for reaction at a temperature of 75-90°C for a time of 450-500 s, wherein the concentration of the texturing additive is 0.5-1.3 wt% and the concentration of KOH is 0.03-0.08 wt%.

[0065] In some embodiments, the concentration of the flocking additive is 0.8-1.3 wt%, and the concentration of KOH is 0.05-0.08 wt%.

[0066] In some embodiments, the concentration of the flocking additive is 1.1-1.3 wt%, and the concentration of KOH is 0.06-0.08 wt%.

[0067] In some embodiments, the silicon wafer is placed in a mixed solution of texturing additive and KOH for reaction at a temperature of 85°C for 480 seconds.

[0068] In some embodiments, the silicon wafer is placed in a mixed solution of texturing additive and KOH for reaction at a temperature of 80°C.

[0069] In this embodiment of the disclosure, a step of removing the PSG layer on the front side of the silicon wafer is added before the texturing process. During the texturing process, a higher concentration of texturing additive is used to increase protection. Furthermore, the reaction temperature can be reduced, for example, to 80°C.

[0070] Secondly, embodiments of this disclosure provide a heterojunction back-polished battery, which is prepared by the preparation method described in the first aspect of this disclosure.

[0071] Thirdly, this disclosure provides a heterojunction back-polished solar cell. Referring to FIG3, the heterojunction back-polished solar cell includes: a silicon wafer 1; the front side of the silicon wafer 1 includes a first amorphous silicon layer 31 and a first TCO film layer 41 in sequence along the direction away from the silicon wafer 1; the back side of the silicon wafer 1 includes a second amorphous silicon layer 32 and a second TCO film layer 42 in sequence along the direction away from the silicon wafer 1; the front side of the heterojunction back-polished solar cell includes a pyramid-shaped structure; the back side of the heterojunction back-polished solar cell includes a pit-shaped structure.

[0072] As shown in Figure 3, the heterojunction back-polished solar cell also includes a metal electrode 5.

[0073] In some embodiments, the depth of the pit-shaped structure on the back of the heterojunction back-polished battery is 500-1000 nm.

[0074] In some embodiments, the depth of the pit-shaped structure on the back of the heterojunction back-polished battery is 600-900 nm, for example, the depth of the pit-shaped structure is 800 nm.

[0075] In some embodiments, the reflectivity of the back surface of the heterojunction back-polished cell is greater than or equal to 45%.

[0076] To enable those skilled in the art to more clearly understand the technical solutions of this disclosure, the technical solutions of this disclosure will be described in detail below through specific embodiments:

[0077] Example 1

[0078] The silicon wafers are pre-cleaned and impermeable, then loaded into baskets of 240 wafers each, and transported from the baskets to the PSG conveyor on the chain conveyor. During the roller transport process, a water film is sprayed on the front of the silicon wafers before they continue to be transported at a speed of 3.8 m / min.

[0079] After the water film was sprayed, the silicon wafer was placed in a mixed solution of 15wt% HF and 10wt% HCl and reacted at room temperature for 2 minutes.

[0080] The silicon wafers are gradually removed from the acid bath and diluted in the water bath via roller transport at a speed of 3.8 m / min.

[0081] After being transported by rollers, the silicon wafers undergo dewatering roller treatment and air knife drying. They are then conveyed by belt to a basket for texturing.

[0082] Texturing adopts a full-groove processing method, with 4 baskets / groove and 240pcs / basket. The silicon wafers are loaded to the loading position through the basket.

[0083] The silicon wafer was placed in a PRE bath and reacted at 65°C for 150 seconds in a mixed solution of KOH concentration of 0.1 wt% and H2O2 concentration of 3 wt%.

[0084] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0085] The silicon wafer was placed in a TEX bath and reacted at 90°C for 450 seconds in a mixed solution of texturing additive concentration of 1.3 wt% and KOH concentration of 0.08 wt%.

[0086] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0087] The silicon wafer was placed in a POST tank and reacted at 65°C for 240 seconds in a mixed solution of KOH (0.4 wt%) and H2O2 (4 wt%).

[0088] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0089] The silicon wafer was placed in a CP bath and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at 20°C for 120 seconds.

[0090] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0091] The silicon wafer was placed in a FINAL bath and reacted at room temperature for 150 seconds in a mixed solution of 8 wt% HF and 3 wt% HCl.

[0092] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0093] The silicon wafer is placed in a slow pull groove and held at room temperature for 150 seconds.

[0094] The silicon wafers were placed in a drying chamber and kept at 95°C for 630 seconds.

[0095] The material feeding process is completed and then processed into flocking.

[0096] After texturing, the side of the silicon wafer that has undergone PSG removal will develop a pyramidal texture, while the side that has not undergone PSG removal will be relatively flat.

[0097] Then, amorphous silicon deposition and TCO film deposition are performed, followed by screen printing metallization and curing sintering to complete the process preparation of HJT solar cells.

[0098] Example 2

[0099] The silicon wafers are pre-cleaned and impermeable, then loaded into baskets of 240 wafers each, and transported from the baskets to the PSG conveyor on the chain conveyor. During the roller transport process, a water film is sprayed on the front of the silicon wafers before they continue to be transported at a speed of 3.8 m / min.

[0100] After the water film was sprayed, the silicon wafer was placed in a mixed solution with a HF concentration of 5 wt% and an HCl concentration of 1 wt%, and the reaction was carried out at room temperature for 5 minutes.

[0101] The silicon wafers are gradually removed from the acid bath and diluted in the water bath via roller transport at a speed of 3.8 m / min.

[0102] After being transported by rollers, the silicon wafers undergo dewatering roller treatment and air knife drying. They are then conveyed by belt to a basket for texturing.

[0103] Texturing adopts a full-groove processing method, with 4 baskets / groove and 240pcs / basket. The silicon wafers are loaded to the loading position through the basket.

[0104] The silicon wafer was placed in a PRE bath and reacted at 65°C for 150 seconds in a mixed solution of KOH concentration of 0.1 wt% and H2O2 concentration of 3 wt%.

[0105] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0106] The silicon wafer was placed in a TEX bath and reacted at 75°C for 500 seconds in a mixed solution of texturing additive concentration of 0.5 wt% and KOH concentration of 0.03 wt%.

[0107] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0108] The silicon wafer was placed in a POST tank and reacted at 65°C for 240 seconds in a mixed solution of KOH (0.4 wt%) and H2O2 (4 wt%).

[0109] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0110] The silicon wafer was placed in a CP bath and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at 20°C for 120 seconds.

[0111] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0112] The silicon wafer was placed in a FINAL bath and reacted at room temperature for 150 seconds in a mixed solution of 8 wt% HF and 3 wt% HCl.

[0113] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0114] The silicon wafer is placed in a slow pull groove and held at room temperature for 150 seconds.

[0115] The silicon wafers were placed in a drying chamber and kept at 95°C for 630 seconds.

[0116] The material feeding process is completed and then processed into flocking.

[0117] After texturing, the side of the silicon wafer that has undergone PSG removal will develop a pyramidal texture, while the side that has not undergone PSG removal will be relatively flat.

[0118] Then, amorphous silicon deposition and TCO film deposition are performed, followed by screen printing metallization and curing sintering to complete the process preparation of HJT solar cells.

[0119] Example 3

[0120] The silicon wafers are pre-cleaned and impermeable, then loaded into baskets of 240 wafers each, and transported from the baskets to the PSG conveyor on the chain conveyor. During the roller transport process, a water film is sprayed on the front of the silicon wafers before they continue to be transported at a speed of 3.8 m / min.

[0121] After the water film was sprayed, the silicon wafer was placed in a mixed solution with a HF concentration of 10 wt% and an HCl concentration of 5 wt%, and the reaction was carried out at room temperature for 3 minutes.

[0122] The silicon wafers are gradually removed from the acid bath and diluted in the water bath via roller transport at a speed of 3.8 m / min.

[0123] After being transported by rollers, the silicon wafers undergo dewatering roller treatment and air knife drying. They are then conveyed by belt to a basket for texturing.

[0124] Texturing adopts a full-groove processing method, with 4 baskets / groove and 240pcs / basket. The silicon wafers are loaded to the loading position through the basket.

[0125] The silicon wafer was placed in a PRE bath and reacted at 65°C for 150 seconds in a mixed solution of KOH concentration of 0.1 wt% and H2O2 concentration of 3 wt%.

[0126] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0127] The silicon wafer was placed in a TEX bath and reacted at 82°C for 480 seconds in a mixed solution of texturing additive concentration of 1 wt% and KOH concentration of 0.05 wt%.

[0128] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0129] The silicon wafer was placed in a POST tank and reacted at 65°C for 240 seconds in a mixed solution of KOH (0.4 wt%) and H2O2 (4 wt%).

[0130] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0131] The silicon wafer was placed in a CP bath and reacted in a mixed solution of 8 wt% HF and 3 wt% HCl at 20°C for 120 seconds.

[0132] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0133] The silicon wafer was placed in a FINAL bath and reacted at room temperature for 150 seconds in a mixed solution of 8 wt% HF and 3 wt% HCl.

[0134] Place the silicon wafer in a water bath and leave it at room temperature for 120 seconds.

[0135] The silicon wafer is placed in a slow pull groove and held at room temperature for 150 seconds.

[0136] The silicon wafers were placed in a drying chamber and kept at 95°C for 630 seconds.

[0137] The material feeding process is completed and then processed into flocking.

[0138] After texturing, the side of the silicon wafer that has undergone PSG removal will develop a pyramidal texture, while the side that has not undergone PSG removal will be relatively flat.

[0139] Then, amorphous silicon deposition and TCO film deposition are performed, followed by screen printing metallization and curing sintering to complete the process preparation of HJT solar cells.

[0140] Comparative Examples 1-3

[0141] HJT solar cells were prepared according to the methods in Examples 1-3, with the only difference being that the step of removing the phosphosilicate glass layer on the front side of the silicon wafer was omitted between the gettering and texturing processes.

[0142] The silicon wafers in the above embodiments and comparative examples were weighed before and after processing, and their weight loss was calculated. After texturing, the reflectivity of the front and back sides of the silicon wafers was measured. The results are shown in Table 1.

[0143] Table 1

[0144] As shown in Figure 3, in the above embodiment, the HJT solar cell has an intrinsic amorphous silicon (ia-Si:H) layer, a doped N-type amorphous silicon or N-type nanocrystalline silicon (na-Si:H or n-nc-Si:H) layer, and a TCO film layer on the front side of the silicon wafer (C-Si), and a TCO film layer on the back side of the silicon wafer. The HJT solar cell also includes a metal electrode (Ag fingers), and the silicon wafer has a pyramidal structure only on the front side. As shown in Figure 4, in the comparative examples above, the HJT solar cells fabricated have the following layers on the front side of the silicon wafer (C-Si): an intrinsic amorphous silicon (ia-Si:H) layer, a doped N-type amorphous silicon or N-type nanocrystalline silicon (na-Si:H or n-nc-Si:H) layer, and a TCO film layer. The back side of the silicon wafer also includes an intrinsic amorphous silicon (ia-Si:H) layer, a doped P-type amorphous silicon or P-type nanocrystalline silicon (pa-Si:H or p-nc-Si:H) layer, and a TCO film layer. The HJT solar cells also include metal electrodes (Ag fingers). Both the front and back sides of the silicon wafer have a pyramidal structure. Scanning electron microscopy was used to photograph the back side of the texturized silicon wafer. Figures 5 and 6 are magnified views of the back side of the silicon wafer in Example 1 and Comparative Example 1, respectively. In Example 1, the back side of the silicon wafer has a pitted structure and does not form a pyramidal textured surface; in Comparative Example 1, the back side of the silicon wafer has a pyramidal structure and forms a pyramidal textured surface.

[0145] As can be seen from the data in the table and the accompanying figures, compared with the comparative example, the silicon wafers obtained according to the preparation method of this disclosure have reduced overall weight. After single-sided texturing on the silicon wafer, a pyramidal textured surface is formed on the front side, and the back side is polished, which improves the back reflectivity. The increased back reflectivity promotes secondary reflection of light. The textured front side and polished back side of the silicon wafer constitute a perfect light-trapping structure, increasing the absorption of the solar cell in the long wavelength range. The polishing of the back side of the silicon wafer makes the surface of the silicon wafer smoother, reduces surface dangling bonds and surface recombination, which is more conducive to the subsequent deposition of amorphous silicon and TCO, improves the passivation effect, and enhances the efficiency of HJT cells.

[0146] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A method for preparing a heterojunction back-polished solar cell, comprising: The silicon wafer is subjected to gettering treatment; Remove the phosphosilicate glass layer on the front side of the silicon wafer; The silicon wafer is then texturized.

2. The preparation method according to claim 1, wherein, The steps for removing the phosphosilicate glass layer on the front side of the silicon wafer include: A water film is sprayed onto the back of the silicon wafer; The phosphorus silica glass layer on the front side of the silicon wafer is removed by etching solution.

3. The preparation method according to claim 2, wherein, The step of removing the phosphosilicate glass layer on the front side of the silicon wafer using an etching solution includes: The silicon wafer is placed in a mixed solution of HF and HCl to react and remove the phosphosilicate glass layer.

4. The preparation method according to claim 3, wherein, In a mixed solution of HF and HCl, the concentration of HF is 5-15 wt% and the concentration of HCl is 1-10 wt%.

5. The preparation method according to claim 3, wherein, The silicon wafer is placed in a mixed solution of HF and HCl for reaction for 1-5 minutes.

6. The preparation method according to claim 5, wherein, In the step of reacting the silicon wafer in a mixed solution of HF and HCl, the silicon wafer is transported by rollers at a speed of 2-5 m / min.

7. The preparation method according to claim 3, wherein, The step of removing the phosphosilicate glass layer on the front side of the silicon wafer further includes: During the reaction process in which the silicon wafer is placed in a mixed solution of HF and HCl, the mixed solution of HF and HCl is added.

8. The preparation method according to claim 7, wherein, The steps for adding a mixed solution of HF and HCl include: For every 4500-5500 half-wafers, add 0.03%-0.08% of the total volume of a mixed solution of HF and HCl.

9. The preparation method according to any one of claims 1 to 8, wherein, The steps of texturing the silicon wafer include: During the texturing process, the silicon wafer is placed in a mixed solution of texturing additive and KOH for reaction at a temperature of 75-90℃; wherein the concentration of the texturing additive is 0.5-1.3wt% and the concentration of KOH is 0.03-0.08wt%.

10. A heterojunction back-polished solar cell, wherein the heterojunction back-polished solar cell is prepared by the preparation method according to any one of claims 1 to 9.

11. The heterojunction back-polished solar cell according to claim 10, wherein, The heterojunction back-polished solar cell includes: Silicon wafers; The front side of the silicon wafer includes, in sequence, a first amorphous silicon layer and a first TCO film layer along the direction away from the silicon wafer; The back side of the silicon wafer includes, in sequence, a second amorphous silicon layer and a second TCO film layer in the direction away from the silicon wafer; The front side of the heterojunction back-polished solar cell includes a pyramid-shaped structure; The back side of the heterojunction back-polished solar cell includes a pitted structure.

12. The heterojunction back-polished solar cell according to claim 11, wherein, The depth of the pit-shaped structure on the back of the heterojunction back-polished solar cell is 500-1000 nm.

13. The heterojunction back-polished solar cell according to claim 12, wherein, The reflectivity of the back surface of the heterojunction back-polished solar cell is greater than or equal to 45%.

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