Power conversion device

Abstract

A multilevel converter (1) comprises a plurality of bit cells (31-35) that output DC voltages different from one another. Each of the bit cells (31-35) includes switching elements (Q1-Q4) configured to charge or discharge a power storage element (C) by performing a switching operation in response to a control command from a control device (7). The control device (7) repeatedly outputs a plurality of switching patterns in which control commands for the bit cells (31-35) are arranged in time series. The switching patterns are temporally symmetrical for each cycle, and are determined such that the length of a charging period and the length of a discharging period for the power storage element (C) are equal.

Description

Power Conversion Device

[0001] The present disclosure relates to a power conversion device.

[0002] The power conversion device disclosed in International Publication No. 2010 / 010710 (Patent Document 1) includes an inverter circuit configured by connecting in series the AC sides of one or more single-phase inverters, each having a semiconductor switching element and a DC voltage source, and connecting the AC sides in series to the output of a DC power supply, so that the sum of the outputs of the single-phase inverters is superimposed on the output of the DC power supply.

[0003] International Publication No. 2010 / 010710 International Publication No. 2009 / 116273 Japanese Patent Application Laid-Open No. 2022-119256

[0004] A converter configured to be able to output multilevel voltages is called a "multilevel converter." The multilevel converter includes a DC power supply circuit, an output node, and a plurality of bit cells connected in series between the DC power supply circuit and the output node. Each of the plurality of bit cells includes one or more switching elements.

[0005] In order to improve the power conversion efficiency of a power conversion device including a multilevel converter, it is desirable to reduce the losses (switching losses of multiple bit cells) of the multilevel converter.

[0006] The present disclosure has been made to solve the above-mentioned problems, and one of the objects of the present disclosure is to reduce losses in a multilevel converter in a power conversion device including a multilevel converter.

[0007] A power conversion device according to an aspect of the present disclosure includes a multilevel converter and a control device that controls the multilevel converter. The multilevel converter includes a DC power supply circuit, an output node, and a plurality of bit cells that are connected in series between the DC power supply circuit and the output node and output different DC voltages. Each of the plurality of bit cells includes a storage element and one or more switching elements configured to charge or discharge the storage element by performing a switching operation in accordance with a control command from the control device. The control device repeatedly outputs a plurality of switching patterns in which control commands for the plurality of bit cells are arranged in a chronological order. The plurality of switching patterns are determined to be symmetrical in time for each period and such that the length of a charging period and the length of a discharging period of the storage element are equal.

[0008] According to the present disclosure, in a power conversion device including a multilevel converter, it is possible to reduce losses in the multilevel converter.

[0009] 1 is a diagram illustrating an example of the overall configuration of a power conversion device according to a first embodiment. FIG. 2 is a diagram illustrating the operation of a linear circuit. FIG. 3 is a diagram illustrating the switching operation of four switching elements included in each bit cell. FIG. 4 is a diagram illustrating output voltages from a power supply circuit and a plurality of bit cells included in a multilevel converter. FIG. 5 is a diagram illustrating a pattern period of a multilevel converter in a first comparative example. FIG. 6 is a diagram illustrating a pattern period of a multilevel converter in a second comparative example. FIG. 7 is a diagram illustrating a pattern period of a multilevel converter according to the first embodiment. FIG. 8 is a time chart illustrating a pattern period of a multilevel converter according to the first embodiment. FIG. 9 is a diagram illustrating switching control of bit cells in a modified example of the first embodiment. FIG. 10 is a time chart illustrating a pattern period of a multilevel converter according to a second embodiment. FIG. 11 is a diagram illustrating a specific example of how to set synchronized adjustment timings of a first bit cell to a third bit cell. FIG. 12 is a diagram illustrating PWM control using a triangular wave. FIG. 13 is a diagram illustrating PWM control using a trapezoidal wave.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0011] First Embodiment <Overall Configuration> Fig. 1 is a diagram showing an example of the overall configuration of a power conversion device according to a first embodiment. The power conversion device 100 includes a multilevel converter 1. The multilevel converter 1 includes a power supply circuit 2, a plurality of bit cells 31 to 35, and an output node 4. The power conversion device 100 further includes a linear circuit 5, a current sensor 6, and a control device 7. Note that Fig. 1 shows a configuration in which the multilevel converter 1 includes five bit cells. However, the number of bit cells is not particularly limited as long as it is two or more.

[0012] The power supply circuit 2 is a DC power supply circuit that performs switching operations in accordance with control commands from the control device 7. In this example, the power supply circuit 2 has a circuit configuration generally called a T-type Neutral Point Clamped (NPC) circuit. More specifically, the power supply circuit 2 includes a positive power supply 21, a negative power supply 22, switching elements 231 to 234, and diodes 241 to 244.

[0013] The positive power supply 21 and the negative power supply 22 are connected in series. A reference potential point V0, which is the neutral point between the positive power supply 21 and the negative power supply 22, is grounded.

[0014] Each of the switching elements 231 to 234 is a semiconductor switching element, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). Each of the switching elements 231 to 234 may also be an insulated gate bipolar transistor (IGBT). Each of the diodes 241 to 244 is, for example, a free wheel diode (FWD). The specific configuration of the switching elements 231 to 234 and the diodes 241 to 244 is not particularly limited as long as they have the function of blocking current in one direction and preventing (blocking) the application of voltage. The same applies to the other switching elements and diodes described below.

[0015] The switching elements 231 and 232 are connected in parallel to the positive power supply 21 and the negative power supply 22. The switching elements 231 and 232 are connected in series in the same direction to form a leg. A connection point M between the upper arm (switching element 231) and the lower arm (switching element 232) of the leg is connected to a first terminal T1 (described later) of the bit cell 31. The diodes 241 and 242 are connected in anti-parallel to the switching elements 231 and 232, respectively.

[0016] The switching elements 233 and 234 are connected in series in opposite directions between the reference potential point V0 and the connection point M. The switching elements 233 and 234 function as bidirectional switches that clamp the voltage between the reference potential point V0 and the connection point M. The diodes 243 and 244 are connected in antiparallel to the switching elements 233 and 234, respectively.

[0017] The power supply circuit 2 configured in this manner can output three levels: positive, negative, or 0 (zero) with respect to the potential of the reference potential point V0. However, the power supply circuit 2 is not limited to a T-type NPC circuit as long as it has a circuit configuration that can output three levels with respect to the reference potential point V0.

[0018] Bit cells 31 to 35 are connected in series between power supply circuit 2 and output node 4. Because bit cells 31 to 35 have a common circuit configuration, the configuration of bit cell 31 will be described below as a representative example. Bit cell 31 is, for example, a full-bridge circuit that performs switching operations in accordance with control commands (switching commands) from control device 7. More specifically, bit cell 31 includes switching elements Q1 to Q4, diodes D1 to D4, a storage element C, a first terminal T1, a second terminal T2, and a voltage sensor VS.

[0019] The switching element Q1 and the switching element Q2 are connected in series to form a first leg. A connection point M1 between the upper arm (switching element Q1) and the lower arm (switching element Q2) of the first leg is connected to a first terminal T1. Diodes D1 and D2 are connected in antiparallel to the switching elements Q1 and Q2, respectively.

[0020] The switching element Q3 and the switching element Q4 are connected in series to form a second leg. A connection point M2 between the upper arm (switching element Q3) and the lower arm (switching element Q4) of the second leg is connected to the second terminal T2. Diodes D3 and D4 are connected in anti-parallel to the switching elements Q3 and Q4, respectively.

[0021] The first leg and the second leg are connected in parallel to a storage element C. The storage element C is typically a capacitor. However, the storage element C may be another type of element, such as a secondary battery (e.g., a lithium ion battery) or an electric double layer capacitor.

[0022] The voltage sensor VS detects the voltage V1 of the first terminal T1 relative to the second terminal T2 (hereinafter also referred to as the "terminal voltage") and outputs the detected value to the control device 7.

[0023] In the bit cell 31 configured in this manner, the inter-terminal voltage V1 takes one of three levels: positive, negative, and 0 (bypass), depending on the voltage of the storage element C. The same applies to the other bit cells 32 to 35. A voltage determined by the combination of the supply voltage from the power supply circuit 2 (hereinafter also referred to as the "power supply voltage") and the inter-terminal voltages of each of the plurality of bit cells 31 to 35 (the sum of the supply voltage and the five inter-terminal voltages) is output from the output node 4. This allows the multi-level converter 1 to output a voltage of any level in a stepped manner from the output node 4. Hereinafter, the level of the voltage output from the output node 4 will be referred to as the "output voltage level."

[0024] The linear circuit 5 is connected to the output node 4 of the multilevel converter 1. The linear circuit 5 functions as a variable resistor by performing a linear operation (an operation of outputting a voltage proportional to an input voltage). In this example, the linear circuit 5 includes switching elements 51 and 52. The switching elements 51 and 52 are connected in opposite directions to each other. Each of the switching elements 51 and 52 is, for example, an N-type MOSFET.

[0025] 2 is a diagram for explaining the operation of the linear circuit 5. The horizontal axis represents the voltage (drain-source voltage) of the switching elements 51 and 52. The vertical axis represents the current (drain current) flowing through the switching elements 51 and 52.

[0026] The linear circuit 5, which includes an N-type MOSFET, has a linear region and a saturation region. The control device 7 controls the gate-source voltage Vgs of the linear circuit 5 (switching elements 51, 52) so that the linear circuit 5 operates linearly as described above. Controlling the gate-source voltage Vgs makes it possible to adjust the drain-source current. This allows the linear circuit 5 to bear the difference voltage between the voltage at the output node 4 and the voltage to be supplied to the load 900 while maintaining the current at a desired value. The linear circuit 5 is configured to output to the load 900 any voltage (e.g., a sinusoidal voltage or a constant voltage) commanded by a control command from the control device 7. The load 900 is not particularly limited as long as it is a device that consumes (or may store) the power supplied from the multilevel converter 1.

[0027] 1 , a voltage corresponding to the difference between the input voltage to the linear circuit 5 (the voltage at the output node 4 of the multilevel converter 1) and the output voltage from the linear circuit 5 (the voltage commanded by the control command from the control device 7) is applied to the linear circuit 5. The smaller the voltage applied to the linear circuit 5, the smaller the loss occurring in the linear circuit 5. By increasing the number of bit cells included in the multilevel converter 1 and thereby allowing the multilevel converter 1 to output a stepped voltage with high resolution, the loss in the power conversion device 100 can be reduced.

[0028] The current sensor 6 is connected between the linear circuit 5 and the load 900. The current sensor 6 detects the current I supplied from the linear circuit 5 to the load 900, and outputs the detected value to the control device 7.

[0029] The control device 7 includes a processor 71 and a memory 72. The processor 71 is an arithmetic processing device such as a central processing unit (CPU) or a microprocessing unit (MPU). The memory 72 includes a volatile storage device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), and a nonvolatile storage device such as a hard disk drive (HDD), a solid state drive (SSD), or a flash memory. The memory 72 stores a system program including an operating system (OS), a control program including computer-readable code, and various parameters for controlling the multilevel converter 1 and the linear circuit 5. The processor 71 reads the system program, the control program, and the parameters, expands them into the memory 72, and executes them to perform various arithmetic processing. The control device 7 may be divided into multiple components (individual control units) for each function. Part or all of the control device 7 may be implemented by a programmable logic controller (PLC).

[0030] The control device 7 controls the multilevel converter 1 and the linear circuit 5 so as to minimize the voltage applied to the linear circuit 5 in order to reduce losses in the power conversion device 100. More specifically, the control device 7 controls the gate-source voltages Vgs of the switching elements 51 and 52 included in the linear circuit 5 based on the detected value of the current I from the current sensor 6. The control device 7 also determines, for each of the plurality of bit cells 31 to 35, a voltage value (command value) to be issued to that bit cell based on the detected voltage values ​​V1 to V5 from the voltage sensor VS. The control device 7 then determines a switching pattern (described below) of the plurality of switching elements Q1 to Q4 included in each of the bit cells 31 to 35 to achieve the command value.

[0031] Although FIG. 1 illustrates an example in which the control device 7 includes only one processor 71, the control device 7 may include multiple processors 71. That is, the control device 7 includes one or more processors 71. The same applies to the memory 72. In this specification, the term "processor" is not limited to a processor in the narrow sense that executes processing using a stored program, but may also include hardwired circuits such as an ASIC (Application Specific Integrated Circuit) or an FPGA (Field-Programmable Gate Array). Therefore, the term "processor" may also be interpreted as a processing circuitry in which processing is predefined by computer-readable code and / or hardwired circuitry.

[0032] <Maintaining Bit Cell Voltage> In the multilevel converter 1, the power supply circuit 2 outputs a positive voltage from the positive power supply 21, a negative voltage from the negative power supply 22, or zero voltage. The positive power supply 21 and the negative power supply 22 are configured to be able to output a constant voltage upon receiving power from an external source, and therefore the output voltage from the power supply circuit 2 is constant. On the other hand, the electrical energy stored in the power storage element C included in each of the bit cells 31 to 35 can increase or decrease, and therefore the output voltage from each of the bit cells 31 to 35 is not necessarily maintained constant. In the first embodiment, the control device 7 controls the switching elements Q1 to Q4 included in each of the bit cells 31 to 35 to perform switching operations so that the output voltage from each of the bit cells 31 to 35 is maintained constant, in order to ensure stable operation of the power conversion device 100.

[0033] FIG. 3 is a diagram illustrating the switching operation of the four switching elements Q1 to Q4 included in each of the bit cells 31 to 35. The polarity of current flowing from the first terminal T1 to the second terminal T2 is defined as positive current polarity, and the polarity of current flowing from the second terminal T2 to the first terminal T1 is defined as negative current polarity. FIG. 3 illustrates how the on / off of the switching elements Q1 to Q4 is controlled to determine the type of current that flows when the current polarity is positive (see FIGS. 3A to 3D) and when the current polarity is negative (see FIGS. 3E to 3H). Note that, to prevent a short circuit of the storage element C, the upper arm and the lower arm that constitute the same leg are not turned on at the same time.

[0034] First, the positive current polarity will be described. As shown in Fig. 3A, when switching elements Q1 to Q4 are off, on, on, and off, respectively, the voltage between the terminals is a positive voltage that is the same as the voltage of storage element C, and storage element C is discharged. On the other hand, as shown in Fig. 3B, when switching elements Q1 to Q4 are on, off, off, and on, respectively (i.e., when the on / off states of all switching elements Q1 to Q4 are reversed from Fig. 3A), the voltage between the terminals is a negative voltage that is opposite to the voltage of storage element C, and storage element C is charged.

[0035] As shown in FIG. 3C, when the switching elements Q1 to Q4 are on, off, on, and off, respectively (i.e., when both upper arms are on), the voltage between the terminals is theoretically zero. Also, as shown in FIG. 3D, when the switching elements Q1 to Q4 are off, on, off, and on, respectively (i.e., when both lower arms are on), the voltage between the terminals is theoretically zero. In these cases, the storage element C is not charged or discharged, so the voltage between the terminals ideally does not fluctuate.

[0036] Although detailed description will not be repeated, when the current polarity is negative, when comparing the on / off conditions of switching elements Q1 to Q4, the sign of the inter-terminal voltage is the same as when the current polarity is positive, but charging and discharging of storage element C are reversed (see FIGS. 3(E) and 3(F)). Furthermore, when both upper arms are on (see FIG. 3(G)) and when both upper arms are on (see FIG. 3(G)), the inter-terminal voltage is zero, and storage element C is not charged or discharged, as in the case when the current polarity is positive.

[0037] When the storage element C is charged, the voltage between its terminals increases, whereas when the storage element C is discharged, the voltage between its terminals decreases. When the detected value by the voltage sensor VS deviates from the command value by the control command for each bit cell, the control device 7 charges or discharges the storage element C so as to reduce the amount of deviation, thereby causing the detected value to follow the command value.

[0038] <Switching Pattern> Fig. 4 is a diagram for explaining output voltages from the power supply circuit 2 and multiple bit cells included in the multilevel converter 1. For ease of understanding, the following describes an example in which the multilevel converter 1 includes three bit cells 31 to 33. The bit cells 31 to 33 are referred to as the "first bit cell" to the "third bit cell," respectively.

[0039] The output voltages (magnitudes) of the first to third bit cells decrease in this order by a power (in this example, a power of 2) from the supply voltage (power supply voltage) from the power supply circuit 2. When the power supply voltage is 144V, 0V, or −144V, the output voltage of the first bit cell is 72V, 0V, or −72V, the output voltage of the second bit cell is 36V, 0V, or −36V, and the output voltage of the third bit cell is 18V, 0V, or −18V.

[0040] By employing such power supply circuit 2 and first to third bit cells, the output voltage level can be set to +18V, +36V, +54V, +72V, +90V, +108V, +126V, or +144V for positive current polarity. The output voltage level can be set to −18V, −36V, −54V, −72V, −90V, −108V, −126V, or −144V for negative current polarity. The output voltage level can also be set to 0V. Incidentally, by periodically (sinusoidally) varying the output voltage level at, for example, 50 Hz or 60 Hz, the output voltage level can also be set to an AC voltage.

[0041] As described above, each component of the multilevel converter 1 (the power supply circuit 2 and the first to third bit cells) is controlled in accordance with a control command from the control device 7. A combination of control commands for the components of the multilevel converter 1 is referred to as a "switching pattern." Furthermore, a repetitive unit in which one or more switching patterns are arranged in time is referred to as a "pattern period." To facilitate understanding of this embodiment, first, the pattern periods of the multilevel converter 1 in two comparative examples (first comparative example and second comparative example) will be described.

[0042] Comparative Example Fig. 5 is a diagram showing a pattern period of the multi-level converter 1 in a first comparative example. In Fig. 5 (and Figs. 6 and 7 described below), three control values ​​(+1, 0, -1) are used to represent how the power supply circuit 2 and the first to third bit cells are controlled. For the power supply circuit 2, 1 corresponds to supplying a positive voltage (+144 V) from the power supply circuit 2, and 0 corresponds to not supplying a voltage from the power supply circuit 2. For the first to third bit cells, 1 corresponds to discharging the bit cells (storage elements C in the bit cells), -1 corresponds to charging the bit cells, and 0 corresponds to not charging or discharging the bit cells.

[0043] When setting the output voltage level to +90V, there are five switching patterns shown in Figure 5. For example, in switching pattern P1, the power supply circuit 2 supplies 144V, the first bit cell is charged, the second bit cell is discharged, and the third bit cell is charged. In this case, 144V - 72V + 36V - 18V = 90V, so the output voltage level can be set to +90V.

[0044] The number of patterns included in a pattern cycle among the five switching patterns P1 to P5 can be determined as appropriate. If a pattern cycle includes only one pattern, charging or discharging continues in one or more of the first to third bit cells. This causes the voltage across the terminals of the bit cell to gradually increase or decrease, causing the output voltage level to change from +90V.

[0045] Therefore, it is conceivable to include all five types of switching patterns P1 to P5 in the pattern cycle and switch between the switching patterns P1 to P5 in sequence at equal time intervals. There is a degree of freedom in how two or more switching patterns are arranged in time, and various arrangements are possible. The pattern cycle shown in Figure 5 switches between the switching patterns in the order of P1-P2-P3-P4-P5 (repeated from P1 onwards). This allows the first bit cell to the third bit cell to both charge and discharge. In other words, it prevents any bit cell from being solely charged or solely discharged. This would appear to allow the output voltage level to be stably maintained at +90V.

[0046] However, the second bit cell is discharged in switching pattern P1, charged in switching pattern P3, and discharged in switching pattern P5. The sum of the control values ​​for the five switching patterns P1 to P5 for the second bit cell is 1. This means that the discharge period of the second bit cell is longer than the charge period. Therefore, even if the five switching patterns P1 to P5 are switched in sequence, the voltage between the terminals of the second bit cell gradually decreases. Conversely, the sum of the control values ​​for the third bit cell is 1, and the charge period is longer than the discharge period, so the voltage between the terminals of the third bit cell gradually increases. As a result, the voltage between the terminals of the second and third bit cells (the detected value of the voltage sensor VS) may deviate from the command value over time. As a result, it may not be possible to stably maintain the output voltage level at +90V.

[0047] FIG. 6 is a diagram showing a pattern cycle of the multilevel converter 1 in the second comparative example. According to the pattern cycle shown in FIG. 6, the switching pattern is switched in the order of P1-P2-P2-P3-P3-P4-P4-P5 (repeated from P1 onward). In this manner, the sum of the control values ​​of the first to third bit cells is zero. In other words, the length of the charging period and the length of the discharging period of the storage element C are equal in each of the first to third bit cells, and the time average of charging and discharging is zero. This prevents any bit cell from being excessively charged or discharged over time, allowing the output voltage level to be stably maintained at +90 V.

[0048] <<Present Embodiment>> FIG. 7 is a diagram showing a pattern period of the multilevel converter 1 according to the first embodiment. The first half of the pattern period shown in FIG. 7 is the same as the pattern period shown in FIG. 6. The second half of the pattern period shown in FIG. 7 is the pattern period shown in FIG. 6 that is the time-inverted version of the pattern period shown in FIG. 6. In other words, the pattern period shown in FIG. 7 is a combination of the pattern period shown in FIG. 6 and a pattern period that is the time-inverted version of the pattern period shown in FIG. 6. Therefore, the pattern period shown in FIG. 7 is symmetrical in time. According to the pattern period shown in FIG. 7, the switching pattern is switched in the order of P1-P2-P2-P3-P3-P4-P4-P5-P5-P4-P4-P3-P3-P2-P2-P1 (repeated from P1 onward).

[0049] FIG. 8 is a time chart showing the pattern period of the multilevel converter 1 in the first embodiment. The time during which each switching pattern continues is defined as a unit time. The pattern period described in FIG. 7 has a time length 16 times the unit time. The point at which a time 8 times the unit time has elapsed is the turning point at which the first half and second half of the pattern period are switched. The vertical axis represents, from top to bottom, the operation of the power supply circuit 2 (control value +1, 0, -1), the operation of the first bit cell, the operation of the second bit cell, and the operation of the third bit cell. The same applies to FIG. 10, which will be described later.

[0050] 7 and 8, in the first embodiment, as in the second comparative example (see FIG. 6), the sum of the control values ​​of the first to third bit cells is zero, which prevents any bit cell from being excessively charged or discharged over time, and therefore the output voltage level can be stably maintained at +90 V.

[0051] The five switching patterns P1 to P5 are arranged so that the lower the voltage of the bit cell, the higher the switching frequency of the charge / discharge. That is, the third bit cell that supplies 18 V has the highest switching frequency, the second bit cell that supplies 36 V has the next highest switching frequency, and the first bit cell that supplies 72 V has the lowest switching frequency. When switching between charge and discharge, switching losses occur in the switching elements Q1 to Q4 included in the bit cells. The higher the voltage of the bit cell, the greater the switching loss can be. By lowering the switching frequency of the charge / discharge of the bit cell for higher voltages, the switching loss of the multilevel converter 1 as a whole can be reduced.

[0052] In the second comparative example (see FIG. 6 ), after the last switching pattern P5 of a certain cycle is performed, the first switching pattern P1 of the next cycle is performed, at which time the power supply circuit 2 is switched from power supply stop (0) to positive voltage supply (1), and the first bit cell is switched from discharging (1) to charging (−1).

[0053] In contrast, in the first embodiment, the multiple switching patterns P1 to P5 are arranged symmetrically in time with respect to the turning point (the point after P5 is performed). In the first embodiment, after the last switching pattern P5 in the first half of a certain cycle is performed, the first switching pattern P5 in the second half of the same cycle is performed. Therefore, there is no need to switch between charging and discharging the power supply circuit 2 and the first to third bit cells. In addition, after the last switching pattern P1 in the second half of a certain cycle is performed, the first switching pattern P1 in the first half of the next cycle is performed. Again, there is no need to switch between charging and discharging the power supply circuit 2 and the first to third bit cells. Therefore, according to the first embodiment, the switching loss of the multilevel converter 1 as a whole can be further reduced compared to the second comparative example.

[0054] Modification of the First Embodiment FIG. 9 is a diagram for explaining switching control of bit cells in a modification of the first embodiment.

[0055] Generally, when the upper arm and the lower arm constituting the same leg are simultaneously in the ON state, a device connected in parallel to the leg (in this example, the energy storage element C) may be short-circuited. Therefore, when one of the upper arm and the lower arm is in the ON state and the other is in the OFF state, it may be possible to provide a dead time during which both the upper arm and the lower arm are temporarily in the OFF state.

[0056] If a dead time is provided in the switching operation of the switching elements Q1 and Q2 of the bit cell 31, the output voltage level may momentarily increase during the dead time, which may result in an excessive voltage being applied to the linear circuit 5, causing the linear circuit 5 to break down or increasing loss in the linear circuit 5.

[0057] Therefore, in this modification, the control device 7 does not provide a dead time when turning off (gate blocking) one of the switching elements Q1 and Q2 and turning on the other in accordance with the current flow in the switching elements Q1 and Q2. Similarly, the control device 7 does not provide a dead time when turning off one of the switching elements Q3 and Q4 and turning on the other in accordance with the current flow in the switching elements Q3 and Q4.

[0058] To explain this using a specific example, as shown in FIG. 9 , when current flows from switching element Q2 to storage element C to switching element Q3, current can flow through diode D1 even if switching element Q1 is not turned on. Furthermore, current can flow through diode D4 even if switching element Q4 is not turned on. Therefore, switching elements Q1 and Q4 do not necessarily need to be switched on. Therefore, when switching elements Q1 and Q4 are turned off, control device 7 maintains switching elements Q1 and Q4 in the off state (gate blocked) while turning on switching elements Q2 and Q3 without a dead time. Similarly, although not shown, when switching elements Q2 and Q3 are turned off, control device 7 maintains switching elements Q2 and Q3 in the off state (gate blocked) while turning on switching elements Q1 and Q4 without a dead time. This prevents short-circuiting of storage element C and suppresses failure or increased loss in linear circuit 5 due to application of excessive voltage to linear circuit 5.

[0059] During the period in which current is circulating through diodes D1 and D4, control device 7 may control switching elements Q1 to Q4 so that switching element Q1 is turned off and switching element Q2 is turned on simultaneously (no dead time provided), and switching element Q3 is turned on and switching element Q4 is turned off simultaneously (no dead time provided). Similarly, during the period in which current is circulating through diodes D2 and D3, control device 7 may control switching elements Q1 to Q4 so that switching element Q1 is turned on and switching element Q2 is turned off simultaneously (no dead time provided), and switching element Q3 is turned off and switching element Q4 is turned on simultaneously (no dead time provided).

[0060] Second Embodiment In the first embodiment, control was described in which the power supply circuit 2 and the first to third bit switches are switched exactly at the unit time (see FIG. 8). In the second embodiment, control is described in which the timing of switching the power supply circuit 2 and the first to third bit switches (the length of the charging period and discharging period of the storage element C) is finely adjusted to reduce the discrepancy between the command value and the actual value (the value detected by the voltage sensor VS) of the voltage of each bit cell. Note that the configuration of the power conversion device according to the second embodiment is similar to the configuration of the power conversion device 100 according to the first embodiment (see FIGS. 1 to 4), and therefore description thereof will not be repeated.

[0061] In the following, we will consider a case in which, in the configuration shown in Figure 4, the first bit cell supplying 72V does not require adjustment of the control timing, and it is desirable to extend the charging period of the second bit cell supplying 36V, and it is desirable to extend the discharging period of the third bit cell supplying 18V.

[0062] 10 is a time chart showing the pattern period of the multilevel converter 1 in embodiment 2. Based on the case where the power supply circuit 2 and the first to third bit switches are switched exactly at the unit time (see FIG. 8), the time for adjusting the rise or fall of the switching of charging and discharging of the second bit cell is referred to as "adjustment time Δt2."

[0063] The length (absolute value) of the adjustment time Δt2 is set to be longer as the difference between the command value and the actual value of the voltage of the second bit cell increases. More specifically, if the command value of the second bit cell is denoted as V2*, the detected value by the voltage sensor VS is denoted as V2, and the control gain (positive coefficient) is denoted as K2, the length |Δt2| of the adjustment time Δt2 can be set as shown in the following equation (1): |Δt2|=|K2×(V2*−V2)| (1)

[0064] Similarly, the length |Δt3| of the adjustment time Δt3 of the third bit cell can be set as shown in the following formula (2): |Δt3|=|K3×(V3*−V3)| (2)

[0065] Here, if the adjustment timing (the timing of the rise and fall of the switching waveform) differs between the first to third bit cells, the output voltage level of the multilevel converter 1 may fluctuate. Therefore, it is desirable to synchronize the adjustment timing between the first to third bit cells. In this case, it is desirable for the control device 7 to synchronize the adjustment timing with the bit cell that switches between charging and discharging most frequently.

[0066] 10 , a more detailed explanation will be given. During time period t1, the power supply circuit 2 and the first bit cell are not switched, while the second and third bit cells are switched. In this case, the adjustment timing of the second bit cell (the timing at which the second bit cell switches from discharging to halting charging and discharging) is synchronized with the adjustment timing of the third bit cell (the timing at which the third bit cell switches from charging to discharging).

[0067] During time period t3, power supply circuit 2 is not switched, while the first to third bit cells are switched. In this case, the adjustment timing of the first bit cell (the timing at which the first bit cell switches from charging to stopping charging / discharging), the adjustment timing of the second bit cell (the timing at which the second bit cell switches from stopping charging / discharging to charging), and the adjustment timing of the third bit cell (the timing at which the third bit cell switches from discharging to charging) are synchronized.

[0068] In time period t5, power supply circuit 2 and all bit cells are switched. In this case, the adjustment timing of power supply circuit 2 (the timing when power supply circuit 2 switches from discharging to power supply stop), the adjustment timing of the first bit cell (the timing when the first bit cell switches from charging / discharging stop to discharging), the adjustment timing of the second bit cell (the timing when the second bit cell switches from charging to charging / discharging stop), and the adjustment timing of the third bit cell (the timing when the third bit cell switches from charging to discharging) are synchronized.

[0069] During time period t7, the power supply circuit 2 and the first bit cell are not switched, while the second and third bit cells are switched. In this case, the adjustment timing of the second bit cell (the timing at which the second bit cell switches from halting charging and discharging to discharging) is synchronized with the adjustment timing of the third bit cell (the timing at which the third bit cell switches from discharging to charging).

[0070] The methods of synchronization in the remaining time periods t9, t11, t13, and t15 are similar to the methods of synchronization in the time periods t1, t3, t5, and t7, which are symmetrical with respect to the turning point, and therefore will not be described repeatedly.

[0071] The synchronized adjustment timing of the first to third bit cells for each time period can be determined based on the following three parameters: (1) a sign σ indicating the direction of change in charge / discharge of each bit cell, (2) a sign s indicating the direction of expansion / contraction of the adjustment time of each bit cell, and (3) the length of the adjustment time of each bit cell.

[0072] In this example, the synchronized adjustment timing ΔT of the first to third bit cells is determined according to the following equation (3): ΔT=σ2×s2×|Δt2|+σ3×s3×|Δt3| (3)

[0073] The right side of equation (3) includes six parameters (below), three for each of the second and third bit cells: a symbol σ2 indicating the direction of change in charge / discharge of the second bit cell; a symbol s2 indicating the direction of extension / contraction of the adjustment time Δt2 of the second bit cell; the length |Δt2| of the adjustment time Δt2 of the second bit cell; a symbol σ3 indicating the direction of change in charge / discharge of the third bit cell; a symbol s3 indicating the direction of extension / contraction of the adjustment time Δt3 of the third bit cell; the length |Δt3| of the adjustment time Δt3 of the third bit cell.

[0074] The signs σ2 and σ3 indicating the direction of change in charge and discharge are positive (+1) in the case of switching from discharge to charge and discharge stop, from discharge to charge, or from charge and discharge stop to charge, while the signs σ2 and σ3 are negative (−1) in the case of switching from charge to charge and discharge stop, from charge to discharge, or from charge and discharge stop to discharge.

[0075] The signs s2 and s3 indicating the direction of extension or shortening of the adjustment time are negative (-1) when the charging time is lengthened (when the discharging time is shortened), and positive (+1) when the discharging time is lengthened (when the charging time is shortened).

[0076] The length of the adjustment time is calculated based on the command value and the detected value one cycle before, according to the above formula (1) or formula (2).

[0077] 11 is a diagram showing a specific example of how to set synchronized adjustment timings for the first to third bit cells. In the example shown in FIG. 11, it is assumed that the length of the adjustment time Δt2 for the second bit cell is |Δt2|=0.1, and the length of the adjustment time Δt3 for the third bit cell is |Δt3|=0.2.

[0078] During time period t1, the second bit cell is switched from discharging to stopping charging and discharging, so σ2 = +1. s2 = -1 is set to lengthen the charging time of the second bit cell. σ3 = -1 is set to the third bit cell, so σ3 = -1 is set to the third bit cell. s3 = +1 is set to lengthen the discharging time of the third bit cell. Therefore, the adjustment timing ΔT(t1) during time period t1 is calculated as shown in equation (4) below. ΔT(t1) = -|Δt2| - |Δt3| = -0.3 ... (4)

[0079] During time period t3, the second bit cell is switched from charging / discharging stopped to charging, so σ2 = +1. To lengthen the charging time of the second bit cell, s2 = -1. To lengthen the charging time of the third bit cell, σ3 = +1. To lengthen the discharging time of the third bit cell, s3 = +1. Therefore, the adjustment timing ΔT(t3) during time period t3 is calculated as in the following formula (5): ΔT(t3) = - |Δt2| + |Δt3| = 0.1 ... (5)

[0080] During time period t5, the second bit cell is switched from charging to stopping charging and discharging, so σ2 = -1. To lengthen the charging time of the second bit cell, s2 = -1. To lengthen the charging time of the third bit cell, σ3 = -1. To lengthen the discharging time of the third bit cell, s3 = +1. Therefore, the adjustment timing ΔT(t5) during time period t5 is calculated as in the following formula (6): ΔT(t5) = |Δt2| - |Δt3| = -0.1 (6)

[0081] During time period t7, the second bit cell is switched from charging / discharging stopped to discharging, so σ2 = -1. To lengthen the charging time of the second bit cell, s2 = -1. To lengthen the charging time of the third bit cell, σ3 = +1. To lengthen the discharging time of the third bit cell, s3 = +1. Therefore, the adjustment timing ΔT(t7) during time period t5 is calculated as in the following formula (7): ΔT(t7) = |Δt2| + |Δt3| = 0.3 (7)

[0082] The synchronized adjustment timings in the remaining time periods t9, t11, t13, and t15 are similar to the synchronized adjustment timings in the time periods t1, t3, t5, and t7 that are symmetrical with respect to the turning point, and therefore will not be described repeatedly.

[0083] <Pulse Waveform Adjustment> The timing adjustment as described with reference to FIGS. 10 and 11 can be realized by PWM (Pulse Width Modulation) control using a triangular wave or a trapezoidal wave as a carrier wave, for example, as follows.

[0084] FIG. 12 is a diagram illustrating PWM control using a triangular wave. The horizontal axis represents elapsed time. The vertical axis represents, from top to bottom, a first triangular waveform, a discharge pulse waveform (a pulse waveform for discharging switching elements Q1 to Q4), a second triangular wave, and a charge pulse waveform (a pulse waveform for charging switching elements Q1 to Q4). In the diagram, the left side shows the waveform before pulse width adjustment (a waveform corresponding to the first embodiment described in FIG. 8), and the right side shows the waveform after pulse width adjustment (a waveform corresponding to the second embodiment described in FIGS. 10 and 11).

[0085] First, referring to the waveform on the left, before adjusting the pulse width, a first reference level REF1 for generating a charge pulse and a second reference level REF2 for generating a charge pulse are used. The first reference level REF1 is constant and is located midway between the peaks and valleys of the first triangular waveform. The second reference level REF2 is obtained by inverting the first reference level REF1 vertically (inverting it in the voltage direction). The second reference level REF2 is also constant and is located midway between the peaks and valleys of the second triangular waveform.

[0086] The discharge pulse waveform is on (high level) when the first reference level REF1 is higher than the first triangular waveform, and off (low level) when the first reference level REF1 is lower than the first triangular waveform. Similarly, the charge pulse waveform is on when the second reference level REF2 is higher than the second triangular waveform, and off when the second reference level REF2 is lower than the second triangular waveform.

[0087] Next, referring to the waveform on the right, when adjusting the pulse width, the first reference level REF1 is changed from the level before the pulse width adjustment (the intermediate level between the peaks and valleys of the first triangular waveform) for each period of the first triangular waveform. Furthermore, the second reference level REF2 is changed from the level before the pulse width adjustment for each period of the second triangular waveform. FIG. 12 shows an example in which the first reference level REF1 is set higher than the level before the pulse width adjustment and the second reference level REF2 is set lower than the level before the pulse width adjustment. This allows the discharge pulse width to be widened (extended) and the charge pulse width to be narrowed (contracted) compared to before the pulse width adjustment. Conversely, although not shown, the discharge pulse width can be narrowed and the charge pulse width to be widened by setting the first reference level REF1 lower than the level before the pulse width adjustment and setting the second reference level REF2 higher than the level before the pulse width adjustment.

[0088] 13 is a diagram for explaining PWM control using a trapezoidal wave. This technique is similar to the technique using a trapezoidal wave except that a trapezoidal wave is used instead of a triangular wave, and therefore description thereof will not be repeated.

[0089] A trapezoidal wave has upper and lower bases instead of the peaks and valleys of a triangular wave. The same discharge pulse or charge pulse is obtained regardless of when the reference level (REF1 or REF2) is changed during the upper or lower base period of the trapezoidal wave. In other words, the reference level can be changed at any time during the upper or lower base period of the trapezoidal wave. Therefore, using a trapezoidal wave allows for greater flexibility in the timing of changing the reference level compared to using a triangular wave.

[0090] As described above, in the second embodiment, the control device 7 adjusts the lengths of the charge and discharge periods of the energy storage elements C included in the first to third bit cells based on the values ​​detected by the voltage sensors VS, thereby reducing the deviation of the actual inter-terminal voltages of the first to third bit cells from their command values. In this case, the control device 7 equalizes the amount of change (expansion / contraction) in the discharge pulse width and the charge pulse width so that the adjustment timings of the first to third bit cells are synchronized. This suppresses fluctuations in the output voltage level of the multilevel converter 1 that may occur when the adjustment timings do not match. Therefore, the output voltage level from the multilevel converter 1 can be more stably maintained constant.

[0091] The modification of the first embodiment (see FIG. 9 ) may be applied to the second embodiment. That is, in the second embodiment as well, the control device 7 may turn off (gate block) one of the switching elements Q1 and Q2 in accordance with the current flow in the switching elements Q1 and Q2, while turning on the other switching element without providing a dead time, in accordance with the current flow in the switching elements Q1 and Q2. Similarly, the control device 7 may turn off one of the switching elements Q3 and Q4 in accordance with the current flow in the switching elements Q3 and Q4, while turning on the other switching element without providing a dead time.

[0092] The embodiments disclosed herein should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is defined by the claims, not by the description of the above embodiments, and is intended to include all modifications within the meaning and scope of the claims.

[0093] 100 Power conversion device, 1 Multilevel converter, 2 Power supply circuit, 21 Positive power supply, 22 Negative power supply, 23-26 Switching elements, 31-38 Bit cells, Q1, Q2, Q3, Q4 Switching elements, D1, D2, D3, D4 Diodes, C Storage element, T1 First terminal, T2 Second terminal, VS Voltage sensor, 4 Output node, 5 Linear circuit, 51, 52 Switching elements, 6 Current sensor, 7 Control device, 71 Processor, 72 Memory, 900 Load.

Claims

1. A power conversion device comprising: a multilevel converter including a DC power supply circuit, an output node, and a plurality of bit cells connected in series between the DC power supply circuit and the output node and outputting different DC voltages; and a control device that controls the multilevel converter, wherein each of the plurality of bit cells includes a storage element and one or more switching elements configured to charge or discharge the storage element by performing a switching operation in accordance with a control command from the control device, and the control device repeatedly outputs a plurality of switching patterns in which control commands for the plurality of bit cells are arranged in chronological order, and the plurality of switching patterns are symmetrical in time for each period, and are determined so that the length of a charging period and the length of a discharging period of the storage element are equal.

2. The power conversion device according to claim 1, wherein each of the plurality of bit cells further includes a voltage sensor that detects the voltage of the storage element and outputs the detected value to the control device, and the control device adjusts the charging period and the discharging period of the storage element for one or more of the plurality of bit cells based on the detected value.

3. The power conversion device according to claim 2, wherein when the control device adjusts the charging period and the discharging period of the storage element for two or more bit cells among the plurality of bit cells, the control device synchronizes the adjustment timing between the two or more bit cells.

4. The power conversion device according to claim 3, wherein the adjustment timing is symmetrical in time for each of the periods.

5. The power conversion device according to claim 3 or 4, wherein the control device synchronizes the adjustment timing with a bit cell that has the highest frequency of switching between charging and discharging among the two or more bit cells.

6. A power conversion device according to any one of claims 1 to 5, wherein the plurality of switching patterns are determined so that the lower the DC voltage output from a bit cell among the plurality of bit cells, the higher the frequency of switching between charging and discharging.

7. The power conversion device according to any one of claims 2 to 5, wherein the control device is configured, for each of the one or more bit cells, to discharge the storage element when a first reference level is higher than a first triangular wave, and to charge the storage element when a second reference level is higher than a second triangular wave obtained by inverting the first triangular wave, and adjusts the charging period and the discharging period of the storage element by adjusting the first reference level and the second reference level based on the detection value by the voltage sensor.

8. The power conversion device according to any one of claims 2 to 5, wherein the control device is configured, for each of the one or more bit cells, to discharge the storage element when a first reference level is higher than a first trapezoidal wave, and to charge the storage element when a second reference level is higher than a second trapezoidal wave that is an inverted version of the first trapezoidal wave, and adjusts the charging period and the discharging period of the storage element by adjusting the first reference level and the second reference level based on the detection value by the voltage sensor.

9. The power conversion device according to any one of claims 1 to 8, further comprising a linear circuit connected to the output node, the linear circuit including a semiconductor element that operates linearly in accordance with a control command from the control device.

10. The power conversion device according to any one of claims 1 to 9, wherein the one or more switching elements include first and second switching elements that respectively form an upper arm and a lower arm of a first leg connected in parallel to the storage element, and third and fourth switching elements that respectively form an upper arm and a lower arm of a second leg connected in parallel to the storage element, each of the plurality of bit cells further includes first to fourth diodes that are connected in anti-parallel to the first to fourth switching elements, respectively, and the control device, when turning off the first and fourth switching elements, turns on the second and third switching elements without providing a dead time, and when turning off the second and third switching elements, turns on the first and fourth switching elements without providing a dead time.

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