Memory and access method therefor, and electronic device

Abstract

A memory and an access method therefor, and an electronic device. The memory comprises: at least one memory array, a plurality of common word lines, and a plurality of common bit lines; the memory array comprises a multi-layer memory cell array and vertically extending bit lines; the memory cell array comprises: a plurality of memory cells and a plurality of word lines; the plurality of word lines are divided into a plurality of word line groups, and each word line group is connected to one common word line; each word line group comprises S word lines, and the S word lines are respectively connected to memory cells in alternate columns; each row of bit lines corresponds to S common bit lines; and each row of bit lines is divided into a plurality of bit line groups comprising two adjacent bit lines, and every S bit line groups is respectively connected to S common bit lines corresponding to the row of bit lines.

Description

Memory and access method thereof, and electronic device

[0001] The present application claims priority from the Chinese patent application No. 202410764197.X filed on June 13, 2024 and entitled "Memory and access method thereof, and electronic device", the contents of which should be understood as incorporated by reference into the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing thereof in the field of semiconductor technology, in particular to a memory and access method thereof, and electronic device. BACKGROUND

[0003] With the development of integrated circuit technology, the critical dimension of devices is increasingly shrinking, and the types and number of devices contained in a single chip are increasing, so that any slight difference in process production can affect the performance of the device.

[0004] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] The present application provides a memory, comprising:

[0008] at least one memory array, a plurality of common word lines, and a plurality of common bit lines;

[0009] The memory array comprises a plurality of memory cell arrays stacked along a direction perpendicular to a substrate, and a plurality of bit lines extending along a direction perpendicular to the substrate and arranged in a first direction and a second direction;

[0010] The memory cell array comprises a plurality of memory cells arranged in the first direction and the second direction, a plurality of word lines extending in the second direction corresponding to each column of memory cells arranged in the second direction, and the word lines connecting the corresponding column of memory cells; the bit lines connect a plurality of memory cells at the same position of different layers, and the first direction and the second direction are parallel to the substrate and intersect each other;

[0011] The plurality of word lines of the same memory cell array are divided into a plurality of word line groups, each word line group connects one common word line, and different word line groups connect different common word lines; each word line group comprises S word lines, and the S word lines in the same word line group are connected to the memory cells of the alternate columns, respectively;

[0012] Each row of bit lines distributed along the first direction corresponds to S common bit lines; and each row of bit lines is divided into a plurality of bit line groups, each bit line group includes two adjacent bit lines, the plurality of bit line groups of each row of bit lines are arranged in the arrangement order of the bit lines, each bit line group is connected to one of the S common bit lines corresponding to the row of bit lines, and the adjacent bit line groups in the plurality of bit line groups connected to the same common bit line are separated by S-1 bit line groups, and the S is greater than or equal to 2.

[0013] In some embodiments, the S is 2, 3 or 4.

[0014] In some embodiments, the memory includes a plurality of memory arrays spaced along the second direction, and adjacent memory cells share the common word line, and in the plurality of word line groups of a memory array, the word line group in which the word lines connected to the memory cells in odd columns are connected to the word line groups of one of the two memory arrays adjacent to the memory array, and the word line group in which the word lines connected to the memory cells in even columns are connected to the word line groups of the other one of the two memory arrays adjacent to the memory array.

[0015] In some embodiments, the word line groups connected to the same common word line and located in different memory arrays are connected to the same column of memory cells.

[0016] In some embodiments, the S is 2, and the common bit line extends along the first direction, a plurality of the common bit lines are spaced along the second direction, and at least between adjacent common bit lines in the plurality of common bit lines of the same memory cell array, a shielding line extending along the first direction is arranged.

[0017] In some embodiments, a first gating sub-circuit is arranged between each of the bit lines and the common bit line, the first gating sub-circuit is connected to a first gating control line, and the first gating sub-circuit is configured to electrically connect or disconnect the bit line and the common bit line under the control of the first gating control line.

[0018] In some embodiments, a plurality of first gating sub-circuits connected to the bit lines in the same column arranged along the second direction are connected to the same first gating control line.

[0019] In some embodiments, each of the bit lines is also connected to a preset voltage terminal through a second gating sub-circuit, the second gating sub-circuit is connected to a second gating control line, and the second gating sub-circuit is configured to electrically connect or disconnect the bit line and the preset voltage terminal under the control of the second gating control line.

[0020] In some embodiments, the plurality of second gating sub-circuits connected to the plurality of bit lines in the same column arranged along the second direction are connected to the same second gating control line.

[0021] Embodiments of the present disclosure provide an access method, applied to any of the above-described memories, comprising:

[0022] In a data read / write phase, according to a word line group in which a target storage unit to be operated is connected, an activation signal is loaded on a common word line connected to the word line group, wherein the target storage unit comprises S column storage units, and the S column storage units are respectively connected to S word lines in the same word line group.

[0023] In some embodiments, the method further comprises loading a turn-on level signal on a first gating control line connected to a first gating sub-circuit connected to S column target bit lines respectively connected to the target storage unit, and loading an off level signal on a second gating control line connected to a second gating sub-circuit connected to the S column target bit lines; loading an off level signal on a first gating control line not connected to the target bit line, and loading a turn-on level signal on a second gating control line not connected to the target bit line.

[0024] Embodiments of the present disclosure provide an electronic device comprising the memory of any of the above-described embodiments.

[0025] In some embodiments, the electronic device further comprises a control circuit configured to access the memory according to the above-described access method.

[0026] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. Other advantages of the present application can be realized and attained by means of the instrumentalities and combinations particularly described herein.

[0027] Other aspects can become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.

[0028] BRIEF DESCRIPTION OF DRAWINGS

[0029] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification that is included to illustrate the embodiments of the present application and to explain the principles of the present application, and are not intended to limit the present application.

[0030] FIG. 1 is a schematic diagram of a logic circuit of a memory according to some embodiments;

[0031] FIG. 2 is a schematic diagram of bit line and common bit line connections according to some embodiments;

[0032] FIG. 3 is a schematic diagram of bit line and common bit line connections according to other embodiments;

[0033] Fig. 4 is a schematic diagram of a logic circuit of a memory according to some embodiments;

[0034] Fig. 5 is a schematic diagram of a bit line and common bit line connection according to some embodiments;

[0035] Fig. 6 is a schematic diagram of a bit line and common bit line connection according to some embodiments.

[0036] DETAILED DESCRIPTION

[0037] The embodiments of the present disclosure will be described in detail hereinafter with reference to the drawings. The features of the embodiments of the present disclosure and the embodiments can be combined with each other as long as they do not conflict with each other.

[0038] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person skilled in the art of the present disclosure.

[0039] The embodiments of the present disclosure are not necessarily limited to the shapes and sizes of the components shown in the drawings, and the shapes and sizes of the components shown in the drawings can be changed as needed.

[0040] The ordinal numbers "first", "second", "third", and so on in the present disclosure are used to distinguish the components of the disclosure and do not limit the sequence, number, or importance of the components.

[0041] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", and "connection" should be interpreted broadly. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be directly connected, or indirectly connected through an intermediate device, or the communication inside two elements. The specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances by those of ordinary skill in the art.

[0042] In the present disclosure, it can be that the first electrode is a drain electrode and the second electrode is a source electrode, or it can be that the first electrode is a source electrode and the second electrode is a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the current direction in the circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0043] In the present disclosure, "connection" includes a case where components are connected together through an element having some electrical action. The element having some electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the connected components. Examples of the element having some electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0044] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state where two straight lines form an angle of -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where two straight lines form an angle of 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0045] Fig. 1 is a schematic diagram of a memory logic circuit according to an example embodiment. As shown in Fig. 1, the memory includes a plurality of memory arrays located in different regions of a substrate, and the plurality of memory arrays can be arranged along a second direction Y. The memory array can include a plurality of layers of memory cell arrays 10 stacked in a direction perpendicular to the substrate, a plurality of bit lines (BL) extending in a direction perpendicular to the substrate. The memory cell array 10 can include a plurality of memory cells 11 arranged in a first direction X and a second direction Y, a plurality of word lines (WL) extending in the second direction Y. The same column of memory cells along the same layer and the second direction Y are connected to the same WL. The memory cells 11 of different columns are connected to different WLs. The memory cells 11 of the same position of different layers are connected to the same BL. The plurality of BLs are arranged in the first direction X and the second direction Y. The memory can also include a plurality of common word lines (CWL) and a plurality of common bit lines (CBL).

[0046] The memory cell 11 can include a transistor and a capacitor, the transistor including a gate electrode, a first electrode, and a second electrode, the gate electrode of the transistor being connected to the WL, the first electrode of the transistor being connected to the BL, the second electrode of the transistor being connected to a first end of the capacitor, and a second end of the capacitor being connected to a first predetermined voltage terminal V PL . The first predetermined voltage terminal V PL may be a fixed potential, such as a value between a voltage corresponding to logical data "0" and a voltage corresponding to logical data "1", such as "0" corresponding to logical data "0" and VDD corresponding to logical data "1", and V PL may be 1 / 2 VDD.

[0047] The plurality of WLs of the same memory cell array 10 are divided into a plurality of groups, referred to as word line groups, each WL belongs to only one word line group, each word line group includes two WLs, and the two WLs of the same word line group are separated by one WL, the WLs of the same word line group are connected to the same CWL, and the WLs of different word line groups of the same memory cell array 10 are connected to different CWLs. For example, the memory cell array 10 includes N rows and 2M columns of memory cells 11, i.e., N*2M memory cells 11, and includes 2M WLs, the jth WL is connected to the jth column of memory cells 11, j is 1 to 2M. The first word line and the third word line form the first word line group, which is connected to the first common word line CWL_0; the second word line and the fourth word line form the second word line group, which is connected to the second common word line CWL_1; the fifth word line and the seventh word line form the third word line group, which is connected to the third common word line CWL_2; the sixth word line and the eighth word line form the fourth word line group, which is connected to the fourth common word line CWL_3; and so on, the 2M-3th word line and the 2M-1th word line form the M-1th word line group, which is connected to the M-1th common word line CWL_M-2; the 2M-2th word line and the 2Mth word line form the Mth word line group, which is connected to the Mth common word line CWL_M-1.

[0048] Each CWL connects the word lines of two word line groups, and the two word line groups belong to the memory cell arrays 10 of the same layer of the memory arrays adjacent to each other, and the memory cells 11 connected by the word lines of the two word line groups are in the same column. For example, the three memory arrays shown in FIG. 1 are the k-1th memory array, the kth memory array, and the k+1th memory array in sequence, the common word line CWL_0 connects the first word line and the third word line of the rth layer of memory cell arrays 10 of the kth memory array, and connects the first word line and the third word line of the rth layer of memory cell arrays 10 of the k-1th memory array.

[0049] The adjacent word line groups of the same memory cell array 10 are connected to the same CWL as the word line groups of different memory arrays. The word line group in which the word lines connected to the memory cells 11 of the odd-numbered columns are connected to the same common word line as the word line group of one of the two memory arrays adjacent to the memory array. The word line group in which the word lines connected to the memory cells of the even-numbered columns are connected to the same common word line as the word line group of the other of the two memory arrays adjacent to the memory array. For example, the word line group in which the word lines connected to the memory cells 11 of the odd-numbered columns in the kth memory array is connected to the same common word line as the word line group in which the word lines connected to the memory cells 11 of the odd-numbered columns in the (k-1)th memory array, the word line group in which the word lines connected to the memory cells 11 of the even-numbered columns in the kth memory array is connected to the same common word line as the word line group in which the word lines connected to the memory cells 11 of the even-numbered columns in the (k+1)th memory array, or the word line group in which the word lines connected to the memory cells 11 of the odd-numbered columns in the kth memory array is connected to the same common word line as the word line group in which the word lines connected to the memory cells 11 of the odd-numbered columns in the (k+1)th memory array, and the word line group in which the word lines connected to the memory cells 11 of the even-numbered columns in the kth memory array is connected to the same common word line as the word line group in which the word lines connected to the memory cells 11 of the even-numbered columns in the (k-1)th memory array, where adjacent word line groups are word line groups in which there are adjacent word lines among the word lines included in the two word line groups. For example, the word lines of the 1st word line group, the 3rd word line group,..., the (M-1)th word line group of the kth memory array are connected to the same common word line as the word lines of the corresponding 1st word line group, the 3rd word line group,..., the (M-1)th word line group of the (k-1)th memory array, and the word lines of the 2nd word line group, the 4th word line group,..., the Mth word line group of the kth memory array are connected to the same common word line as the word lines of the corresponding 2nd word line group, the 4th word line group,..., the Mth word line group of the (k+1)th memory array. As shown in FIG. 1, the 1st word line group of the kth memory array (including the word lines connected to the memory cells of the odd-numbered columns, the 1st word line and the 3rd word line) is connected to the same common word line CWL_0 as the 1st word line group of the (k-1)th memory array, and the 2nd word line group of the kth memory array (including the word lines connected to the memory cells of the even-numbered columns, the 2nd word line and the 4th word line) is connected to the same common word line CWL_1 as the 2nd word line group of the (k+1)th memory array.

[0050] Each row of bit lines distributed along the first direction X corresponds to two CBLs, each adjacent two BLs form a bit line group, the BLs in the same bit line group are connected to the same CBL, and the BLs in the same row form a plurality of bit line groups, and the BLs in adjacent bit line groups are connected to different CBLs corresponding to the row of BLs. Adjacent bit line groups refer to the existence of adjacent bit lines in the bit lines contained in the two bit line groups. For example, as shown in FIG. 2, the plurality of BLs in the i+1th row correspond to the common bit lines CBL_i_0 and CBL_i_1, i is 0 to N-1, wherein the bit lines in the first column and the second column of the i+1th row form the first bit line group, the bit lines in the third column and the fourth column of the i+1th row form the second bit line group, and so on, the bit lines in the 2M-1th column and the 2Mth column of the i+1th row form the Mth bit line group, and the first bit line group, the third bit line group, and the M-1th bit line group are connected to the common bit line CBL_i_0, and the second bit line group, the fourth bit line group, and the Mth bit line group are connected to the common bit line CBL_i_1. The scheme provided in this embodiment has only two common bit lines in the region where a row of storage units is located, and the distance between the common bit lines is large, which can reduce the coupling between the common bit lines, so that one common bit line can connect more bit lines, and the corresponding memory can use fewer common bit lines, and the number of sense amplifiers connected to the common bit lines is reduced.

[0051] In some embodiments, the CBLs extend along the first direction X, and when each row of bit lines corresponds to two CBLs, at least between two adjacent CBLs, a shielding line extending along the first direction X is arranged. The shielding line can be connected to a third preset voltage terminal, and the voltage of the third preset voltage terminal is, for example, 0, 1 / 2VDD, VDD, etc. The shielding line can shield adjacent CBLs and reduce the coupling capacitance between adjacent CBLs. The shielding line can be consistent with the shape of the CBL, that is, the same plurality of conductive lines can be manufactured, part of which is used as a CBL and part of which is used as a shielding line, but not limited thereto.

[0052] In some embodiments, a shielding line is arranged between adjacent CBLs. The shielding line can be arranged between the two CBLs corresponding to the bit lines in the same row, and can also be arranged between the CBLs corresponding to the bit lines in adjacent rows, for example, the bit lines in the first row correspond to the first CBL and the second CBL, and the bit lines in the second row correspond to the third CBL and the fourth CBL. The shielding line can be arranged between the first CBL and the second CBL, between the second CBL and the third CBL, and between the third CBL and the fourth CBL.

[0053] Among the M common word lines connected by each memory cell array 10, only one common word line is activated at the same time, so that only the transistor of the memory cell connected by the bit line of the 1st bit line among the multiple bit lines connected by the same common bit line is turned on. For example, when the common word line CWL_0 is activated, the transistors of the first column of memory cells 11 and the third column of memory cells 11 connected by the first word line and the third word line are turned on, and the BLs connected with the first column of memory cells 11 and the third column of memory cells 11, respectively, perform data reading or writing through charge sharing. That is, at this time, the working BLs are the BL connected with the first column of memory cells 11 and the BL connected with the third column of memory cells 11, rather than the adjacent BLs. The first column of BLs and the third column of BLs are separated by two memory cells 11, and the distance is very far, the coupling between the first column of BLs and the third column of BLs is very small, and the second column of BLs can shield the first column of BLs and the third column of BLs, so as to further reduce the coupling between the first column of BLs and the third column of BLs. Therefore, one common bit line can connect more bit lines, and the memory can use fewer common bit lines. Since the common bit line is connected with the sense amplifier, the number of common bit lines is reduced, and the number of sense amplifiers connected with the common bit line is also reduced.

[0054] In some embodiments, as shown in FIG. 3, each BL can be connected to the CBL through a first gating sub-circuit 21, and the first gating sub-circuit 21 is also connected with a first gating control line. The first gating sub-circuit 21 is configured to connect or disconnect the BL and the CBL (i.e., to make the BL and the CBL electrically connected, or to disconnect) under the control of the first gating control line. The scheme provided in this embodiment can only select the target bit line to be operated by setting the first gating sub-circuit 21, and turn off the non-target bit line, thereby reducing the capacitive reactance of the CBL, reducing power consumption, and improving operation speed. When the capacitive reactance of the CBL is smaller, the voltage change ΔVBL on the BL is larger after the BL and the memory cell perform charge sharing. Therefore, the CBL can connect more bit lines, and the memory can use fewer CBLs. Since the CBL is connected with the sense amplifier, the number of CBLs is reduced, and the number of sense amplifiers connected with the CBL is also reduced. Alternatively, the number of bit lines connected with the CBL can remain unchanged, and a capacitor with a smaller capacitance value can be used, that is, a capacitor with a smaller area can be used, thereby reducing the area occupied by the memory cell and improving the device density. However, the embodiments of the present disclosure are not limited thereto, and in another exemplary embodiment, the first gating sub-circuit 21 can not be provided.

[0055] In some embodiments, as shown in FIG. 3, each of the bit lines can also be connected to a second preset voltage terminal Vpre through a second gating sub-circuit 22 connected to a second gating control line, and the second gating sub-circuit 22 is configured to connect or disconnect the bit line and the second preset voltage terminal Vpre (i.e., to make the bit line and the second preset voltage terminal Vpre electrically connected, or disconnected) under the control of the second gating control line. The scheme provided in this embodiment can connect the non-target bit line to the preset voltage terminal through the second gating sub-circuit 22, so as to avoid the voltage change of the non-target bit line and the interference on the target bit line. However, the embodiments of the present disclosure are not limited thereto, and in some other embodiments, the second gating sub-circuit 22 can not be provided.

[0056] In some embodiments, the voltage of the second preset voltage terminal Vpre can be a value between the voltage corresponding to the logic data "0" and the voltage corresponding to the logic data "1", such as 1 / 2VDD.

[0057] In some embodiments, the first gating sub-circuits 21 connected to the bit lines in the same column arranged along the second direction Y are connected to the same first gating control line, and the first gating sub-circuits 21 connected to the bit lines in different columns are connected to different first gating control lines, i.e., the first gating sub-circuits 21 connected to the 2M columns of bit lines are connected to 2M different first gating control lines. For example, as shown in FIG. 3, the memory cell array includes N*2M bit lines, and the bit line in the i-th row and the j-th column is BL_i-1_j-1, i is 1 to N, and j is 1 to 2M, i.e., BL_0_0 to BL_N-1_2M-1. The first gating sub-circuits 21 connected to the bit lines in the first column are all connected to the first first gating control line Ctrl_0_0, the first gating sub-circuits 21 connected to the bit lines in the second column are all connected to the second first gating control line Ctrl_0_3, the first gating sub-circuits 21 connected to the bit lines in the third column are all connected to the third first gating control line Ctrl_1_0, the first gating sub-circuits 21 connected to the bit lines in the fourth column are all connected to the fourth first gating control line Ctrl_1_3, and so on, the first gating sub-circuits 21 connected to the bit lines in the 2M-1-th column are all connected to the 2M-1-th first gating control line Ctrl_M-1_0, and the first gating sub-circuits 21 connected to the bit lines in the 2M-th column are all connected to the 2M-th first gating control line Ctrl_M-1_3. The scheme provided in this embodiment can select a bit line through the CBL and the first gating control line.

[0058] In some embodiments, the second sub-gating circuits 22 connected with the bit lines of the same column in the second direction Y are connected with the same second gating control line, the second sub-gating circuits 22 connected with the bit lines of different columns are connected with different second gating control lines, and the second sub-gating circuits 22 connected with the bit lines of 2M columns are connected with 2M different second gating control lines. For example, as shown in FIG. 3, the second sub-gating circuits 22 connected with the bit lines of the first column are connected with the first second gating control line Ctrl_0_1, the second sub-gating circuits 22 connected with the bit lines of the second column are connected with the second second gating control line Ctrl_0_2, the second sub-gating circuits 22 connected with the bit lines of the third column are connected with the third second gating control line Ctrl_1_1, the second sub-gating circuits 22 connected with the bit lines of the fourth column are connected with the fourth second gating control line Ctrl_1_2, and so on, the second sub-gating circuits 22 connected with the bit lines of the 2M-1 column are connected with the 2M-1 second gating control line Ctrl_M-1_1, and the second sub-gating circuits 22 connected with the bit lines of the 2M column are connected with the 2M second gating control line Ctrl_M-1_2.

[0059] In the read operation or write operation stage, the gating states of the first sub-gating circuit 21 and the second sub-gating circuit 22 connected with the same bit line BL are opposite.

[0060] In some embodiments, the first sub-gating circuit 21 can include a first transistor T1, the gate electrode of the first transistor T1 is connected with the first gating control line, the first electrode is connected with the bit line BL, and the second electrode is connected with the common bit line CBL. The structure of the first sub-gating circuit 21 in the embodiment is only an example, and other circuits that can realize gating can be used.

[0061] In some embodiments, the first transistor T1 is an N-type transistor, but the embodiment of the present disclosure is not limited thereto, and the first transistor T1 can be a P-type transistor.

[0062] In some embodiments, the second sub-gating circuit 22 can include a second transistor T2, the gate electrode of the second transistor T2 is connected with the second gating control line, the first electrode is connected with the bit line BL, and the second electrode is connected with a second preset voltage terminal Vpre. The structure of the second sub-gating circuit 22 in the embodiment is only an example, and other circuits that can realize gating can be used.

[0063] In some embodiments, the second transistor T2 is an N-type transistor, but the embodiment of the present disclosure is not limited thereto, and the second transistor T2 can be a P-type transistor.

[0064] The embodiment of the present disclosure further provides an access method of the memory, which can include the following steps:

[0065] In the data read-write stage, according to the word line group in which the word lines connected to the two columns of target storage units are located, an activation signal is loaded on the common word line connected to the word line group, a conduction level signal is loaded on the first gating control line corresponding to the two columns of target bit lines connected to the target storage units, so as to turn on the two columns of target bit lines and the corresponding common bit line; a turn-off level signal is loaded on the second gating control line connected to the second gating subcircuit connected to the two columns of target bit lines, so that the target bit line is disconnected from the second preset voltage terminal; a turn-off level signal is loaded on the first gating control line connected to the first gating subcircuit connected to the non-target bit line (i.e., the first gating control line connected to the first gating subcircuit connected to the non-target bit line), and a conduction level signal is loaded on the second gating control line connected to the second gating subcircuit connected to the non-target bit line (i.e., the second gating control line connected to the second gating subcircuit connected to the non-target bit line), so that the non-target bit line is connected to the second preset voltage terminal. The word lines connected to the two columns of target storage units belong to the same word line group.

[0066] The conduction level signal is a signal that can make the corresponding gating subcircuit in a connected state, and the turn-off level signal is a signal that can make the corresponding gating subcircuit in an off state. The data read-write stage can include a read data stage and a write data stage.

[0067] As shown in FIG. 3, the target storage units are the storage units in the 2nd column and the 4th column, the word lines connected to the storage units in the 2nd column and the 4th column are located in a word line group connected to a common word line CWL_1, an activation signal is loaded on the common word line CWL_1, then the 2nd word line and the 4th word line are loaded with the activation signal, the transistors of the storage units 11 in the 2nd column and the 4th column are turned on, the first gating control lines (Ctrl_0_3, Ctrl_1_3) connected to the bit lines in the 2nd column and the 4th column are loaded with a conduction level signal, the second gating control lines (Ctrl_0_2, Ctrl_1_2) connected to the bit lines in the 2nd column and the 4th column are loaded with a turn-off level signal, so that the bit lines in the 2nd column and the 4th column (i.e., the target bit lines) are connected to the common bit line and are in communication, and are disconnected from the second preset voltage terminal Vpre, the bit lines connected to the storage units 11 in the 2nd column and the 4th column can share charges with the storage units 11, the first gating control lines corresponding to the bit lines in other columns except the 2nd column and the 4th column (i.e., the non-target bit lines) are loaded with a turn-off level signal, the second gating control lines corresponding to the bit lines in other columns except the 2nd column and the 4th column are loaded with a conduction level signal, so that the bit lines in other columns except the 2nd column and the 4th column are disconnected from the corresponding common bit line and are connected to the second preset voltage terminal Vpre.

[0068] The scheme provided in the embodiment can realize the operation of two columns of storage units without the word line selection transistor, can disconnect the connection between the common bit line and the non-target bit line, reduce the capacitive reactance of the common bit line, and can reduce the interference of the non-target bit line on the target bit line by connecting the non-target bit line to the fixed voltage terminal.

[0069] In another example embodiment, as shown in FIG. 4, a plurality of WLs of the same storage unit array are divided into a plurality of word line groups, each word line belongs to only one word line group, and each 4 word lines form a word line group. The word lines in the same word line group are distributed along the first direction X, and there is one word line between adjacent word lines. Taking the storage unit array including N rows and 2M columns of storage units 11, i.e., N*2M storage units 11, and 2M WLs as an example, the jth WL is connected with the jth column of storage units, and j is 1 to 2M. The 1st, 3rd, 5th, and 7th word lines form the 1st word line group, which is connected to the 1st common word line CWL_0; the 2nd, 4th, 6th, and 8th word lines form the 2nd word line group, which is connected to the 2nd common word line CWL_1, and so on. The scheme provided in the embodiment can increase the number of word lines connected to the same common word line, reduce the number of common word lines, thereby reducing the area occupied by the lead-out of the common word line, and reduce the number of word line drivers. However, the number of common bit lines increases, and therefore, a proper number of common word lines and common bit lines can be selected based on design requirements.

[0070] Similar to the embodiment in which each word line group includes two word lines, each CWL is connected with the word lines of two word line groups, and the two word line groups can belong to the storage unit arrays 10 of the same layer of the adjacent two storage arrays, respectively, and the columns of the storage units 11 connected by the word lines in the two word line groups can be the same.

[0071] The adjacent word line groups of the same storage unit array 10 and the word line groups of different storage arrays are connected to the same CWL. The current storage array in which the storage unit array 10 is located includes two adjacent storage arrays, which are referred to as the first storage array and the second storage array. One of the two adjacent word line groups of the storage unit array 10 is connected to the same CWL with the word line group of the first storage array, and the other word line group is connected to the same CWL with the word line group of the second storage array.

[0072] Correspondingly, each row of bit lines distributed along the first direction X corresponds to 4 CBLs, in each row of bit lines, every 2 adjacent BLs are a bit line group, the BLs in the same bit line group are connected to the same CBL, and in the multiple bit line groups formed by the BLs in the same row and arranged in the order of the distribution of the BLs, the BLs in every 4 continuously distributed bit line groups are connected to different CBLs in the 4 CBLs corresponding to the row of bit lines, and the bit line groups connected to the same CBL are spaced by 3 bit line groups. For example, as shown in FIG. 5, the multiple BLs in the i+1th row correspond to 4 common bit lines CBL_i_0, CBL_i_1, CBL_i_2, and CBL_i_3, i is 0 to N-1. Among them, the bit lines in the first column and the second column of the i+1th row form the first bit line group, the bit lines in the third column and the fourth column of the i+1th row form the second bit line group, the bit lines in the fifth column and the sixth column of the i+1th row form the third bit line group, the bit lines in the seventh column and the eighth column of the i+1th row form the fourth bit line group, and the first bit line group is connected to the common bit line CBL_i_0, the second bit line group is connected to the common bit line CBL_i_1, the third bit line group is connected to the common bit line CBL_i_2, and the fourth bit line group is connected to the common bit line CBL_i_3. The connection modes of the subsequent fifth to eighth bit line groups and more bit line groups are similar, and are not described herein again. The connection mode between the above bit line group and the CBL is only an example, and can be other connection modes.

[0073] Among the multiple common word lines connected to each memory cell array 10, only one common word line is activated at the same time, so that only the transistor of the memory cell 11 connected to the bit line of the same common bit line is turned on.

[0074] In some embodiments, as shown in FIG. 6, each of the BLs is connected to the CBL through a first gating sub-circuit 21, the first gating sub-circuit 21 is also connected to a first gating control line, and the first gating sub-circuit 21 is configured to connect or disconnect the BL and the CBL under the control of the first gating control line. The scheme provided in this embodiment can only select the target bit line to be operated by setting the first gating sub-circuit 21, and turn off the non-target bit line, thereby reducing the capacitive reactance of the CBL, reducing power consumption, and improving operation speed. However, the embodiments of the present disclosure are not limited thereto, and in another exemplary embodiment, the first gating sub-circuit 21 can not be provided.

[0075] In some embodiments, as shown in FIG. 6, each of the bit lines can also be connected to a second preset voltage terminal Vpre through a second gating sub-circuit 22 connected to a second gating control line, and the second gating sub-circuit 22 is configured to connect or disconnect the bit line and the second preset voltage terminal Vpre under the control of the second gating control line. The scheme provided in this embodiment can connect the non-target bit line to the preset voltage terminal by setting the second gating sub-circuit 22, so as to avoid the voltage change of the non-target bit line and the interference on the target bit line. However, the embodiments of the present disclosure are not limited thereto, and in some other embodiments, the second gating sub-circuit 22 can not be set.

[0076] In some embodiments, the first gating sub-circuits 21 connected to the same column of bit lines arranged along the second direction Y are connected to the same first gating control line, and the first gating sub-circuits 21 connected to different columns of bit lines are connected to different first gating control lines. As shown in FIG. 6, the storage unit array includes N*2M bit lines, and the bit line in the i-th row and the j-th column is BL_i-1_j-1, i is 1 to N, and j is 1 to 2M, i.e., BL_0_0 to BL_N-1_2M-1. The first gating sub-circuits 21 connected to the bit lines in the first column are all connected to the first first gating control line Ctrl_0_0, the first gating sub-circuits 21 connected to the bit lines in the second column are all connected to the second first gating control line Ctrl_0_3, the first gating sub-circuits 21 connected to the bit lines in the third column are all connected to the third first gating control line Ctrl_1_0, the first gating sub-circuits 21 connected to the bit lines in the fourth column are all connected to the fourth first gating control line Ctrl_1_3, and so on. The first gating sub-circuits 21 connected to the bit lines in the 2M-1-th column are all connected to the 2M-1-th first gating control line Ctrl_M-1_0, and the first gating sub-circuits 21 connected to the bit lines in the 2M-th column are all connected to the 2M-th first gating control line Ctrl_M-1_3.

[0077] In some embodiments, the second gating sub-circuits 22 connected with the bit lines of the same column arranged along the second direction Y are connected with the same second gating control line, the second gating sub-circuits 22 connected with the bit lines of different columns are connected with different second gating control lines, and the second gating sub-circuits 22 connected with the bit lines of 2M columns are connected with 2M different second gating control lines. For example, as shown in FIG. 3, the second gating sub-circuits 22 connected with the bit lines of the first column are all connected with the first second gating control line Ctrl_0_1, the second gating sub-circuits 22 connected with the bit lines of the second column are all connected with the second second gating control line Ctrl_0_2, the second gating sub-circuits 22 connected with the bit lines of the third column are all connected with the third second gating control line Ctrl_1_1, the second gating sub-circuits 22 connected with the bit lines of the fourth column are all connected with the fourth second gating control line Ctrl_1_2, and so on, the second gating sub-circuits 22 connected with the bit lines of the 2M-1th column are all connected with the 2M-1th second gating control line Ctrl_M-1_1, and the second gating sub-circuits 22 connected with the bit lines of the 2Mth column are all connected with the 2Mth second gating control line Ctrl_M-1_2.

[0078] The embodiments of the present disclosure further provide a method for accessing the above memory, which can include:

[0079] In the data read / write stage, according to the word line group to which the target storage unit to be operated is connected, an activation signal is loaded on the common word line connected with the word line group, the target storage unit includes 4 columns of storage units, and the 4 columns of storage units are respectively connected to 4 word lines of the same word line group; a conduction level signal is loaded on the first gating control line connected with the first gating sub-circuit connected with 4 columns of target bit lines respectively connected with the target storage unit, so as to turn on the 4 columns of target bit lines and the corresponding common bit lines; a turn-off level signal is loaded on the second gating control line connected with the second gating sub-circuit connected with the 4 columns of target bit lines, so as to turn off the target bit lines and the second preset voltage terminal; a turn-off level signal is loaded on the first gating control line connected with the non-target bit line, and a conduction level signal is loaded on the second gating control line connected with the non-target bit line, so as to disconnect the non-target bit line and the corresponding common bit line, and connect the non-target bit line to the second preset voltage terminal.

[0080] As shown in FIG. 6, the storage units in columns 2, 4, 6 and 8 are target storage units, the word line groups connected by the target storage units are connected to the common word line CWL_1, and the activation signal is loaded on the common word line CWL_1. Then, the second word line, the fourth word line, the sixth word line and the eighth word line are loaded with the activation signal, the transistors of the storage units in columns 2, 4, 6 and 8 are turned on, the first gating control lines (Ctrl_0_3, Ctrl_1_3, Ctrl_2_3 and Ctrl_3_3) connected to the bit lines in columns 2, 4, 6 and 8 (i.e., target bit lines) are loaded with the turn-on level signal, the second gating control lines (Ctrl_0_2, Ctrl_1_2, Ctrl_2_2 and Ctrl_3_2) connected to the bit lines in columns 2, 4, 6 and 8 are loaded with the turn-off level signal, so that the bit lines in columns 2, 4, 6 and 8 are connected and communicated with the common bit line, and are turned off between the second preset voltage terminal, so that the bit lines connected to the storage units in columns 2, 4, 6 and 8 can share the charge with the storage units. The first gating control lines connected to the bit lines in other columns except columns 2, 4, 6 and 8 (i.e., non-target bit lines) are loaded with the turn-off level signal, and the second gating control lines connected to the bit lines in other columns except columns 2, 4, 6 and 8 (i.e., non-target bit lines) are loaded with the turn-on level signal, so that the bit lines in other columns except columns 2, 4, 6 and 8 are disconnected with the corresponding common bit line and connected to the second preset voltage terminal Vpre.

[0081] In the above embodiments, the word line group includes 2 or 4 word lines as an example. However, the embodiments of the present disclosure are not limited thereto, and the word line group can include other numbers of word lines, such as 3 word lines.

[0082] The embodiments of the present disclosure provide a memory, which can include:

[0083] at least one storage array, a plurality of common word lines and a plurality of common bit lines;

[0084] The storage array includes a plurality of storage unit arrays stacked along a direction perpendicular to a substrate, and a plurality of bit lines extending along a direction perpendicular to the substrate and arranged in a first direction X and a second direction Y;

[0085] The storage unit array includes a plurality of storage units arranged in the first direction X and the second direction Y, a plurality of word lines extending along the second direction Y and corresponding to each column of storage units arranged in the second direction Y, and the word lines are connected to the corresponding column of storage units; and the bit lines are connected to a plurality of storage units at the same position in different layers;

[0086] The plurality of word lines of the same memory cell array are divided into a plurality of word line groups, each word line group is connected to a common word line, and different word line groups are connected to different common word lines; each word line group includes S word lines, and the S word lines in the same word line group are respectively connected to memory cells in different columns; the word lines in the same word line group are distributed along a first direction X, and adjacent word lines in the same word line group are spaced by one word line;

[0087] Each row of bit lines distributed along the first direction X corresponds to S common bit lines; and each row of bit lines is divided into a plurality of bit line groups, each bit line group includes two adjacent bit lines, that is, every two adjacent BLs form a bit line group, the plurality of bit line groups of each row of bit lines are arranged in the arrangement order of the bit lines, the bit lines in the same bit line group are connected to the same common bit line, each bit line group is connected to one of the S common bit lines corresponding to the row of bit lines, and adjacent bit line groups connected to the same common bit line are spaced by S-1 bit line groups. In the plurality of bit line groups formed by the BLs in the same row and arranged in the distribution order of the BLs, the BLs of every S bit line groups are respectively connected to different CBLs of the S CBLs corresponding to the row of bit lines, each bit line group is connected to one CBL, and the S bit line groups are respectively connected to the S CBLs. S is greater than or equal to 2.

[0088] S is greater than or equal to 2. The maximum value of S can be the number of common bit lines that can be accommodated in the region where the row of memory cells is located. For example, S can be 2, 3, 4, etc.

[0089] Similarly, each bit line is connected to a common bit line through a first gating subcircuit 21 and connected to a second preset voltage terminal Vpre through a second gating subcircuit 22. The plurality of first gating subcircuits 21 connected to the plurality of BLs in the same column are connected to the same first gating control line, and the plurality of second gating subcircuits 22 connected to the plurality of bit lines in the same column are connected to the same second gating control line. For details, please refer to the description of the embodiments of the above-mentioned two word lines or four word lines in each word line group.

[0090] The embodiments of the present disclosure also provide an access method of the above-mentioned memory, which can include:

[0091] In the data read / write phase, according to the word line group to which the target memory cell to be operated is connected, an activation signal is loaded on the common word line connected to the word line group; wherein the target memory cell includes S columns of memory cells, and the S columns of memory cells are respectively connected to the S word lines in the same word line group.

[0092] In some embodiments, the method can further include: S column bit lines connected with the S column memory cells respectively are called S column target bit lines, a turn-on level signal is loaded on a first gating control line connected with a first gating sub-circuit connected with the S column target bit lines, so as to turn on the S column target bit lines and corresponding common bit lines; a turn-off level signal is loaded on a second gating control line connected with a second gating sub-circuit connected with the S column target bit lines, so as to avoid the S column target bit lines from being connected to a second preset voltage terminal; a turn-off level signal is loaded on the first gating control line connected with a non-target bit line, and a turn-on level signal is loaded on the second gating control line connected with the non-target bit line, so as to make the non-target bit line connected to the second preset voltage terminal. The scheme provided in the embodiment can disconnect the common bit line and the non-target bit line, reduce the capacitive reactance of the common bit line, and make the voltage of the non-target bit line stable, thereby reducing the interference on the target bit line.

[0093] The embodiments of the present disclosure further provide an electronic device including the memory as described in any of the foregoing embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0094] In some embodiments, the electronic device can further include a control circuit configured to access the memory according to the access method as described in any of the foregoing embodiments. The control circuit can include a driver generating a control signal to the common word line, the first gating control line, and the second gating control line, and the like. The control circuit and a sense amplifier, and the like, can realize the access to the memory.

[0095] Although the embodiments of the present disclosure are disclosed as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A memory, comprising: at least one memory array, a plurality of common word lines and a plurality of common bit lines; the memory array comprises a plurality of memory cell arrays stacked along a direction perpendicular to a substrate, a plurality of bit lines extending along a direction perpendicular to the substrate and arranged along a first direction and a second direction; the memory cell array comprises a plurality of memory cells arranged along the first direction and the second direction, a plurality of word lines extending along the second direction corresponding to each column of memory cells arranged along the second direction, and the word lines connecting the corresponding column of memory cells; the bit lines connecting a plurality of memory cells at the same position of different layers, and the first direction and the second direction being parallel to the substrate and intersecting each other; a plurality of the word lines of the same memory cell array are divided into a plurality of word line groups, each word line group connecting one common word line, and different word line groups connecting different common word lines; each word line group comprises S word lines, and the S word lines in the same word line group are respectively connected to memory cells separated by a column; each row of bit lines arranged along the first direction corresponds to S common bit lines; and each row of bit lines is divided into a plurality of bit line groups, each bit line group comprising two adjacent bit lines, the plurality of bit line groups of each row of bit lines are arranged in the order of arrangement of the bit lines, each bit line group is connected to one of the S common bit lines corresponding to the row of bit lines, and the adjacent bit line groups in the plurality of bit line groups connected to the same common bit line are separated by S-1 bit line groups, and the S is greater than or equal to 2.

2. The memory of claim 1, wherein, The S is 2, 3 or 4.

3. The memory of claim 1, wherein, The memory comprises a plurality of memory arrays arranged along the second direction at intervals, and adjacent memory cells share the common word lines, and in the plurality of word line groups of the memory array, the word line groups in which the word lines connected to the memory cells in odd columns connect the word line groups of one of the two memory arrays adjacent to the memory array to the same common word line, and the word line groups in which the word lines connected to the memory cells in even columns connect the word line groups of the other one of the two memory arrays adjacent to the memory array to the same common word line.

4. The memory of claim 3, wherein, The memory cells in a plurality of columns connected by the word line groups connected to the same common word line and located in different memory arrays are in the same column.

5. The memory of claim 1, wherein, The S is 2, and the common bit lines extend along the first direction, a plurality of the common bit lines are arranged along the second direction at intervals, and at least between adjacent common bit lines, a shielding line extending along the first direction is arranged in the plurality of common bit lines of the same memory cell array.

6. The memory of any one of claims 1 to 5, wherein, A first gating sub-circuit is arranged between each of the bit lines and the common bit lines, the first gating sub-circuit is connected to a first gating control line, and the first gating sub-circuit is configured to electrically connect or disconnect the bit lines and the common bit lines under the control of the first gating control line.

7. The memory of claim 6, wherein, A plurality of first gating sub-circuits connected to the bit lines in the same column arranged along the second direction are connected to the same first gating control line.

8. The memory of claim 7, wherein, Each of the bit lines is also connected to a preset voltage terminal through a second gating sub-circuit, the second gating sub-circuit is connected to a second gating control line, and the second gating sub-circuit is configured to electrically connect or disconnect the bit lines and the preset voltage terminal under the control of the second gating control line.

9. The memory of claim 8, wherein, The plurality of second gating sub-circuits connected with the bit lines in the same column arranged along the second direction are connected to the same second gating control line.

10. An accessing method applied to the memory of any one of claims 1 to 9, comprising: In a data read / write phase, according to a target memory cell to be operated, loading an activation signal on a common word line connected with the word line group in which the word line connected with the target memory cell is located, wherein the target memory cell comprises S memory cells, and the S memory cells are connected to S word lines in the same word line group respectively. The memory is the memory of claim 8 or 9, and the method further comprises: loading a turn-on level signal on a first gating control line connected with a first gating sub-circuit connected with a first target bit line connected with the target memory cell, and loading an off level signal on a second gating control line connected with a second gating sub-circuit connected with a second target bit line connected with the target memory cell; and loading an off level signal on a first gating control line not connected with the target bit line, and loading a turn-on level signal on a second gating control line not connected with the target bit line.

11. The access method of claim 10, wherein, 12. An electronic device comprising the memory of any one of claims 1 to 9. The electronic device further comprises a control circuit configured to access the memory according to the accessing method of claim 10 or 11.

13. The electronic device of claim 12, wherein, ​

Images