Method and apparatus for determining optimal read voltage parameter of flash memory, and flash memory device

Abstract

The present application relates to the technical field of storage, and provides a method and apparatus for determining an optimal read voltage parameter of a flash memory, and a flash memory device. The method comprises: on the basis of a linear relationship model between a read retry voltage offset value and a bit flip count, acquiring a new read retry voltage offset value corresponding to a minimized predicted bit flip count of the flash memory; determining whether data can be successfully read under the new read retry voltage offset value; if yes, adding the new read retry voltage offset value to the header of a read retry offset table to form a new read retry offset table; and on the basis of the new read retry offset table, updating the linear relationship model by means of an adaptive learning model. By means of the efficient and adaptive voltage parameter determination method, the present application can improve the success rate of data recovery and reduce performance loss.

Description

A flash memory optimal read voltage parameter determination method and device and a flash memory device

[0001] Cross-reference to Related Applications

[0002] This application claims priority from the Chinese Patent Application No. 202410756574.5, filed on June 13, 2024, and entitled "A flash memory optimal read voltage parameter determination method and device and a flash memory device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of storage, and in particular to a flash memory optimal read voltage parameter determination method and device and a flash memory device. BACKGROUND

[0004] In modern electronic devices, NAND Flash memory is widely used due to its high density and non-volatility. With the advancement of technology, the storage density of NAND Flash memory is continuously increasing, but at the same time, the reliability of the storage unit is facing challenges. As the use time of the memory increases, the storage unit may age, and the cumulative effects of charge loss or program / erase cycles also increase, leading to an increase in the probability of read errors. To address this challenge, the existing technology adopts a Read Retry (read retry offset) mechanism, which tries to find a parameter configuration that can successfully read data by repeatedly retrying the read operation and adjusting specific read parameters in each retry.

[0005] The existing Read Retry technology mainly relies on pre-set parameter gears, which are usually determined according to the standard characteristics of Flash. When a read operation fails, the controller will try these pre-set gears one by one. Although this method can effectively recover data in some cases, it also has some obvious limitations. First, the pre-set gears may not cover all possible error patterns, especially when the memory ages or works in non-standard environmental conditions. Second, this method often lacks flexibility in finding effective gears because it cannot adjust according to real-time errors. In addition, due to the limited number of pre-set gears, when all gears fail to successfully correct errors, the traditional Read Retry method may cause unnecessary performance degradation. Therefore, the existing technology lacks adaptability and efficiency in dealing with data recovery in NAND Flash, especially when facing complex or unexpected errors. SUMMARY

[0006] Therefore, the application provides a flash memory optimal read voltage parameter determination method and device with high efficiency and self-adaptive effect, which can improve the success rate of data recovery and reduce performance loss.

[0007] The application provides a flash memory optimal read voltage parameter determination method, which comprises the following steps:

[0008] constructing a linear relationship model between read retry voltage offset values and bit flip numbers;

[0009] According to the linear relationship model between read retry voltage offset values and bit flip numbers, a new read retry voltage offset value corresponding to the predicted minimum bit flip number is obtained;

[0010] determining whether data can be successfully read under the new read retry voltage offset value;

[0011] If yes, the new read retry voltage offset value is added to the head of the read retry offset table to form a new read retry offset table;

[0012] According to the new read retry offset table, the linear relationship model is updated through an adaptive learning model;

[0013] The linear relationship model is as follows:

[0014] y = β0 + β1x1 + β2x2 +... + β w x w + ∈

[0015] The y is the bit flip number, the independent variables (x1, x2,..., x w ) are read retry voltage offset values applied to different registers, β0 to β w are coefficients of the linear relationship model, ∈ is the difference between the actually observed bit flip number and the bit flip number predicted through the linear relationship model, and w is the number of registers in the flash memory.

[0016] The linear relationship model is as follows:

[0017] According to the linear relationship model, a new read retry voltage offset value corresponding to the predicted minimum bit flip number is obtained by using a gradient descent method;

[0018] The linear relationship model is as follows:

[0019] apply the new read retry voltage offset value to the linear relationship model to obtain an adaptive updating rule of coefficients in the linear relationship model;

[0020] wherein the new read retry voltage offset value is applied to the linear relationship model to obtain a formula:

[0021] wherein x new,1 ,x new,2 ,…,x new,w is the new read retry voltage offset value, is based on the current coefficients β0, β1, β2, …, β w the predicted value of the number of bit flips obtained by solving;

[0022] wherein the updating rule of the coefficients is:

[0023] wherein, is a loss function, is a partial derivative of the loss function with respect to the coefficient β j , and α is a learning rate, and y new is the new number of bit flips.

[0024] In some embodiments, before obtaining the new read retry voltage offset value corresponding to the predicted minimized number of bit flips according to the linear relationship model between the read retry voltage offset value and the number of bit flips, the method further comprises:

[0025] constructing the linear relationship model, specifically comprising:

[0026] performing read retry operations on the storage page according to each read retry voltage offset value in the read retry offset table to obtain a set of bit flip data sets;

[0027] each element in the data set is one-to-one corresponding to a read retry voltage offset value;

[0028] constructing a linear relationship model containing w independent variables according to the number w of registers in the flash memory.

[0029] In some embodiments, the determination of the coefficients of the linear relationship model comprises:

[0030] minimizing the sum of squares of the difference amount ε;

[0031] taking the partial derivative of each coefficient and setting the partial derivative to 0 to obtain a set of normal equations;

[0032] obtaining the values of the coefficients according to the normal equations.

[0033] In some embodiments, the formula for minimizing the sum of squares of the difference amount ε is:

[0034] where y i is the number of bit flips observed after the i-th read operation, (x ij |j∈(0,w]) is the j-th read retry voltage offset value corresponding to the i-th read operation;

[0035] The formula for taking the partial derivative of each of the coefficients is:

[0036] A set of normal equations is obtained as:

[0037] x T Xβ=X T y;

[0038] where X is a design matrix, y is a vector of observed bit flips, and β is a coefficient vector;

[0039] where,

[0040] According to the normal equations, the value of the coefficient vector β is obtained as: β = (X T X) -1 X T y.

[0041] In some embodiments, the obtaining, according to the linear relationship model between read retry voltage offset values and bit flips, of a new read retry voltage offset value corresponding to the predicted minimized bit flips includes:

[0042] According to the linear relationship model between read retry voltage offset values and bit flips, a gradient descent method is used to obtain a new read retry voltage offset value corresponding to the predicted minimized bit flips;

[0043] wherein the using a gradient descent method to obtain a new read retry voltage offset value corresponding to the predicted minimized bit flips includes:

[0044] selecting, from the read retry offset table, a read retry voltage offset value that minimizes the bit flips as an initial read retry voltage offset value for iteration of the gradient descent method;

[0045] for each iteration, calculating the gradient of the predicted bit flips with respect to each read retry voltage offset value, and updating the read retry voltage offset value;

[0046] applying the read retry voltage offset value obtained in each iteration to a read retry operation, and recording the corresponding bit flips;

[0047] When the termination iteration condition is reached, the gradient descent iteration is terminated, and the read retry voltage offset value of the current iteration is outputted, and the current read retry voltage offset value is taken as the new read retry voltage offset value.

[0048] In some embodiments, the termination iteration condition comprises:

[0049] terminating the iteration when the read retry voltage offset value change amount in the iteration process is less than the minimum adjustment granularity supported by hardware; or

[0050] terminating the iteration when a maximum preset iteration number is reached.

[0051] In some embodiments, after the method is started, when the firmware enters the read retry operation, it is first checked whether a linear relationship model between the read retry voltage offset value and the bit flip number previously constructed is saved in the solid state disk. If it is saved, the new read retry voltage offset value corresponding to the predicted minimum bit flip number is obtained according to the linear relationship model. If it is not saved, the linear relationship model is first constructed.

[0052] In some embodiments, if the flash memory is in SLC mode, w is equal to 1; if the flash memory is in MLC mode, w is equal to 3; and if the flash memory is in TLC mode, w is equal to 7.

[0053] In some embodiments, for each iteration, the read retry voltage offset value is updated by calculating the gradient of the predicted bit flip number with respect to each read retry voltage offset value according to the following formula:

[0054] wherein the gradient represents the change rate of the predicted bit flip number with respect to the i th read retry voltage offset value, a is the learning rate, which determines the size of the update step, and t is the number of iterations.

[0055] In some embodiments, if it is judged that data cannot be successfully read at the new read retry voltage offset value, the current round of algorithm is ended, and an error message is outputted.

[0056] In some embodiments, the adaptive learning model is an online learning method.

[0057] Embodiments of the present application also provide a flash memory optimal read voltage parameter determination device, comprising:

[0058] An obtaining module is configured to obtain a new read retry voltage offset value corresponding to a predicted minimum bit flip number according to a linear relationship model between a read retry voltage offset value and a bit flip number.

[0059] A judging module is configured to judge whether data can be successfully read at the new read retry voltage offset value.

[0060] An add module is used to add the new read retest voltage offset value to the beginning of the read retest offset table if the condition is met, thus forming a new read retest offset table.

[0061] The update module is used to update the linear relationship model based on the new read retry offset table using an adaptive learning model.

[0062] The linear relationship model is as follows:

[0063] y = β0 + β1x1 + β2x2 + ... + β w x w +∈

[0064] Where y is the number of bit flips, and the independent variables are x1, x2, ..., x... w For the read retry voltage offset values ​​applied to different registers, β0 to β w The coefficients of the linear relationship model are ε, where ε is the difference between the actual observed number of bit flips and the number of bit flips predicted by the linear relationship model.

[0065] The method for obtaining the new read retry voltage offset value corresponding to the predicted minimum number of bit flips, based on the linear relationship model, includes:

[0066] Based on the linear relationship model between the read retry voltage offset value and the number of bit flips, the gradient descent method is used to obtain the new read retry voltage offset value corresponding to the predicted minimum number of bit flips.

[0067] Based on the new read retry offset table, the coefficients of the linear relationship model are updated using an adaptive learning model to obtain the updated linear relationship model, specifically including:

[0068] The new retest voltage offset value is applied to the linear relationship model to obtain the adaptive update rule of the coefficients in the linear relationship model;

[0069] The formula obtained by applying the new retest voltage offset value to the linear relationship model is as follows:

[0070] Among them, (x new,1 ,x new,2 ,…,x new,w ) represents the new read retest voltage offset value. Based on the current coefficients (β0, β1, β2, ..., β) w The predicted value of the number of bit flips obtained;

[0071] The update rule for the coefficients is as follows:

[0072] wherein, is a loss function, is a partial derivative of the loss function with respect to the coefficient β j .

[0073] The embodiment of the present application also provides a flash memory device, which comprises a processor and a memory, the memory stores a computer program, and the processor is used for executing the computer program to implement the flash memory optimal read voltage parameter determination method.

[0074] The embodiment of the present application has the following beneficial effects: the real-time analysis and dynamic adjustment of the read retry voltage parameter can significantly improve the accuracy and reliability of the flash memory in the data read process, and the dynamic adjustment mechanism can adapt to various working conditions and aging states, and compared with the static parameter adjustment in the prior art, it can more accurately adapt to the actual situation of the flash memory unit. BRIEF DESCRIPTION OF DRAWINGS

[0075] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0076] Fig. 1 shows a first flowchart of the flash memory optimal read voltage parameter determination method of the embodiment of the present application;

[0077] Fig. 2 shows a second flowchart of the flash memory optimal read voltage parameter determination method of the embodiment of the present application;

[0078] Fig. 3 shows a structure diagram of the flash memory optimal read voltage parameter determination device of the embodiment of the present application. DETAILED DESCRIPTION

[0079] The technical solutions of the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments.

[0080] The components of the embodiments of the present application generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of the present application.

[0081] Hereinafter, the terms "include", "have", and their conjugates, used in the various embodiments of the present application, merely indicate the presence of the features, numbers, steps, operations, elements, components, or combinations thereof, and do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0082] Unless defined otherwise, all terms used herein (including technical terms and scientific terms) have the same meanings as those generally understood by those with ordinary knowledge in the field of the various embodiments of the present application. The terms, such as those defined in a generally used dictionary, will be interpreted to have the same meanings as those in the context of relevant technology and will not be interpreted to have ideal or excessively formal meanings unless clearly defined in the various embodiments of the present application.

[0083] Some embodiments of the present application will be described below in detail with reference to the accompanying drawings. The following embodiments and features of the embodiments can be combined with each other unless there is a conflict.

[0084] The flash memory optimal read voltage parameter determination method will be described below in connection with some specific embodiments.

[0085] FIG. 1 shows a flowchart of a flash memory optimal read voltage parameter determination method according to an embodiment of the present application. The flash memory optimal read voltage parameter determination method includes the following steps:

[0086] In step S100, a new read retry voltage offset value corresponding to the minimum predicted bit flip number is obtained according to the linear relationship model between the read retry voltage offset value and the bit flip number.

[0087] The method of the present application is to analyze the relationship between the read retry voltage offset value (Read Retry voltage parameter) stored in the SSD (Solid State Disk) host memory and the bit flip number in real time, and dynamically adjust the voltage offset value to reduce the bit flip number (bit flip number).

[0088] After the method starts, when the firmware enters the read retry (Read Retry) operation, it first checks whether the linear relationship model between the read retry voltage offset value and the bit flip number previously constructed is saved in the solid state disk. If it is saved, step S100 is performed.

[0089] If the linear relationship model between the read retry voltage offset value and the bit flip number is not saved in the solid state disk, the linear relationship model is first constructed.

[0090] As shown in FIG. 2, the step of constructing the linear relationship model includes:

[0091] The step of constructing the linear relationship model includes:

[0092] In step S110, a read retry operation is performed on the storage page according to each read retry voltage offset value in the read retry offset table, and a set of bit flip number data is obtained.

[0093] In this step, in the read retry operation, the Page is read multiple times according to the Read Retry Offset Table, and a set of bit flip number data C is obtained. For a read retry offset table with a length of n, the data set C contains n elements, respectively representing the bit flip number corresponding to each group of data in the read retry offset table.

[0094] Meanwhile, each group of read retry voltage offset values (offset values) corresponding to each read retry operation is recorded, wherein each group of read retry voltage offset values is a row of the read retry offset table, and is essentially a vector. Each group of read retry voltage offset values corresponding to each read retry operation is formed into a data corresponding set V, including elements V1-Vn. n Each element of V is a vector.

[0095] In step S120, each bit flip number value in the data set C is one-to-one corresponding to each group of read retry voltage offset values in the set V.

[0096] In this step, the data set C is obtained according to the read retry operation under each group of read retry voltage offset values, so that each group of read retry voltage offset values in the set V corresponds to an element in the data set C.

[0097] In step S130, a linear relationship model containing w independent variables is constructed according to the number w of registers in the flash memory.

[0098] In this step, each flash memory has different number of read voltages that can be adjusted according to the number of bits it can store, which are controlled by a corresponding number of read voltage offset registers. The NAND read voltage can be adjusted by writing each set of read retry voltage offset values into the corresponding register. For example, SLC (Single-Level Cell flash memory) has one register, and TLC (Triple-Level Cell flash memory) has seven registers. In the multiple linear relationship model, the voltage offset of each register (i.e., the corresponding read retry voltage offset value) is taken as the independent variable, and a linear relationship model with w independent variables is constructed. The linear relationship model can be represented by formula 1, where formula 1 is:

[0099] y = β0 + β1X1 + β2x2 +... + β w x w + ∈

[0100] wherein the y is the number of bit flips, the independent variables (x1, x2,..., x w ) are the read retry voltage offset values applied to different registers, β0 to β w are the coefficients of the linear relationship model, and ∈ captures all other possible factors that affect the number of bit flips other than the voltage offset, i.e., the difference between the actual observed number of bit flips and the number of bit flips predicted by the linear relationship model. Wherein w represents the number of read voltage offset registers of the flash memory, i.e.:

[0101] That is, if the flash memory is in SLC mode, then w equals 1; if the flash memory is in MLC mode, then w equals 3; if the flash memory is in TLC mode, then w equals 7, and so on. If the flash memory is in other modes, the value of w can also be different from the above values, which are not specifically limited here.

[0102] It should be noted that the linear relationship model in this application is a multiple linear regression model.

[0103] The purpose of this application, for example, includes obtaining a set of coefficients (β0, β1,..., β w ) such that the difference between the number of bit flips predicted by the linear relationship model and the actual observed number of bit flips is minimized, wherein the actual observed number of bit flips can be obtained from the firmware after each read operation. In this application, the coefficients in the linear relationship model are determined by the least squares method.

[0104] The determination of the coefficients (β0, β1,..., β w ) in the linear relationship model includes:

[0105] The coefficients in the linear relationship model are obtained by minimizing the sum of squares of the difference ∈.

[0106] wherein the formula for minimizing the sum of squares of the difference amount ε is formula 2; wherein formula 2 is:

[0107] wherein i indexes each read operation, x ij represents the voltage offset value written on the jth register in the ith read operation, and y i represents the corresponding number of bit flips, i.e., y i is the number of bit flips observed after the ith read operation, and (x ij |j∈(0,w]) is the jth read retry voltage offset value corresponding to the ith read operation.

[0108] Optionally, to minimize the sum of squares of the difference amount ε, it is necessary to take the partial derivative of each coefficient β j in formula 2 and set the partial derivative to 0, as shown in formula 3; wherein formula 3 is:

[0109] Optionally, according to the formula 3, a set of normal equations can be obtained, as shown in formula 4; wherein formula 4 is:

[0110] x T Xβ=X T y.

[0111] wherein X in formula 4 is a design matrix, each row of which corresponds to a voltage offset value of a read operation, y is a vector of observed bit flip numbers, and β is a coefficient vector;

[0112] wherein,

[0113] Optionally, according to the normal equation formula 4, the value of the coefficient vector β can be obtained, as shown in formula 5; wherein formula 5 is:

[0114] β=(X T X) -1 X T y,

[0115] The values of the coefficients (β0, β1, β2, …, β w ) obtained according to formula 5 make the number of bit flips predicted by the linear relationship model closest to the actual observed value.

[0116] The values of the coefficients (β0, β1, β2, …, β wAfter the value of the read retry voltage offset is obtained, the gradient descent method is used to find a read retry voltage offset value that can minimize the predicted bit flip number. The gradient descent method is an iterative optimization algorithm used to find the local minimum of a derivable function. The gradient descent method is used to iteratively update the read retry voltage offset value to reduce the predicted bit flip number.

[0117] In particular, the gradient descent method is used to obtain a new read retry voltage offset value that minimizes the predicted bit flip number of the flash memory, and the gradient descent method includes the following steps.

[0118] First, a read retry voltage offset value that minimizes the bit flip number is selected from the read retry offset table as an initial read retry voltage offset value for iteration of the gradient descent method. The initial read retry voltage offset value is

[0119] Then, for each iteration, the read retry voltage offset value is updated by calculating the gradient of the predicted bit flip number with respect to each read retry voltage offset value according to formula 6.

[0120] wherein formula 6 is:

[0121] In formula 6, the gradient represents the rate of change of the predicted bit flip number with respect to the i-th read retry voltage offset value, and a is the learning rate, which determines the size of the update step, and t is the number of iterations.

[0122] Optionally, the read retry voltage offset value obtained in each iteration is applied to the read retry operation, and the corresponding bit flip number is recorded.

[0123] In each iteration, the read retry voltage offset value obtained in the last iteration is used as the read retry voltage offset value for the current iteration.

[0124] Finally, when the termination iteration condition is reached, the gradient descent method iteration is terminated, and the read retry voltage offset value of the current iteration is output, and the current read retry voltage offset value is used as the new read retry voltage offset value. That is, when any one of the iteration termination conditions is met, the iteration is terminated, and the read retry voltage offset value updated in the last iteration is output

[0125] wherein the termination iteration condition includes:

[0126] (1) If the read retry voltage offset value is less than the minimum adjustment granularity θ supported by the hardware during the iteration process, it means that the read retry voltage offset value has stabilized, and the iteration can be terminated.

[0127] That is, when the absolute value of the difference between the read retry voltage offset value obtained in the last iteration and the read retry voltage offset value obtained in the current iteration is less than the minimum adjustment granularity θ supported by the hardware, the iteration can be terminated.

[0128] (2) To avoid endless iteration, a maximum number of iterations T is preset max If this number is reached, the iteration is stopped, i.e. t≥T max The iteration can be stopped.

[0129] Step S200, determine whether the data can be successfully read at the new read retry voltage offset value.

[0130] If the data can be successfully read, step S300 is performed, the new read retry voltage offset value is added to the head of the read retry offset table to form a new read retry offset table. If the data cannot be successfully read, the current algorithm is ended and an error message is output. Adding the new read retry voltage offset value to the head of the read retry offset table in this step is beneficial to subsequent debugging and transplantation.

[0131] Step S400, update the linear relationship model according to the new read retry offset table through an adaptive learning model.

[0132] In this step, the adaptive learning model is an online learning method.

[0133] This step is to ensure that the linear relationship model is always optimized. The online learning method is used to dynamically update the coefficients of the linear relationship model to form a new linear relationship model. The online learning method allows the linear relationship model to reflect new data patterns in real time without the need to retrain the entire model. Step S400 specifically includes:

[0134] The new read retry voltage offset value is substituted into formula 1 to obtain formula 7;

[0135] Formula 7 is:

[0136] (x new,1 ,x new,2 ,…,x new,w ) in formula 7 is the new read retry voltage offset value, is the predicted value of the number of bit flips based on the current coefficients (β0, β1, β2, …, β w ).

[0137] According to formula 7, the online update rule of the coefficients (β0, β1, β2, …, β w ) is obtained; wherein the update rule is Wherein, α is the learning rate.

[0138] Wherein, is the loss function, and here a square loss is the loss function with respect to the coefficient β jpartial derivative. According to the above, the updating rule of the coefficients (β0, β1, β2, …, β w ) can be:

[0139] In this embodiment, after the new linear relationship model is formed in step S400, the new linear relationship model and the new read retry offset table are saved.

[0140] According to the above steps, the coefficients (β0, β1, β2, …, β w ) and the new read retry voltage offset value are obtained, and according to the coefficients (β0, β1, β2, …, β w ) and the new read retry voltage offset value, the new linear relationship model and the new read retry offset table can be obtained. In this embodiment, the new linear relationship model and the new read retry offset table are saved for next use.

[0141] Firstly, according to the linear relationship model between the read retry voltage offset value and the bit flip number, the new read retry voltage offset value corresponding to the minimized predicted bit flip number is obtained in the present application. If the data can be successfully read under the new read retry voltage offset value, the new read retry voltage offset value is added to the head of the read retry offset table to form a new read retry offset table. And according to the new read retry offset table, the linear relationship model is updated through the adaptive learning model to form a new linear relationship model. Through the real-time analysis and dynamic adjustment of the read retry voltage parameter, the accuracy and reliability of the flash memory in the data reading process are significantly improved. The dynamic adjustment mechanism of the present application enables the flash memory to adapt to various working conditions and aging states. Compared with the static parameter adjustment in the prior art, it can more accurately adapt to the actual situation of the flash memory unit.

[0142] FIG. 3 shows a structural schematic diagram of a flash optimal read voltage parameter determination device according to an embodiment of the present application. The flash optimal read voltage parameter determination device includes, for example:

[0143] The obtaining module 10 is configured to obtain, according to the linear relationship model between the read retry voltage offset value and the bit flip number, the new read retry voltage offset value corresponding to the minimized predicted bit flip number.

[0144] The judging module 20 is configured to judge whether the data can be successfully read under the new read retry voltage offset value.

[0145] The adding module 30 is configured to add, if the data can be successfully read under the new read retry voltage offset value, the new read retry voltage offset value to the head of the read retry offset table to form a new read retry offset table.

[0146] The updating module 40 is configured to update the linear relationship model according to a new read retry offset table through adaptive learning.

[0147] It can be understood that the device of the embodiment corresponds to the flash memory optimal read voltage parameter determination method of the above-mentioned embodiment, and the optional items in the above-mentioned embodiment are also applicable to the embodiment, and therefore will not be described again here.

[0148] The application further provides a flash memory device, which exemplarily comprises a processor and a memory, wherein the memory stores a computer program, and the processor executes the computer program to enable the terminal device to perform the functions of each module in the flash memory optimal read voltage parameter determination method or the flash memory optimal read voltage parameter determination device.

[0149] The processor can be an integrated circuit chip with a signal processing capability. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU), and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations thereof. The general-purpose processor can be a microprocessor, or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps, and logic block diagrams in the embodiments of the application.

[0150] The memory can be, but is not limited to, a random access memory (RAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is configured to store a computer program, and the processor can execute the computer program after receiving an execution instruction.

[0151] The application further provides a readable storage medium for storing the computer program used in the terminal device.

[0152] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other means. The apparatus embodiments described above are only illustrative, for example, the flowcharts and structural diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in alternative implementation, the functions noted in the blocks can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the structural diagram and / or flowchart, and the combination of blocks in the structural diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0153] In addition, the functional modules or units in the various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0154] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0155] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Industrial applicability

[0156] The embodiment of the application provides a flash memory optimal read voltage parameter determination method and device with high efficiency and self-adaptive effect, and a flash memory equipment, which significantly improves the accuracy and reliability of the flash memory in a data reading process.

[0157] In addition, it can be understood that the flash memory optimal read voltage parameter determination method and device and the flash memory equipment are reproducible and can be widely applied to the technical field of storage.

Claims

1. A method for determining optimal read voltage parameters for a flash memory, the method comprising: The method comprises the following steps: constructing a linear relationship model between read retry voltage offset values and bit flip numbers; obtaining a new read retry voltage offset value corresponding to a predicted minimum bit flip number according to the linear relationship model; judging whether data can be successfully read under the new read retry voltage offset value; if yes, adding the new read retry voltage offset value to the head of a read retry offset table to form a new read retry offset table; updating the linear relationship model through an adaptive learning model according to the new read retry offset table; wherein the linear relationship model is: y = β0+ β1x1+ β2x2+... + β w x w + ε; wherein y is the number of bit flips, the independent variables x1, x2,..., x w are read retry voltage offset values applied on different registers, β0 to β w are coefficients of the linear relationship model, ε is the difference between the actual observed number of bit flips and the predicted number of bit flips by the linear relationship model, and w is the number of registers in the flash memory. wherein the step of obtaining a new read retry voltage offset value corresponding to a predicted minimum bit flip number according to the linear relationship model comprises: obtaining a new read retry voltage offset value corresponding to a predicted minimum bit flip number by using a gradient descent method according to the linear relationship model between read retry voltage offset values and bit flip numbers; wherein the step of updating the linear relationship model through an adaptive learning model according to the new read retry offset table comprises: applying the new read retry voltage offset value to the linear relationship model to obtain an adaptive updating rule of coefficients in the linear relationship model; wherein the new read retry voltage offset value is applied in the linear relationship model, and the obtained formula is: wherein x new,1 ,x new,2 ,…,x new,w is the new read retry voltage offset value, To obtain the prediction value of the number of bit flips based on the current coefficients β0, β1, β2, …, β w the obtained prediction value of the number of bit flips; The updating rule of the coefficient is: wherein, For the loss function, is the partial derivative of the loss function with respect to the coefficient β j , α is the learning rate, and y new is the new number of bit flips.

2. The method of claim 1, wherein, the step of constructing a linear relationship model between read retry voltage offset values and bit flip numbers comprises: performing read retry operations on a storage page according to each read retry voltage offset value in the read retry offset table to obtain a set of bit flip number data sets; establishing a one-to-one correspondence between each element in the data set and a read retry voltage offset value; constructing a linear relationship model containing w independent variables according to the number w of registers in the flash memory.

3. The method of claim 1, wherein the step of determining the optimal read voltage parameter of the flash memory is performed by a computer program. the determination of the coefficients of the linear relationship model comprises: minimizing the sum of squares of the difference amount ε; taking the partial derivative of each coefficient and setting the partial derivative to 0 to obtain a set of normal equations; obtaining the values of the coefficients according to the normal equations.

4. The flash memory optimal read voltage parameter determination method according to claim 3, wherein The formula for minimizing the sum of squares of the difference amount ε is: where y i is the number of bit flips observed after the i-th read operation, n is the maximum number of bit flip read operations, x ij | j e (0, w] is the j-th read retry voltage offset value corresponding to the i-th read operation; The formula for taking the partial derivative of each of the coefficients is: the step of obtaining a set of normal equations is: X T Xβ= X T y; wherein X is a design matrix, y is a vector composed of observed bit flip numbers, and β is a coefficient vector; wherein According to the normal equation, the value of the coefficient β vector is obtained, which is expressed as: β = (X T X) -1 X T y.

5. The method of claim 1, wherein, the step of obtaining a new read retry voltage offset value corresponding to a predicted minimum bit flip number by using a gradient descent method comprises: selecting a read retry voltage offset value that minimizes the bit flip number from the read retry offset table as an initial read retry voltage offset value for iteration of the gradient descent method; for each iteration, calculating the gradient of the predicted bit flip number with respect to each read retry voltage offset value and updating the read retry voltage offset value; applying the read retry voltage offset value obtained in each iteration to the read retry operation and recording the corresponding bit flip number; when the termination iteration condition is reached, terminating the iteration of the gradient descent method and outputting the read retry voltage offset value of the current iteration, and taking the current read retry voltage offset value as the new read retry voltage offset value.

6. The method of claim 5, wherein, the termination iteration condition comprises: terminating iteration when the change in the read retry voltage offset value during iteration is less than the minimum adjustment granularity supported by hardware; or terminating iteration when the maximum preset number of iterations is reached.

7. The method of claim 1, wherein, After the method starts, when the firmware enters the read retry operation, first check whether the linear relationship model between the read retry voltage offset value and the bit flip number previously constructed is saved in the solid state disk, if saved, according to the linear relationship model, obtain the new read retry voltage offset value corresponding to the predicted minimum bit flip number; if not saved, first construct the linear relationship model.

8. The method of claim 2, wherein, If the flash memory is in SLC mode, w is equal to 1; if the flash memory is in MLC mode, w is equal to 3; if the flash memory is in TLC mode, w is equal to 7.

9. The method for determining the optimal read voltage parameters of flash memory according to claim 5, characterized in that, For each iteration, the read retry voltage offset value is updated by calculating the gradient of the predicted bit flip number with respect to each read retry voltage offset value according to the following equation: wherein the gradient The change rate of the predicted bit flip number with respect to the i-th read retry voltage offset value, α is the learning rate, which determines the size of the update step, and t is the number of iterations.

10. The method of any of claims 1-9, wherein, If it is judged that the data cannot be successfully read under the new read retry voltage offset value, the current algorithm is ended, and an error message is output.

11. The method of any of claims 1-10, wherein, The adaptive learning model is an online learning method.

12. A device for determining the optimal read voltage parameters of flash memory, characterized in that, Comprise: The construction module is used for constructing the linear relationship model between the read retry voltage offset value and the bit flip number; The acquisition module is used for acquiring the new read retry voltage offset value corresponding to the predicted minimum bit flip number according to the linear relationship model; The judgment module is used for judging whether the data can be successfully read under the new read retry voltage offset value; The addition module is used for if yes, adding the new read retry voltage offset value to the head of the read retry offset table to form a new read retry offset table; The update module is used for updating the linear relationship model through the adaptive learning model according to the new read retry offset table; The linear relationship model is: y = β0+ β1x1+ β2x2+... + β w x w + ε; wherein y is the number of bit flips, the independent variables x1, x2,..., x w are read retry voltage offset values applied on different registers, β0to β w are coefficients of the linear relationship model, and ε is the difference between the actual observed number of bit flips and the number of bit flips predicted by the linear relationship model. The linear relationship model is: According to the linear relationship model, the new read retry voltage offset value corresponding to the predicted minimum bit flip number is obtained by using the gradient descent method. The new read retry voltage offset value is applied to the linear relationship model to obtain the adaptive update rule of the coefficients in the linear relationship model. The flash memory device comprises a processor and a memory, the memory stores a computer program, and the processor is used for executing the computer program to implement the flash memory optimal read voltage parameter determination method in any one of claims 1-11. wherein the new read retry voltage offset value is applied in the linear relationship model, and the obtained formula is: wherein x new,1 ,x new,2 ,…,x new,w is the new read retry voltage offset value, To obtain the prediction value of the number of bit flips based on the current coefficients β0, β1, β2, …, β w The prediction value of the number of bit flips obtained, w is the number of registers in the flash memory; The updating rule of the coefficient is: wherein For the loss function, is the partial derivative of the loss function with respect to the coefficient β j , a is the learning rate, and y new is the new number of bit flips.

13. A flash memory device, comprising: ​

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