Channel encoding method and apparatus, and channel decoding method and apparatus

Abstract

The present application relates to channel encoding in the field of communications. In existing channel encoding technology, an encoding end performs channel encoding on a CB, wherein CB refers to a long code block. The complexity of decoding long code blocks is relatively high, resulting in low decoding efficiency. In the present application, an encoding end divides a CB into a plurality of short code blocks, and each short code block is independently encoded to generate a plurality of corresponding second check bit sets, and the plurality of short code blocks are coupled together on the basis of N first check bit sets to form a first bit sequence. During decoding, each short code block may be first decoded on the basis of the plurality of second check bit sets, and if the decoding is successful, a decoding result is output, and decoding the first bit sequence on the basis of the N first check bit sets is no longer performed. In this way, the decoding of a high-complexity long code block is converted into the decoding of low-complexity short code blocks, thereby improving the decoding efficiency and thus increasing the decoding throughput.

Description

Methods and apparatus for channel coding, and methods and apparatus for channel decoding.

[0001] This application claims priority to Chinese Patent Application No. 202410921307.9, filed on July 10, 2024, entitled “Method and Apparatus for Channel Coding, and Method and Apparatus for Channel Decoding”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communications, specifically to a method and apparatus for channel coding, and a method and apparatus for channel decoding. Background Technology

[0003] Channel coding is a technique that adds redundant information during data transmission to enhance transmission reliability. For example, after acquiring a code block (CB), the transmitter can encode the CB using polar codes or low-density parity-check codes (LDPC), and then perform rate matching and other processing on the encoded result. After receiving the bit sequence, the receiver performs channel decoding based on the channel coding method used by the transmitter.

[0004] With the application of services such as extended reality (XR), higher demands are placed on decoding throughput and other performance characteristics. Improving decoding throughput is a problem that needs to be addressed. Summary of the Invention

[0005] Embodiments of this application provide a method, apparatus, computer-readable storage medium, and computer program product for channel coding, as well as a method, apparatus, computer-readable storage medium, and computer program product for channel decoding, which can improve the throughput of channel coding and channel decoding.

[0006] In a first aspect, embodiments of this application provide a channel coding method. The execution entity of this method can be an encoding end, which can be a base station or a chip applied to a base station, or the encoding end can be a terminal or a chip applied to a terminal. The method includes: determining N first parity bit sets based on a first check bit set (CB), where N is a positive integer; dividing the first CB and the N first parity bit sets into C target bit sets, where C is a positive integer greater than 1; determining C second parity bit sets based on the C target bit sets; and outputting a first bit sequence, the first bit sequence including the C target bit sets and the C second parity bit sets.

[0007] In this embodiment, the first CB, which is a long code block, is divided into C short code blocks (e.g., C target bit sets). Each short code block is independently encoded to generate a corresponding second parity bit set. The C short code blocks are coupled together based on N first parity bit sets to form a first bit sequence. During decoding, each short code block can be decoded based on the C second parity bit sets first. If decoding is successful, the decoding result is output, and the first bit sequence is no longer decoded based on the N first parity bit sets. If decoding fails, the first bit sequence is then decoded based on the N first parity bit sets. Compared to directly decoding the long code block (e.g., the first CB), in this embodiment, the high-complexity long code block decoding is transformed into low-complexity short code block decoding, improving decoding efficiency and thus increasing decoding throughput.

[0008] In an optional implementation of the first aspect, the number of bits in the first CB is a first value, the number of bits in the N first parity bit sets is a second value, and dividing the first CB and the N first parity bit sets into C target bit sets includes: dividing the first CB and the N first parity bit sets into C target bit sets when the sum of the first value and the second value is an integer multiple of C; or, when the sum of the first value and the second value is not an integer multiple of C, determining a first padding bit set, wherein the sum of the number of bits in the first CB, the number of bits in the N first parity bit sets, and the number of bits in the first padding bit set is an integer multiple of C; and dividing the first CB, the N first parity bit sets, and the first padding bit set into C target bit sets.

[0009] When dividing the first CB and the N sets of first parity bits into C target bit sets, padding can be determined based on the number of bits in the first CB (first value) and the number of bits in the N sets of first parity bits (second value). If the sum of the first value and the second value is an integer multiple of C, no padding is needed; otherwise, padding can be performed. Through simple integer multiple judgment and padding operations, the encoding end can achieve the division of the first CB and the N sets of first parity bits without performing complex operations such as modulo and integer division, thereby reducing the computational overhead of dividing the first CB and the N sets of first parity bits.

[0010] In an alternative implementation of the first aspect, the number of bits in the C target bit sets is equal.

[0011] When the number of bits in each of the C target bit sets is equal, the encoding and decoding ends can perform the same operation on each target bit set, reducing the complexity of subsequent processes.

[0012] In an optional implementation of the first aspect, the number of bits in the first CB is a first value, the number of bits in the N first parity bit sets is a second value, and dividing the first CB and the N first parity bit sets into C target bit sets includes: determining γ based on the first value, the second value, and C, wherein the sum of the first value and the second value is a third value, and γ is the result of modulo operation of the third value divided by C; dividing the first CB and the N first parity bit sets into C target bit sets based on γ, wherein the C target bit sets include γ target bit sets and C-γ target bit sets, the number of bits in any set of the γ target bit sets is the result of floor operation ...

[0013] In this embodiment, when the first CB and the N sets of first parity bits are divided into C sets of target bits, the first CB is no longer padded regardless of whether the sum of the first value and the second value is an integer multiple of C, thereby increasing the code rate of the first bit sequence.

[0014] In an optional implementation of the first aspect, determining C sets of second parity bits based on C sets of target bits includes: determining M sets of second padding bits based on the C sets of target bits, wherein the number of bits in set i among the C sets of target bits is K. ri The number of bits in the M second padding bit sets is equal to k b z is the result of subtracting the number of rows from the number of columns in the basis matrix. i For the set of expansion factors that satisfy k b ·z i ≥K ri The minimum expansion factor, M is a positive integer, 1≤i≤C; the C sets of second parity bits are determined based on the M sets of second padding bits and the C sets of target bits.

[0015] The basis matrix is ​​a block representation of the parity-check matrix (PCM). Therefore, the basis matrix can also be called a block parity-check matrix or other names. The lengths of the target bit set and the second parity bit set may differ from the code length supported by the PCM. Therefore, padding is required for the target bit set to adapt to the code length of the PCM.

[0016] In an alternative implementation of the first aspect, M equals C, the M second padding bit sets have the same number of bits, and there is a second padding bit set between any two adjacent sets in the C target bit sets.

[0017] In this embodiment, the design of M second padding bit sets ensures that each of the C target bit sets contains the same or approximately the same number of information bits. If an error occurs in a target bit set during transmission, it will not cause too many information bits to be corrupted, thus better resisting sudden errors during transmission.

[0018] In an optional implementation of the first aspect, M equals C, and the number of bits in the M second padding bit sets is not equal, wherein the number of bits in the second padding bit set closer to the beginning of the first bit sequence is greater than the number of bits in the second padding bit set closer to the end of the first bit sequence.

[0019] In this embodiment, the number of bits in the M second padding bit sets is unequal and gradually decreases from the beginning of the first bit sequence. This causes the bit rate of each code block in the first bit sequence (including the bit sets of the target bit set and the second parity bit set) to gradually increase. If the decoding end adopts a serial decoding method, the low bit rate code block at the beginning is decoded first, and the high bit rate code block at the end is decoded later, which can improve the decoding success rate of the low bit rate code block. After the low bit rate code block is successfully decoded, it can help the high bit rate code block to be decoded, thereby improving the overall decoding success rate of each code block in the first bit sequence.

[0020] In an alternative implementation of the first aspect, M equals 1.

[0021] When M equals 1, the M second padding bit sets can be located before or after a target bit set. In this case, the encoder only needs to perform padding operations when encoding the target bit set, and does not need to perform padding operations when encoding other target bit sets, thereby reducing the hardware complexity of parallel encoding.

[0022] In an alternative implementation of the first aspect, N equals C, the number of bits in the N first check bit sets is equal, and any one of the C target bit sets includes a first check bit set.

[0023] In this embodiment, the N first check bit sets are discretely distributed in the first bit sequence, and the number of information bits contained in each of the C target bit sets is the same or approximately the same, thereby better resisting sudden errors during transmission.

[0024] In an optional implementation of the first aspect, N equals 1, and in the target bit set containing the N first check bit sets, the N first check bit sets are connected to the bits of the first CB.

[0025] In this embodiment, the bits of the first CB and the N sets of first parity bits are not separated by bits that do not need to be sent (e.g., the second padding bit set). When the encoder performs rate matching on the target bit set, it does not need to perform the operation of skipping the second padding bit set, thereby reducing the complexity of rate matching.

[0026] In an optional implementation of the first aspect, N equals 1, and the N first check bits are located at the first position of the first target bit set in the C target bit sets, where the first position is the position in the first target bit set connected to the punch position.

[0027] In some cases, one or more of the C target bit sets may be transmitted after being punctured. If the N first parity bit sets are located in the punctured target bit sets (i.e., the first target bit sets), it is necessary to avoid the punctured positions. For example, the N first parity bit sets can be located at a position connected to the punctured position (i.e., the first position), thereby improving the transmission reliability of the N first parity bit sets.

[0028] In an optional implementation of the first aspect, the first bit sequence further includes M second padding bit sets, the M second padding bit sets being a set determined based on C target bit sets, the second padding bit sets being used to determine C second check bit sets; the method further includes: determining C subsequences based on the first bit sequence, the C subsequences not including the M second padding bit sets; and sending the C subsequences.

[0029] The set of M second padding bits cannot serve as a verification function and is considered invalid information. Skipping the set of M second padding bits during rate matching can reduce the occupation of transmission resources by invalid information and improve resource utilization.

[0030] Secondly, embodiments of this application provide a channel decoding method. The executing entity of this method can be a decoding end, which can be a base station or a chip applied to a base station, or the decoding end can be a terminal or a chip applied to a terminal. The method includes: receiving a first signal; determining a first bit sequence based on the first signal, the first bit sequence including C target bit sets and C second parity bit sets, where C is a positive integer greater than 1 and N is a positive integer; decoding the C target bit sets based on the C second parity bit sets to generate a first checksum (CB), wherein the C second parity bit sets are parity bit sets of the C target bit sets, the C second parity bit sets correspond one-to-one with the C target bit sets, the C target bit sets include N first parity bit sets and the first CB, the N first parity bit sets are parity bit sets of the first CB, and N is a positive integer.

[0031] In this embodiment, the first CB, which is a long code block, is divided into C short code blocks. Each short code block is independently encoded to generate a corresponding second parity bit set. The C short code blocks are coupled together based on N first parity bit sets to form a first bit sequence. During decoding, each short code block can be decoded based on the C second parity bit sets first. If decoding is successful, the decoding result is output, and the first bit sequence is no longer decoded based on the N first parity bit sets. If decoding fails, the first bit sequence is decoded again based on the N first parity bit sets. Compared to directly decoding a long code block (e.g., the first CB), in this embodiment, the high-complexity long code block decoding is transformed into low-complexity short code block decoding, improving decoding efficiency and thus increasing decoding throughput.

[0032] In an optional implementation of the second aspect, the number of bits in the first CB is a first value, and the number of bits in the N first parity bit sets is a second value, wherein the sum of the first value and the second value is an integer multiple of C; or, the sum of the first value, the second value, and the number of bits in the first padding bit set is an integer multiple of C, and the first padding bit set is the set of bits in the first bit sequence.

[0033] When the encoder divides the first CB and the N sets of first parity bits into C target bit sets, it can determine whether padding is needed based on the number of bits in the first CB (first value) and the number of bits in the N sets of first parity bits (second value). If the sum of the first value and the second value is an integer multiple of C, no padding is needed; otherwise, padding is performed. Through simple integer multiple judgment and padding operations, the encoder can achieve the division of the first CB and the N sets of first parity bits without performing complex operations such as modulo and integer division, thereby reducing the computational overhead of dividing the first CB and the N sets of first parity bits.

[0034] In an alternative implementation of the second aspect, the number of bits in the C target bit sets is equal.

[0035] When the number of bits in the C target bit sets is equal, the decoder can decode each short code block based on the same base matrix, thereby reducing the decoding complexity.

[0036] In an optional implementation of the second aspect, the C target bit sets include γ target bit sets and C-γ target bit sets. The number of bits in any set of the γ target bit sets is the result of flooring the third value divided by C. The number of bits in any set of the C-γ target bit sets is the result of flooring the third value divided by C. Here, γ is the result of modulo the third value divided by C, the third value is the sum of the first value and the second value, the first value is the number of bits in the first CB, and the second value is the number of bits in the N first check bit sets.

[0037] In this embodiment, when the encoder divides the first CB and the N sets of first parity bits into C sets of target bits, it no longer fills the first CB regardless of whether the sum of the first value and the second value is an integer multiple of C, thereby improving the code rate of the first bit sequence.

[0038] In an optional implementation of the second aspect, the method further includes: determining M second padding bit sets based on C target bit sets, wherein the number of bits in set i among the C target bit sets is K. ri The number of bits in the M second padding bit sets is equal to k b z is the result of subtracting the number of rows from the number of columns in the basis matrix. i For the set of expansion factors that satisfy k b ·z i ≥K ri The minimum expansion factor, M is a positive integer, 1≤i≤C; the first CB is generated by decoding C target bit sets according to C second parity bit sets, including: decoding C second parity bit sets according to M second padding bit sets and C second parity bit sets to generate the first CB.

[0039] The lengths of the target bit set and the second parity bit set may differ from the code length supported by the parent code parity check matrix. Therefore, the target bit set needs to be padded to match the code length of the parent code parity check matrix.

[0040] In an alternative implementation of the second aspect, M equals C, the number of bits in the M second padding bit sets is equal, and there is a second padding bit set between any two adjacent sets in the C target bit sets.

[0041] In this embodiment, the design of M second padding bit sets ensures that each of the C target bit sets contains the same or approximately the same number of information bits. If an error occurs in a target bit set during transmission, it will not cause too many information bits to be corrupted, thus better resisting sudden errors during transmission.

[0042] In an alternative implementation of the second aspect, M equals C, and the number of bits in the M second padding bit sets is not equal, wherein the number of bits in the second padding bit set closer to the beginning of the first bit sequence is greater than the number of bits in the second padding bit set closer to the end of the first bit sequence.

[0043] In this embodiment, the number of bits in the M second padding bit sets is unequal and gradually decreases from the beginning of the first bit sequence. This causes the bit rate of each code block in the first bit sequence (including the bit sets of the target bit set and the second parity bit set) to gradually increase. If the decoding end adopts a serial decoding method, the low bit rate code block at the beginning is decoded first, and the high bit rate code block at the end is decoded later, which can improve the decoding success rate of the low bit rate code block. After the low bit rate code block is successfully decoded, it can help the high bit rate code block to be decoded, thereby improving the overall decoding success rate of each code block in the first bit sequence.

[0044] In an alternative implementation of the second aspect, M equals 1.

[0045] When M equals 1, the M second padding bit sets can be located before or after a target bit set. In this case, the decoder only needs to perform padding operations when encoding the target bit set, and does not need to perform padding operations when encoding other target bit sets, thereby reducing the hardware complexity of parallel decoding.

[0046] In an alternative implementation of the second aspect, N equals C, the number of bits in the N first check bit sets is equal, and any one of the C target bit sets includes a first check bit set.

[0047] In this embodiment, the N first check bit sets are discretely distributed in the first bit sequence, and the number of information bits contained in each of the C target bit sets is the same or approximately the same, thereby better resisting sudden errors during transmission.

[0048] In an optional implementation of the second aspect, N equals 1, and in the target bit set containing the N first check bit sets, the N first check bit sets are connected to the bits of the first CB.

[0049] In this embodiment, the bits of the first CB and the N sets of first parity bits are not separated by bits that do not need to be sent (e.g., the second padding bit set). When the encoder performs rate matching on the target bit set, it does not need to perform the operation of skipping the second padding bit set, thereby reducing the complexity of rate matching.

[0050] In an optional implementation of the second aspect, N equals 1, and the N sets of first check bits are located at the first position of the first target bit set in the C sets of target bits, where the first position is the position in the first target bit set that is connected to the punching position.

[0051] In some cases, one or more of the C target bit sets may be transmitted after being punctured. If the N first parity bit sets are located in the punctured target bit sets (i.e., the first target bit sets), it is necessary to avoid the punctured positions. For example, the N first parity bit sets can be located at a position connected to the punctured position (i.e., the first position), thereby improving the transmission reliability of the N first parity bit sets.

[0052] Thirdly, embodiments of this application provide a channel coding apparatus. This channel coding apparatus may include a processing unit and an output unit, for performing any of the methods described in the first aspect and its optional embodiments.

[0053] Fourthly, embodiments of this application provide a channel decoding apparatus. The channel decoding apparatus may include a processing unit and an input unit for performing any of the methods described in the second aspect and its optional embodiments.

[0054] Fifthly, embodiments of this application provide a channel coding apparatus, which may be a terminal or a base station, or a chip applied to a terminal or base station. The channel coding apparatus may include a processor for executing any of the methods described in the first aspect and its optional embodiments.

[0055] Optionally, the channel coding device may further include a transceiver. When the channel coding device is a terminal or a base station, the transceiver may be a transceiver circuit, an antenna, etc.; when the channel coding device is a chip applied to a terminal or a base station, the transceiver may be an input / output interface, pins, circuits, etc.

[0056] Optionally, the channel coding apparatus may further include a memory for storing computer programs or instructions. The processor executes the computer programs or instructions stored in the memory to cause the channel coding apparatus to perform any of the methods described in the first aspect and its optional embodiments. When the channel coding apparatus is a terminal or base station, the memory may be a read-only memory, random access memory, etc.; when the channel coding apparatus is a chip applied to a terminal or base station, the memory may be a register, cache, etc.

[0057] Sixthly, embodiments of this application provide a channel decoding apparatus, which may be a terminal or a base station, or a chip applied to a terminal or base station. The channel decoding apparatus may include a processor for executing any of the methods described in the second aspect and its optional embodiments.

[0058] Optionally, the channel decoding device may further include a transceiver. When the channel decoding device is a terminal or a base station, the transceiver may be a transceiver circuit, an antenna, etc.; when the channel decoding device is a chip applied to a terminal or a base station, the transceiver may be an input / output interface, pins, circuits, etc.

[0059] Optionally, the channel decoding device may further include a memory for storing computer programs or instructions. The processor executes the computer programs or instructions stored in the memory to cause the channel decoding device to perform any of the methods described in the second aspect and its optional embodiments. When the channel decoding device is a terminal or base station, the memory may be a read-only memory, random access memory, etc.; when the channel decoding device is a chip applied to a terminal or base station, the memory may be a register, cache, etc.

[0060] In a seventh aspect, embodiments of this application provide a communication system comprising: the channel coding apparatus described in the third aspect and the channel decoding apparatus described in the fourth aspect, or the channel coding apparatus described in the fifth aspect and the channel decoding apparatus described in the sixth aspect.

[0061] Eighthly, embodiments of this application provide a computer-readable storage medium storing a computer program or instructions; when the computer program or instructions are executed on a channel coding device, the channel coding device performs any method of the first aspect and its optional embodiments; when the computer program or instructions are executed on a channel decoding device, the channel decoding device performs any method of the second aspect and its optional embodiments.

[0062] Ninthly, embodiments of this application provide a computer program product comprising: a computer program or instructions; when the computer program or instructions are executed by a channel coding device, causing the channel coding device to perform any method of the first aspect and its optional embodiments; and when the computer program or instructions are executed by a channel decoding device, causing the channel decoding device to perform any method of the second aspect and its optional embodiments. Attached Figure Description

[0063] Figure 1 is a schematic diagram of the architecture of the communication system used in the embodiments of this application;

[0064] Figure 2 is a schematic diagram of an O-RAN architecture provided by an embodiment of this application;

[0065] Figure 3 is a flowchart illustrating a communication method provided in an embodiment of this application;

[0066] Figure 4 is a schematic flowchart of a channel coding method and a channel decoding method provided in an embodiment of this application;

[0067] Figure 5 is a schematic diagram of a method for dividing CB according to an embodiment of this application;

[0068] Figure 6 is a schematic diagram of another method for dividing CB provided by an embodiment of this application;

[0069] Figure 7 is a schematic diagram of another method for dividing CB provided in an embodiment of this application;

[0070] Figure 8 is a schematic diagram of the filling positions of the M second filling bit sets provided in an embodiment of this application;

[0071] Figure 9 shows specific examples of some of the filled positions in Figure 8;

[0072] Figure 10 is a schematic diagram of the filling positions of the N first parity bit sets provided in an embodiment of this application;

[0073] Figure 11 shows specific examples of some of the filled positions in Figure 10;

[0074] Figure 12 is a schematic diagram of a first bit sequence provided in an embodiment of this application;

[0075] Figure 13 is a schematic diagram of another channel coding method provided by an embodiment of this application;

[0076] Figure 14 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0077] Figure 15 is a schematic diagram of another communication device provided in an embodiment of this application. Detailed Implementation

[0078] Figure 1 is a schematic diagram of the architecture of the communication system 1000 used in the embodiments of this application. As shown in Figure 1, the communication system includes a radio access network (RAN) 100, wherein the RAN 100 includes at least one RAN node (110a and 110b in Figure 1, collectively referred to as 110), and may also include at least one terminal (120a-120j in Figure 1, collectively referred to as 120). The RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). The terminal 120 is wirelessly connected to the RAN node 110. Terminals and RAN nodes can be interconnected via wired or wireless means. The communication system 1000 may also include a core network 200. The RAN node 110 is connected to the core network 200 via wireless or wired means. The core network equipment in the core network 200 and the RAN node 110 in the RAN 100 may be independent and different physical devices, or they may be the same physical device that integrates the logical functions of the core network equipment and the logical functions of the RAN node. The communication system 1000 may also include the Internet 300.

[0079] RAN100 can be an evolved universal terrestrial radio access (E-UTRA) system, a new radio (NR) system, or a future radio access system as defined in the 3rd generation partnership project (3GPP), or it can be a Wi-Fi system. RAN100 can also include two or more of the above-mentioned different radio access systems. RAN100 can also be an open RAN (O-RAN).

[0080] RAN nodes, also known as network devices, wireless access network devices, RAN entities, or access nodes, are used to help terminals access communication systems wirelessly.

[0081] In one application scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future communication network, an access point (AP) in a Wi-Fi system, an AP in a long-range radio (LoRa) system, or an AP in a vehicle-to-everything (V2X) system. A RAN node can be a macro base station (as shown in Figure 1, 110a), a micro base station or an indoor station (as shown in Figure 1, 110b), or a relay node or donor node.

[0082] In another application scenario, multiple RAN nodes can collaborate to help terminals achieve wireless access, with different RAN nodes implementing different functions of the base station. For example, a RAN node can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). Here, the CU performs the functions of the base station's Radio Resource Control (RRC) and Packet Data Convergence Protocol (PDCP), and can also perform the functions of the Service Data Adaptation Protocol (SDAP). The DU performs the functions of the base station's Radio Link Control (RANC) and Medium Access Control (MAC) layers, and can also perform some or all of the physical layer functions. For specific descriptions of these protocol layers, refer to the relevant 3GPP technical specifications. The RU can be used to implement radio frequency signal transmission and reception. The CU and DU can be two independent RAN nodes, or they can be integrated into the same RAN node, such as within a baseband unit (BBU). RUs can be included in radio frequency equipment, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs). CUs can be further divided into two types of RAN nodes: CU-control plane and CU-user plane.

[0083] Figure 2 is a schematic diagram of an O-RAN architecture provided by an embodiment of this application.

[0084] As shown in Figure 2, O-RAN 200 includes CU 210, DU 220, and RU 230. Optionally, CU 210 and DU 220 can be integrated into BBU 240. BBU 240 and RU 230 can be co-located or non-co-located. CU 210 can communicate with the core network 250 via a backhaul link, CU 210 and DU 220 can communicate via a midhaul link, DU 220 and RU 230 can communicate via a fronthaul link, and RU 230 and UE 260 can communicate via an air interface.

[0085] In different systems, RAN nodes may have different names. For example, in an O-RAN system, a CU can be called an open CU (O-CU), a DU can be called an open DU (O-DU), and an RU can be called an open RU (O-RU). The RAN nodes in the embodiments of this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. For example, a RAN node can be a server loaded with the corresponding software modules. The embodiments of this application do not limit the specific technology or device form used in the RAN nodes. For ease of description, a base station is used as an example of a RAN node in the following description.

[0086] A terminal is a device with wireless transceiver capabilities, capable of sending signals to or receiving signals from a base station. Terminals are also known as terminal equipment, user equipment (UE), mobile stations, mobile terminals, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality (VR), augmented reality (AR), industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. The terminal can be a mobile phone (as shown in Figure 1, 120a, 120e, 120f, and 120j), a tablet computer (as shown in Figure 1, 120g), a printer with wireless transceiver capabilities (as shown in Figure 1, 120h), a wearable device, a vehicle (as shown in Figure 1, 120b), a charging station (as shown in Figure 1, 120c), an airplane (as shown in Figure 1, 120i), a ship, a robot, a robotic arm, a smart home device (as shown in Figure 1, 120d), etc. The embodiments of this application do not limit the specific technology or device form used in the terminal.

[0087] By way of example and not limitation, in the embodiments of this application, wearable devices may also be referred to as wearable smart devices. This is a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not only hardware devices but also achieve powerful functions through software support, data interaction, and cloud interaction. In a broad sense, wearable smart devices include fully functional, large-sized electronic devices that can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses; or electronic devices that focus on a specific type of application function and require cooperation with other devices such as smartphones, such as various smart bracelets and smart jewelry for measuring vital signs.

[0088] All the terminals described above, if located in a vehicle (e.g., placed inside or installed inside a vehicle), can be considered vehicle-mounted terminals. Vehicle-mounted terminals can also be called vehicle modules, vehicle components, vehicle chips, or on-board units (OBU).

[0089] Base stations and terminals can be fixed or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can be deployed on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of the base stations and terminals.

[0090] The roles of base stations and terminals can be relative. For example, 120i in Figure 1 (which could be a helicopter or a drone) can be configured as a mobile base station. For those 120j accessing the wireless access network 100 via 120i, 120i is a base station; however, for 110a, 120i is a terminal. That is, 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a base station-to-base station interface protocol. In this case, 120i is also a base station relative to 110a. Therefore, both base stations and terminals can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be called communication devices with base station functions, and 120a-120j in Figure 1 can be called communication devices with terminal functions.

[0091] Communication between base stations and terminals, between base stations, and between terminals can be conducted using licensed spectrum, unlicensed spectrum, or both simultaneously. Communication can be conducted using spectrum below 6 GHz, spectrum above 6 GHz, or both simultaneously. The embodiments of this application do not limit the spectrum resources used for wireless communication.

[0092] In the embodiments of this application, the functions of the base station can be executed by modules (such as chips) within the base station, or by a control subsystem that includes base station functions. This control subsystem, including base station functions, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. Similarly, the functions of the terminal can be executed by modules (such as chips or modems) within the terminal, or by a device that includes terminal functions.

[0093] To facilitate understanding of the embodiments of this application, the technologies involved in the embodiments of this application will be briefly introduced below.

[0094] Figure 3 is a flowchart illustrating a communication method provided in an embodiment of this application.

[0095] In this communication method, the transmitting end sends the wireless signal obtained by source coding, channel coding, modulation, and resource mapping of the source to the receiving end. This wireless signal may be subject to noise interference during transmission over the channel between the transmitting and receiving ends. After receiving the wireless signal, the receiving end performs resource demapping, demodulation, channel decoding, and source decoding to obtain the destination (i.e., the reconstructed source). The main steps of this communication method are briefly described below.

[0096] 1. Source coding and source decoding.

[0097] A source of information is the origin of information. The information generated by a source can be one or more of sound, images, and text, or other forms of information. For the sake of simplicity, the distinction between source and information is not made in the embodiments of this application.

[0098] Source coding is a transformation of a source aimed at improving communication efficiency, or a transformation to reduce or eliminate source redundancy. Its main metric is coding efficiency. Specifically, it involves finding a method based on the statistical characteristics of the source to transform it into the shortest possible sequence of information bits, increasing the average information content carried by each bit, while ensuring lossless reconstruction of the source.

[0099] The reverse process of source coding is source decoding, which is the process of restoring the signal before source decoding to obtain the source signal.

[0100] 2. Channel coding and channel decoding.

[0101] Channel coding, also known as error control coding, involves adding redundant bits to the information bits (also called source bits or systematic bits) at the transmitting end. These redundant bits are associated with the information bits. The channel-coded signal includes both information bits and redundant bits. The main goal of channel coding is to improve the reliability of information transmission.

[0102] The reverse process of channel coding is channel decoding. Channel decoding is when the receiver detects and corrects errors generated during transmission based on the correlation between redundant bits and information bits, and restores the information bits, thereby combating interference during transmission and improving the reliability of data transmission.

[0103] 3. Modulation and demodulation.

[0104] Modulation refers to mapping the bits in the bit sequence output by channel coding onto constellation symbols in a constellation diagram. A constellation symbol consists of one or more bits, and one bit in the bit sequence can be mapped to one bit in the constellation symbol.

[0105] The purpose of modulation is to process the digital signal to be transmitted (e.g., the bit sequence mentioned above) in the time domain, frequency domain, or code domain in order to transmit as much information as possible with the smallest possible bandwidth.

[0106] The reverse process of modulation is demodulation, which is the process of recovering the bit sequence from the constellation symbols.

[0107] 4. Resource mapping and resource demapping.

[0108] Resource mapping is the process of mapping a signal (e.g., a constellation-modulated signal) onto transmission resources (e.g., time-domain, frequency-domain, or spatial-domain resources).

[0109] The inverse process of resource mapping is resource demapping, which is the process of restoring the signal mapped onto the transmission resource to its original state.

[0110] Optionally, channel coding may include steps such as adding cyclic redundancy check (CRC) codes, code block segmentation, error correction coding, rate matching, code block concatenation, data interleaving, and data scrambling. Among these, error correction coding is a crucial part of channel coding. The purpose of error correction coding is to ensure that the receiver can automatically correct errors that occur during data transmission with minimal redundancy overhead. At the same bit error rate, the lower the overhead required, the higher the coding efficiency. Traditional channel coding and decoding generally include linear block codes (such as Hamming codes and Gray codes), convolutional codes, and concatenated codes. These codes have their own distinct characteristics and performance, and are suitable for different scenarios.

[0111] In third-generation (3G) and fourth-generation (4G) mobile communication systems, Turbo codes, as a coding-decoding technology defined by the 3GPP standard, exhibit excellent performance, approaching the limits of Shannon's theory. In the 5G era, data transmission rates are orders of magnitude higher than in 4G. For Turbo codes, their serial-processing-based decoders struggle to effectively support such high-speed data transmission. Simultaneously, the 5G era has brought about richer service application scenarios and new requirements for channel coding. For example, massive machine-type communication (mMTC) scenarios require smaller data packets, while ultra-reliable low-latency communication (URLLC) scenarios have high requirements for encoding / decoding latency and low error rates. Therefore, based on different channel coding needs, LDPC and polar codes are applied in different scenarios. Compared to traditional linear block codes and convolutional codes, these two types of codes offer superior performance, approaching the limits of Shannon's theory, but they also have different characteristics in terms of applicable scenarios and the complexity of their codecs.

[0112] With the application of real-time high data rate services such as XR, higher requirements are placed on the peak throughput and area efficiency of encoding and decoding, while the power consumption of decoders must be further reduced. LDPC and polar codes can no longer meet these extremely high requirements. Therefore, channel encoding and decoding for future communication systems need to seek technological breakthroughs in new directions.

[0113] The following describes the encoding and decoding methods provided by embodiments of this application. In the embodiments of this application, the term "encoding" can also be described as "channel encoding / decoding," "network encoding," "external code," or "source-channel joint encoding / decoding." The term "encoding structure" can also be simply referred to as "encoding," "code pattern," or "code design," and can also be described as "concatenated code," "layered code," "coupled code," "external code," "sliding window code," "product code," or "ladder code." The term "start position" can also be described as "head" or "preceding edge," and the term "end position" can also be described as "tail" or "end." The "start position" and "end position" can be distinguished based on the transmission and reception time. For example, for the encoding end, the bit located at the "start position" can be the bit that is output or transmitted first, and the bit located at the "end position" can be the bit that is output or transmitted last; for the decoding end, the bit located at the "start position" can be the bit that is input or received first, and the bit located at the "end position" can be the bit that is input or received last. The "start position" and "end position" can also be distinguished in other ways, and the embodiments of this application are not limited in this regard. It should also be noted that the bit located at the "start position" or "end position" can be one bit or multiple bits. For example, a bit sequence includes 1000 bits, the bit located at the "start position" can be the first bit or the first 100 bits of the 1000 bits, and the bit located at the "end position" can be the last bit or the last 100 bits of the 1000 bits.

[0114] As shown in Figure 4, method 400 is executed by an encoding end and a decoding end, respectively. The encoding end can be a base station or a chip applied to a base station, or the encoding end can be a terminal or a chip applied to a terminal. Similarly, the decoding end can be a base station or a chip applied to a base station, or the decoding end can be a terminal or a chip applied to a terminal. The embodiments of this application do not limit the specific form of the encoding end and the decoding end.

[0115] Method 400 includes:

[0116] S410, the encoding end determines the first CB.

[0117] S410 is an optional step. The first CB can be obtained by dividing the transport block (TB). For example, the encoder can divide the TB evenly into multiple CBs to determine the first CB. Alternatively, the encoder can pad the TB and then divide the padded TB evenly into multiple CBs to determine the first CB.

[0118] Optionally, if the number of bits in TB is small, TB may not be divided and may be regarded as the first CB. The embodiments of this application do not limit the method by which the encoding end determines the first CB.

[0119] The first CB may include information bits and cyclic redundancy check (CRC) bits, or the first CB may include information bits but not CRC bits.

[0120] For example, the number of bits in the first CB is B', where B' = A + L CRC Where A is the number of information bits contained in the first CB, and L CRC L is the number of CRC bits contained in the first CB. CRC The value of can be 0.

[0121] The first CB may also include other types of bits. The embodiments of this application do not limit the specific content of the first CB.

[0122] After determining the first CB, the encoding end can perform the following steps.

[0123] S420, the encoding end determines a set of N first parity bits based on the first CB, where N is a positive integer.

[0124] In various embodiments of this application, the bit set may be a group, block, or sequence consisting of at least one bit, or the bit set may be called a codeword or an encoded sequence. The embodiments of this application do not limit the specific form and name of the bit set.

[0125] As an alternative example, a set of bits consisting of 1011100110, when these bits are input (or received) or output (or transmitted) in sequence, can be called a bit sequence. As another alternative example, when all the bits in a set are stored as a whole at the encoding or decoding end, the set can be called a bit group or a bit block.

[0126] The encoder can encode the first CB based on the parity bit matrix to determine the set of N first parity bits. This parity bit matrix can be called the global parity bit matrix.

[0127] Depending on whether or not the first check digit (CB) is padded, the encoder can determine the set of N first check bits in two ways. The set of N first check bits can also be called global check bits.

[0128] Method 1:

[0129] Without padding the first check bit (CB), the encoder encodes the first CB based on the global parity bit matrix to determine N sets of first parity bits, where the size of the global parity bit matrix is ​​L. Gch ×B, L Gch Let B be the length of the global parity bits, i.e., the number of bits contained in the N sets of first parity bits, and let B be the number of bits obtained after encoding the first CB, where B = B' + L. Gch .

[0130] Method 2:

[0131] When padding the first check bit (CB), the encoder can first determine the first padding bit set (i.e., the global padding bits), and then encode the first CB and the global padding bits based on the global parity bit matrix to determine N sets of first parity bits. In this case, the global padding bits are treated as information bits and participate in the encoding. The size of the global parity bit matrix is ​​L. Gch ×B, L Gch Let B be the length of the global parity bits, i.e., the number of bits contained in the N sets of first parity bits, and let B be the number of bits obtained after encoding the first CB and the global padding bits, where B = B' + L. Gch +F G F G The length of the global padding bits, i.e., the number of bits contained in the first padding bit set.

[0132] The purpose of global padding bits is to ensure that each of the C target bit sets mentioned below has the same number of bits. The method for determining global padding bits will be described in detail below.

[0133] After determining the set of N first parity bits, the encoding end can perform the following steps.

[0134] S430, the encoder divides the first CB and the N first parity bits into C target bit sets, where C is a positive integer greater than 1.

[0135] The encoder divides the first CB and the N first parity bits into C target bit sets, meaning that the C target bit sets include the first CB and the N first parity bits. In the term "target bit set," "target" is used to distinguish different bit sets, and there are no other restrictions. Therefore, "target" can also be replaced by words such as "first," "second," and "third."

[0136] C can be a preset value or determined by other means. The embodiments of this application do not limit the specific way of determining C.

[0137] Based on whether it is ensured that each set in the C target bit sets has the same number of bits, the encoder can handle the division of the C target bit sets in the following two ways.

[0138] Method 3:

[0139] The first value is determined based on the first CB, and the first value is the number of bits in the first CB;

[0140] The second value is determined based on the N sets of first check bits, and the second value is the number of bits in the N sets of first check bits;

[0141] When the sum of the first value and the second value is an integer multiple of C, divide the first CB and the N sets of first check bits into C sets of target bits; or;

[0142] When the sum of the first value and the second value is a non-integer multiple of C, the first padding bit set is determined, wherein the sum of the number of bits in the first CB, the number of bits in the N first parity bit sets, and the number of bits in the first padding bit set is an integer multiple of C; the first CB, the N first parity bit sets, and the first padding bit set are divided into C target bit sets.

[0143] As an optional example, the first value is B', B' = 6998, and the second value is L. Gch L Gch =96, C=4, B'+L Gch =7094, which is not a multiple of 4, so the first CB needs to be padded. Optionally, the number of bits F in the first padded bit set... G It can be 2, so B'+L Gch +F G =7096, 7096 is an integer multiple of 4, which ensures that each of the C target bit sets has the same number of bits. Optionally, F G It could also be other things that can make B'+L Gch +F G A number that is an integer multiple of 4, such as 6, 10, or 14.

[0144] The first set of padding bits can be placed at any position in the first CB. For example, the first set of padding bits can include multiple (e.g., C) subsets, where the spacing between these subsets (i.e., the number of bits between each subset) is the same or approximately the same, thereby better resisting burst errors during the transmission of the first CB. As another example, the first set of padding bits can be located at a punched position in the first CB, such as the header (or start position) of the first CB. The header of the first CB may be punched; placing the first set of padding bits at the punched position can prevent information bits from being punched. For example, the first padding bit set may include multiple (e.g., C) subsets, wherein the subsets located near the head (or starting position) of the first CB contain more bits than the subsets located near the tail (or ending position) of the first CB. This causes the bit rate of each code block (including the bit sets of the target bit set and the second parity bit set) in the first bit sequence described below to gradually increase. If the decoding end adopts a serial decoding method, the low bit rate code block located at the starting position is decoded first, and the high bit rate code block located at the end is decoded later, which can improve the decoding success rate of the low bit rate code block. After the low bit rate code block is successfully decoded, it can help the high bit rate code block to be decoded, thereby improving the overall decoding success rate of each code block in the first bit sequence.

[0145] Optionally, as shown in Figure 5, the encoding end can fill the first padding bit set into the header of the first CB; then, the encoding end encodes the first padding bit set and the first CB to generate N first parity bit sets; the encoding end can divide the bit sequence composed of the first padding bit set, the first CB and the first parity bit set into 4 equal parts to obtain 4 target bit sets, each target bit set containing 1774 bits.

[0146] As another alternative example, the first value is B', where B' = 7000, and the second value is L. Gch L Gch =96, C=4, B'+L Gch =7096, 7096 is an integer multiple of 4, so the first CB does not need to be padded at the encoding end.

[0147] As shown in Figure 6, the encoder can directly encode the first CB to generate the first parity bit set; then, the encoder divides the bit sequence composed of the first CB and the first parity bit set into 4 equal parts to obtain 4 target bit sets, each containing 1774 bits.

[0148] Based on method three, the encoder can obtain a set of C target bits with the same number of bits. In this way, the decoder can decode each short code block (each sub-code block obtained by dividing the first CB) based on the same base matrix, thereby reducing the complexity of decoding.

[0149] Furthermore, when dividing the first CB and the N sets of first parity bits into C target bit sets, padding can be determined based on the number of bits in the first CB (first value) and the number of bits in the N sets of first parity bits (second value). If the sum of the first value and the second value is an integer multiple of C, no padding is needed; otherwise, padding can be performed. Through simple integer multiple judgment and padding operations, the encoding end can achieve the division of the first CB and the N sets of first parity bits without performing complex operations such as modulo and integer division, thereby reducing the computational overhead of dividing the first CB and the N sets of first parity bits.

[0150] Method 4:

[0151] The first value is determined based on the first CB, and the first value is the number of bits in the first CB;

[0152] The second value is determined based on the N sets of first check bits, and the second value is the number of bits in the N sets of first check bits;

[0153] γ is determined based on the first value, the second value, and C, where the sum of the first value and the second value is the third value, and γ is the result of the modulo operation of the third value divided by C.

[0154] Based on γ, the first CB and N sets of first check bits are divided into C sets of target bits. The C sets of target bits include γ sets of target bits and C-γ sets of target bits. The number of bits in any set of γ sets of target bits is the result of the floor operation of the third value divided by C. The number of bits in any set of C-γ sets of target bits is the result of the floor operation of the third value divided by C.

[0155] Use mod to represent the modulo operation. This indicates the floor function. The integer part is represented by γ = B mod C, where B is the third value, i.e., the number of bits obtained after encoding the first CB at the encoding end, B = B' + L. Gch .

[0156] As shown in Figure 7, B = 6998 + 96 = 7094, C = 4, then γ = 7094 mod 4 = 2, that is, the number of bits contained in 2 of the C target bit sets is... The remaining 2(C-γ) target bit sets contain the following number of bits:

[0157] In this embodiment, when the first CB and the N sets of first parity bits are divided into C sets of target bits, the first CB is no longer padded regardless of whether the sum of the first value and the second value is an integer multiple of C, thereby increasing the code rate of the first bit sequence.

[0158] In the examples above, N equals 1. Optionally, N can also take other values, and the position of the N first parity bits is not limited to the position in the examples above. The following text will describe in detail the possible values ​​of N and the position of the N first parity bits. It will not be described in detail here.

[0159] After determining the set of C target bits, the encoding end can perform the following steps.

[0160] S440, the encoding end determines C sets of second parity bits based on C sets of target bits.

[0161] The parity bit matrix used by the encoder when calculating the second parity bit set can be called the local parity bit matrix. The local parity bit matrix may differ from the parent code parity bit matrix; therefore, the target bit set needs to be padded before calculating the second parity bit set. The method for padding the target bit set is described below.

[0162] For example, the mother code parity bit matrix is ​​a globally coupled low-density parity check (GC-LDPC) basis matrix. The GC-LDPC basis matrix is ​​a block matrix, where each block is a z×z square matrix, z∈Z, z is the spread factor, and Z is the set of possible values ​​for the spread factor. The GC-LDPC basis matrix has m blocks. b line n b Column. When filling the target bit set, it is possible to find the smallest z from Z such that k b ·z≥K r Then the length F of the padded bits L =k b ·zK r , where k b =n b -m b K r Let K be the number of bits in any one of the C target bit sets. If the C target bit sets have the same number of bits, then K r =B / C.

[0163] The padding bits in the above example can be called the second padding bit set or local padding bits. It should be noted that F... L The length of the padding bits in a target bit set (i.e., the number of bits contained in the second padding bit set) is given. For C target bit sets, the encoder can determine M second padding bit sets as follows.

[0164] The encoder can determine M sets of second padding bits based on C sets of target bits, where the number of bits in set i among the C sets of target bits is K. ri The number of bits in the M second padding bit sets is equal to k b z is the result of subtracting the number of rows from the number of columns in the basis matrix. i For the set of expansion factors that satisfy k b ·z i ≥K ri The minimum expansion factor, M is a positive integer, 1≤i≤C; the C sets of second parity bits are determined based on the M sets of second padding bits and the C sets of target bits.

[0165] For example, when C=4, the number of bits in the M second padding bit sets is Among them, K r1 Let z1 be the number of bits in the first target bit set, z1 be the expansion factor of the first target bit set, and K be the number of bits in the first target bit set. r2 Let z2 be the number of bits in the second target bit set, z2 be the expansion factor of the second target bit set, and K be the number of bits in the second target bit set. r3 Let z3 be the number of bits in the third target bit set, z3 be the expansion factor of the third target bit set, and K be the number of bits in the third target bit set. r4 Let z4 be the number of bits in the fourth target bit set, and z4 be the expansion factor of the fourth target bit set. If the number of bits in the C target bit sets is the same, and M equals C, then the number of bits in the M second padding bit sets can be expressed as C·(k b ·zK r )express.

[0166] The M second padding bit sets can be placed at any position in the target bit set. Optionally, Figure 8 shows several examples of padding positions for the M second padding bit sets.

[0167] As shown in Figure 8, the first CB, the first padding bit set, and the first parity bit set are divided into four parts. Each part can be called a local code (i.e., the target bit set). Options 1 to 5 are schematic diagrams of the padding positions of the M second padding bit sets in these four local codes.

[0168] Option 1: M equals C, and the number of bits in each second padding bit set is equal.

[0169] In Option 1, each local code is filled with a second padding bit set, and each second padding bit set is located at the end of the corresponding local code. Optionally, the second padding bit set can also be located at the beginning of the corresponding local code or at other positions, that is, there is a second padding bit set between any two adjacent sets in the C target bit sets.

[0170] The design of M sets of second padding bits ensures that each set in the C target bit sets contains the same or approximately the same number of information bits. If an error occurs in a target bit set during transmission, it will not cause too many information bits to be corrupted, thus better resisting sudden errors during transmission.

[0171] Option 2: M equals C, and the number of bits in each second padding bit set decreases sequentially from the head to the tail.

[0172] The head refers to the first bit output after error correction coding, and the tail refers to the last bit output after error correction coding. For example, after the encoder performs error correction coding, it outputs the first bit sequence. If local code 1 is located at the beginning of the first bit sequence, then local code 1 is the head; if local code 4 is located at the end of the first bit sequence, then local code 4 is the tail.

[0173] In option 2, the second padding bit set corresponding to local code 1 has the most bits, the second padding bit set corresponding to local code 4 has the fewest bits, and the second padding bit set corresponding to local code 2 has more bits than the second padding bit set corresponding to local code 3.

[0174] Option 3: M equals C, and the number of bits in each second padding bit set is not equal. The number of bits in the second padding bit set closer to the beginning of the first bit sequence is greater than the number of bits in the second padding bit set closer to the end of the first bit sequence.

[0175] Option 3 is similar to Option 2, that is, the second padding bit set corresponding to local code 1 has the most bits, and the second padding bit set corresponding to local code 4 has the fewest bits. The difference is that the second padding bit set corresponding to local code 2 has the same number of bits as the second padding bit set corresponding to local code 3.

[0176] In options 3 and 2, the number of bits in the M second padding bit sets is unequal and gradually decreases from the beginning of the first bit sequence. This causes the bit rate of each code block in the first bit sequence (including the bit sets of the target bit set and the second parity bit set) to gradually increase. If the decoding end uses a serial decoding method, the low-bit-rate code block at the beginning is decoded first, and the high-bit-rate code block at the end is decoded later, which can improve the decoding success rate of the low-bit-rate code block. After the low-bit-rate code block is successfully decoded, it can help decode the high-bit-rate code block, thereby improving the overall decoding success rate of each code block in the first bit sequence.

[0177] Option 4: M equals 1, and the set of M second padding bits is located at the end of local code 1.

[0178] Option 5: M equals 1, and the set of M second padding bits is located at the end of local code 4.

[0179] When M equals 1, options 4 and 5 respectively provide two possible padding positions for the second padding bit set. Optionally, the M second padding bit sets can be located before or after any of the C target bit sets, or they can be located at the beginning or end of any of the C target bit sets, or they can be connected to the beginning or end of any of the C target bit sets. In this way, the encoder only needs to perform padding operations when encoding one target bit set, and does not need to perform padding operations when encoding other target bit sets, thereby reducing the hardware complexity of parallel encoding.

[0180] Furthermore, in options 4 and 5, the first parity bit set is connected to the bits of the first CB. This design ensures that the bits of the first CB and the first parity bit set are not separated by bits that do not need to be sent (e.g., the second padding bit set). When performing rate matching on the target bit set, there is no need to skip the second padding bit set, thereby reducing the complexity of rate matching.

[0181] The following are some specific examples with reference to Figure 9.

[0182] Let B represent the number of bits obtained after encoding the first CB and the global padding bits; that is, the number of bits in the first CB, the first padding bit set, and the first parity bit set is B. If B = 7096, C = 4, and the number of bits in each local code is equal, then the number of bits in each local code is K. r =7096 / 4=1774; if m b =5,n b =27, then k b =n b -m b=22, the encoder can find the smallest z in Z such that k b ·z≥K r The value of z is 96. The length of the global parity bits in GC-LDPC is equal to the spread factor. Therefore, the number of bits in the N first parity bit sets is 96. Subsequently, the encoder calculates according to F... L =k b ·zK r The number of bits in a second padding bit set is determined to be 338.

[0183] For option 1, the number of bits in the second padding bit set corresponding to each local code is 338, and the number of bits in each local code is K. r +F L =2112, the sum of the number of bits in the four second padding bit sets is 1352.

[0184] For option 3, the second padding bit set corresponding to local code 1 has the most bits, 446; the second padding bit set corresponding to local code 4 has the fewest bits, 230; and the second padding bit sets corresponding to local codes 2 and 3 both have 338 bits. Each local code has 2112 bits, and the sum of the bits in the four second padding bit sets is 1352.

[0185] For option 5, only local code 4 has a corresponding second padding bit set, which has 1352 bits. All local codes have 2112 bits.

[0186] The previous section introduced examples of the positions of the M sets of second padding bits. The following section introduces examples of the positions of the N sets of first parity bits.

[0187] As shown in Figure 10, the first CB, the first padding bit set, and the N first parity bit sets are divided into four parts. Each part can be called a local code (i.e., the target bit set). Options 6 to 8 are schematic diagrams of the padding positions of the N first parity bit sets in these four local codes.

[0188] Option 6: N equals C, and the number of bits in each first parity bit set is equal.

[0189] In option 6, each local code corresponds to a first parity bit set, and each first parity bit set is located at the end of the corresponding local code. Optionally, each first parity bit set can also be located at the beginning or other positions of the corresponding local code; that is, any one of the C target bit sets includes a first parity bit set.

[0190] Option 6 is designed so that each set in the C target bit sets contains the same or approximately the same number of information bits, and the N first parity bit sets are discretely distributed in the first bit sequence, thus better resisting sudden errors during transmission.

[0191] Optionally, in Option 6, the second padding bit set and the first parity bit set of each local code can be swapped to avoid the target bit set and the first parity bit set being interrupted by the bits to be sent (e.g., the second padding bit set).

[0192] Option 7: N equals 1, and the set of N first parity bits is located at the beginning of local code 1.

[0193] Optionally, the set of N first parity bits can be located at the head of local code 2, local code 3, or local code 4.

[0194] Option 7 is designed so that the bits of the first CB and the N sets of first parity bits are not separated by bits that do not need to be sent (e.g., the second padding bit set). When the encoder performs rate matching on the target bit set, it does not need to perform the operation of skipping the second padding bit set, thereby reducing the complexity of rate matching.

[0195] Option 8: N equals 1, and the set of N first check bits is located at the first position of local code 1. The first position is the position in the first target bit set that is connected to the punch position.

[0196] In some cases, the encoding end will punch holes in the first few bits of the local code during transmission, and place the set of N first parity bits in the position connected to the punched position (i.e., the first position). This can prevent the set of N first parity bits from being punched, thereby improving the transmission reliability of the set of N first parity bits.

[0197] Optionally, the set of N first parity bits can also be located in the first position of local code 2, local code 3, or local code 4.

[0198] Options 6 through 8 are examples, not limitations. The set of N first parity bits can also be located in other positions of any local code, such as between the target bit set and the second padding bits.

[0199] The following are some specific examples with reference to Figure 11.

[0200] Let B represent the number of bits obtained after encoding the first CB and the global padding bits; that is, the number of bits in the first CB, the first padding bit set, and the first parity bit set is B. If B = 7096, C = 4, and the number of bits in each local code is equal, then the number of bits in each local code is K. r =7096 / 4=1774; if mb =5,n b =27, then k b =n b -m b =22, the encoder can find the smallest z in Z such that k b ·z≥K r The value of z is 96. The length of the global parity bits in GC-LDPC is equal to the spread factor. Therefore, the number of bits in the N first parity bit sets is 96. Subsequently, the encoder calculates according to F... L =k b ·zK r The number of bits in a second padding bit set is determined to be 338.

[0201] For option 6, the four first parity bit sets are located at the tails of the four local codes, the sum of the number of bits in the four first parity bit sets is 96, and the number of bits in each first parity bit set is 24; the number of bits in the second padding bit set corresponding to each local code is 338, and the number of bits in each local code is K. r +F L =2112.

[0202] For option 7, a first parity bit set is located at the beginning of local code 1, with a bit count of 96; the second padding bit set corresponding to each local code has a bit count of 338, and each local code has a bit count of K. r +F L =2112.

[0203] After determining the N sets of first parity bits and the M sets of second padding bits, the encoder can encode each local code and calculate the parity bits of each local code, that is, determine the C sets of second parity bits.

[0204] For example, if B = 7096, C = 4, and the number of bits in each local code is equal, then the number of bits in each local code is K. r =7096 / 4=1774; if m b =5,n b =27, then k b =n b -m b =22, the encoder can find the smallest z in Z such that k b ·z≥K r The value of z is 96; the number of bits before encoding each local code is 2112 (i.e., 22×96), the number of bits after encoding a local code at the encoding end is 2592 (i.e., 27×96), and the number of bits in each second parity bit set is 480 (i.e., 2592-2112).

[0205] Each set of second parity bits can be located at the end of each encoded local code, as shown in Figure 12. Subsequently, the encoding end can perform the following steps.

[0206] S450, the encoding end outputs the first bit sequence, which includes C target bit sets and C second parity bit sets.

[0207] The following describes a method for rate matching of the first bit sequence.

[0208] Let G represent the number of bits after rate matching, and Q... m N represents the number of bits in each modulation symbol. L This indicates the layer number of the transport block mapping. The encoding end can determine this based on G, Q... m and N L Determine G′, G′ = G / (Q) m ·N L Subsequently, the encoder can determine β based on G′ and C, where β = G′ mod C; subsequently, the encoder can determine β based on G′ and Q. m N L C and β determine C subsequences of the first bit sequence. These C subsequences include β subsequences and C-β subsequences, where the number of bits in any one of the β subsequences is . The number of bits in any one of the C-β subsequences is Finally, the sender can send C subsequences.

[0209] Since the set of M second padding bits cannot serve as a check and is considered invalid information, the encoder can skip the set of M second padding bits during rate matching to reduce the occupation of transmission resources by invalid information and improve resource utilization.

[0210] For example, if C subsequences include a first subsequence, and the first subsequence is any one of the C subsequences, the encoder can perform the following when sending the C subsequences:

[0211] When the number of bits in the first subsequence is less than E r At that time, starting from the beginning position of the first subsequence, E is sent cyclically. r The number of bits carried by the resource mapped to the first subsequence.

[0212] For β subsequences For C-β subsequences

[0213] The following example, with reference to Figure 13, illustrates the execution of method 400 at the encoding end.

[0214] As an optional example, the length of the first CB is B' = 6998, the transmission length after rate matching is G = 9998, and Q... m ·N L =2, the GC-LDPC basis matrix of the local code has 5 rows and 27 columns, that is, m b =5,n b =27, the length L of the global parity bits (i.e., the set of N first parity bits) Gch =96, C=4, the set of possible values ​​for the expansion factor Z is:

[0215] As shown in Figure 13, the encoding end can execute steps 1 to 6.

[0216] Step 1: Add global padding bits.

[0217] Given B' = 6998, L Gch =96, C=4, in order to make (B'+L Gch +F G F is divisible by C. G The value of is 2, that is, 2 global padding bits are added to the beginning of the first CB, and these 2 global padding bits are an example of the first padding bit set.

[0218] Step 2: Calculate the global parity bits.

[0219] After adding global padding bits, (B'+F G =7000, the encoding end encodes the first CB and the first padding bit set to obtain a global parity bit of length 96 (i.e., N sets of first parity bits).

[0220] Step 3: Divide the local code.

[0221] The encoding end divides the encoding result from step 2 into four local codes (i.e., four target bit sets), each local code having a length K. r =7096 / 4=1774.

[0222] Step 4: Add local padding bits.

[0223] Given K r =1774,k b =n b -m b =22, then 22·z≥1774. Searching for the value of z in the above Z, we get z=96. The length F of the local padding bits (i.e., the second padding bit set) of each local code. L =k b ·zK r=22.96–1774 = 338. The length of each local code after padding is 1774 + 338 = 2112.

[0224] Step 5: Calculate the local parity bits.

[0225] Given z = 96, the number of bits obtained after encoding a padded local code at the encoding end is 2592 (i.e., 27 × 96), and the number of local parity bits in each second parity bit set is 480 (i.e., 2592 - 2112). Thus, the encoding end obtains the first bit sequence.

[0226] The encoding end can remove the local padding bits in the first bit sequence to obtain four subsequences, namely subsequence 1 to subsequence 4, each subsequence consisting of 2162 bits.

[0227] Step 6: Rate matching.

[0228] Given G = 9998, Q m ·N L =2, then G′=G / (Q m ·N L )=4999, β=G′mod C=4999mod 4=3.

[0229] Therefore, one of the four subsequences (e.g., subsequence 1) corresponds to E. r for The other three subsequences (e.g., subsequences 2 to 4) correspond to E. r for

[0230] The number of bits in each subsequence is less than its corresponding E. r The sending end can start from the beginning position of each subsequence and send each subsequence cyclically until the number of bits sent reaches the E corresponding to each subsequence. r Until then, as shown by the arrow in Figure 13.

[0231] For example, for subsequence 1, the sender starts transmitting from the first padding bit set and transmits until the second parity bit set is completed, transmitting a total of 2162 bits. The sender can then start transmitting another 336 bits from the first padding bit set. In total, the sender has transmitted 2498 bits, satisfying the E condition corresponding to subsequence 1. r Requirements.

[0232] For example, for subsequence 2, the sender starts transmitting from the information bits of the first check byte (CB) until the second check bit set is completed, transmitting a total of 2162 bits. The sender can then start transmitting another 338 bits from the information bits of the first CB. In total, the sender has transmitted 2500 bits, satisfying the E condition corresponding to sequence 2. r Requirements.

[0233] If the number of bits in each subsequence is greater than E r Then, each subsequence needs to be truncated. For example, it can start sending from the beginning of each subsequence until the number of bits sent reaches E. r In this way, some local parity bits in each subsequence will be discarded. Compared to the method of concatenating the subsequences first and then performing rate matching, performing rate matching on each subsequence separately can avoid discarding too many local parity bits in the last transmitted subsequence, thus improving the decoding success rate of the last transmitted subsequence.

[0234] If the number of bits in each subsequence is equal to E r The encoding end does not need to perform cyclic sending or truncation processing on each subsequence.

[0235] After rate matching, the encoder performs subsequent processing on each sub-sequence to generate the first signal and sends it out. The first signal can be a baseband signal or a radio frequency signal.

[0236] Accordingly, the decoding end can perform the following steps.

[0237] S460, the decoding end receives the first signal.

[0238] If the first signal is a radio frequency (RF) signal, the decoding end can receive the first signal using modules such as a receiving antenna and RF circuitry. If the first signal is a baseband signal, the decoding end can receive the first signal using modules such as baseband circuitry.

[0239] S470, the decoding end determines the first bit sequence based on the first signal. The first bit sequence includes a set of C target bits and a set of C second parity bits, where C is a positive integer greater than 1.

[0240] The first signal carries a first bit sequence. After receiving the first signal, the decoding end recovers the first bit sequence from the first signal.

[0241] S480, the decoding end decodes C target bit sets based on C second check bit sets to generate a first CB. Here, the C second check bit sets are the check bit sets of the C target bit sets, and the C second check bit sets correspond one-to-one with the C target bit sets. The C target bit sets include N first check bit sets and the first CB. The N first check bit sets are the check bit sets of the first CB, and N is a positive integer.

[0242] The construction of the first bit sequence is known to the decoding end, which can perform decoding based on various decoding methods. The embodiments of this application do not limit the decoding method of the decoding end.

[0243] For example, the decoding end can first decode the C target bit sets based on the C second parity bit sets respectively. If the decoding is successful, the decoding end does not need to perform overall decoding of the first bit sequence based on the N first parity bit sets. If the decoding fails, the decoding end can perform overall decoding of the first bit sequence based on the N first parity bit sets to try to recover the first CB.

[0244] For example, the decoding end can directly decode the first bit sequence based on the N sets of first parity bits to try to recover the first CB.

[0245] It should be noted that the decoding end may generate M sets of second padding bits during the decoding process to match the code length of the master code parity check matrix. The M sets of second padding bits generated by the decoding end may be the same as or different from the M sets of second parity bits generated by the encoding end. For example, the decoding end may generate M sets of second padding bits where all bits are 0, and decode C sets of target bits based on the M sets of second padding bits and C sets of second parity bits to generate the first CB.

[0246] As described above, in method 400, the first CB, which is a long code block, is divided into C short code blocks. Each short code block is independently encoded to generate a corresponding set of second parity bits. The C short code blocks are coupled together based on N sets of first parity bits to form a first bit sequence. During decoding, each short code block can be decoded based on the C sets of second parity bits. In this way, the high-complexity long code block decoding is transformed into low-complexity short code block decoding, improving decoding efficiency and thus increasing decoding throughput.

[0247] The foregoing has detailed the method examples provided by the embodiments of this application. It is understood that the corresponding apparatus, in order to achieve the above functions, includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0248] Figures 14 and 15 are schematic diagrams of two communication devices provided in the embodiments of this application. These devices can be used to implement the functions of the encoding end or the decoding end in the above method embodiments, and therefore also possess the beneficial effects of the above method embodiments. When devices 1400 and 1500 are used to implement the function of the encoding end, devices 1400 and 1500 are channel coding devices; when devices 1400 and 1500 are used to implement the function of the decoding end, devices 1400 and 1500 are channel decoding devices.

[0249] As shown in Figure 14, the device 1400 includes a processing unit 1410 and a transceiver unit 1420. Under the control of the processing unit 1410, the transceiver unit 1420 performs receiving and / or output steps. When performing the output step (or sending step), the transceiver unit 1420 acts as a sending unit; when performing the receiving step, it acts as a receiving unit. The device 1400 is used to implement the functions of the encoding or decoding end in the embodiment described in Figure 4.

[0250] When device 1400 is used to implement the function of the encoding end in the embodiment of the method described in FIG4, processing unit 1410 is used to: determine N first parity bit sets according to the first CB, where N is a positive integer; divide the first CB and the N first parity bit sets into C target bit sets, where C is a positive integer greater than 1; determine C second parity bit sets according to the C target bit sets; transceiver unit 1420 is used to: output a first bit sequence, the first bit sequence including the C target bit sets and the C second parity bit sets.

[0251] Optionally, the number of bits in the first CB is a first value, and the number of bits in the N first parity bit sets is a second value. The processing unit 1410 is specifically used to: when the sum of the first value and the second value is an integer multiple of C, divide the first CB and the N first parity bit sets into C target bit sets; or, when the sum of the first value and the second value is not an integer multiple of C, determine the first padding bit set, wherein the sum of the number of bits in the first CB, the number of bits in the N first parity bit sets, and the number of bits in the first padding bit set is an integer multiple of C; and divide the first CB, the N first parity bit sets, and the first padding bit set into C target bit sets.

[0252] Optionally, the number of bits in the C target bit sets is equal.

[0253] Optionally, the number of bits in the first CB is a first value, and the number of bits in the N first parity bit sets is a second value. The processing unit 1410 is specifically used to: determine γ based on the first value, the second value, and C, wherein the sum of the first value and the second value is a third value, and γ is the result of the modulo operation of the third value divided by C; divide the first CB and the N first parity bit sets into C target bit sets based on γ, wherein the C target bit sets include γ target bit sets and C-γ target bit sets, the number of bits in any set of the γ target bit sets is the result of the floor operation of the third value divided by C, and the number of bits in any set of the C-γ target bit sets is the result of the floor operation of the third value divided by C.

[0254] Optionally, the processing unit 1410 is specifically used to: determine M second padding bit sets based on C target bit sets, wherein the number of bits in set i among the C target bit sets is K. ri The number of bits in the M second padding bit sets is equal to k b z is the result of subtracting the number of rows from the number of columns in the basis matrix. i For the set of expansion factors that satisfy k b ·z i ≥K ri The minimum expansion factor, M is a positive integer, 1≤i≤C; the C sets of second parity bits are determined based on the M sets of second padding bits and the C sets of target bits.

[0255] Optionally, M equals C, the number of bits in the M second padding bit sets is equal, and there is a second padding bit set between any two adjacent sets in the C target bit sets.

[0256] Optionally, M equals C, and the number of bits in the M second padding bit sets is not equal, wherein the number of bits in the second padding bit set closer to the beginning of the first bit sequence is greater than the number of bits in the second padding bit set closer to the end of the first bit sequence.

[0257] Optionally, M equals 1.

[0258] Optionally, N equals C, the number of bits in the N first parity bit sets is equal, and any one of the C target bit sets includes a first parity bit set.

[0259] Optionally, N equals 1, and in the target bit set containing the N sets of first check bits, the N sets of first check bits are connected to the bits of the first CB.

[0260] Optionally, N equals 1, and the N sets of first check bits are located at the first position of the first target bit set in the C sets of target bits. The first position is the position in the first target bit set that is connected to the punching position.

[0261] Optionally, the first bit sequence further includes M sets of second padding bits, the M sets of second padding bits being a set determined based on C sets of target bits, the second padding bit sets being used to determine C sets of second parity bits; the processing unit 1410 is further configured to: determine C sub-sequences based on the first bit sequence, the C sub-sequences not including the M sets of second padding bits; the transceiver unit 1420 is further configured to: transmit the C sub-sequences.

[0262] When device 1400 is used to implement the function of the decoding end in the embodiment of the method described in FIG4, transceiver unit 1420 is used to: receive a first signal; processing unit 1410 is used to: determine a first bit sequence according to the first signal, the first bit sequence including C target bit sets and C second check bit sets, where C is a positive integer greater than 1 and N is a positive integer; decode C target bit sets according to C second check bit sets to generate a first CB, wherein C second check bit sets are check bit sets of C target bit sets, C second check bit sets correspond one-to-one with C target bit sets, C target bit sets include N first check bit sets and the first CB, N first check bit sets are check bit sets of the first CB, where N is a positive integer.

[0263] Optionally, the number of bits in the first CB is a first value, and the number of bits in the N first parity bit sets is a second value, wherein the sum of the first value and the second value is an integer multiple of C; or, the sum of the number of bits in the first value, the second value, and the first padding bit set is an integer multiple of C, and the first padding bit set is the set of bits in the first bit sequence.

[0264] Optionally, the number of bits in the C target bit sets is equal.

[0265] Optionally, the C target bit sets include γ target bit sets and C-γ target bit sets. The number of bits in any set of the γ target bit sets is the result of flooring the third value divided by C. The number of bits in any set of the C-γ target bit sets is the result of flooring the third value divided by C. Here, γ is the result of modulo the third value divided by C, the third value is the sum of the first value and the second value, the first value is the number of bits in the first CB, and the second value is the number of bits in the N first check bit sets.

[0266] Optionally, the processing unit 1410 is further configured to: determine M second padding bit sets based on C target bit sets, wherein the number of bits in set i among the C target bit sets is K. ri The number of bits in the M second padding bit sets is equal to k b z is the result of subtracting the number of rows from the number of columns in the basis matrix. i For the set of expansion factors that satisfy k b ·z i ≥K ri The minimum expansion factor, M is a positive integer, 1≤i≤C; the processing unit 1410 is specifically used to: decode C sets of second parity bits according to M sets of second padding bits and C sets of second parity bits to generate the first CB.

[0267] Optionally, M equals C, the number of bits in the M second padding bit sets is equal, and there is a second padding bit set between any two adjacent sets in the C target bit sets.

[0268] Optionally, M equals C, and the number of bits in the M second padding bit sets is not equal, wherein the number of bits in the second padding bit set closer to the beginning of the first bit sequence is greater than the number of bits in the second padding bit set closer to the end of the first bit sequence.

[0269] Optionally, M equals 1.

[0270] Optionally, N equals C, the number of bits in the N first parity bit sets is equal, and any one of the C target bit sets includes a first parity bit set.

[0271] Optionally, N equals 1, and in the target bit set containing the N sets of first check bits, the N sets of first check bits are connected to the bits of the first CB.

[0272] Optionally, N equals 1, and the N sets of first check bits are located at the first position of the first target bit set in the C sets of target bits. The first position is the position in the first target bit set that is connected to the punching position.

[0273] Device 1400 may be a terminal or a base station, or it may be a chip applied to a terminal or a base station. Processing unit 1410 may be implemented in hardware or software. When implemented in hardware, processing unit 1410 may be a logic circuit, integrated circuit, etc.; when implemented in software, processing unit 1410 may be a general-purpose processor that reads software code stored in a storage unit. This storage unit may be integrated into processing unit 1410 or may exist independently outside of processing unit 1410.

[0274] As shown in Figure 15, device 1500 includes a processor 1510 and an interface circuit 1520. The processor 1510 and the interface circuit 1520 are coupled to each other. It is understood that the interface circuit 1520 can be a transceiver or an input / output interface. Optionally, device 1500 may further include a memory 1530 for storing instructions executed by the processor 1510, or storing input data required by the processor 1510 to execute instructions, or storing data generated after the processor 1510 executes instructions.

[0275] When the device 1500 is used to implement the method shown in FIG4, the processor 1510 is used to implement the function of the processing unit 1410, and the interface circuit 1520 is used to implement the function of the transceiver unit 1420.

[0276] When device 1500 is a terminal chip (i.e., a chip applied to a terminal), the terminal chip implements the functions of the encoding end or decoding end in the above method embodiments. The terminal chip receives information from the base station, which can be understood as the information being first received by other modules in the terminal (such as an RF module or antenna), and then sent to the terminal chip by these modules. The terminal chip sends information to the base station, which can be understood as the information being first sent to other modules in the terminal (such as an RF module or antenna), and then sent to the base station by these modules.

[0277] When device 1500 is a base station chip (i.e., a chip applied to a base station), the base station chip implements the functions of the encoding end or decoding end in the above method embodiments. The base station chip receives information from the terminal, which can be understood as the information being first received by other modules in the base station (such as an RF module or antenna), and then sent to the base station chip by these modules. The base station chip sends information to the terminal, which can be understood as the information being sent down to other modules in the base station (such as an RF module or antenna), and then sent to the terminal by these modules.

[0278] In this application, entity A sends information to entity B, either directly or indirectly through other entities. Similarly, entity B receives information from entity A, either directly or indirectly through other entities. Entities A and B can be RAN nodes, or modules within a RAN node or terminal. Information transmission and reception can be between a RAN node and a terminal, such as between a base station and a terminal; between two RAN nodes, such as between a CU and a DU; or between different modules within a single device, such as between a terminal chip and other modules of the terminal, or between a base station chip and other modules of the base station.

[0279] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU) or a system-on-chip (SoC), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0280] The method steps in the embodiments of this application can be implemented in hardware or in software instructions executable by a processor. The software instructions can consist of corresponding software modules, which can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, hard disks, portable hard disks, compact disc read-only memory (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. The storage medium can also be a component of the processor. The processor and storage medium can reside in an ASIC. Alternatively, the ASIC can reside in a base station or terminal. The processor and storage medium can also exist as discrete components in the base station or terminal.

[0281] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of this application are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video optical disc; or it can be a semiconductor medium, such as a solid-state drive. The computer-readable storage medium may be a volatile or non-volatile storage medium, or may include both types of storage media.

[0282] Finally, the following points should be noted regarding the embodiments of this application:

[0283] First, in the embodiments of this application, the terms "first," "second," and various numerical designations are used for ease of description and are not intended to limit the scope of the embodiments of this application. The order of the sequence numbers of the above processes does not imply the order of execution; the execution order of each process should be determined by its function and internal logic.

[0284] Second, in the embodiments of this application, "instruction" can include direct and indirect instructions, as well as explicit and implicit instructions. The information indicated by a certain piece of information is called the information to be instructed. In specific implementations, there are many ways to instruct the information to be instructed. For example, the information to be instructed can be directly instructed, such as the information to be instructed itself or its index. The information to be instructed can also be indirectly indicated by instructing other information, where there is a correlation between the other information and the information to be instructed. Furthermore, a part of the information to be instructed can be indicated, while the other parts are known or pre-agreed upon. For example, the indication of the information to be instructed can be achieved by pre-agreed upon (e.g., by a protocol specifying the existence of a certain information element), thereby reducing the instruction overhead to some extent.

[0285] Third, the “protocol” involved in the embodiments of this application may refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the NR protocol, and related protocols in future communication systems. This application does not limit this.

[0286] Fourth, "predefined" or "preconfigured" can be achieved by pre-storing corresponding codes, tables, or other information-indicating mechanisms in the device (e.g., a terminal or base station). This application does not limit the specific implementation method. "Storing" can refer to storing in one or more memories, which can be separate installations or integrated into the processor or communication device; alternatively, some memories can be separate installations, while others are integrated into the processor or communication device. The type of memory can be any form of storage medium, and this application does not limit this.

[0287] Fifth, "at least one" means one or more, while "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, or A and B exist simultaneously. Here, A and B can be a single object or multiple objects. The character " / " generally indicates that the preceding and following related objects have an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can each be a single object or multiple objects.

[0288] Sixth, in the embodiments of this application, descriptions such as "when," "in the case of," "if," and "if" all refer to the fact that the device (e.g., a terminal or a base station) will make corresponding processing under certain objective circumstances. They are not time limits, nor do they require the device to make a judgment action when implementing it, nor do they imply any other limitations.

[0289] Seventh, in the various embodiments of this application, unless otherwise specified or logically conflicting, the terms and / or descriptions between different embodiments are consistent and can be referenced by each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

Claims

1. A channel coding method, characterized in that, include: Based on the first coded block CB, determine the set of N first parity bits, where N is a positive integer; Divide the first CB and the N sets of first check bits into C sets of target bits, where C is a positive integer greater than 1; Based on the C target bit sets, determine C sets of second check bits; Output a first bit sequence, which includes the C target bit sets and the C second check bit sets.

2. The method according to claim 1, characterized in that, The number of bits in the first CB is a first value, the number of bits in the N first check bit sets is a second value, and the step of dividing the first CB and the N first check bit sets into C target bit sets includes: When the sum of the first value and the second value is an integer multiple of C, the first CB and the N sets of first check bits are divided into the C sets of target bits; or, When the sum of the first value and the second value is a non-integer multiple of C, a first padding bit set is determined, wherein the sum of the number of bits in the first CB, the number of bits in the N first check bit sets, and the number of bits in the first padding bit set is an integer multiple of C; the first CB, the N first check bit sets, and the first padding bit set are divided into the C target bit sets.

3. The method according to claim 1 or 2, characterized in that, The number of bits in the C target bit sets is equal.

4. The method according to claim 1, characterized in that, The number of bits in the first CB is a first value, the number of bits in the N first check bit sets is a second value, and the step of dividing the first CB and the N first check bit sets into C target bit sets includes: γ is determined based on the first value, the second value, and C, wherein the sum of the first value and the second value is the third value, and γ is the result of the modulo operation of the third value divided by C. The first CB and the N sets of first check bits are divided into C sets of target bits according to γ. The C sets of target bits include γ sets of target bits and C-γ sets of target bits. The number of bits in any set of the γ sets of target bits is the result of the floor operation of the third value divided by C. The number of bits in any set of the C-γ sets of target bits is the result of the floor operation of the third value divided by C.

5. The method according to any one of claims 1 to 4, characterized in that, The step of determining the C sets of second parity bits based on the C sets of target bits includes: Based on the C target bit sets, M second padding bit sets are determined, wherein the number of bits in set i among the C target bit sets is K. ri The number of bits in the M second padding bit sets is equal to k b z is the result of subtracting the number of rows from the number of columns in the basis matrix. i For the set of expansion factors that satisfy k b ·z i ≥K ri The smallest expansion factor, M is a positive integer, 1≤i≤C; The C sets of second parity bits are determined based on the M sets of second padding bits and the C sets of target bits.

6. The method according to claim 5, characterized in that, M equals C, the number of bits in the M second padding bit sets is equal, and there is a second padding bit set between any two adjacent sets in the C target bit sets.

7. The method according to claim 5, characterized in that, M equals C, and the number of bits in the M second padding bit sets is not equal, wherein the number of bits in the second padding bit set closer to the beginning of the first bit sequence is greater than the number of bits in the second padding bit set closer to the end of the first bit sequence.

8. The method according to claim 5, characterized in that, M equals 1.

9. The method according to any one of claims 1 to 8, characterized in that, N equals C, the number of bits in the N first check bit sets is equal, and any one of the C target bit sets includes a first check bit set.

10. The method according to any one of claims 1 to 8, characterized in that, N equals 1, and in the target bit set containing the N sets of first check bits, the N sets of first check bits are connected to the bits of the first CB.

11. The method according to any one of claims 1 to 8, characterized in that, N equals 1, and the N sets of first check bits are located at the first position of the first target bit set in the C sets of target bits. The first position is the position in the first target bit set that is connected to the punching position.

12. The method according to any one of claims 1 to 11, characterized in that, The first bit sequence further includes M sets of second padding bits, wherein the M sets of second padding bits are sets determined based on the C target bit sets, and the second padding bit sets are used to determine the C sets of second check bits; the method further includes: C subsequences are determined based on the first bit sequence, wherein the C subsequences do not include the M sets of second padding bits; Send the C subsequences.

13. A channel decoding method, characterized in that, include: Receive the first signal; A first bit sequence is determined based on the first signal. The first bit sequence includes C target bit sets and C second check bit sets, where C is a positive integer greater than 1. The first coded block CB is generated by decoding the C target bit sets according to the C second check bit sets. The C second check bit sets are check bit sets of the C target bit sets, and the C second check bit sets correspond one-to-one with the C target bit sets. The C target bit sets include N first check bit sets and the first CB. The N first check bit sets are check bit sets of the first CB, and N is a positive integer.

14. The method according to claim 13, characterized in that, The number of bits in the first CB is a first value, and the number of bits in the N first check bit sets is a second value, wherein, The sum of the first value and the second value is an integer multiple of C; or, The sum of the first value, the second value, and the number of bits in the first padding bit set is an integer multiple of C, and the first padding bit set is the set of bits in the first bit sequence.

15. The method according to claim 13 or 14, characterized in that, The number of bits in the C target bit sets is equal.

16. The method according to claim 13, characterized in that, The C target bit sets include γ target bit sets and C-γ target bit sets. The number of bits in any set of the γ target bit sets is the result of flooring the third value divided by C. The number of bits in any set of the C-γ target bit sets is the result of flooring the third value divided by C. γ is the result of modulo the third value divided by C. The third value is the sum of the first value and the second value. The first value is the number of bits in the first CB, and the second value is the number of bits in the N first check bit sets.

17. The method according to any one of claims 13 to 16, characterized in that, The method further includes: Based on the C target bit sets, M second padding bit sets are determined, wherein the number of bits in set i among the C target bit sets is K. ri The number of bits in the M second padding bit sets is equal to k b z is the result of subtracting the number of rows from the number of columns in the basis matrix. i For the set of expansion factors that satisfy k b ·z i ≥K ri The smallest expansion factor, M is a positive integer, 1≤i≤C; The step of decoding the C target bit set based on the C second check bit set to generate the first CB includes: The first CB is generated by decoding the C sets of second parity bits based on the M sets of second padding bits and the C sets of second parity bits.

18. The method according to claim 17, characterized in that, M equals C, the number of bits in the M second padding bit sets is equal, and there is a second padding bit set between any two adjacent sets in the C target bit sets.

19. The method according to claim 17, characterized in that, M equals C, and the number of bits in the M second padding bit sets is not equal, wherein the number of bits in the second padding bit set closer to the beginning of the first bit sequence is greater than the number of bits in the second padding bit set closer to the end of the first bit sequence.

20. The method according to claim 17, characterized in that, M equals 1.

21. The method according to any one of claims 13 to 20, characterized in that, N equals C, the number of bits in the N first check bit sets is equal, and any one of the C target bit sets includes a first check bit set.

22. The method according to any one of claims 13 to 20, characterized in that, N equals 1, and in the target bit set containing the N sets of first check bits, the N sets of first check bits are connected to the bits of the first CB.

23. The method according to any one of claims 13 to 20, characterized in that, N equals 1, and the N sets of first check bits are located at the first position of the first target bit set in the C sets of target bits. The first position is the position in the first target bit set that is connected to the punching position.

24. A channel coding apparatus, characterized in that, include: A module for performing the method according to any one of claims 1 to 12.

25. A channel decoding apparatus, characterized in that, include: A module for performing the method according to any one of claims 13 to 23.

26. A channel coding apparatus, characterized in that, include: A processor and an interface circuit, the interface circuit being used to receive signals from other communication devices and transmit them to the processor or to send signals from the processor to other communication devices, the processor being used to implement the method as described in any one of claims 1 to 12 via logic circuits or executing code instructions.

27. A channel decoding device, characterized in that, include: A processor and an interface circuit, the interface circuit being used to receive signals from other communication devices and transmit them to the processor or to send signals from the processor to other communication devices, the processor being used to implement the method as described in any one of claims 13 to 23 via logic circuits or executing code instructions.

28. A communication system, characterized in that, include: The channel coding apparatus of claim 24, and the channel coding apparatus of claim 25; or, The channel coding apparatus of claim 26, and the channel coding apparatus of claim 27.

29. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed by a channel coding device, implement the method as described in any one of claims 1 to 12; and when executed by a channel decoding device, implement the method as described in any one of claims 13 to 23.

30. A computer program product, characterized in that, The computer program product includes a computer program or instructions that, when executed by a channel coding device, implement the method as described in any one of claims 1 to 12; and when executed by a channel decoding device, implement the method as described in any one of claims 13 to 23.

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