Lateral-vertical composite multi-junction TBC solar cell and manufacturing method therefor

Abstract

The present invention relates to the field of solar cells. Disclosed are a lateral-vertical composite multi-junction TBC solar cell and a manufacturing method therefor. The TBC solar cell comprises an N-type silicon wafer. The front surface of the N-type silicon wafer is sequentially provided with a pyramid textured surface and a passivation layer; the back surface of the N-type silicon wafer is provided with a deposition region A and a deposition region B distributed in an interdigitated manner; a gap between the deposition region A and the deposition region B serves as an isolation region, and the surface of the isolation region is sequentially provided with the pyramid textured surface and the passivation layer; the surface of the deposition region A is sequentially provided with a boron diffusion layer A, a phosphorus diffusion layer A, a tunneling oxide layer A, a phosphorus diffusion layer B, the passivation layer and an electrode layer; the surface layer of the N-type silicon wafer located at the bottom of the deposition region B is a boron diffusion layer B, and the surface of the deposition region B is sequentially provided with a tunneling oxide layer B, a boron diffusion layer C, the passivation layer and the electrode layer. The TBC solar cell of the present invention has a lateral-vertical composite multi-junction structure, which is beneficial to further improving the cell conversion efficiency of the cell and also reducing the manufacturing cost and technical difficulty of the cell.

Description

A transverse and longitudinal composite multi-junction TBC solar cell and a preparation method thereof TECHNICAL FIELD

[0001] The present application relates to the field of solar cells, in particular to a transverse and longitudinal composite multi-junction TBC solar cell and a preparation method thereof. BACKGROUND

[0002] IBC cell, also known as cross finger back contact solar cell, is a structural technology that can be compatible with various interface passivation technologies to form TBC, HBC, HPBC and other solar cells. The biggest feature is that the metal cell contact is placed on the back of the cell, and there is no metal electrode on the front surface, so it has a higher short-circuit current J sc , and the back surface can allow wider metal grid lines to reduce the series resistance R s , thereby improving the fill factor FF, so BC type cells often have higher conversion efficiency. In addition, IBC cell module packaging is more flexible, changing from the conventional "Z" shape welding to full back "I" shape welding, avoiding the complex packaging process of conventional modules, and effectively improving the anti-cracking ability of the module. As a TOPCon+ technology, TBC solar cell combines the excellent tunneling silicon oxide / doped amorphous silicon interface passivation technology of TOPCon cell, has higher conversion efficiency potential, and is expected to become the next generation of mass-produced cells.

[0003] Currently, TBC solar cells are generally prepared by high-temperature deposition of p + / n + -poly-Si layer, corresponding laser grooving and wet process steps to form a back cross finger single-junction contact cell. As shown in FIG. 8, currently, the conventional TBC solar cell is generally a single-junction (p-n junction) cell, and its theoretical limit is only ~ 29.43%. Patent CN118136703A discloses a TBC back contact structure crystalline silicon solar cell and a preparation method thereof. The cell includes an N-type silicon substrate, a first tunneling oxide layer, a P-type poly-Si layer, a second tunneling oxide layer, an N-type poly-Si layer, a front passivation film, a back passivation film and an electrode assembly; the back surface of the N-type silicon substrate is distributed with a first and a second deposition area, the first deposition area has a first gap with the side edge of the N-type silicon substrate, and the first and second deposition areas have a second gap; the first tunneling oxide layer and the P-type poly-Si layer are sequentially deposited in the first deposition area; the second tunneling oxide layer covers the second deposition area and part of the P-type poly-Si layer; the N-type poly-Si layer is arranged on the second tunneling oxide layer; the front and back passivation films are arranged on the front and back surfaces of the N-type silicon substrate, respectively; and the electrode assembly includes a first electrode, a second electrode and a third electrode.

[0004] In order to break through the limit efficiency of single-junction cells, the current common method is to use a stacked cell scheme. The common mainstream stacked cell structure is a perovskite cell + crystalline silicon solar cell to form a double-junction (p-n junction) structure, but there are many problems to be solved in the current stacked cell. On the one hand, perovskite cells are ionic crystal cells, which have much poorer long-term outdoor working stability than atomic crystal crystalline silicon cells, resulting in poor reliability of the stacked cell. On the other hand, the preparation process of the cell is quite complex, and the technical difficulty is high, and the required preparation cost is also expensive, which makes it difficult to be used in large areas.

[0005] In summary, in order to break through the limit efficiency of single-junction (p-n junction) TBC solar cells, while reducing the preparation cost and technical difficulty, it is urgent to continuously develop new structures of TBC solar cells. SUMMARY

[0006] In order to solve the above technical problems, the present application provides a horizontal and vertical composite multi-junction TBC solar cell and a preparation method thereof. The TBC solar cell of the present application has a horizontal and vertical composite multi-junction structure (p-n junction), which is beneficial to further improve the cell conversion efficiency of the cell, and at the same time reduces the cell preparation cost and technical difficulty.

[0007] The specific technical scheme of the present application is as follows: In the first aspect, the present application provides a horizontal and vertical composite multi-junction TBC solar cell, which comprises an N-type silicon wafer, and the front surface of the N-type silicon wafer is provided with a pyramid texture and a passivation layer in sequence. The back surface of the N-type silicon wafer is provided with a deposition area A and a deposition area B in a cross-finger distribution; the gap between the deposition area A and the deposition area B is an isolation area, and the surface of the isolation area is provided with a pyramid texture and a passivation layer in sequence.

[0008] The surface of the deposition area A is provided with a boron diffusion layer A, a phosphorus diffusion layer A, a tunneling oxide layer A, a phosphorus diffusion layer B, a passivation layer and an electrode layer in sequence.

[0009] The surface layer of the N-type silicon wafer at the bottom of the deposition area B is a boron diffusion layer B, and the surface of the deposition area B is provided with a tunneling oxide layer B, a boron diffusion layer C, a passivation layer and an electrode layer in sequence.

[0010] As shown in FIG. 1, the above-mentioned TBC solar cell of the present application has a horizontal-vertical composite multi-junction structure (p-n junction). Among them, the first p-n junction a is in a horizontal structure, which is composed of a boron diffusion layer B (p-type region) and the N-type silicon wafer on its left and right sides (the N-type silicon wafer base is an n-type region); the second p-n junction b is in a vertical structure, which is composed of a boron diffusion layer A and an N-type silicon wafer at the bottom thereof; and the third p-n junction c is in a vertical structure, which is composed of a boron diffusion layer A and a phosphorus diffusion layer A (n-type region). First, compared with a conventional single vertical single-junction cell (PERC, TOPCon, HJT, etc.), the above-mentioned horizontal-vertical composite multi-junction TBC solar cell can form a laminated structure in the silicon base itself, which can obtain a higher V oc number, further improving the cell conversion efficiency; secondly, compared with a conventional perovskite + crystalline silicon laminated cell (preparation steps > 20 steps), the preparation steps of the cell are more simple (< 16 steps), the preparation cost is lower, and the laminated structure is entirely composed of atomic crystals, which is more stable in long-term aging (light decay, humidity and heat, ultraviolet, etc.) environment.

[0011] As a preferred, the thickness of the boron diffusion layer A is 200-1300 nm; the thickness of the boron diffusion layer B is 100-500 nm; the thickness of the boron diffusion layer C is 100-300 nm; the thickness of the phosphorus diffusion layer A is 50-400 nm; and the thickness of the phosphorus diffusion layer B is 100-300 nm.

[0012] Secondly, the present application provides a preparation method of the above-mentioned horizontal-vertical composite multi-junction TBC solar cell, which comprises the following steps: S1, double-sided polishing of an N-type silicon wafer.

[0013] S2, boron diffusion, generating a boron diffusion layer A and a BSG layer A on the back surface of the N-type silicon wafer, wherein the boron atom concentration of the boron diffusion layer A is 1E+18-1E+19 cm -3 .

[0014] After the first boron diffusion, the boron diffusion layer A and the BSG layer A can be generated on the back surface of the N-type silicon wafer in sequence.

[0015] S3, removing the BSG layer A.

[0016] The BSG layer A on the back surface after the boron diffusion can be removed by adopting a chain machine or the like, so as to lay a foundation for the subsequent deposition step.

[0017] S4, sequentially depositing a tunneling oxide layer A and an intrinsic polysilicon layer A on the surface of the boron diffusion layer A.

[0018] The purpose of this step is to form the intrinsic polysilicon layer A, which provides conditions for the subsequent conversion into a phosphorus diffusion layer B.

[0019] S5, phosphorus diffusion, the surface layer of boron diffusion layer A, the inner layer and the surface layer of intrinsic polysilicon layer A are respectively converted into phosphorus diffusion layer A (phosphorus atom concentration is 5E+18~2E+20 cm -3 ), phosphorus diffusion layer B (phosphorus atom concentration is >1E+20 cm -3 ) and PSG layer.

[0020] In the phosphorus diffusion process, by controlling the phosphorus atom concentration of the phosphorus diffusion surface to be greater than the boron atom concentration of the first boron diffusion surface, the phosphorus atoms can pass through the tunneling oxide layer A, so that the surface layer of the boron diffusion layer A is converted from a p-type region (i.e. a boron diffusion region) to an n-type region (i.e. a phosphorus diffusion region), while the deep layer of the boron diffusion layer A remains a p-type doped region. At the same time, the inner layer of the intrinsic polysilicon layer A is also converted into a phosphorus diffusion layer B after phosphorus diffusion.

[0021] S6, the PSG layer of the N-type silicon wafer back surface deposition area B and the isolation area is removed by laser patterning treatment.

[0022] S7, alkaline cleaning to remove the deposition layer (including boron diffusion layer A, phosphorus diffusion layer A, tunneling oxide layer A and phosphorus diffusion layer B) of the deposition area B and the isolation area.

[0023] When the PSG layer of the deposition area B and the isolation area is removed by laser, the deposition area at the bottom of the original PSG layer in this area can be removed during alkaline cleaning, so that the back surface of the silicon wafer is exposed to provide conditions for subsequent deposition. While the deposition area A is protected by PSG, the bottom deposition area is retained.

[0024] S8, tunneling oxide layer B and intrinsic polysilicon layer B are deposited on the surface of deposition area A, deposition area B and isolation area in sequence.

[0025] The purpose of this step is to form intrinsic polysilicon layer B to provide conditions for subsequent conversion into boron diffusion layer C.

[0026] S9, boron diffusion, the surface layer of the N-type silicon wafer at the bottom of the deposition area B and the isolation area, the inner layer and the surface layer of intrinsic polysilicon layer B are respectively converted into boron diffusion layer B (boron atom concentration is 1E+19~2E+19 cm -3 ), boron diffusion layer C (boron atom concentration is 1E+19~1E+20 cm -3 ) and BSG layer B.

[0027] In the present boron diffusion process, by controlling the surface concentration of boron atoms, the boron atoms can pass through the tunneling oxide layer B of the deposition area A and the isolation area to the bottom of the N-type silicon wafer, so that the surface layer of the N-type silicon wafer is converted into P-type silicon, i.e., the boron diffusion layer B. The surface of the deposition area A is effectively blocked from the bottom area of the PSG layer due to the presence of the intermediate PSG layer. Meanwhile, the inner layer and the surface layer of the intrinsic polysilicon layer B are converted into the boron diffusion layer C and the BSG layer B after the present boron diffusion.

[0028] S10, removing the BSG layer B of the deposition area A and the isolation area by laser patterning treatment.

[0029] S11, removing the sputtering layer on the front surface and the side surface of the N-type silicon wafer.

[0030] S12, cleaning and texturing.

[0031] In the process, since there is no sputtering layer on the front surface of the silicon wafer, an effective light-trapping textured surface (i.e., a pyramid textured surface) can be formed under the action of an alkali solution; and the deposition area A on the back surface of the silicon wafer is effectively corroded and removed by the alkali solution until the deposition layer of the PSG layer, i.e., each deposition layer formed after the PSG layer on the surface of the deposition area A on the back surface of the N-type silicon wafer is removed by the alkali solution (the deposition area A is prevented from being further corroded due to the blocking of the PSG layer), and each deposition layer in the junction between the deposition area A and the deposition area B (the isolation area) is also removed after being corroded by the alkali solution, thereby forming a gap (the gap has no deposition layer, i.e., the back surface of the N-type silicon wafer is in an exposed state), and a pyramid textured surface is formed in the gap after further corrosion by the alkali solution. In addition, since the BSG layer B still exists in the deposition area B, the parts of the deposition area B are protected from being damaged during the cleaning and texturing process. Finally, the PSG layer on the back surface of the silicon wafer is removed by acid washing (i.e., the boron diffusion layer B in the deposition area A is exposed), and the BSG layer B on the outermost layer of the deposition area B is also removed.

[0032] S13, double-sided film plating.

[0033] S14, screen printing, sintering, light injection, to obtain a finished battery.

[0034] Preferably, in S1, the N-type silicon wafer is an N-type single crystal silicon wafer cut by a diamond wire.

[0035] Preferably, in S2, the boron diffusion conditions are as follows: boron diffusion temperature 900-950℃, diffusion time 10-50min, BCl3 gas flow rate 50-500sccm, O2 gas flow rate 500-2000sccm; oxidation promotion temperature 1000-1050℃, O2 gas flow rate 3000-50000sccm, promotion time 30-80min, and the thickness of the obtained BSG layer A is 30-70nm.

[0036] As preferred, in S4, the conditions for depositing the tunnel oxide layer A are: O2 flow rate 10000-80000sccm, temperature 400-800℃, time 200-1000s, and the thickness of the obtained tunnel oxide layer A is 1-10nm.

[0037] As preferred, in S4, the conditions for depositing the intrinsic polysilicon layer A are: SiH4 flow rate 300-2000sccm, temperature 500-700℃, time 2-4h, working pressure 100-500mTorr, and the thickness of the obtained intrinsic polysilicon layer A is 100-300nm.

[0038] As preferred, in S5, the conditions for phosphorus diffusion are: phosphorus diffusion temperature 750-850℃, diffusion time 5-30min, POCl3 carried by nitrogen with a flow rate of 500-2500sccm, and O2 flow rate 500-3000sccm; followed by oxidation promotion, temperature 850-950℃, promotion time 5-60min, and O2 flow rate 1000-10000sccm; and the thickness of the obtained PSG layer is 30-70nm.

[0039] As further preferred, in S5, the conditions for phosphorus diffusion are: phosphorus diffusion temperature 750-850℃, diffusion time 5-30min, POCl3 carried by nitrogen with a flow rate of 500-2500sccm, and O2 flow rate 500-3000sccm; followed by oxidation promotion, and simultaneously again introducing POCl3 carried by nitrogen with a flow rate of 1000-5000sccm for 2-10min; oxidation promotion temperature 850-950℃, promotion time 5-20min, and O2 flow rate 5000-20000sccm; and the thickness of the obtained PSG layer is 30-70nm.

[0040] In the above process, the method of "high surface doping concentration + short oxidation promotion time" is used to make the PSG layer contain a higher concentration of phosphorus source, which has the advantages that: on the one hand, the phosphorus atoms can again pass through the tunnel oxide layer A to form a phosphorus diffusion layer A with better diffusion effect; on the other hand, the concentration of phosphorus atoms in the phosphorus diffusion layer B can be maintained at a stable value and not be greatly reduced.

[0041] As preferred, in S6, the conditions for laser patterning are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0042] As preferred, in S8, the conditions for depositing the tunneling oxide layer B are: O2 gas flow 10000-80000sccm, temperature 400-800℃, time 200-1000s, and the thickness of the obtained tunneling oxide layer B is 1-10nm.

[0043] As preferred, in S8, the conditions for depositing the intrinsic polysilicon layer B are: SiH4 gas flow 300-2000sccm, temperature 500-700℃, time 2-4h, working pressure 100-500mTorr, and the thickness of the obtained intrinsic polysilicon layer B is 100-300nm.

[0044] As preferred, in S9, the conditions for boron diffusion are: boron diffusion temperature 800-950℃, diffusion time 5-50min, BCl3 gas flow 50-500sccm, O2 gas flow 500-2000sccm; oxidation promotion temperature 900-1050℃, O2 flow 5000-30000sccm, promotion time 30-80min, and the thickness of the obtained BSG layer B is 30-70nm.

[0045] As preferred, in S10, the conditions for laser patterning are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and processing time 1-5s.

[0046] Compared with the prior art, the present application has the following beneficial effects: (1) The TBC solar cell of the present application has a horizontal and vertical composite multi-junction structure (p-n junction), which can obtain a higher V oc value, and is beneficial to further improve the cell conversion efficiency.

[0047] (2) The present application successfully obtains a TBC solar cell with a horizontal and vertical composite multi-junction structure through a series of ingenious process step designs, and can also reduce the cell preparation cost and technical difficulty.

[0048] (3) The present application strictly controls the phosphorus diffusion and the second boron diffusion processes respectively, so that the phosphorus atoms and boron atoms can respectively pass through the tunneling oxide layer, and are respectively converted into the phosphorus diffusion layer A and the boron diffusion layer B at the surface layer of the boron diffusion layer A and the surface layer of the N-type silicon wafer, thereby successfully constructing a horizontal and vertical composite multi-junction structure. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 is a structure schematic diagram of a horizontal and vertical composite multi-junction TBC solar cell according to an embodiment of the present application.

[0050] Figure 2 is a structure schematic diagram of a silicon wafer after double-sided polishing in Example 1 of the present application.

[0051] Figure 3 is a structural schematic diagram of a silicon wafer after boron diffusion in Embodiment 1 of the present application.

[0052] Figure 4 is a structural schematic diagram of a silicon wafer after phosphorus diffusion in Embodiment 1 of the present application.

[0053] Figure 5 is a structural schematic diagram of a silicon wafer after alkaline cleaning in Embodiment 1 of the present application.

[0054] Figure 6 is a structural schematic diagram of a silicon wafer after boron diffusion in Embodiment 1 of the present application.

[0055] Figure 7 is a structural schematic diagram of a silicon wafer after cleaning and texturing in Embodiment 1 of the present application.

[0056] Figure 8 is a structural schematic diagram of a conventional back cross-finger single-junction contact cell.

[0057] The reference signs are: N-type silicon wafer 1, boron diffusion layer A 2, phosphorus diffusion layer A 3, tunneling oxide layer A 4, phosphorus diffusion layer B 5, PSG layer 6, tunneling oxide layer B 7, boron diffusion layer C 8, BSG layer B 9, pyramid texturing 10, passivation layer 11, electrode layer 12, boron diffusion layer B 13, first p-n junction a, second p-n junction b, third p-n junction c. DETAILED DESCRIPTION

[0058] The present application is further described below in conjunction with embodiments.

[0059] Firstly, the present application provides a horizontal and vertical composite multi-junction TBC solar cell, comprising an N-type silicon wafer, and a pyramid texturing and a passivation layer arranged on the front surface of the N-type silicon wafer in sequence. The back surface of the N-type silicon wafer is provided with a deposition area A and a deposition area B in a cross-finger distribution; the gap between the deposition area A and the deposition area B is an isolation area, and the surface of the isolation area is provided with a pyramid texturing and a passivation layer in sequence.

[0060] The surface of the deposition area A is provided with a boron diffusion layer A, a phosphorus diffusion layer A, a tunneling oxide layer A, a phosphorus diffusion layer B, a passivation layer and an electrode layer in sequence. The surface layer of the N-type silicon wafer at the bottom of the deposition area B is a boron diffusion layer B, and the surface of the deposition area B is provided with a tunneling oxide layer B, a boron diffusion layer C, a passivation layer and an electrode layer in sequence.

[0061] In some specific embodiments, the thickness of the boron diffusion layer A is 200-1300 nm; the thickness of the boron diffusion layer B is 100-500 nm; the thickness of the boron diffusion layer C is 100-300 nm; the thickness of the phosphorus diffusion layer A is 50-400 nm; and the thickness of the phosphorus diffusion layer B is 100-300 nm.

[0062] Secondly, the application provides a preparation method of the above-mentioned horizontal and vertical composite multi-junction TBC solar cell, specifically comprising the following steps: S1, double-side polishing of an N-type silicon wafer.

[0063] In some specific embodiments, a N-type monocrystalline silicon wafer is selected after being cut by a diamond wire, the thickness of the wafer is 100-200 μm, and the size of the wafer is 182.2 mm x 186.7 mm. The cut N-type monocrystalline silicon wafer is placed into an alkali polishing tank, the temperature is maintained at 75-85 ℃, and the double-side polishing is performed for 6-8 min, the polishing thickness is 3-7 μm, and the thinning amount is 0.35-0.45 g.

[0064] S2, boron diffusion, to generate a boron diffusion layer A and a BSG layer A on the back surface of the N-type silicon wafer. After the first boron diffusion, the boron diffusion layer A and the BSG layer A are sequentially generated on the back surface of the N-type silicon wafer.

[0065] In some specific embodiments, the boron diffusion conditions are as follows: the boron diffusion temperature is 900-950 ℃, the diffusion time is 10-50 min, the BCl3 gas flow rate is 50-500 sccm, the O2 gas flow rate is 500-2000 sccm, the oxidation advancing temperature is 1000-1050 ℃, the O2 gas flow rate is 3000-50000 sccm, the advancing time is 30-80 min, and the thickness of the obtained BSG layer A is 30-70 nm. The boron atom concentration in the boron diffusion layer A is 1E+18-1E+19 cm -3 .

[0066] S3, removing the BSG layer A.

[0067] In some specific embodiments, a chain machine is used to remove the BSG layer A on the back surface after boron diffusion, wherein the concentration of the HF solution in the chain machine is 20-80 wt%, and the belt speed is 0.5-5 m / min.

[0068] S4, sequentially depositing a tunnel oxide layer A and an intrinsic polysilicon layer A on the surface of the boron diffusion layer A. The purpose of this step is to form the intrinsic polysilicon layer A, to provide conditions for subsequent conversion into a phosphorus diffusion layer B.

[0069] In some specific embodiments, the conditions for depositing the tunnel oxide layer A are as follows: the O2 gas flow rate is 10000-80000 sccm, the temperature is 400-800 ℃, and the time is 200-1000 s, and the thickness of the obtained tunnel oxide layer A is 1-10 nm.

[0070] In some specific embodiments, the conditions for depositing the intrinsic polysilicon layer A are as follows: the SiH4 gas flow rate is 300-2000 sccm, the temperature is 500-700 ℃, the time is 2-4 h, the working gas pressure is 100-500 mTorr, and the thickness of the obtained intrinsic polysilicon layer A is 100-300 nm.

[0071] S5, phosphorus diffusion, the surface layer of boron diffusion layer A, the inner layer and the surface layer of intrinsic polysilicon layer A are respectively converted into phosphorus diffusion layer A (phosphorus atom concentration is 5E+18~2E+20cm -3 ), phosphorus diffusion layer B (phosphorus atom concentration >1E+20cm -3 ) and PSG layer. In the phosphorus diffusion process, by controlling the phosphorus atom concentration of the phosphorus diffusion surface to be greater than the boron atom concentration of the first boron diffusion surface, the phosphorus atoms can pass through the tunneling oxide layer A, so that the surface layer of the boron diffusion layer A is converted from a p-type region (i.e. a boron diffusion region) to an n-type region (i.e. a phosphorus diffusion region), while the deep layer of the boron diffusion layer A remains a p-type doped region. At the same time, the inner layer of the intrinsic polysilicon layer A is also converted into a phosphorus diffusion layer B after phosphorus diffusion.

[0072] In some specific embodiments, the conditions of the phosphorus diffusion are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30min, POCI3 carried by nitrogen with a flow rate of 500~2500sccm, O2 flow rate 500~3000sccm; then oxidation promotion, temperature 850~950℃, promotion time 5~60min, O2 flow rate 1000~10000sccm; the obtained PSG layer thickness is 30~70nm.

[0073] In some more preferred embodiments, the conditions of the phosphorus diffusion are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30min, POCI3 carried by nitrogen with a flow rate of 500~2500sccm, O2 flow rate 500~3000sccm; then oxidation promotion, simultaneously again inputting POCI3 carried by nitrogen with a flow rate of 1000~5000sccm, inputting time 2~10min; oxidation promotion temperature 850~950℃, promotion time 5~20min, O2 flow rate 5000~20000sccm; the obtained PSG layer thickness is 30~70nm.

[0074] S6, removing the PSG layer of the deposition area B and the isolation area on the back surface of the N-type silicon wafer by laser patterning treatment.

[0075] In some specific embodiments, the conditions of the laser patterning treatment are: laser wavelength 400~600nm, frequency 500~700KHz, marking speed 40000~50000mm / s, power 10~50W, processing time 1~5s.

[0076] S7, remove the deposited layers (including boron diffusion layer A, phosphorus diffusion layer A, tunneling oxide layer A and phosphorus diffusion layer B) in the deposition region B and the isolation region by alkali cleaning. After the PSG layer in the deposition region B and the isolation region is removed by laser, the deposited layers in the bottom of the PSG layer in the deposition region B and the isolation region can be removed in the alkali cleaning process, so that the back surface of the silicon wafer is exposed to provide conditions for subsequent deposition. The deposited layers in the bottom of the deposition region A are protected by the PSG and are not removed.

[0077] In some specific embodiments, the conditions of the alkali solution are as follows: the concentration of KOH solution is 1.7-2.2 wt%, the temperature is 75-85°C, the time is 200-600 s, and the etching depth is 1-5 μm.

[0078] S8, deposit tunneling oxide layer B and intrinsic polysilicon layer B on the surfaces of the deposition region A, the deposition region B and the isolation region in sequence. The purpose of this step is to form the intrinsic polysilicon layer B to provide conditions for subsequent conversion into boron diffusion layer C.

[0079] In some specific embodiments, the conditions of depositing the tunneling oxide layer B are as follows: the gas flow of O2 is 10000-80000 sccm, the temperature is 400-800°C, the time is 200-1000 s, and the thickness of the obtained tunneling oxide layer B is 1-10 nm.

[0080] In some specific embodiments, the conditions of depositing the intrinsic polysilicon layer B are as follows: the gas flow of SiH4 is 300-2000 sccm, the temperature is 500-700°C, the time is 2-4 h, the working pressure is 100-500 mTorr, and the thickness of the obtained intrinsic polysilicon layer B is 100-300 nm.

[0081] S9, boron diffusion, so that the surface layer of the N-type silicon wafer in the deposition region B and the isolation region, the inner layer and the surface layer of the intrinsic polysilicon layer B are respectively converted into boron diffusion layer B (boron atom concentration is 1E+19-2E+19 cm -3 ), boron diffusion layer C (boron atom concentration is 1E+19-1E+20 cm -3 ) and BSG layer B. In this boron diffusion process, the surface concentration of boron atoms is controlled to make the boron atoms pass through the tunneling oxide layer B in the deposition region B and the isolation region to the bottom of the N-type silicon wafer, so that the surface layer of the N-type silicon wafer is converted into P-type silicon, i.e. boron diffusion layer B. The surface of the deposition region A is effectively blocked from boron atoms entering the bottom region of the PSG layer due to the existence of the intermediate PSG layer. Meanwhile, the inner layer and the surface layer of the intrinsic polysilicon layer B are respectively converted into boron diffusion layer C and BSG layer B after this boron diffusion.

[0082] In some specific embodiments, the boron diffusion conditions are: boron diffusion temperature 800-950℃, diffusion time 5-50min, BCl3 gas flow 50-500sccm, O2 gas flow 500-2000sccm, oxidation promotion temperature 900-1050℃, O2 flow 5000-30000sccm, promotion time 30-80min, and the B thickness of the BSG layer B obtained is 30-70nm.

[0083] S10. Removing the BSG layer B in the deposition area A and the isolation area by laser patterning treatment.

[0084] In some specific embodiments, the laser patterning treatment conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, and treatment time 1-5s.

[0085] S11. Removing the wrap plating layer on the front side and the side surface of the N-type silicon wafer.

[0086] In some specific embodiments, the silicon wafer is removed from the front side and the side surface of the wafer by the chain machine to remove the boron diffusion layer and the phosphorus diffusion layer, etc. on the wafer, wherein the volume ratio of the HF solution (concentration 45-55wt%) and the HNO3 solution (concentration 65-75wt%) in the acid tank is 1:2-1:8; the temperature is room temperature, and the belt speed is 1-10m / min.

[0087] S12. Cleaning and texturing.

[0088] In some specific embodiments, the silicon wafer after removing the wrap plating layer is put into an alkali texturing tank for wet cleaning and integrated texturing treatment, wherein the KOH solution concentration in the texturing tank is 1.5-1.8wt%, the temperature is maintained at 80-85℃, and the time is 6-12min. Subsequently, the subsequent self-acid (HF / HCl) cleaning tank after the texturing tank can further remove the residual PSG layer and BSG layer B of the silicon wafer.

[0089] In the process, since the front side of the silicon wafer has no wrap plating layer, an effective light trapping velvet surface (i.e. pyramid velvet surface) can be formed under the action of an alkali solution; and the deposition area A of the back side of the silicon wafer, since losing the protection of the BSG layer B, the alkali solution can effectively remove the deposition layer until the PSG layer, i.e. the surface PSG layer after the formation of each deposition layer of the back side of the N-type silicon wafer in the deposition area A is removed by alkali washing (the deposition layer before the PSG can be avoided from being further corroded due to the blockage of the PSG layer in the deposition area A), and meanwhile, each deposition layer (including the bottom boron diffusion layer A) in the junction of the deposition area A and the deposition area B (the isolation area) is also removed after being corroded by the alkali, so as to form a gap (the gap has no deposition layer, i.e. the back side of the N-type silicon wafer is in an exposed state), and on this basis, a pyramid velvet surface is formed in the gap after being further corroded by the alkali solution. In addition, since the deposition area B still has the BSG layer B, the deposition area B can be protected from being damaged during the cleaning and texturing process. Finally, the PSG layer on the back side of the silicon wafer is removed by acid washing (i.e. the boron diffusion layer B in the deposition area A is exposed) and the BSG layer B on the outermost layer of the deposition area B is removed.

[0090] S13, double-sided plating film.

[0091] In some specific embodiments, ALD deposition is used to deposit AlO x The thin film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of 8-10 nm and a process temperature controlled at 220-280°C. Subsequently, a SiN x film is deposited on the front and back sides of the silicon wafer by using a tube PECVD device, with the thickness of the SiN x film on the front side being 80-100 nm and the refractive index being 2.0-2.1, and the thickness of the SiN x film on the back side being 80-120 nm and the refractive index being 1.9-2.1; the reaction gas in the tube cavity is SiH4 and NH3, the working pressure is 1500-1700 mTorr, the power is 10000-15000 W, the temperature is 400-600°C, the flow rate of SiH4 gas is 900-2000 sccm, the flow rate of NH3 gas is 7000-12000 sccm, the silicon-nitrogen ratio is 0.1-0.3:1, and the deposition time is 5-20 min.

[0092] S14, screen printing, sintering, light injection, to obtain a finished battery.

[0093] In some specific embodiments, the silicon wafer after plating is subjected to screen printing to form a metal contact on the back side, then sintering at 700-800°C to form an Ag-Si ohmic contact, and finally light injection repair to obtain a final finished battery.

[0094] Specific embodiments and comparative examples.

[0095] Embodiment 1 A method for preparing the above-described horizontal-vertical composite multi-junction TBC solar cell, specifically comprising the following steps: S1, double-side polishing of an N-type silicon wafer: selecting an N-type monocrystalline silicon wafer after being cut by a diamond wire, with a thickness of 150 μm and a size of 182.2 mm x 186.7 mm. The cut N-type monocrystalline silicon wafer is placed into an alkali polishing tank, with the temperature maintained at 75°C and the time being 6 min for double-side polishing, with a polishing thickness of 4 μm and a thinning amount of 0.42 g. FIG. 2 is a structural schematic diagram of the silicon wafer after double-side polishing.

[0096] S2, boron diffusion, generating a boron diffusion layer A and a BSG layer A on the back surface of the N-type silicon wafer. The boron diffusion conditions are as follows: boron diffusion temperature 930°C, diffusion time 25 min, BCl3 gas flow rate 200 sccm, O2 gas flow rate 1200 sccm, oxidation pushing temperature 1050°C, O2 gas flow rate 20000 sccm, pushing time 60 min, and the obtained BSG layer A has a thickness of about 48 nm. The boron atom concentration in the boron diffusion layer A is 4E+18 cm -3 . FIG. 3 is a structural schematic diagram of the silicon wafer after boron diffusion.

[0097] S3, removing the BSG layer A: removing the BSG layer A on the back surface after boron diffusion by using a chain machine, wherein the concentration of the HF solution in the chain machine is 40 wt%, and the belt speed is 3 m / min.

[0098] S4, sequentially depositing a tunnel oxide layer A and an intrinsic polysilicon layer A on the surface of the boron diffusion layer A. The conditions for depositing the tunnel oxide layer A are as follows: O2 gas flow rate 40000 sccm, temperature 600°C, time 600 s, and the obtained tunnel oxide layer A has a thickness of about 3 nm. The conditions for depositing the intrinsic polysilicon layer A are as follows: SiH4 gas flow rate 900 sccm, temperature 550°C, time 2.5 h, working gas pressure 300 mTorr, and the obtained intrinsic polysilicon layer A has a thickness of about 200 nm.

[0099] S5, phosphorus diffusion, the surface layer of the boron diffusion layer A, the inner layer of the intrinsic polysilicon layer A, and the surface layer are respectively converted into the phosphorus diffusion layer A, the phosphorus diffusion layer B and the PSG layer. The conditions of the phosphorus diffusion are: the phosphorus diffusion temperature is 790℃, the diffusion time is 20min, the POCI3 is carried by the nitrogen gas with the flow rate of 1100sccm, the O2 flow rate is 700sccm, after the preliminary diffusion is completed, the O2 is introduced to perform the oxidation promotion, the oxidation promotion temperature is 890℃, the O2 gas flow rate is 3000sccm, and the promotion time is 40min; the PSG thickness is about 42nm. In the phosphorus diffusion process, by controlling the phosphorus atom concentration of the phosphorus diffusion surface to be greater than the boron atom concentration of the first boron diffusion surface, the phosphorus atoms can pass through the tunneling oxide layer A, so that the surface layer of the boron diffusion layer A is converted from the p-type region (i.e. the boron diffusion region) to the n-type region (i.e. the phosphorus diffusion layer A, the thickness is about 200nm, and the phosphorus atom concentration is 5E+19cm -3 ), while the deep layer of the boron diffusion layer A remains as the p-type doped region. At the same time, the inner layer of the intrinsic polysilicon layer A is also converted into the phosphorus diffusion layer B (the phosphorus atom concentration is 2E+20cm -3 ). Fig. 4 is a structural schematic diagram of the silicon wafer after the phosphorus diffusion.

[0100] S6, the PSG layers of the deposition area B and the isolation area on the back surface of the N-type silicon wafer are removed by the laser patterning treatment. The conditions of the laser patterning treatment are: the laser wavelength is 532nm, the frequency is 600KHz, the marking speed is 45000mm / s, the power is 25W, and the treatment time is 2.7s.

[0101] S7, the deposition layers (including the boron diffusion layer A, the phosphorus diffusion layer A, the tunneling oxide layer A and the phosphorus diffusion layer B) of the deposition area B and the isolation area are removed by the alkali cleaning. After the PSG layers of the deposition area B and the isolation area are removed by the laser, the original deposition layers at the bottom of the PSG layers in the deposition area B and the isolation area can be removed in the alkali cleaning process, so that the back surface of the silicon wafer is exposed to provide conditions for the subsequent deposition. The bottom deposition layers of the deposition area A are retained due to the protection of the PSG. The conditions of the alkali solution are: the KOH solution concentration is 2.0wt%, the temperature is 75℃, the time is 400s, and the corrosion depth is 3μm. Fig. 5 is a structural schematic diagram of the silicon wafer after the alkali cleaning.

[0102] S8, the tunneling oxide layer B and the intrinsic polysilicon layer B are sequentially deposited on the surfaces of the deposition area A, the deposition area B and the isolation area. The conditions of the deposition of the tunneling oxide layer B are: the O2 gas flow rate is 50000sccm, the temperature is 600℃, the time is 800s, and the obtained tunneling oxide layer B thickness is about 5nm. The conditions of the deposition of the intrinsic polysilicon layer B are: the SiH4 gas flow rate is 920sccm, the temperature is 550℃, the time is 3.4h, the working gas pressure is 300mTorr, and the obtained intrinsic polysilicon layer B thickness is about 295nm.

[0103] S9, boron diffusion, the surface layer of the N-type silicon wafer in the deposition area B and the bottom of the isolation area, the inner layer and the surface layer of the intrinsic polysilicon layer B are respectively converted into boron diffusion layer B (boron atom concentration is 1.5E+19cm -3 ), boron diffusion layer C (boron atom concentration is 3E+19cm -3 ) and BSG layer B. The boron diffusion conditions are: boron diffusion temperature 850℃, diffusion time 10min, BCl3gas flow rate 200sccm, O2gas flow rate 1200sccm, oxidation pushing temperature 950℃, O2flow rate 7000sccm, pushing time 30min, and BSG layer thickness is about 45nm. In this boron diffusion process, by controlling the surface concentration of boron atoms, the boron atoms can pass through the tunneling oxide layer B in the deposition area B and the isolation area to the bottom of the N-type silicon wafer, so that the surface layer is converted from n-type silicon to p-type silicon, that is, boron diffusion layer B. The surface of the deposition area A can effectively block boron atoms from entering the bottom area of the PSG layer due to the presence of the intermediate PSG layer. At the same time, the inner layer and the surface layer of the intrinsic polysilicon layer B are respectively converted into boron diffusion layer C and BSG layer B after this boron diffusion. Figure 6 is a schematic diagram of the structure of the silicon wafer after boron diffusion.

[0104] S10, remove the BSG layer B in the deposition area A and the isolation area by laser patterning treatment. The laser patterning treatment conditions are: laser wavelength 532nm, frequency 600KHz, marking speed 45000mm / s, power 50W, and treatment time 3s.

[0105] S11, remove the boron diffusion layer and phosphorus diffusion layer on the front surface and side surface of the N-type silicon wafer: use a chain machine to remove the boron diffusion layer and phosphorus diffusion layer on the front surface and side surface of the silicon wafer, wherein the volume ratio of HF solution (concentration 49wt%) and HNO3solution (concentration 69wt%) in the acid tank is 1:4; the temperature is room temperature, and the tape speed is 1.3m / min.

[0106] S12, cleaning and texturing: the silicon wafer after removing the wrap plating layer is put into an alkali texturing tank for wet cleaning and integrated texturing treatment, wherein the KOH solution concentration in the texturing tank is 1.7wt%, the temperature is maintained at 82℃, and the time is 7min. Subsequently, the texturing tank is followed by a self-acid (HF / HCl) cleaning tank to further remove the residual PSG layer of the silicon wafer. In this process, since the front surface of the silicon wafer has no wrap plating layer, an effective light-trapping textured surface (i.e. pyramid textured surface) can be formed under the action of the alkali solution; and the deposition area A on the back surface of the silicon wafer, since losing the protection of the BSG layer B, the alkali solution can effectively corrode and remove the deposition layer until the PSG layer, i.e. the deposition layers formed after the PSG layer on the surface of the deposition area A of the N-type silicon wafer are removed by alkali cleaning (the deposition layers before the PSG layer can be avoided from being further corroded due to the blockage of the PSG layer in the deposition area A), and at the same time, the deposition layers (including the bottom boron diffusion layer A) in the junction (isolation area) between the deposition area A and the deposition area B are removed after being corroded by alkali, thereby forming a gap (the gap has no deposition layer, i.e. the back surface of the N-type silicon wafer is in an exposed state), and on this basis, the pyramid textured surface is formed in the gap after further corrosion by the alkali solution. In addition, since the deposition area B still has the BSG layer B, the parts of the deposition area B can be protected from being damaged during the cleaning and texturing process. Finally, the PSG layer on the back surface of the silicon wafer is removed by acid cleaning (i.e. the boron diffusion layer B in the deposition area A is exposed) and the BSG layer B on the outermost layer of the deposition area B. FIG. 7 is a structural schematic diagram of the silicon wafer after cleaning and texturing.

[0107] S13, double-sided film plating: ALD is adopted to deposit AlO x thin film generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8nm, and the process temperature is controlled at 250℃. Subsequently, a tube PECVD device is adopted to deposit SiN x thin film, SiN x The thickness of the thin film is about 90nm, and the refractive index is 2.0. SiN x thin film, the reaction gas in the tube cavity is SiH4 and NH3, the working pressure is 1600mTorr, the power is 12000W, the temperature is 440℃, the flow rate of SiH4 gas is 980sccm, the flow rate of NH3 gas is 8000sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10min.

[0108] S14, after the film plating, the silicon wafer is subjected to screen printing on the back surface to form a metal contact, and then sintering at 770℃ to form an Ag-Si ohmic contact, and finally light injection repair to obtain the final product battery.

[0109] As shown in Fig. 1, the TBC solar cell prepared in the embodiment comprises an N-type silicon wafer 1, and the front surface of the N-type silicon wafer 1 is sequentially provided with a pyramidal texture 10 and a passivation layer 11; the back surface of the N-type silicon wafer 1 is provided with a deposition area A and a deposition area B in the form of interdigital distribution; the gap between the deposition area A and the deposition area B is an isolation area, and the isolation area is sequentially provided with the pyramidal texture 10 and the passivation layer 11.

[0110] The surface of the deposition area A is sequentially provided with a boron diffusion layer A 2 (thickness of about 800 nm), a phosphorus diffusion layer A 3 (thickness of about 200 nm), a tunneling oxide layer A 4, a phosphorus diffusion layer B 5 (thickness of about 158 nm), the passivation layer 11 and an electrode layer 12.

[0111] The surface layer of the N-type silicon wafer 1 at the bottom of the deposition area B is a boron diffusion layer B 13 (thickness of about 200 nm), and the surface of the deposition area B is sequentially provided with a tunneling oxide layer B 7, a boron diffusion layer C 8 (thickness of about 250 nm), the passivation layer 11 and the electrode layer 12.

[0112] As shown in Fig. 1, the TBC solar cell prepared in the embodiment has a horizontal-vertical composite multi-junction structure (p-n junction). The first p-n junction a is in a horizontal structure and is composed of the boron diffusion layer B (p-type region) and the N-type silicon wafer on the left and right sides thereof (N-type silicon wafer base is n-type region); the second p-n junction b is in a vertical structure and is composed of the boron diffusion layer A and the N-type silicon wafer at the bottom thereof; and the third p-n junction c is in a vertical structure and is composed of the boron diffusion layer A and the phosphorus diffusion layer A (n-type region).

[0113] Example 2 differs from Example 1 in S5, i.e., the S5 of Example 2 adopts a "high surface doping concentration + short oxidation pushing time" phosphorus diffusion process, which can be more conducive to the penetration of phosphorus atoms through the tunneling oxide layer, and the specific process is as follows: S5, phosphorus diffusion, so that the surface layer of the boron diffusion layer A, the inner layer and the surface layer of the intrinsic polysilicon layer A are respectively converted into a phosphorus diffusion layer A (thickness of about 160 nm, phosphorus atom concentration of 7E+19 cm-3), a phosphorus diffusion layer B (phosphorus atom concentration of 3.5E+20 cm-3) and a PSG layer. -3 -3 The conditions for phosphorus diffusion are as follows: phosphorus diffusion temperature of 790 ℃, diffusion time of 20 min, POCI3 carried by nitrogen gas with a flow rate of 1100 sccm, O2 flow rate of 700 sccm; then oxidation pushing, and POCI3-containing nitrogen gas is synchronously introduced again with a flow rate of 2500 sccm for 5 min, the oxidation pushing temperature is 890 ℃, the pushing time is 10 min, the O2 flow rate is 8000 sccm, and a PSG layer with a thickness of about 35 nm is generated.

[0114] ​Comparative Example 1 S1, N-type single crystal silicon wafer cut by diamond wire, thickness of 150 μm, size of 182.2 mm x 186.7 mm. The cut silicon wafer was put into an alkali polishing tank, temperature was maintained at 75°C, time was 6 min for double-side polishing, polishing thickness was 4 μm, and thinning amount was 0.42 g.

[0115] S2, then a tunneling SiO x layer was grown on the back surface of the polished silicon wafer by LPCVD, O2 gas flow was 40000 sccm, temperature was 600°C, time was 600 s, and the grown tunneling SiO x layer had a thickness of about 3 nm; then an i-poly-Si layer was grown on the tunneling SiO x layer, wherein SiH4 gas flow was 920 sccm, temperature was 550°C, time was 3.3 h, working pressure was 300 mTorr, and the i-poly-Si layer had a thickness of about 290 nm.

[0116] S3, then the inner layer and surface layer of the i-poly-Si layer were converted into p + -poly-Si layer and BSG layer by high-temperature boron diffusion, boron diffusion temperature was 850°C, diffusion time was 10 min, BCl3 gas flow was 200 sccm, O2 gas flow was 1200 sccm, oxidation pushing temperature was 950°C, O2 flow was 7000 sccm, pushing time was 30 min, and the BSG layer had a thickness of about 45 nm.

[0117] S4, one-time patterned grooving of the BSG layer was performed by picosecond laser, laser wavelength was 532 nm, frequency was 600 KHZ, marking speed was 45000 mm / s, power was 50 W, and processing time was 3 s.

[0118] S5, the silicon wafer after laser patterned grooving was put into an alkali solution for cleaning, temperature was 75°C, time was 360 s, and etching depth was 1.7 μm.

[0119] S6, then a tunneling SiO x layer was grown on the back surface of the silicon wafer by LPCVD for the second time, O2 gas flow was 30000 sccm, temperature was 600°C, time was 450 s, and the grown tunneling SiO x layer had a thickness of about 2.5 nm; then an i-poly-Si layer was grown on the tunneling SiO x layer, wherein SiH4 gas flow was 920 sccm, temperature was 550°C, time was 1.5 h, working pressure was 300 mTorr, and the i-poly-Si layer had a thickness of about 180 nm.

[0120] S7, the inner layer and the surface layer of the i-poly-Si layer are respectively converted into n + -poly-Si layer and PSG layer, phosphorus diffusion temperature 790°C, diffusion time 15 min, POCI3 carried by nitrogen flow rate 1000 sccm, O2 flow rate 650 sccm, oxidation push temperature 890°C, O2 flow rate 3000 sccm, push time 20 min, PSG layer thickness about 39 nm.

[0121] S8, then the p + -poly bottom corresponds to the PSG layer and the p + -poly and n + -poly junction area PSG layer loose, laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, processing time 2.7 s.

[0122] S9, the above silicon wafer is removed by a chain machine to remove the n + -poly-Si and p + -poly-Si layer, wherein the volume ratio of hydrofluoric acid solution and nitric acid solution in the acid tank is 1:4 (hydrofluoric acid solution concentration is 49wt%, nitric acid solution concentration is 69wt%), belt speed 1.3m / min.

[0123] S10, the silicon wafer after removing the wrap layer is put into an alkali texturing tank for back laser grooving area wet cleaning and front texturing integrated processing, wherein the KOH solution concentration in the texturing tank is 1.7wt%, the temperature is maintained at 82°C, the time is 7 min, the weight loss is 0.36g, and the cleaning and texturing are carried out. Due to the fact that the front surface of the silicon wafer has been removed from the wrap layer and there is no oxidized area, an effective light trapping textured surface can be formed during the texturing process; and for the back laser patterned area, the alkali solution can effectively etch the bottom poly-Si to form an isolated insulating structure. Subsequently, the subsequent self-acid (HF / HCl) cleaning tank after the texturing tank body can further remove the residual PSG layer and BSG layer of the silicon wafer.

[0124] S11, AlO x thin film is generated by reaction of Al(CH3)3 with water vapor, thickness 8 nm, process temperature controlled at 250°C. Subsequently, SiN x film is deposited on the front and back surfaces of the silicon wafer by a tube PECVD device, the thickness of the front SiN x thin film is about 82 nm, and the refractive index is 2.1; the thickness of the back SiN xThe thickness of the thin film is about 90 nm, and the refractive index is 2.0; the tube cavity reaction gas is SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440 ℃, the SiH4 gas flow rate is 980 sccm, the NH3 gas flow rate is 8000 sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10 min.

[0125] S12, screen printing the plated wafer on the back to form a metal contact, then sintering at 770 ℃ to form an Ag-Si ohmic contact, and finally repairing by light injection to obtain a final TBC finished product battery.

[0126] Comparative Example 2 Compared with Example 1, the difference is only that the S5 phosphorus diffusion process is different: the POCl3 source concentration is lower, and the time is shorter, so that there are not enough phosphorus atoms to pass through the tunneling oxide layer A to make the surface layer of the boron diffusion layer A not fully inverted to n-type, as follows: S5, phosphorus diffusion, so that the surface layer of the boron diffusion layer A and the intrinsic polysilicon layer A are respectively converted into a phosphorus diffusion layer A and a phosphorus diffusion layer B, and a PSG layer is formed on the surface of the phosphorus diffusion layer B. The phosphorus diffusion conditions are as follows: phosphorus diffusion temperature 790 ℃, diffusion time 3.5 min, POCl3 carried by nitrogen gas with a flow rate of 370 sccm, O2 flow rate 400 sccm, after completing the preliminary diffusion, O2 is introduced for oxidation promotion, oxidation promotion temperature 870 ℃, O2 gas flow rate 1200 sccm, promotion time 3.2 min; the thickness of the PSG is about 25 nm.

[0127] Comparative Example 3 Compared with Example 1, the difference is only that the S9 second boron diffusion process is different: the BCl3 source concentration is lower, and the time is shorter, so that there are not enough boron atoms to pass through the tunneling oxide layer to make the surface layer of the N-type silicon wafer at the bottom converted into p-type, so that the boron atoms cannot fully penetrate the tunneling oxide layer B during the second boron diffusion, as follows: S9, the boron diffusion conditions are as follows: boron diffusion temperature 830 ℃, diffusion time 4 min, BCl3 gas flow rate 40 sccm, O2 gas flow rate 450 sccm, oxidation promotion temperature 930 ℃, O2 flow rate 2000 sccm, promotion time 15 min, and the thickness of the obtained BSG layer B is about 32 nm.

[0128] Performance test The electrical properties of the solar cells obtained in each example and comparative example were tested, and the results are shown in Table 1.

[0129] Table 1

[0130] From the comparison of the data in Table 1, it can be seen that: (1) from the comparison of the data of Example 1 and Comparative Example 1, the solar cell with the horizontal and vertical composite multi-junction structure of the application has better performance.

[0131] (2) From the data comparison of Comparative Example 2, Comparative Example 3 and Example 1, it can be seen that, by optimizing the process parameters of S5 phosphorus diffusion and S9 boron diffusion in Example 1, phosphorus atoms and boron atoms can more easily pass through the tunneling oxide layer, respectively, so as to form more ideal phosphorus diffusion layer A and boron diffusion layer B, respectively, and finally obtain a solar cell with higher performance.

[0132] (3) Compared with Example 1, Example 2 adopts a more optimized "high surface doping concentration + short oxidation promotion time" phosphorus diffusion process in S5, so that the PSG layer contains a higher concentration of phosphorus source, and the advantages are that, in the subsequent secondary boron diffusion high-temperature process: on the one hand, phosphorus atoms can pass through the tunneling oxide layer A again to form a phosphorus diffusion layer A with better diffusion effect; on the other hand, the concentration of phosphorus atoms in the phosphorus diffusion layer B can be kept at a stable value, so as not to be greatly reduced, so that a solar cell with higher performance can be finally obtained.

[0133] The raw materials and equipment used in the present application are all common raw materials and equipment in the art unless otherwise specified; the methods used in the present application are all conventional methods in the art unless otherwise specified.

[0134] The above is only a preferred embodiment of the present application, and does not limit the present application in any way, and any simple modification, change and equivalent transformation of the above embodiment according to the technical essence of the present application still belongs to the protection scope of the technical solution of the present application.

Claims

1. A transverse-longitudinal composite multi-junction TBC solar cell, comprising an N-type silicon wafer, the front surface of the N-type silicon wafer being provided with a pyramidal texture and a passivation layer in sequence; characterized in that: the back surface of the N-type silicon wafer is provided with a deposition area A and a deposition area B in a cross-finger distribution; the gap between the deposition area A and the deposition area B is an isolation area, and the surface of the isolation area is provided with a pyramidal texture and a passivation layer in sequence; the surface of the deposition area A is provided with a boron diffusion layer A, a phosphorus diffusion layer A, a tunneling oxide layer A, a phosphorus diffusion layer B, a passivation layer and an electrode layer in sequence; the surface layer of the N-type silicon wafer at the bottom of the deposition area B is a boron diffusion layer B, and the surface of the deposition area B is provided with a tunneling oxide layer B, a boron diffusion layer C, a passivation layer and an electrode layer in sequence. 2.The transverse-longitudinal composite multi-junction TBC solar cell according to claim 1, characterized in that: the thickness of the boron diffusion layer A is 200-1300 nm; the thickness of the boron diffusion layer B is 100-500 nm; the thickness of the boron diffusion layer C is 100-300 nm; the thickness of the phosphorus diffusion layer A is 50-400 nm; the thickness of the phosphorus diffusion layer B is 100-300 nm.

3. A method of fabricating a crosswise-longitudinal composite multi-junction TBC solar cell according to claim 1 or 2, characterized by comprising: S1, polishing both surfaces of the N-type silicon wafer; S2, boron diffusion, to form a boron atomic concentration of 1E+18 to 1E+19 cm -3 of a boron diffusion layer A and a BSG layer A; S3, removing the BSG layer A; S4, depositing a tunneling oxide layer A and an intrinsic polysilicon layer A on the surface of the boron diffusion layer A; S5, phosphorus diffusion, the surface layer of boron diffusion layer A, the inner layer and the surface layer of intrinsic polysilicon layer A are respectively converted into phosphorus atom concentration 5E+18~2E+20 cm -3 phosphorus diffusion layer A, phosphorus atom concentration >1E+20 cm -3 phosphorus diffusion layer B and PSG layer; S6, removing the PSG layer of the deposition area B and the isolation area by laser patterning treatment; S7, removing the deposited layer of the deposition area B and the isolation area by alkali cleaning; S8, depositing a tunneling oxide layer B and an intrinsic polysilicon layer B on the surface of the deposition area A, the deposition area B and the isolation area in sequence; S9, boron diffusion, the surface layer of N-type silicon wafer in the deposition area B and the bottom of the isolation area, the inner layer and the surface layer of the intrinsic polysilicon layer B are respectively converted into boron atom concentration 1E+19~2E+19cm -3 the boron diffusion layer B with boron atom concentration 1E+19~1E+20cm -3 the boron diffusion layer C and the BSG layer B S10, removing the BSG layer B of the deposition area A and the isolation area by laser patterning treatment; S11, removing the plating layer; S12, cleaning and texturing; S13, plating films on both surfaces; S14, screen printing, sintering and photo injection.

4. The method of claim 3, wherein: In S2, the boron diffusion conditions are as follows: boron diffusion temperature 900-950℃, diffusion time 10-50 min, BCl3 flow rate 50-500 sccm, O2 flow rate 500-2000 sccm; oxidation advancing temperature 1000-1050℃, O2 flow rate 3000-50000 sccm, advancing time 30-80 min, and the obtained BSG layer A has a thickness of 30-70 nm.

5. The method of claim 3, wherein: In S4, the conditions for depositing the tunneling oxide layer A are as follows: O2 flow rate 10000-80000 sccm, temperature 400-800℃, time 200-1000 s, and the obtained tunneling oxide layer A has a thickness of 1-10 nm; the conditions for depositing the intrinsic polysilicon layer A are as follows: SiH4 flow rate 300-2000 sccm, temperature 500-700℃, time 2-4 h, working pressure 100-500 mTorr, and the obtained intrinsic polysilicon layer A has a thickness of 100-300 nm.

6. The method of claim 3, wherein: In S5, the phosphorus diffusion conditions are: phosphorus diffusion temperature 750-850℃, diffusion time 5-30min, POCI3 carried by nitrogen with a flow rate of 500-2500sccm, O2 flow rate 500-3000sccm; then oxidation promotion, temperature 850-950℃, promotion time 5-60min, O2 flow rate 1000-10000sccm; the obtained PSG layer thickness is 30-70nm.

7. The method of claim 3, wherein: In S5, the phosphorus diffusion conditions are: phosphorus diffusion temperature 750-850℃, diffusion time 5-30min, POCI3 carried by nitrogen with a flow rate of 500-2500sccm, O2 flow rate 500-3000sccm; then oxidation promotion, simultaneously again inputting POCI3 carried by nitrogen with a flow rate of 1000-5000sccm, inputting time 2-10min, oxidation promotion temperature 850-950℃, promotion time 5-20min, O2 flow rate 5000-20000sccm; the obtained PSG layer thickness is 30-70nm.

8. The method of claim 3, wherein: In S8, The conditions for depositing the tunneling oxide layer B are: O2 flow rate 10000-80000sccm, temperature 400-800℃, time 200-1000s, the obtained tunneling oxide layer B thickness is 1-10nm; The conditions for depositing the intrinsic polysilicon layer B are: SiH4 flow rate 300-2000sccm, temperature 500-700℃, time 2-4h, working pressure 100-500mTorr, the obtained intrinsic polysilicon layer B thickness is 100-300nm.

9. The method of claim 3, wherein: In S9, the boron diffusion conditions are: boron diffusion temperature 800-950℃, diffusion time 5-50min, BCl3 flow rate 50-500sccm, O2 flow rate 500-2000sccm; oxidation promotion temperature 900-1050℃, O2 flow rate 3000-50000sccm, promotion time 30-80min, the obtained BSG layer B thickness is 30-70nm.

10. The method of claim 3, wherein: In S10, the laser patterning processing conditions are: laser wavelength 400-600nm, frequency 500-700KHz, marking speed 40000-50000mm / s, power 10-50W, processing time 1-5s.

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