A system and a method for estimating a frequency of a complex input signal

Abstract

A system (1) for estimating a frequency of a complex input signal, wherein said system (1) comprises: - at least one frequency generator module (2) for generating a multi-frequency reference signal; - a single complex multiplier module (3) for multiplying in a time-sharing manner the reference signal with the input signal; - at least one coherent accumulate-and-dump filter (4) configured to accumulate an output signal of the a complex multiplier module (3); - at least one non-coherent accumulate-and-dump filter (5) configured to accumulate an output signal of the at least one coherent accumulate-and-dump filter (4); and - at least one max-finder module (6) configure to estimate a maximum value of an output signal of the at least one non-coherent accumulate-and-dump filter (5). The invention also relates to method estimating a frequency of a complex input signal by using components of said system (1).

Description

[0001] A system and a method for estimating a frequency of a complex input signalThe invention relates to a system and a method for estimating afrequency of a complex input signal. Frequency estimation is an important step in the carrier synchronization of receivers in communications and navigation systems. Three different approaches are generally used in the acquisition phase of the carrier synchronization. These are serial search, parallel search and FFT based methods [1,2,5]. In [2,3], different frequency estimation methods are discussed in the context of GNSS doppler frequency acquisition. Thecoherent and non-coherent accumulators are each implemented withtheir own memory blocks which is expensive in terms of siliconarea, power consumption and memory utilization. These paperscompare a parallel frequency search (with one digital frequency synthesizer and complex multiplier per frequency step), a Serial frequency search (with one digital frequency synthesizer and complex-multiplier) and an FFT based method. These methods arebased on maximum spectral power measurement. The frequencyestimation with FFT is described in [1, 4, 5, 6] for the acquisition of doppler frequency in GNSS receivers. The frequency resolution with the FFT method is the inverse of the coherent integration time [8], which poses a limitation, as it may be required to use a lower frequency step in the frequency search. It is an object of the invention to correct the short-comingsof the prior art and to provide a solution for frequencyestimation which optimizes the silicon area, power consumptionand memory utilization. This and other objects which will becomeapparent from the following disclosure, are provided with asystem and a method for estimating a frequency of a complexinput signal, wherein said system and method have the features of one or more of the appended claims.In a first aspect of the invention, the method for estimating afrequency of a complex input signal comprises the steps of:- generating a multi-frequency complex reference signal usingat least one frequency generator module; -multiplying said reference signal with the input signal;- accumulating a product of said multiplication in a firstprogrammable memory using at least two accumulate-and-dump filters; and -estimating the frequency of the complex input signal byfeeding the output signal of the non-coherent accumulate- and-dump filter into a max-finder module, wherein themethod comprises the step of configuring the at least two accumulate-and-dump filters to share a same memory word per frequency by storing accumulated signals corresponding to said frequency in a same address of said first programmable memory.Compared to an architecture which uses two separate memories forthe same operation, the architecture proposed by the invention can result in reduced silicon area because of the reduction in the number of auxiliary hardware such as memory controllers. The proposed architecture also reduces the number of memory accesses, thereby reducing the power consumption. In a second aspect of the invention, that may be applied independently or in combination with the first aspect of the invention, the method comprises the step of using a single complex multiplier module in a time-sharing manner for multiplying the reference signal with the input signal. Multiplying the reference signal by the input signal using asingle complex multiplier in a time-sharing manner means sharinga single hardware multiplier module / unit to perform the four multiplication operations required for a complex multiplication sequentially, instead of using four dedicated multipliers, which saves on hardware resources, power, and chip area. This may be achieved by a time-multiplexed or sequential approach where a single complex multiplier performs the operations, or a single real multiplier is used repeatedly to calculate the complexproduct. A time-shared multiplier significantly reduces thenumber of multipliers needed, freeing up valuable silicon area. Additionally, less hardware directly translates to lower power consumption. And, by using fewer resources, the overall cost of the chip or system can be reduced.The frequency generator can be any electronic device capable ofgenerating electrical waveforms, such as square or sinusoidalwaves or pulses, with a controllable frequency and duty cycle.The coherent accumulate-and-dump filter, also known as anintegrate-and-dump filter, is a digital signal processing module used to recover a known signal from noise by summing the signal's samples over a specific interval (integrate) and then resetting (dumping) the accumulator for the next interval. The max-finder module identifies and outputs the peak (local maximum) values and / or their indices within an input signal. It functions by comparing each sample's amplitude to its neighbors, flagging a sample as a peak if it is higher than both adjacent points. Depending on its configuration, it can output just the maximum value, its position (index), or both, and can track running maximums over time.Suitably, the step of accumulating a product of themultiplication may comprise:- providing the at least two accumulate-and-dump filters asat least one coherent accumulate-and-dump filter and at least one non-coherent accumulate-and-dump filter; -coherently accumulating an output signal of the complexmultiplier module using at least one coherent accumulate- and-dump filter; and- non-coherently accumulating an output signal of the atleast one coherent accumulate-and-dump filter using at least one non-coherent accumulate-and-dump filter. The coherent aspect signifies that the filter relies on a reference signal or phase to correctly align with the incoming data, often utilizing matched filters for signal detection andphase recovery. On the other hand, the non-coherent accumulate-and-dump filter is a digital signal processing module used indigital communication systems that integrates (accumulates) a received signal over a specific time interval and then dumps the accumulated value to determine the presence or absence of a signal, without needing precise phase information of the carrier signal. Unlike its coherent counterpart, the non-coherent version doesn't rely on carrier synchronization, making it more robust in weak signal conditions or environments with signal attenuation and multipath propagation. It's particularly useful in non-coherent modulation schemes like Frequency-Shift Keying (FSK) or when signal phase information is unavailable, improving performance by reducing noise and providing a more stable operation in challenging scenarios.Advantageously, the method may comprise the step of operatingthe complex multiplier module at a frequency equal to at leasta product of multiplying a number of frequencies in the referencesignal by a sampling rate of the input signal. The high clockfrequency of the shared multiplier module allows it to efficiently process multiple data streams at the required speedenabling parallel processing. As mentioned earlier, the complexmultiplications of the input signal with the multiple frequencyoutputs may be done in a time-shared manner. To reduce area andcost, the hardware resources of this complex multiplier (or its constituent real multipliers and adders) are shared. Instead of having a dedicated module for each complex multiplication, one module is used for several, but it must operate at a higher frequency to handle the increased workload within the requiredtimeframe. The frequency of operation may be doubled orquadrupled to allow a single logic block (like an FPGA's DSP slice) to serve multiple computational groups or channels concurrently. More advantageously, the method comprises the step of operating the coherent and the non-coherent accumulate-and-dump filters at a frequency of at least two times a product of multiplying the frequency of the reference signal by the frequency of theinput signal. The factor two allows for two clock cycles to readand write from / to the memory.Furthermore, the method may comprise the step of generating a multi-frequency complex reference signal using a direct digitalsynthesizer as the frequency generator module. More suitably,the multi-frequency complex reference signal comprises linearly-spaced reference frequencies. Direct Digital FrequencySynthesizers (DDS) offer many benefits like precise and fine frequency and phase control, rapid frequency switching (frequency hopping), superior frequency stability tied to the reference clock, and easy integration with digital systems for remote control and advanced modulation. These advantages make DDS ideal for military, communications, and instrumentation applications requiring agility, accuracy, and advanced digital signal processing.To further reduce the memory size and power consumption, themethod may comprise the step of providing a second programmable memory and at least one source of a reference frequency, wherein the method comprises the steps of: -generating an initial phase value using a first phaseaccumulator; -generating a discrete amount of phase increment using asecond phase accumulator;- generating an incremented phase value by adding thediscrete amount of phase increment to the initial phase value using a third phase accumulator receivingly connected to the first phase accumulator and to the second phase accumulator.Ultimately, the method may comprise the step of using no otherphase accumulator than said first phase accumulator, said secondphase accumulator, and said third phase accumulator. Limitingat three the number of accumulators needed for processing theinput signal significantly reduces the silicon area, the powerconsumption and the memory size of the system used for estimatingthe frequency of the input signal.In a third aspect of the invention, the system for estimating afrequency of a complex input signal comprises:- at least one frequency generator module for generating amulti-frequency reference signal; -a complex multiplier module for multiplying the referencesignal with the input signal; -at least two accumulate-and-dump filters configured toaccumulate an output signal of the complex multipliermodule in a first programmable memory; and- at least one max-finder module configure to estimate amaximum value of an output signal of the at least two accumulate-and-dump filters, wherein said maximum value corresponds to the frequency of the complex input signal, wherein at least two accumulate-and-dump filters are configured to share a same memory word per frequency by storing accumulated signals corresponding to said frequency in a same address of thefirst programmable memory. Compared to an architecture whichuses two separate memories for the same operation, thearchitecture proposed by the invention can result in reduced silicon area because of the reduction in the number of auxiliary hardware such as memory controllers. The proposed architecture also reduces the number of memory accesses, thereby reducing the power consumption. In a fourth aspect of the invention, that can be applied independently or in combination with the third aspect of theinvention, the system comprises only one complex multipliermodule for multiplying in a time-sharing manner the multi- frequency complex reference signal with the input signal.In this fourth aspect of the invention, the system uses a singlecomplex multiplier in a time-sharing manner for multiplying thereference signal by the input signal by sharing a single hardwaremultiplier module / unit to perform the four multiplication operations required for a complex multiplication sequentially, instead of using four dedicated multipliers. This has thebenefit of saving on hardware resources, power, and chip area.This benefit is achieved by a time-multiplexed or sequentialapproach where a single complex multiplier performs the operations, or a single real multiplier is used repeatedly tocalculate the complex product. A time-shared multipliersignificantly reduces the number of multipliers needed, freeing up valuable silicon area. Additionally, less hardware directly translates to lower power consumption. And, by using fewer resources, the overall cost of the chip or system can be reduced. The complex multiplier module is configured to operate at afrequency equal to at least a product of multiplying the numberof frequencies in the reference signal by the sampling rate of the input signal. The high clock frequency of the shared multiplier module allows it to efficiently process multiple datastreams at the required speed enabling parallel processing.Advantageously, the at least two accumulate-and-dump filters may comprise: -at least one coherent accumulate-and-dump filter configured to accumulate an output signal of the complex multiplier module; -at least one non-coherent accumulate-and-dump filterconfigured to accumulate an output signal of the at least one coherent accumulate-and-dump filter. The coherent and the non-coherent accumulate-and-dump filtersmay be configure to operate at a frequency of at least two timesa product of multiplying the number of frequencies in thereference signal by the sampling rate of the input signal. Thisfactor two multiplication allows for two clock cycles to readand write from / to the memory.More suitably, the first programmable memory may be a randomaccess memory comprising a single port or comprising a dualport. Single-port memory is simpler and cheaper, but dual-portmemory offers superior performance by providing two independent access paths to the memory array, making it the preferred choice for high-performance, real-time data processing applications.The at least one frequency generator module may be a directdigital frequency synthesizer. Synthesizers (DDS) offer manybenefits like precise and fine frequency and phase control, rapid frequency switching (frequency hopping), superior frequency stability tied to the reference clock, and easy integration with digital systems for remote control and advanced modulation. These advantages make DDS ideal for military, communications, and instrumentation applications requiring agility, accuracy, and advanced digital signal processing. To further reduce the memory size and power consumption, the at least one frequency generator module may comprise: -a second programmable memory;- at least one source of a reference frequency;- a first phase accumulator configured to generate an initial phase value; -a second phase accumulator configured to generate adiscrete amount of phase increment; and -a third phase accumulator receivingly connected to thefirst phase accumulator and to the second phase accumulator and configured to generate an incremented phase value by adding the discrete amount of phase increment to the initial phase value.Optionally, the at least one frequency generator modulecomprises no other phase accumulator than said first phaseaccumulator, said second phase accumulator, and said third phaseaccumulator. Limiting at three the number of accumulators neededfor processing the input signal significantly reduces the silicon area, the power consumption and the memory size of second programmable memory, and by extension the memory size of thesystem, used for estimating the frequency of the input signal.Advantageously, the at least one source of reference frequencycomprises a first clock and a second clock. For a faster frequency sampling speed of the system, the firstand the second phase accumulators of the frequency generatormodule may be configured to operate at a frequency of the firstclock and the third phase accumulator may be configured tooperate at a frequency of the second clock, wherein the frequency of the first clock and the frequency of the second clock are different from each other.Suitably, the second clock may be faster than the first clock.More suitably, the second clock is N times faster than thefirst clock, wherein N is a number of frequencies synthesizedby the system. To enable a parallel operation and for a fastersampling speed, the system may be configured to serially synthesize frequencies, i.e. waveforms of multiple frequencies,at a rate proportional to the frequency of the second clockTo truncate the signal coming out of the third phase accumulator and discard the Less Significant Bits (LSBs), the at least onefrequency generator module may comprise a bit-slicing module fortruncating an output of the third phase accumulator, whereinsaid bit-slicing module is placed between the third phaseaccumulator and the input of the second programmable memory.The at least one frequency generator module may comprises afrequency selector placed between the third phase accumulatorand the input of the second programmable memory.The at least one frequency generator module of the invention is particularly adapted for generating linearly space frequencies.However, said at least one frequency generator module may alsobe adapted to generate non-linearly spaced frequencies by placing a frequency selector between the third phase accumulatorand the input of the second programmable memory. Optionally, thefrequency selector may be controlled by the second clock.The invention will hereinafter be further elucidated with reference to the drawing of an exemplary embodiment of a systemor a method according to the invention that is not limiting asto the appended claims. In the drawing: -figure 1 shows a schematic of the system according to theinvention; -figure 2 shows a schematic of the coherent accumulate-and-dump filter according to the invention;- figure 3 shows a schematic of the non-coherent accumulate-and-dump filter according to the invention;- figure 4 shows a schematic of the first programmable memoryaccording to the invention; and- figure 5 shows a schematic of the max-finder moduleaccording to the invention;- figure 6 shows a schematic of the frequency generatormodule according to the invention; and- figure 7 shows a schematic of experimental results usingthe system or the method according to the invention.Whenever in the figures the same reference numerals are applied, these numerals refer to the same parts. This invention is about a frequency estimator using a parallel digital frequency generator, a complex multiplier, accumulators and a max-finder. The received signal samples are multiplied by complex sinusoidal waveforms of different frequencies parallelly, and then accumulated and down-sampled, as shown in figure 1. The resulting samples can be used to estimate the frequency of the received signal. The architecture of the proposed invention is shown in figure 1. It is assumed that the complex input signal ^^^has a sample- rate ^^. The frequency generator gives ^^complex sinusoid waveforms parallelly at a sample-rate ^^. A single complex- multiplier is used to perform all the ^^multiplications of the input signal ^^^with the frequency generator outputs. This is done in a time-shared manner with the complex-multiplieroperating at a higher clock rate ^^^ which is at-least ^^ × ^^.These parallel streams of signals are accumulated and decimated by the coherent and non-coherent accumulate-dump blocks. Finally, the max-finder block detects the frequency at which the accumulated values are the largest. Unlike the FFT method, there is no restriction on the frequency step for this parallel architecture.The Frequency Generator Module 2The Frequency generator module 2 may be configure to generatevarious types of waveforms: sinusoidal, rectangular, triangular,etc. When the waveform is sinusoidal it typically has a frequency^ of this waveform is digitally sampled at a rate^^ and ^ = ^ / ^^, it gives ^(^) = ^^^(2^(^ / ^^)^). Here ^ is thediscrete-time index. Consider a number of complex sinusoids that are linearly-spaced in frequency, sampled at a rate ^^. Let the frequency of the first sinusoid be ^^, and the other frequencies be separated by Δ^.Now define ^^ = ^^ / ^^ and ^ = Δ^ / ^^. The frequency of the ^^^sinusoid is ^^ + ^ × Δ^. So, the ^^^sinusoid samples can be written as: ^^(^) = cos(2^ (^^ + ^^) ^) + ^ ^^^(2^ (^^ + ^^) ^)The samples for ^^ frequencies (^ = 0,1,2, . ^^ − 1) can be digitallysynthesized as shown in figure 6 where only three phaseaccumulator are needed for generating reference frequencies forthe system. Figure 6 further shows that only one programmablememory 7.2 is needed to store the look-up-table (LUT) for theprocess of generating said refence frequencies. Thissignificantly reduces the memory size of the frequency generator module 2, and by extension of the system 1. The waveform samplesmay be generated in series at the clock-rate of the second clock8.2, having the higher clock rate, to enable effective paralleloperation at ^^.Accumulate-and-dump filters 4, 5In the system and the method of the invention, there are ^^memory elements-one reserved for each frequency. The complex-multiplier 3 output signal is first accumulated coherently andthen non-coherently after the absolute value is calculated. Thecoherent 4 and non-coherent 5 accumulate-and-dump filters areas shown in figures 2 and 3 respectively. It is possible to use the square value instead of the absolute value, but the neededmemory size of the first programmable memory 7.1 (RAM) increasesin that case. Each address to the first programmable memory 7.1is associated with a frequency as it can be seen in figures 2,3, and 4. The input samples are added with the samples read from the first programmable memory 7.1 and the sum is written back to the same address in the first programmable memory 7.1. When the ‘dump signal’ (^^^^^, ^^^^^^) becomes active, the accumulated values-which are the output samples of the adder- are transferred(dumped) to the output. When this ‘dump’ happens, the registers in the first programmable memory 7.1 are not updated. This saves ^^clock cycles for the write operation. The ^^^^^and ^^^^^^signals are provided according to the required durations ofcoherent 4 and non-coherent 5 accumulations. The accumulate-and-dump filters 4,5 are operated at clock rate ^^^ which is at-least 2 × ^^ × ^^. The reason for the factor two is that two clockcycles are needed to read and write from / to first programmable memory 7.1.The coherent 4 and non-coherent 5 accumulate-and-dump filterscan share the same memory word, by using different parts of it. The first ^^bits of the word (^^) can be used by the coherentaccumulate-and-dump filter 4 and the other ^^ bits (^^^) can beused by non-coherent accumulate-and-dump filter 5, as shown infigure 4. In general, ^^and ^^^, shown in figure 4, can use any combination of and ^^bits of the memory word. This reduces the number of clock cycles needed for read / write operations on the first programmable memory 7.1. The first programmable memory 7.1 can be a single port or dual port, SRAM or DRAM. During the coherent accumulation, the incoming samples are added to ^^and the sum is stored back in the same memory location, while the same value of ^^^is written back. When the coherent accumulation is completed, its output is passed on tothe non-coherent accumulate-and-dump filter 5. These samples areadded to ^^^and the sum is stored back in the same memory location. Compared to an architecture which uses two separate RAMs for the same operation, the proposed architecture of the invention can result in reduced silicon area because of the reduction in the number of auxiliary hardware such as memory controllers. The proposed architecture also reduces the number of memoryaccesses, thereby reducing the power consumption of the system1 as a whole. The samples from the non-coherent accumulate-and-dump filter 5 are serially read in to the max finder module 6, shown in figure1 and 5, and compared to find the maximum value in said samples.The estimate of the frequency of the input signal is the onewhich gives the maximum value. Experimental Results To showcase the superiority of the system 1 and method according to the invention, experimental results are included as follows.The proposed system 1 frequency estimator with ^^ = 64frequencies centered at DC and separated by 100^^ is implemented.A signal containing two tones at 1^^^ , −1.7^^^ and Gaussiannoise is given as the input to this system 1. The input samplingrate is ^^ = 31^^^ and the amplitude of the tone at 1^^^ is twicethat of −1.7^^^. The coherent integration interval is chosen as4^^ and the total integration interval is chosen as 20^^. Thismeans that blocks of 31 × 4 input samples are accumulatedcoherently, and the non-coherent integration is performed on =5 output samples of the coherent accumulate-and-dump filter4. In this case, the number of memory accesses for each frequency-step is reduced from 38 to 34 because of the memory sharing architecture. The spectral estimates (outputs of the accumulate-and-dump filter) normalized by the maximum amplitude (output of the max finder) are shown below in figure 7. Although the invention has been discussed in the foregoing with reference to an exemplary embodiment of the method of the invention, the invention is not restricted to this particular embodiment which can be varied in many ways without departing from the invention. The discussed exemplary embodiment shall therefore not be used to construe the append-ed claims strictly in accordance therewith. On the contrary the embodiment is merely intended to explain the wording of the appended claims without intent to limit the claims to this exemplary embodiment. The scope of protection of the invention shall therefore be construed in accordance with the appended claims only, wherein a possible ambiguity in the wording of the claims shall be resolved using this exemplary embodiment.

[0002] References:1. Jerome Leclere et.al, Resource and Performance Comparisonsfor Different Acquisition Methods that can be Applied to a VHDL-based GPS Receiver in Standalone and Assisted Cases, IEEE / ION Position, Location and Navigation Symposium, 20102. Jerome Leclere et.al, Comparison Framework of FPGA-basedGNSS Signals Acquisition Architectures, IEEE Transactions on Aerospace and Electronic Systems, 20113. Yuheng Yang, A Novel VLSI Architecture for Multi-Constellation and Multi-Frequency GNSS Acquisition Engine, IEEE Access, vol. 7, pp. 655-665, 2019.4. Steven Jasper, Method of Doppler Searching in a digital GPSReceiver, 1987, US Patent 47019345. Rafiullah Khan, Acquisition Strategies of GNSS Receiver,International Conference on Computer Networks and Information Technology, 20246. Pieter Cardoen, Design of a hardware accelerated GPSreceiver, Master’s thesis, Faculty of Engineering and Architecture, University of Gent, 20117. Sascha M. Spangenberg, An FFT-Based Approach for FastAcquisition in Spread Spectrum Communication Systems, Wireless Personal Communications 13, 2000.8. Heinz Mathis, An Analytic Way to Optimize the Detector of aPost-Correlation FFT Acquisition Algorithm, 16th International Technical Meeting of the Satellite Division of The Institute of Navigation, 2003.9. Qualinx Patent Application, Direct digital synthesis ofmultiple sinusoidal waveforms.

Claims

CLAIMS 1. A method for estimating a frequency of a complexinput signal (^^^) comprising the steps of:- generating a multi-frequency complex reference signal byat least one frequency generator module (2); -multiplying said multi-frequency complex reference signalwith the input signal (^^^);- accumulating a product of said multiplication in a firstprogrammable memory (7.1) using at least two accumulate- and-dump filters (4,5); and- estimating the frequency of the complex input signal byestimating a max value of said accumulated product, whereinsaid maximum value corresponds to the frequency of thecomplex input signal,characterized in that the method comprises the step ofconfiguring the at least two accumulate-and-dump filters (4,5) to share a same memory word per frequency by storing accumulated signals corresponding to said frequency in a same address of said first programmable memory (7.1).

2. The method according to the preamble of claim 1 oraccording to claim 1, characterized in that the method comprisesthe step of using a single complex multiplier module (3) in atime-sharing manner for multiplying the multi-frequency complexreference signal with the complex input signal.

3. The method according to claim 1 or 2, characterizedin that the step of accumulating a product of themultiplication comprises:- providing the at least two accumulate-and-dump filters(4,5) as at least one coherent accumulate-and-dump filter (4) and at least one non-coherent accumulate-and-dump filter (5); -coherently accumulating an output signal of the complexmultiplier module (3) using at least one coherentaccumulate-and-dump filter (4); and- non-coherently accumulating an output signal of the atleast one coherent accumulate-and-dump filter (4) using atleast one non-coherent accumulate-and-dump filter (5).

4. The method according to any one of the precedingclaims, characterized in that the step of estimating thefrequency of the complex input signal by estimating a max valueof said accumulated product comprises feeding the output signalof the non-coherent accumulate-and-dump filter (5) into a max-finder module (6).

5. The method according to any one of the precedingclaims, characterized in that the method comprises the step ofoperating the complex multiplier module (3) at a frequency equalto at least a product of multiplying a number of frequencies inthe reference signal by a sampling rate of the input signal.

6. The method according to any one of the precedingclaims, characterized in that the method comprises the step ofoperating the coherent accumulate-and-dump filter (4) and thenon-coherent accumulate-and-dump filter (5) at a frequency ofat least two times a product of multiplying the frequency of thereference signal with the frequency of the input signal.

7. The method according to any one of the precedingclaims, characterized in that the method comprises the step ofgenerating a multi-frequency complex reference signal using adirect digital synthesizer as the frequency generator module(2).

8. The method according to claim 7, characterized inthat the multi-frequency complex reference signal compriseslinearly-spaced reference frequencies.

9. The method according to claim 7 or 8, characterizedin that the method comprises the step of providing a secondprogrammable memory (7.2) and at least one source (8.1, 8.2) ofa reference frequency, characterized in that the methodcomprises the steps of: -generating an initial phase value using a first phaseaccumulator (9);- generating a discrete amount of phase increment using asecond phase accumulator (10); -generating an incremented phase value by adding thediscrete amount of phase increment to the initial phase value using a third phase accumulator (11) receivingly connected to the first phase accumulator (9) and to the second phase accumulator (10).

10. The method according to claim 9, characterized inthat the method comprises the step of using no other phaseaccumulator than said first phase accumulator (9), said second phase accumulator (10), and said third phase accumulator (11) 11. A system (1) for estimating a frequency of a complexinput signal (^^^), wherein said system (1) comprises:- at least one frequency generator module (2) for generatinga multi-frequency complex reference signal;- a complex multiplier module (3) for multiplying the multi-frequency complex reference signal with the input signal;- at least two accumulate-and-dump filters (4,5) configuredto accumulate an output signal of the complex multipliermodule (3) in a first programmable memory (7.1); and- at least one max-finder module (6) configured to estimatea maximum value of an output signal of the at least twoaccumulate-and-dump filters, wherein said maximum value corresponds to the frequency of the complex input signal,characterized in that at least two accumulate-and-dump filters(4,5) are configured to share a same memory word per frequencyby storing accumulated signals corresponding to said frequency in a same address of the first programmable memory (7.1).

12. The system (1) according to claim 11 or accordingto the preamble of claim 11, characterized in that the system(1) comprises only one complex multiplier module (3) for multiplying in a time-sharing manner the multi-frequency complex reference signal with the input signal.

13. The system (1) according to claim 11 or 12,characterized in that the at least two accumulate-and-dumpfilters (4,5) comprise: -at least one coherent accumulate-and-dump filter (4)configured to accumulate an output signal of the complexmultiplier module (3);- at least one non-coherent accumulate-and-dump filter (5)configured to accumulate an output signal of the at leastone coherent accumulate-and-dump filter (4).

14. The system (1) according to any one of claims 11or 13, characterized in that the complex multiplier module (3)is configured to operate at a frequency equal to at least aproduct of multiplying a number of frequencies in the referencesignal by a sampling rate of the input signal.

15. The system (1) according to any one of claims 11or 14, characterized in that the coherent accumulate-and-dumpfilter (4) and the non-coherent accumulate-and-dump filter (5)are configure to operate at a frequency of at least two times a product of multiplying the frequency of the reference signalwith the frequency of the input signal.

16. The system (1) according to any one of claims 11or 15, characterized in that said first programmable memory(7.1) is a random access memory comprising a single port orcomprising a dual port.

17. The system (1) according to any one of claims 11or 16, characterized in that the at least one frequency generatormodule (2) is a direct digital frequency synthesizer.

18. The system (1) according to claim 17 characterizedin that the at least one frequency generator module (2)comprises: -a second programmable memory (7.2);- at least one source (8.1, 8.2) of a reference frequency;- a first phase accumulator (9) configured to generate aninitial phase value; -a second phase accumulator (10) configured to generate adiscrete amount of phase increment; and -a third phase accumulator (11) receivingly connected to thefirst phase accumulator (9) and to the second phase accumulator (10) and configured to generate an incremented phase value by adding the discrete amount of phase increment to the initial phase value.

19. The system (1) according to claim 17 or 18,characterized in that the at least one frequency generatormodule (2) comprises no other phase accumulator than said firstphase accumulator (9), said second phase accumulator (10), andsaid third phase accumulator (11).

20. The system (1) according to any one of claims 17-19, characterized in that the at least one source of referencefrequency comprises a first clock (8.1) and a second clock (8.2),wherein the second clock (8.2) is faster than the first clock(8.1).

21. The system (1) according to claim 20,characterized in that the second clock (8.2) is N times fasterthan the first clock (8.1), wherein N is a number of frequenciessynthesized by the system (1).

22. The system (1) according to any one of claims 17-21 characterized in that the first (9) and the second (10) phaseaccumulators are configured to operate at a frequency of the first clock (8.1) and the third phase accumulator (11) is configured to operate at a frequency of the second clock (8.2), wherein the frequency of the first clock (8.1) and the frequency of the second clock (8.2) are different from each other.

23. The system (1) according to any one of claims 17-22 characterized in that the at least one frequency generatormodule (2) comprises a bit-slicing module (12) for truncatingan output of the third phase accumulator (11), wherein said bit-slicing module (12) is placed between the third phaseaccumulator (11) and the input of the second programmable memory(7.2).

24. The system (1) according to any one of claims 17-23,characterized in that the at least one frequency generatormodule (2) comprises a frequency selector (13) placed betweenthe third phase accumulator (11) and the input of the secondprogrammable memory (7.2).

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