Light detection device, electronic apparatus, and control method of light detection device

Abstract

[PROBLEM] Provided are a light detection device for accurately focusing by using an event signal while imaging a stationary object, an electronic apparatus, and a control method of the light detection device. [SOLUTION] A light detection device according to one aspect disclosed herein comprises: a light reception unit that photoelectrically converts incident light to generate an electric signal; a conversion circuit that converts the electric signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; a second buffer circuit that outputs a second detection signal corresponding to an arbitrary first pseudo signal that does not depend on the voltage signal; and a subtractor that outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal, and outputs a second output signal when the first or second detection signal is below a second threshold voltage lower than the first or second detection signal.

Description

Optical Detection Device, Electronic Device, and Control Method for Optical Detection Device

[0001] The present disclosure relates to an optical detection device, an electronic device, and a control method for an optical detection device.

[0002] An optical detection device that detects an event signal in real time when the light amount of a pixel exceeds a threshold has been developed. Such an optical detection device that detects an event signal is called an EVS (Event Vision Sensor). The EVS is a sensor that detects a change in the luminance of a pixel and outputs the changed data in combination with information on coordinates and time.

[0003] Japanese Patent No. 7141440

[0004] However, in the EVS, when photographing a stationary object, no event signal is output, so it is difficult to know the situation within the angle of view. Therefore, in the EVS, when focusing, it is necessary to adjust the focus while photographing a moving object. In this case, there is a problem that the focusing accuracy deteriorates.

[0005] The present technology has been made in view of such problems, and provides an optical detection device, an electronic device, and a control method for an optical detection device that can accurately focus using an event signal while photographing a stationary object.

[0006] The optical detection device according to one aspect of the present disclosure includes a light receiving unit that photoelectrically converts incident light to generate an electrical signal, a conversion circuit that converts the electrical signal into a voltage signal, a first buffer circuit that outputs a first detection signal corresponding to the voltage signal, a second buffer circuit that outputs a second detection signal corresponding to an arbitrary first pseudo signal that does not depend on the voltage signal, and a subtractor that outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal and outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

[0007] When the first buffer circuit outputs the first detection signal, the second buffer circuit does not output the second detection signal, and when the second buffer circuit outputs the second detection signal, the first buffer circuit does not output the first detection signal.

[0008] The subtractor includes a first comparator that outputs a first output signal and a second comparator that outputs a second output signal. The photodetector further includes a first capacitive element provided between the outputs of the first and second buffer circuits and one input terminal of the first comparator, and a second capacitive element provided between the outputs of the first and second buffer circuits and one input terminal of the second comparator. A first threshold voltage is applied to the other input terminal of the first comparator, and a second threshold voltage is applied to the other input terminal of the second comparator.

[0009] The photodetector further includes a current source that supplies a constant current to first and second buffer circuits. The first buffer circuit includes a first transistor that receives a voltage signal at its gate and has one end connected to a first voltage source, and a second transistor that receives a first selection signal at its gate, has one end connected to the other end of the first transistor, and the other end connected to an output node. The second buffer circuit includes a third transistor that receives a first pseudo-signal at its gate and has one end connected to a first voltage source, and a fourth transistor that receives a second selection signal at its gate, has one end connected to the other end of the third transistor, and the other end connected to an output node. The current source is connected to the output node.

[0010] The voltage of the first pseudo-signal is constant.

[0011] The voltage of the first pseudo-signal changes in steps.

[0012] The voltage of the first pseudo-signal changes to cross the voltage signal.

[0013] The voltage of the first pseudo-signal changes approximately linearly.

[0014] During testing, the second buffer circuit outputs the second detection signal to the subtractor.

[0015] The photodetector further includes a third buffer circuit that outputs a third detection signal corresponding to an arbitrary second pseudo-signal that is independent of the voltage signal, and the subtractor outputs a first output signal when one of the first to third detection signals selected exceeds a first threshold voltage, and outputs a second output signal when one of the first to third detection signals selected falls below a second threshold voltage.

[0016] When the first buffer circuit outputs the first detection signal, the second and third buffer circuits do not output the second and third detection signals; when the second buffer circuit outputs the second detection signal, the first and third buffer circuits do not output the first and third detection signals; and when the third buffer circuit outputs the third detection signal, the first and second buffer circuits do not output the first and third detection signals.

[0017] The subtractor includes a first comparator that outputs a first output signal and a second comparator that outputs a second output signal. The photodetector further includes a first capacitive element provided between the outputs of the first to third buffer circuits and one input terminal of the first comparator, and a second capacitive element provided between the outputs of the first to third buffer circuits and one input terminal of the second comparator. A first threshold voltage is applied to the other input terminal of the first comparator, and a second threshold voltage is applied to the other input terminal of the second comparator.

[0018] The photodetector further includes a current source that supplies a constant current to the first to third buffer circuits. The first buffer circuit includes a first transistor that receives a voltage signal at its gate and has one end connected to the first voltage source, and a second transistor that receives a first selection signal at its gate, has one end connected to the other end of the first transistor, and the other end connected to the output node. The second buffer circuit includes a third transistor that receives a first pseudo-signal at its gate and has one end connected to the first voltage source, and a fourth transistor that receives a second selection signal at its gate, has one end connected to the other end of the third transistor, and the other end connected to the output node. The third buffer circuit includes a fifth transistor that receives a second pseudo-signal at its gate and has one end connected to the first voltage source, and a sixth transistor that receives a third selection signal at its gate, has one end connected to the other end of the fifth transistor, and the other end connected to the output node. The current source is connected to the output node.

[0019] During testing, the second and third buffer circuits alternately output the second and third detection signals to the subtractor.

[0020] One aspect of the present disclosure is an electronic device comprising: a photodetector that generates an electrical signal by photoelectric conversion of incident light; a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; a second buffer circuit that outputs a second detection signal corresponding to an arbitrary first pseudo-signal that is independent of the voltage signal; and a subtractor that outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal, and outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

[0021] When the first buffer circuit outputs the first detection signal, the second buffer circuit does not output the second detection signal, and when the second buffer circuit outputs the second detection signal, the first buffer circuit does not output the first detection signal.

[0022] The subtractor includes a first comparator that outputs a first output signal and a second comparator that outputs a second output signal. The electronic device further includes a first capacitive element provided between the outputs of the first and second buffer circuits and one input terminal of the first comparator, and a second capacitive element provided between the outputs of the first and second buffer circuits and one input terminal of the second comparator. A first threshold voltage is applied to the other input terminal of the first comparator, and a second threshold voltage is applied to the other input terminal of the second comparator.

[0023] A control method for a photodetector, one aspect of the present disclosure, comprises a light receiving unit that converts incident light into an electrical signal, a conversion circuit that converts the electrical signal into a voltage signal, a first buffer circuit, a second buffer circuit, a first comparator, and a second comparator, wherein the first buffer circuit outputs a first detection signal corresponding to the voltage signal, or the second buffer circuit outputs a second detection signal corresponding to an arbitrary first pseudo-signal that does not depend on the voltage signal, a first output signal is output when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal, and a second output signal is output when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

[0024] A block diagram showing an example configuration of a light detection device according to the first embodiment. A diagram showing an example of the stacked structure of a solid-state image sensor according to the first embodiment. An example of a plan view of a light-receiving chip. An example of a plan view of a pixel array. An example of a plan view of a detection chip. An example of a plan view of a detection unit. A block diagram showing an example of the configuration of an event detection circuit. A circuit diagram showing an example of the configuration of an event detection circuit. A timing diagram showing an example of the operation of an event detection circuit according to the first embodiment. A timing diagram showing an example of the operation of an event detection circuit according to the second embodiment. A timing diagram showing an example of the operation of an event detection circuit according to the third embodiment. A circuit diagram showing an example of the configuration of an event detection circuit according to the fourth embodiment. A timing diagram showing an example of the operation of an event detection circuit according to the fourth embodiment. A diagram showing an example of the configuration of a comparator. A diagram showing an example of the configuration of a subtractor. A block diagram showing an example of the schematic configuration of a vehicle control system. An explanatory diagram showing an example of the installation position of the external information detection unit and the imaging unit.

[0025] The following describes specific embodiments of this technology with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0026] (First Embodiment) Figure 1 is a block diagram showing an example configuration of a light detection device 1 according to the first embodiment. The light detection device 1 is, for example, an EVS or DVS (Dynamic Vision Sensor). The light detection device 1 comprises an imaging lens 10, a solid-state image sensor 20, a recording area 30, and a control unit 40. Examples of the light detection device 1 include electronic devices such as cameras mounted on industrial robots, in-vehicle cameras, and surveillance cameras.

[0027] The imaging lens 10 focuses the incident light and guides it to the solid-state image sensor 20. The solid-state image sensor 20 converts the incident light into electricity to generate a voltage signal corresponding to the amount of light received, and also detects changes in the amount of light received as an event signal based on the change in the voltage signal. The detected event signal is output to the recording area 30.

[0028] The recording area 30 records event signals from the solid-state image sensor 20. The recording area 30 may be, for example, a latch circuit, a DRAM (Dynamic Random Access Memory), or a semiconductor memory such as flash memory. The internal configuration of the recording area 30 will be described in more detail later.

[0029] The control unit 40 is configured with a microcomputer equipped with, for example, a CPU (Central Processing Unit), ROM (Read Only Memory), RAM, etc., and controls the operation of the light detection device 1 by having the CPU execute processing according to the program. In particular, the control unit 40 controls the solid-state image sensor 20 to perform the event signal detection operation described above, controls the recording area 30 to record the event signal, and executes processing to read the event signal from the recording area 30.

[0030] Figure 2 shows an example of a stacked structure of a solid-state image sensor 20 according to the first embodiment. The solid-state image sensor 20 comprises a detection chip 202 and a light-receiving chip 201 stacked on the detection chip 202. In such a stacked structure, the light-receiving chip 201 and the detection chip 202 are electrically connected via connection parts such as vias. In addition to vias, connections can also be made by Cu-Cu junctions or bumps.

[0031] Figure 3 is an example of a plan view of the light-receiving chip 201. The light-receiving chip 201 is provided with a pixel array section 220 and via arrangement sections 211, 212, and 213. Vias connected to the detection chip 202 are arranged in the via arrangement sections 211, 212, and 213.

[0032] Figure 4 is an example of a plan view of the pixel array section 220. The pixel array section 220 has a plurality of light-receiving sections 221 arranged in a two-dimensional grid. The light-receiving sections 221 are, for example, photodiodes. The light-receiving sections 221 convert incident light into photoelectric current. Each light-receiving section 221 is assigned a pixel address consisting of a row address and a column address.

[0033] Figure 5 is an example of a plan view of the detection chip 202. The detection chip 202 is provided with via arrangement sections 231, 232, and 233, a signal processing circuit 240, a row drive circuit 251, a column drive circuit 252, and a detection unit 260. Vias connected to the light receiving chip 201 are arranged in the via arrangement sections 231, 232, and 233.

[0034] The row drive circuit 251 selects a row address in the pixel array section 220 and outputs a photocurrent corresponding to that row address to the detection unit 260. The column drive circuit 252 selects a column address in the pixel array section 220 and outputs a photocurrent corresponding to that column address to the detection unit 260.

[0035] The detection unit 260 detects an event signal by quantizing the voltage signal obtained by logarithmically transforming the input photocurrent, and outputs the detected event signal to the signal processing circuit 240. An event indicates that the amount of change in the voltage signal obtained by logarithmically transforming the photocurrent has exceeded or fallen below a predetermined threshold. The event signal is activated (for example, raised) when an event occurs. The event signal is a signal that has been quantized (binarized) by the quantizer 340. The signal processing circuit 240 performs predetermined signal processing on the event signal output from the detection unit 260 and outputs it to the recording area 30.

[0036] Figure 6 is an example of a plan view of the detection unit 260. Multiple event detection circuits 300 are arranged in a two-dimensional grid within the detection unit 260. Each event detection circuit 300 is assigned a pixel address and connected to a light receiving unit 221 with the same address. The event detection circuit 300 quantizes the voltage signal corresponding to the photocurrent from the corresponding light receiving unit 221 and outputs it as an event signal.

[0037] Figure 7 is a block diagram showing an example of the configuration of the event detection circuit 300. The event detection circuit 300 includes a logarithmic transformation circuit 310, a buffer 320, a subtractor 330, and a quantizer 340.

[0038] The logarithmic conversion circuit 310 converts the photocurrent from the corresponding light receiving unit 221 into a voltage signal that has been logarithmically converted. The logarithmic conversion circuit 310 supplies the converted voltage signal to the buffer 320.

[0039] The buffer 320 corrects the voltage signal from the logarithmic conversion circuit 310. The buffer 320 outputs the corrected voltage signal to the subtractor 330.

[0040] The subtractor 330 compares the change amount of the input voltage signal with a predetermined threshold value (comparison reference voltage), and outputs a detection signal indicating that the threshold value has been exceeded or fallen below to the quantizer 340.

[0041] The quantizer 340 quantizes the detection signal into a digital signal and outputs it as an event signal to the signal processing circuit 240.

[0042] The control unit 40 performs operation control on the subtractor 330 and the quantizer 340, and controls the reading of the event signal.

[0043] FIG. 8 is a circuit diagram showing an example of the configuration of the event detection circuit 300. The logarithmic conversion circuit 310 includes N-type transistors 311 to 314 and a P-type transistor 315. As these transistors, for example, MOS (Metal-Oxide-Semiconductor) transistors are used.

[0044] The source of the transistor 311 is connected to the ground, and the drain of the transistor 311 is connected to the source of the transistor 313 and the gate of the N-type transistor 312. The gate of the transistor 311 is connected to the cathode of the light receiving unit 221.

[0045] The drain of the transistor 312 is connected to the source of the transistor 314, and the source of the transistor 312 is connected to the cathode of the light receiving unit 221. The gate of the transistor 312 is connected to the node between the transistor 311 and the transistor 313.

[0046] The drain of transistor 313 is connected to the gate of transistor 314 and the drain of transistor 315, and the source of transistor 313 is connected to the drain of transistor 311. The gate of transistor 313 is connected to the node between transistor 312 and transistor 314.

[0047] The drain of transistor 314 is connected to the power supply line of voltage PVDD, and the source of transistor 314 is connected to the drain of transistor 312 and the gate of transistor 313. The gate of transistor 314 is connected to node Npr between the drain of transistor 313 and the drain of transistor 315.

[0048] The drain of transistor 315 is connected to the gate of transistor 314 and the drain of transistor 313, and the source of transistor 315 is connected to the power supply line of voltage AVDD. The gate of transistor 315 receives a predetermined bias voltage Bias_pr.

[0049] P-type transistor 315 and N-type transistors 313, 311 are connected in series between the power supply line of voltage AVDD and the ground. Also, N-type transistor 314 and N-type transistor 312 are connected in series between the power supply line of voltage PVDD and the cathode of the light receiving portion 221.

[0050] N-type transistors 311 to 314 constitute a source follower circuit. By these source follower circuits, the photocurrent from the light receiving portion 221 is converted into a voltage signal Vpr that has been logarithmically converted. The voltage signal Vpr is transmitted to node Npr. Also, P-type transistor 315 supplies a constant current to N-type transistors 311, 313. Thus, the logarithmic conversion circuit 310 logarithmically converts the light intensity received by the light receiving portion 221 and converts it into the voltage signal Vpr.

[0051] Furthermore, the ground of the light-receiving chip 201 and the ground of the detection chip 202 in Figure 2 are separated from each other to prevent interference. In addition, the light-receiving chip 201 is equipped with the light-receiving unit 221 and the N-type transistors 311 to 314 of the event detection circuit 300, while the detection chip 202 may be equipped with the event detection circuit 300 composed of CMOS (Complementary MOS) circuits other than the N-type transistors 311 to 314.

[0052] The buffer 320 includes a first buffer circuit 321 and a second buffer circuit 322. The first buffer circuit 321 outputs a detection signal (first detection signal) Vsf that depends on the illuminance and changes in illuminance of the light received by the light receiving unit 221. The second buffer circuit 322 outputs a pseudo-signal that does not depend on illuminance or changes in illuminance as a detection signal (second detection signal) Vsf. The first buffer circuit 321 and the second buffer circuit 322 are driven exclusively and selectively. Therefore, if either the first buffer circuit 321 or the second buffer circuit 322 is driven, the other is stopped.

[0053] The first buffer circuit 321 includes N-type transistors 324 and 325. The drain of transistor 324 is connected to the power supply line (first voltage source) of voltage AVDD. The source of transistor 324 is connected to the drain of transistor 325. The gate of transistor 324 is connected to node Npr and receives the voltage signal Vpr. The drain of transistor 325 is connected to the source of transistor 324. The source of transistor 325 is connected to the drain of transistor 323. Also, the source of transistor 325 is connected to node Nsf between the first buffer circuit 321 and the second buffer circuit 322. The gate of transistor 325 receives the selection signal SEL_px.

[0054] The second buffer circuit 322 includes N-type transistors 326 and 327. The drain of transistor 326 is connected to the power supply line of voltage AVDD. The source of transistor 326 is connected to the drain of transistor 327. The gate of transistor 326 receives a pseudo-signal V_Lux. The drain of transistor 327 is connected to the source of transistor 326. The source of transistor 327 is connected to node Nsf. The gate of transistor 327 receives a selection signal xSEL_px. The selection signals SEL_px and xSEL_px are mutually exclusive signals; when one is selected to a high level, the other is deselected to a low level. The selection signals SEL_px and xSEL_px can be controlled by the control unit 40. The pseudo-signal V_Lux is used in place of the voltage signal Vpr and is a voltage signal that does not depend on the light received by the light receiving unit 221; it can be arbitrarily set by the control unit 40.

[0055] The drain of the N-type transistor 323 is connected to node Nsf. The source of the transistor 323 is connected to ground. The gate of the transistor 323 receives a predetermined bias voltage Bias_fo. The transistor 323 functions as a constant current source that supplies a constant current to the first and second buffer circuits 321 and 322. As a result, the first buffer circuit 321 outputs a detection signal Vsf according to the voltage signal Vpr to the subtractor 330. The second buffer circuit 322 outputs a detection signal Vsf according to the pseudo-signal V_Lux to the subtractor 330.

[0056] The subtractor 330 includes a first subtraction circuit 331 and a second subtraction circuit 332. The first subtraction circuit 331 compares the detection signal Vsf with a first threshold voltage Vth_on. When the detection signal Vsf exceeds the first threshold voltage Vth_on, the first subtraction circuit 331 raises the output signal. The second subtraction circuit 332 compares the detection signal Vsf with a second threshold voltage Vth_off. When the detection signal Vsf falls below the second threshold voltage Vth_off, the second subtraction circuit 332 lowers the output signal. The first threshold voltage Vth_on is greater than the second threshold voltage Vth_off. Therefore, when the detection signal Vsf is between the first threshold voltage Vth_on and the second threshold voltage Vth_off, the first and second subtraction circuits 331 and 332 do not change the output signals. Furthermore, the first threshold voltage Vth_on is set to a voltage that is a predetermined voltage (a predetermined percentage) higher than the detection signal Vsf when reset. The second threshold voltage Vth_off is set to a voltage that is a predetermined voltage (a predetermined percentage) lower than the detection signal Vsf when reset.

[0057] The first subtraction circuit 331 includes a capacitive element C1 and a comparator CMP1. One end of the capacitive element C1 is connected to node Nsf, and the other end is connected to the first input terminal of the comparator CMP1. That is, the capacitive element C1 is provided between the output of buffer circuits 321 and 322 and the first input terminal of the comparator CMP1. The capacitive element C1 may be, for example, a MIM (Metal-Insulator-Metal), MOM (Metal-Oxide-Metal), etc. The first input terminal of the comparator CMP1 is connected to the other end of the capacitive element C1, and the second input terminal receives the first threshold voltage Vth_on. The comparator CMP1 is capacitively connected to node Nsf via the capacitive element C1 and receives the detection signal Vsf at the first input terminal. The comparator CMP1 is powered by the voltage source of voltage DVDD and ground. The comparator CMP1 compares the detection signal Vsf with the first threshold voltage Vth_on, and raises the output signal when the detection signal Vsf exceeds the first threshold voltage Vth_on. When the detection signal Vsf exceeds the first threshold voltage Vth_on, the first subtraction circuit 331 is reset, and the first threshold voltage Vth_on is set to a voltage that is a predetermined voltage (a predetermined percentage) higher than the detection signal Vsf at that time.

[0058] The second subtraction circuit 332 includes a capacitive element C2 and a comparator CMP2. One end of the capacitive element C2 is connected to node Nsf, and the other end is connected to the third input terminal of the comparator CMP2. That is, the capacitive element C2 is provided between the output of buffer circuits 321 and 322 and the third input terminal of the comparator CMP2. The capacitive element C2 may also be, for example, a MIM or MOM. The third input terminal of the comparator CMP2 is connected to the other end of the capacitive element C2, and the fourth input terminal receives the second threshold voltage Vth_off. The comparator CMP2 is capacitively connected to node Nsf via the capacitive element C2 and receives the detection signal Vsf at the third input terminal. The comparator CMP2 is powered by the voltage source of voltage DVDD and ground. Comparator CMP2 compares the detection signal Vsf with the second threshold voltage Vth_off, and lowers the output signal when the detection signal Vsf falls below the second threshold voltage Vth_off. When the detection signal Vsf falls below the second threshold voltage Vth_off, the second subtraction circuit 332 is reset, and the second threshold voltage Vth_off is set to a voltage that is lower than the detection signal Vsf at that time by a predetermined voltage (a predetermined percentage). Comparators CMP1 and CMP2 are not shown in the diagram, but for example, they may be composed of CMOS circuits.

[0059] The quantizer 340 includes a first quantization circuit 341 and a second quantization circuit 342. The first quantization circuit 341 outputs an on-event Eon in response to the rising edge of the output signal from the first subtraction circuit 331. The second quantization circuit 342 outputs an off-event Eoff in response to the falling edge of the output signal from the second subtraction circuit 332.

[0060] The first quantization circuit 341 includes a P-type transistor 343 and an N-type transistor 344. The drain of transistor 343 is connected to the output node Non and the drain of transistor 344. The source of transistor 343 is connected to the power line of the voltage DVDD. The gate of transistor 343 receives the output signal of the first subtraction circuit 331. The drain of transistor 344 is connected to the output node Non and the drain of transistor 343. The source of transistor 344 is connected to ground. The gate of transistor 344 receives a predetermined voltage. Transistors 343 and 344 are connected in series between the power line of the voltage DVDD and ground. Transistor 344 supplies a constant current to transistor 343. As a result, when the first subtraction circuit 331 raises its output signal, the first quantization circuit 341 outputs an on-event Eon from the output node Non.

[0061] The second quantization circuit 342 includes a P-type transistor 345 and an N-type transistor 346. The drain of transistor 345 is connected to the output node Noff and the drain of transistor 346. The source of transistor 345 is connected to the power supply line of the voltage DVDD. The gate of transistor 345 receives the output signal of the second subtraction circuit 332. The drain of transistor 346 is connected to the output node Noff and the drain of transistor 345. The source of transistor 346 is connected to ground. The gate of transistor 346 receives a predetermined voltage. Transistors 345 and 346 are connected in series between the power supply line of the voltage DVDD and ground. Transistor 346 supplies a constant current to transistor 345. As a result, when the second subtraction circuit 332 lowers the output signal, the second quantization circuit 342 outputs an off-event Eoff from the output node Noff. For example, MOS transistors are used for transistors 343 to 346.

[0062] The on-event Eon and off-event Eoff are output to the signal processing circuit 240.

[0063] Next, the operation of the light detection device 1 according to this embodiment will be described. The following operations are used for focusing, evaluating the event detection circuit, or inspecting the illumination of stationary objects. When imaging a normal moving object, the selection signal SEL_px is always at a high level and in a selected state, and the first buffer circuit 321 is used. At this time, the selection signal xSEL_px is deactivated to a low level, and there is no need to use the second buffer circuit 322.

[0064] Figure 9 is a timing diagram showing an example of the operation of an event detection circuit according to the first embodiment. In this embodiment, the pseudo-signal V_Lux is constant. For example, the pseudo-signal V_Lux is set to a voltage approximately equal to the voltage signal Vpr corresponding to 100 lux. On the other hand, the light receiving unit 221 is in a dark state, and the voltage signal Vpr is constant at, for example, 10 lux. Thus, the pseudo-signal V_Lux is set to a voltage that is significantly different from the actual voltage signal Vpr.

[0065] The selection signal SEL_px is at a high level during t1-t2, t3-t4, and t5-t6, causing transistor 325 to conduct. As a result, the first buffer circuit 321 is selectively connected to node Nsf, and a detection signal Vsf corresponding to the voltage signal Vpr is output to the subtractor 330. At this time, the selection signal xSEL_px is at a low level, and transistor 327 is not conducting. Therefore, the second buffer circuit 322 is electrically isolated from node Nsf.

[0066] On the other hand, the selection signal xSEL_px is at a high level from t0 to t1, t2 to t3, and t4 to t5, causing transistor 327 to conduct. As a result, the second buffer circuit 322 is selectively connected to node Nsf, and the detection signal Vsf corresponding to the pseudo-signal V_Lux is output to the subtractor 330. At this time, the selection signal SEL_px is at a low level, and transistor 325 is not conducting. Therefore, the first buffer circuit 321 is electrically isolated from node Nsf.

[0067] In this way, the first buffer circuit 321 and the second buffer circuit 322 are exclusively and alternately connected to node Nsf, and exclusively and alternately output to the subtractor 330 a detection signal Vsf corresponding to the voltage signal Vpr and a detection signal Vsf corresponding to the pseudo signal V_Lux. Hereinafter, the detection signal Vsf corresponding to the voltage signal Vpr will also be called the first detection signal Vsf1. The detection signal Vsf corresponding to the pseudo signal V_Lux will also be called the second detection signal Vsf2.

[0068] Between t0 and t1, the second detection signal Vsf2 is output to the subtractor 330. The first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on1 and Vth_off1, respectively. Since the pseudo-signal V_Lux is a known signal that has been set in advance, the first threshold voltage Vth_on1 is set to a voltage that is a predetermined voltage (predetermined percentage) higher than the second detection signal Vsf2 corresponding to the pseudo-signal V_Lux. The second threshold voltage Vth_off1 is set to a voltage that is a predetermined voltage (predetermined percentage) lower than the second detection signal Vsf2.

[0069] At t1, a first detection signal Vsf1 corresponding to the voltage signal Vpr is output to the subtractor 330. At this time, the first detection signal Vsf1 is lower than the second threshold voltage Vth_off1, and the second subtraction circuit 332 raises the output signal. Therefore, the second quantization circuit 342 lowers the off-event Eoff. The output signal of the first subtraction circuit 331 remains unchanged at a high level, and the on-event Eon is maintained at a low level.

[0070] Immediately afterward, the output terminal and first input terminal of comparator CMP1 are short-circuited, and comparator CMP1 is reset. The output terminal and third input terminal of comparator CMP2 are short-circuited, and comparator CMP2 is reset. The first input terminal of comparator CMP1 is isolated from node Nsf by capacitive element C1. The third input terminal of comparator CMP2 is isolated from node Nsf by capacitive element C2. Therefore, the charge at node Nsf is maintained. As a result, based on the voltage signal Vpr, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on2 and Vth_off2, respectively. The first threshold voltage Vth_on2 is set to a voltage that is a predetermined voltage (predetermined percentage) higher than the first detection signal Vsf1. The second threshold voltage Vth_off2 is set to a voltage that is a predetermined voltage (predetermined percentage) lower than the first detection signal Vsf1.

[0071] At t2, a second detection signal Vsf2 corresponding to the pseudo-signal V_Lux is output to the subtractor 330. At this time, the second detection signal Vsf2 is a higher voltage than the first threshold voltage Vth_on2, and the first subtraction circuit 331 lowers the output signal. Therefore, the first quantization circuit 341 raises the on-event Eon. The output signal of the second subtraction circuit 332 remains unchanged at a low level, and the off-event Eoff is maintained at a high level.

[0072] Immediately afterward, the output terminal and first input terminal of comparator CMP1 are short-circuited, and comparator CMP1 is reset. The output terminal and third input terminal of comparator CMP2 are short-circuited, and comparator CMP2 is reset. The first input terminal of comparator CMP1 is isolated from node Nsf by capacitive element C1. The third input terminal of comparator CMP2 is isolated from node Nsf by capacitive element C2. Therefore, the charge at node Nsf is maintained. As a result, based on the pseudo-signal V_Lux, the first threshold voltage Vth_on and the second threshold voltage Vth_off are reset to Vth_on1 and Vth_off1, respectively.

[0073] Thus, in this embodiment, an off-event Eoff is output at t1, t3, and t5, and an on-event Eon is output at t2, t4, and t6. In other words, the light detection device 1 according to this embodiment enables the second buffer circuit 322 to output a second detection signal Vsf2 corresponding to the pseudo-signal V_Lux as a detection signal Vsf, so that even if the light receiving unit 221 is receiving a constant illumination from a stationary object, the pixels can repeatedly output on-event Eon and off-event Eoff according to their respective illumination levels. As a result, the light detection device 1 can accurately focus on a stationary object even when imaging it.

[0074] Furthermore, since there is no need to use modulated light which is easily affected by the characteristics of the optical system, the latency and other characteristics of the circuit itself after the output of the buffer 320 (node ​​Nsf), which is free from the influence of the optical system, can be easily and accurately evaluated. When the logic circuit including the subtractor 330 and quantizer 340 after node Nsf is placed on the detection chip 202 shown in Figure 2, the characteristics of the detection circuit can be evaluated using only the semiconductor wafer of the detection chip 202.

[0075] (Second Embodiment) Figure 10 is a timing diagram showing an example of operation of an event detection circuit according to the second embodiment. The light detection device 1 according to the second embodiment is the same as that of the first embodiment. In the second embodiment, the pseudo-signal V_Lux changes stepwise from a voltage lower than the voltage signal Vpr to a voltage higher than the voltage signal Vpr. For example, the pseudo-signal V_Lux is set to step up to voltages corresponding to 10 lux, 50 lux, 75 lux, and 100 lux, respectively. On the other hand, the voltage signal Vpr from the light receiving unit 221 is constant at a voltage corresponding to, for example, 50 lux. In this way, the pseudo-signal V_Lux is set to cross the voltage signal Vpr.

[0076] The operation of the selection signals SEL_px and xSEL_px is the same as their operation in Figure 9. Therefore, at t1-t2, t3-t4, and t5-t6, the first buffer circuit 321 outputs a first detection signal Vsf1 corresponding to the voltage signal Vpr to the subtractor 330. At t0-t1, t2-t3, and t4-t5, the second buffer circuit 322 outputs a second detection signal Vsf2 corresponding to the pseudo-signal V_Lux to the subtractor 330.

[0077] Between t0 and t1, a second detection signal Vsf2 corresponding to the pseudo-signal V_Lux is output to the subtractor 330. The first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on1, which is a voltage (predetermined percentage) higher than the second detection signal Vsf2 (for example, the voltage corresponding to 10 lux), and Vth_off1, which is a voltage (predetermined percentage) lower than the second detection signal Vsf2, respectively.

[0078] At t1, a first detection signal Vsf1 (for example, a voltage corresponding to 50 lux) corresponding to the voltage signal Vpr is output to the subtractor 330. At this time, the first detection signal Vsf1 is a voltage higher than the first threshold voltage Vth_on1, and the first subtraction circuit 331 lowers the output signal. Therefore, the first quantization circuit 341 raises the on-event Eon at t1. The output signal of the second subtraction circuit 332 remains unchanged at a low level, and the off-event Eoff is maintained at a high level.

[0079] Immediately afterward, the output terminal and the first input terminal of comparator CMP1 are short-circuited, and comparator CMP1 is reset. The output terminal and the third input terminal of comparator CMP2 are short-circuited, and comparator CMP2 is reset. As a result, based on the voltage signal Vpr, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on2 and Vth_off2, respectively. The first threshold voltage Vth_on2 is set to a voltage that is a predetermined voltage (a predetermined percentage) higher than the first detection signal Vsf1 corresponding to the voltage signal Vpr. The second threshold voltage Vth_off2 is set to a voltage that is a predetermined voltage (a predetermined percentage) lower than the first detection signal Vsf1.

[0080] Furthermore, at one of the timings t1 to t2, the pseudo-signal V_Lux is stepped up to a voltage corresponding to, for example, 10 lux to 50 lux.

[0081] At t2, a second detection signal Vsf2 corresponding to the pseudo-signal V_Lux is output to the subtractor 330. At this time, the second detection signal Vsf2 is set to a voltage corresponding to 50 lux, which is equal to the first detection signal Vsf1. Therefore, the detection signal Vsf does not cross the first and second threshold voltages Vth_on2 and Vth_off2. Consequently, no event signal is generated, and the on-event Eon and off-event Eoff remain unchanged.

[0082] At t3, a first detection signal Vsf1 corresponding to the voltage signal Vpr is output to the subtractor 330. The first detection signal Vsf1 is constant, for example, at a voltage corresponding to 50 lux. Therefore, the detection signal Vsf does not cross the first and second threshold voltages Vth_on2 and Vth_off2. Consequently, no event signal is generated, and the on-event Eon and off-event Eoff remain unchanged.

[0083] At some point between t3 and t4, the pseudo-signal V_Lux is stepped up to a voltage corresponding to, for example, 50 lux to 75 lux.

[0084] At t4, a second detection signal Vsf2 corresponding to the pseudo-signal V_Lux is output to the subtractor 330. At this time, the second detection signal Vsf2 is a voltage higher than the first threshold voltage Vth_on2 (for example, a voltage corresponding to 75 lux), and the first subtraction circuit 331 lowers the output signal. Therefore, the first quantization circuit 341 raises the on-event Eon at t4. The output signal of the second subtraction circuit 332 remains unchanged at a low level, and the off-event Eoff is maintained at a high level.

[0085] Immediately afterward, the output terminal and the first input terminal of comparator CMP1 are short-circuited, and comparator CMP1 is reset. The output terminal and the third input terminal of comparator CMP2 are short-circuited, and comparator CMP2 is reset. As a result, based on the pseudo-signal V_Lux, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on3 and Vth_off3, respectively. The first threshold voltage Vth_on3 is set to a voltage that is a predetermined voltage (predetermined percentage) higher than the second detection signal Vsf2. The second threshold voltage Vth_off2 is set to a voltage that is a predetermined voltage (predetermined percentage) lower than the second detection signal Vsf2.

[0086] At t5, a first detection signal Vsf1 corresponding to the voltage signal Vpr is output to the subtractor 330. The first detection signal Vsf1 is a voltage lower than the second threshold voltage Vth_off3 (for example, a voltage corresponding to 50 lux), and the second subtraction circuit 332 raises the output signal. Therefore, the second quantization circuit 342 lowers the off-event Eoff at t5. The output signal of the first subtraction circuit 331 remains unchanged at a high level, and the on-event Eon is maintained at a low level.

[0087] Immediately afterward, the output terminal and the first input terminal of comparator CMP1 are short-circuited, and comparator CMP1 is reset. The output terminal and the third input terminal of comparator CMP2 are short-circuited, and comparator CMP2 is reset. As a result, based on the voltage signal Vpr, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on2 and Vth_off2, respectively.

[0088] At t6, a second detection signal Vsf2 corresponding to the pseudo-signal V_Lux is output to the subtractor 330. At this time, the second detection signal Vsf2 is a voltage higher than the first threshold voltage Vth_on2 (for example, a voltage corresponding to 100 lux), and the first subtraction circuit 331 lowers the output signal. Therefore, the first quantization circuit 341 raises the on-event Eon at t6. The output signal of the second subtraction circuit 332 remains unchanged at a low level, and the off-event Eoff is maintained at a high level.

[0089] Immediately afterward, the output terminal and the first input terminal of comparator CMP1 are short-circuited, and comparator CMP1 is reset. The output terminal and the third input terminal of comparator CMP2 are short-circuited, and comparator CMP2 is reset. As a result, based on the pseudo-signal V_Lux, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on4 and Vth_off4, respectively. The first threshold voltage Vth_on4 is set to a voltage that is a predetermined voltage (predetermined percentage) higher than the second detection signal Vsf2. The second threshold voltage Vth_off4 is set to a voltage that is a predetermined voltage (predetermined percentage) lower than the second detection signal Vsf2.

[0090] Thus, even when the pseudo-signal V_Lux is changed to intersect with the voltage signal Vpr, the photodetector 1 can output the on-event Eon and the off-event Eoff. Therefore, the second embodiment can obtain the same effects as the first embodiment.

[0091] Furthermore, by varying the pseudo-signal V_Lux to intersect with the voltage signal Vpr, the actual illuminance of light from a stationary object can be estimated. For example, if the voltage signal Vpr is unknown, at t2, when the voltage signal Vpr is selectively output, neither event signal (Eon, Eoff) occurs. Therefore, it can be seen that the voltage signal Vpr is between the first threshold voltage Vth_on2 and the second threshold voltage Vth_off2. In other words, the actual illuminance of light is found to be approximately 50 lux.

[0092] The pseudo-signal V_Lux may be changed arbitrarily. For example, the pseudo-signal V_Lux may be changed over time. The pseudo-signal V_Lux may be changed each time the selection signals SEL_px and xSEL_px are switched. The pseudo-signal V_Lux may be changed so that it crosses the voltage signal Vpr from top to bottom.

[0093] (Third Embodiment) Figure 11 is a timing diagram showing an example of operation of an event detection circuit according to the third embodiment. The light detection device 1 according to the third embodiment is the same as that of the first embodiment. In the third embodiment, the pseudo-signal V_Lux changes substantially linearly from a voltage lower than the voltage signal Vpr to a voltage higher than the voltage signal Vpr. For example, the second detection signal Vsf2 corresponding to the pseudo-signal V_Lux increases linearly from a voltage corresponding to less than 10 lux to 1000 lux. On the other hand, the light receiving unit 221 is in a dark state, and the first detection signal Vsf1 corresponding to the voltage signal Vpr is constant at a voltage corresponding to, for example, 10 lux.

[0094] In the third embodiment, the selection signal SEL_px remains at a low level, and the selection signal xSEL_px remains at a high level. Therefore, the second buffer circuit 322 is continuously selected and outputs the second detection signal Vsf2 corresponding to the pseudo-signal V_Lux to the subtractor 330. The first buffer circuit 321 is in a non-selected state, and the voltage signal Vpr is not output.

[0095] Between t0 and t1, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on1, which is a voltage (a predetermined percentage) higher than the second detection signal Vsf2 (for example, the voltage corresponding to 10 lux), and Vth_off1, which is a voltage (a predetermined percentage) lower than the second detection signal Vsf2, respectively.

[0096] At t1, the second detection signal Vsf2 is at a voltage higher than the first threshold voltage Vth_on1, and the first quantization circuit 341 triggers the on-event Eon.

[0097] Immediately afterward, comparators CMP1 and CMP2 are reset. As a result, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on2 and Vth_off2, respectively, based on the pseudo-signal V_Lux. The first threshold voltage Vth_on2 is set to a voltage that is a predetermined voltage (a predetermined percentage) higher than the second detection signal Vsf2 at t1. The second threshold voltage Vth_off2 is set to a voltage that is a predetermined voltage (a predetermined percentage) lower than the second detection signal Vsf2 at t1.

[0098] At t2, the second detection signal Vsf2 is at a higher voltage than the first threshold voltage Vth_on2, and the first quantization circuit 341 triggers the on-event Eon.

[0099] Immediately afterward, comparators CMP1 and CMP2 are reset. As a result, based on the pseudo-signal V_Lux, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on3 and Vth_off3, respectively. The first threshold voltage Vth_on3 is set to a voltage that is a predetermined voltage (a predetermined percentage) higher than the second detection signal Vsf2 at t2. The second threshold voltage Vth_off2 is set to a voltage that is a predetermined voltage (a predetermined percentage) lower than the second detection signal Vsf2 at t2.

[0100] Similarly, during t3 to t8, the on-event Eon is output. Each time, based on the pseudo-signal V_Lux, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on3 to Vth_on8 and Vth_off3 to Vth_off8, respectively.

[0101] In this way, by linearly changing the pseudo-signal V_Lux, the photodetector 1 can evaluate the first threshold voltages Vth_on1 to Vth_on8 and the second threshold voltages Vth_off0 to Vth_off8 set at each of t1 to t8 (evaluation of the contrast for the threshold portion).

[0102] Furthermore, the latency and other parameters after the output of the buffer 320 (node ​​Nsf) can be easily and accurately evaluated for the first subtraction circuit 331 and the first quantization circuit 341.

[0103] (Fourth Embodiment) Figure 12 is a circuit diagram showing an example of the configuration of the event detection circuit 300 according to the fourth embodiment. In the fourth embodiment, the buffer 320 further includes a third buffer circuit 328. The third buffer circuit 328 has the same configuration as the second buffer circuit 322 and outputs a pseudo third detection signal Vsf3 that is independent of illuminance or changes in illuminance. One of the first to third buffer circuits 321, 322, and 328 is selectively driven. Therefore, when one of the first to third buffer circuits 321, 322, and 328 is driven, the other buffer circuits are stopped.

[0104] The third buffer circuit 328 includes N-type transistors 326 and 327, similar to the second buffer circuit 322. The connection relationship between transistors 326 and 327 may be the same as that of the second buffer circuit 322. The gate of transistor 326 in the second buffer circuit 322 receives the first pseudo-signal V_Lux1, and the gate of transistor 327 in the second buffer circuit 322 receives the selection signal xSEL_px1. The gate of transistor 326 in the third buffer circuit 328 receives the second pseudo-signal V_Lux2, and the gate of transistor 327 in the third buffer circuit 328 receives the selection signal xSEL_px2. The first pseudo-signal V_Lux1 and the second pseudo-signal V_Lux2 are set to different voltages.

[0105] The selection signals SEL_px, xSEL_px1, and xSEL_px2 are selectively activated to a high level, while the other two selection signals are deselected to a low level. The selection signals xSEL_px1 and xSEL_px2 can also be controlled by the control unit 40. The pseudo-signals V_Lux1 and V_Lux2 are used in place of the voltage signal Vpr and are voltage signals that do not affect the light received by the light receiving unit 221. They can be arbitrarily set by the control unit 40.

[0106] Other configurations of the fourth embodiment may be the same as the corresponding configurations of the first embodiment.

[0107] Figure 13 is a timing diagram showing an example of the operation of an event detection circuit according to the fourth embodiment. In the fourth embodiment, the pseudo-signal V_Lux1 is set to a voltage corresponding to, for example, 10 lux, which corresponds to a dark state. The pseudo-signal V_Lux2 is set to a voltage higher than the pseudo-signal V_Lux1, for example, a voltage corresponding to 100 lux.

[0108] In the fourth embodiment, the selection signal SEL_px is kept at a low level, and the selection signals xSEL_px1 and xSEL_px2 are selected alternately. In other words, in the fourth embodiment, the circuit from node Nsf onward is evaluated using the pseudo-signals V_Lux1 and V_Lux2, regardless of the actual light intensity.

[0109] Between t0 and t1, a third detection signal Vsf3 corresponding to the pseudo-signal V_Lux2 is output to the subtractor 330. The first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on1 and Vth_off1, respectively. The first threshold voltage Vth_on1 is set to a voltage that is a predetermined voltage (predetermined percentage) higher than the third detection signal Vsf3 corresponding to the pseudo-signal V_Lux2. The second threshold voltage Vth_off1 is set to a voltage that is a predetermined voltage (predetermined percentage) lower than the third detection signal Vsf3.

[0110] At t1, a second detection signal Vsf2 corresponding to the pseudo-signal V_Lux1 is output to the subtractor 330. At this time, the second detection signal Vsf2 is lower than the second threshold voltage Vth_off1, and the second subtraction circuit 332 raises the output signal. Therefore, the second quantization circuit 342 lowers the off-event Eoff.

[0111] Immediately afterward, comparators CMP1 and CMP2 are reset. As a result, based on the pseudo-signal V_Lux1, the first threshold voltage Vth_on and the second threshold voltage Vth_off are set to Vth_on2 and Vth_off2, respectively. The first threshold voltage Vth_on2 is set to a voltage that is a predetermined voltage (a predetermined percentage) higher than the second detection signal Vsf2. The second threshold voltage Vth_off2 is set to a voltage that is a predetermined voltage (a predetermined percentage) lower than the second detection signal Vsf2.

[0112] At t2, a third detection signal Vsf3 corresponding to the pseudo-signal V_Lux2 is output to the subtractor 330. At this time, the third detection signal Vsf3 is a voltage higher than the first threshold voltage Vth_on2, and the first subtraction circuit 331 lowers the output signal. Therefore, the first quantization circuit 341 raises the on-event Eon.

[0113] Immediately afterward, comparators CMP1 and CMP2 are reset. As a result, the first threshold voltage Vth_on and the second threshold voltage Vth_off are reset to Vth_on1 and Vth_off1, respectively, based on the pseudo-signal V_Lux2.

[0114] Thus, in this embodiment, an off-event Eoff is output at t1, t3, and t5, and an on-event Eon is output at t2, t4, and t6. That is, the light detection device 1 according to the fourth embodiment can repeatedly output on-event Eon and off-event Eoff by enabling the output of second and third detection signals Vsf2 and Vsf3 corresponding to pseudo signals V_Lux1 and V_Lux2, regardless of the actual illuminance at the light receiving unit 221. Therefore, the latency and other aspects of the circuit itself after the output of the buffer 320 (node ​​Nsf), with the influence of the optical system removed, can be evaluated easily and accurately.

[0115] Furthermore, by also using the first detection signal Vsf1, the fourth embodiment can achieve the same effects as the first embodiment.

[0116] (Modification) When multiple buffer circuits 321 and 322 simultaneously apply voltage to node Nsf, the higher of the output voltages of buffer circuits 321 and 322 is output as the detection signal Vsf. Therefore, for example, by simultaneously activating both the selection signals SEL_px and xSEL_px in Figure 8, buffer 320 outputs the voltage signal Vpr and the pseudo-signal V_Lux to node Nsf. In this case, the voltage signal Vpr is kept constant, and the pseudo-signal V_Lux is a ramp signal that increases linearly from a voltage lower than the voltage signal Vpr. In this case, until the pseudo-signal V_Lux exceeds the voltage signal Vpr, the detection signal Vsf is at a voltage corresponding to the voltage signal Vpr. After the pseudo-signal V_Lux exceeds the voltage signal Vpr, the detection signal Vsf increases linearly according to the pseudo-signal V_Lux. When the detection signal Vsf exceeds the first threshold voltage Vth_on, the on-event Eon is output. This allows the illuminance of the light irradiated onto the light receiving unit 221 to be measured from the time from the start of change in the pseudo-signal V_Lux (at the time of reset) to the output of the on-event Eon, and from the slope of the pseudo-signal V_Lux.

[0117] If it is not possible to select both selection signals SEL_px and xSEL_px simultaneously, illuminance can still be measured by performing an exclusive selection of SEL_px and xSEL_px at a high frequency.

[0118] Figure 14 shows example configurations of comparators CMP1 and CMP2. Comparators CMP1 and CMP2 have the same configuration. Therefore, only the configuration of comparator CMP1 will be described here.

[0119] The comparator CMP1 includes a P-type transistor 334 and N-type transistors 335-337. The source of transistor 334 is connected to the power line of the voltage DVDD. The drain of transistor 334 is connected to the drain of transistor 335 and to the quantizer 341 as the output terminal of CMP1. The gate of transistor 334 is connected to the capacitive element C1 as the first input terminal.

[0120] The source of transistor 335 is connected to ground. The drain of transistor 335 is connected to the drain of transistor 334 and the output terminal of CMP1. The gate of transistor 335 receives either a first threshold voltage Vth_on or a reset voltage VAZ. During the reset operation, transistor 335 becomes conductive upon receiving VAZ.

[0121] Transistors 336 and 337 are connected in series between the first input terminal and the output terminal. The gate of transistor 336 receives a reset signal AZSW. The gate of transistor 337 receives a predetermined reference voltage Refr.

[0122] Transistors 335 and 336 become conductive during the reset operation, short-circuiting the first input terminal and output terminal to ground via transistor 337, thereby resetting the comparator CMP1. Transistor 336 remains non-conductive during normal operation, test operation, etc., other than the reset operation.

[0123] Comparator CMP2 has the same configuration as comparator CMP1. The gate of transistor 334 of comparator CMP2 is connected to capacitive element C2 as the third input terminal. The gate of transistor 335 of comparator CMP2 receives the second threshold voltage Vth_off or the reset voltage VAZ.

[0124] Figure 15 shows another example of the configuration of the subtractor 330. The subtractor 330 is composed of one comparator. The subtractor 330 comprises P-type transistors 334 and 336, an N-type transistor 335, and capacitive elements C1 and C2.

[0125] The source of transistor 334 is connected to the power line of the voltage DVD. The drain of transistor 334 is connected to the drain of transistor 335 and to the output terminal of subtractor 330, which is connected to quantizer 341. The gate of transistor 334 is connected to capacitive element C1.

[0126] The source of transistor 335 is connected to ground. The drain of transistor 335 is connected to the drain of transistor 334 and the output terminal of subtractor 330. The gate of transistor 335 receives a threshold voltage Vth_on, Vth_off, or reset voltage VAZ.

[0127] Transistor 336 is connected between the gate and output terminal of transistor 334. The gate of transistor 336 receives the reset signal AZSW.

[0128] One end of the capacitive element C1 is connected to node Nsf, and the other end is connected to the gate of transistor 334. One end of the capacitive element C2 is connected to the gate of transistor 334, and the other end is connected to the output terminal.

[0129] Transistors 334 and 335 operate in the same manner as transistors 334 and 335 in Figure 14. However, when an on-event is detected, transistor 335 receives a first threshold voltage Vth_on at its gate. When an off-event is detected, transistor 335 receives a second threshold voltage Vth_off at its gate. When a reset occurs, transistor 335 receives a reset voltage VAZ at its gate.

[0130] Transistors 335 and 336 become conductive during the reset operation, short-circuiting the gate and output terminal of transistor 334 to ground and resetting comparator CMP1. Transistor 336 remains non-conductive during normal operation, test operation, etc., other than the reset operation.

[0131] The capacitance ratio (gain) between capacitive element C1 and capacitive element C2 sets the output voltage based on the voltage signal Vsf. In the reset operation, both ends of capacitive element C2 are short-circuited via transistor 336 and connected to ground via transistor 335. This returns capacitive element C2 to its state before the detection of the event signal. Since the gate of transistor 334 is isolated from node Nsf by capacitive element C1, the charge at node Nsf is maintained even after the reset operation. Therefore, the power signal Vsf for on-event or off-event is held at node Nsf. The subtractor 330 can set the first and second threshold voltages for the next event based on the voltage signal Vsf after the event occurred.

[0132] Thus, even if the subtractor 330 is composed of only one comparator, it can operate in the same way as comparators CMP1 and CMP2.

[0133] (Examples of application to mobile devices) The technology disclosed herein (the technology) can be applied to various electronic devices. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile device such as an automobile, electric vehicle, hybrid electric vehicle, motorcycle, bicycle, personal mobility device, airplane, drone, ship, or robot.

[0134] Figure 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technology described herein may be applied.

[0135] The vehicle control system 12000 comprises a plurality of electronic control units connected via a communication network 12001. In the example shown in Figure 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. The functional configuration of the integrated control unit 12050 is shown in the figure, which includes a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface 12053.

[0136] The drivetrain control unit 12010 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 12010 functions as a control device for a drivetrain generating device that generates driving force for the vehicle, such as an internal combustion engine or a drive motor; a drivetrain transmission mechanism that transmits driving force to the wheels; a steering mechanism that adjusts the steering angle of the vehicle; and a braking device that generates braking force for the vehicle.

[0137] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 12020 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0138] The external information detection unit 12030 detects information from outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the external information detection unit 12030. The external information detection unit 12030 causes the imaging unit 12031 to capture images of the outside of the vehicle and receives the captured images. Based on the received images, the external information detection unit 12030 may perform object detection processing such as detecting people, cars, obstacles, signs, or characters on the road surface, or distance detection processing.

[0139] The imaging unit 12031 is a light sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0140] The in-vehicle information detection unit 12040 detects information inside the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver status detection unit 12041 that detects the driver's state. The driver status detection unit 12041 includes, for example, a camera that captures images of the driver, and the in-vehicle information detection unit 12040 may calculate the driver's level of fatigue or concentration, or determine whether the driver is drowsy, based on the detection information input from the driver status detection unit 12041.

[0141] The microcomputer 12051 can calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on information inside and outside the vehicle acquired by the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning.

[0142] Furthermore, the microcomputer 12051 can perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on information about the vehicle's surroundings acquired by the external information detection unit 12030 or the internal information detection unit 12040.

[0143] Furthermore, the microcomputer 12051 can output control commands to the body system control unit 12020 based on external information acquired by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights according to the position of a preceding or oncoming vehicle detected by the external information detection unit 12030, and perform coordinated control aimed at reducing glare, such as switching from high beams to low beams.

[0144] The audio-image output unit 12052 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying information to the vehicle's occupants or to those outside the vehicle. In the example shown in Figure 16, the output devices include an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an onboard display and a head-up display.

[0145] Figure 17 shows an example of the installation position of the imaging unit 12031.

[0146] In Figure 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0147] The imaging units 12101, 12102, 12103, 12104, and 12105 are installed, for example, on the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the vehicle 12100. The imaging unit 12101 installed on the front nose and the imaging unit 12105 installed on the upper part of the windshield inside the vehicle mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 installed on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 installed on the upper part of the windshield inside the vehicle is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0148] Figure 17 shows an example of the imaging range of imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of imaging unit 12101 located on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of imaging units 12102 and 12103 located on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of imaging unit 12104 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 12101 to 12104, an overhead view image of the vehicle 12100 can be obtained.

[0149] At least one of the imaging units 12101 to 12104 may have a function for acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera consisting of multiple image sensors, or an image sensor having pixels for phase difference detection.

[0150] For example, the microcomputer 12051, based on distance information obtained from the imaging units 12101 to 12104, can determine the distance to each object within the imaging range 12111 to 12114 and the temporal change of this distance (relative speed to the vehicle 12100). In particular, it can extract the closest object on the vehicle 12100's path that is traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or more) as the preceding vehicle. Furthermore, the microcomputer 12051 can set a predetermined distance to be maintained before the preceding vehicle and perform automatic braking control (including follow-and-stop control) and automatic acceleration control (including follow-and-start control), etc. In this way, cooperative control aimed at autonomous driving, where the vehicle drives autonomously without driver intervention, can be performed.

[0151] For example, the microcomputer 12051 can use distance information obtained from imaging units 12101 to 12104 to classify and extract three-dimensional object data related to three-dimensional objects, such as motorcycles, passenger cars, large vehicles, pedestrians, utility poles, and other three-dimensional objects, and use this data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle. If the collision risk is above a set value and there is a possibility of collision, the microcomputer 12051 can provide driving assistance to avoid collisions by outputting a warning to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or evasive steering via the drive system control unit 12010.

[0152] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 can recognize pedestrians by determining whether or not pedestrians are present in the images captured by the imaging units 12101 to 12104. Such pedestrian recognition is performed, for example, by a procedure to extract feature points from the images captured by the imaging units 12101 to 12104 as infrared cameras, and a procedure to perform pattern matching on a series of feature points that indicate the contour of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the imaging units 12101 to 12104 and recognizes a pedestrian, the audio-image output unit 12052 controls the display unit 12062 to superimpose a rectangular contour line for emphasis on the recognized pedestrian. The audio-image output unit 12052 may also control the display unit 12062 to display an icon indicating a pedestrian at a desired position.

[0153] The above describes an example of a vehicle control system to which the technology relating to this disclosure may be applied. The technology relating to this disclosure can be applied to, for example, the imaging unit 12031 of the configuration described above.

[0154] Furthermore, this technology can be configured as follows:

[0155] (1) A photodetector comprising: a light receiving unit that converts incident light into an electrical signal; a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; a second buffer circuit that outputs a second detection signal corresponding to an arbitrary first pseudo signal independent of the voltage signal; and a subtractor that outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal, and outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

[0156] (2) The light detection device according to (1), wherein when the first buffer circuit outputs the first detection signal, the second buffer circuit does not output the second detection signal, and when the second buffer circuit outputs the second detection signal, the first buffer circuit does not output the first detection signal.

[0157] (3) The photodetector according to (1) or (2), wherein the subtractor includes a first comparator that outputs the first output signal and a second comparator that outputs the second output signal, and further comprises a first capacitive element provided between the outputs of the first and second buffer circuits and one input terminal of the first comparator, and a second capacitive element provided between the outputs of the first and second buffer circuits and one input terminal of the second comparator, the first threshold voltage is applied to the other input terminal of the first comparator, and the second threshold voltage is applied to the other input terminal of the second comparator.

[0158] (4) The photodetector according to any one of (1) to (3), further comprising a current source for supplying a constant current to the first and second buffer circuits, wherein the first buffer circuit includes a first transistor that receives the voltage signal at its gate and has one end connected to the first voltage source, and a second transistor that receives a first selection signal at its gate and has one end connected to the other end of the first transistor and the other end connected to an output node, and the second buffer circuit includes a third transistor that receives the first pseudo-signal at its gate and has one end connected to the first voltage source, and a fourth transistor that receives a second selection signal at its gate and has one end connected to the other end of the third transistor and the other end connected to an output node, and the current source is connected to the output node.

[0159] (5) The photodetector according to any one of (1) to (4), wherein the voltage of the first pseudo-signal is constant.

[0160] (6) The photodetector according to any one of (1) to (4), wherein the voltage of the first pseudo-signal changes in steps.

[0161] (7) The photodetector according to any one of (1) to (4), wherein the voltage of the first pseudo-signal changes to cross the voltage signal.

[0162] (8) The photodetector according to any one of (1) to (4), wherein the voltage of the first pseudo-signal changes substantially linearly.

[0163] (9) The light detection device according to (8), wherein in the inspection, the second buffer circuit outputs the second detection signal to the subtractor.

[0164] (10) The photodetector according to (1), further comprising a third buffer circuit that outputs a third detection signal corresponding to an arbitrary second pseudo signal independent of the voltage signal, wherein the subtractor outputs a first output signal when one of the first to third detection signals selected exceeds the first threshold voltage, and outputs a second output signal when one of the first to third detection signals selected falls below the second threshold voltage.

[0165] (11) The photodetector according to (10), wherein when the first buffer circuit outputs the first detection signal, the second and third buffer circuits do not output the second and third detection signals; when the second buffer circuit outputs the second detection signal, the first and third buffer circuits do not output the first and third detection signals; and when the third buffer circuit outputs the third detection signal, the first and second buffer circuits do not output the first and third detection signals.

[0166] (12) The photodetector according to (10) or (11), wherein the subtractor includes a first comparator that outputs the first output signal and a second comparator that outputs the second output signal, and further comprises a first capacitance element provided between the outputs of the first to third buffer circuits and one input terminal of the first comparator, and a second capacitance element provided between the outputs of the first to third buffer circuits and one input terminal of the second comparator, wherein the first threshold voltage is applied to the other input terminal of the first comparator and the second threshold voltage is applied to the other input terminal of the second comparator.

[0167] (13) The photodetector according to any one of (10) to (12), further comprising a current source for supplying a constant current to the first to third buffer circuits, wherein the first buffer circuit includes a first transistor that receives the voltage signal at its gate and has one end connected to the first voltage source, and a second transistor that receives a first selection signal at its gate and has one end connected to the other end of the first transistor and the other end connected to an output node, wherein the second buffer circuit includes a third transistor that receives the first pseudo-signal at its gate and has one end connected to the first voltage source, and a fourth transistor that receives a second selection signal at its gate and has one end connected to the other end of the third transistor and the other end connected to an output node, wherein the third buffer circuit includes a fifth transistor that receives the second pseudo-signal at its gate and has one end connected to the first voltage source, and a sixth transistor that receives a third selection signal at its gate and has one end connected to the other end of the fifth transistor and the other end connected to an output node, and the current source is connected to the output node.

[0168] (14) The photodetector according to any one of (10) to (13), wherein, in the inspection, the second and third buffer circuits alternately output the second and third detection signals to the subtractor.

[0169] (15) An electronic device comprising a photodetector, which includes: a light receiving unit that converts incident light into an electrical signal by photoelectric conversion; a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; a second buffer circuit that outputs a second detection signal corresponding to an arbitrary first pseudo signal that does not depend on the voltage signal; and a subtractor that outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal, and outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

[0170] (16) The electronic device according to (15), wherein when the first buffer circuit outputs the first detection signal, the second buffer circuit does not output the second detection signal, and when the second buffer circuit outputs the second detection signal, the first buffer circuit does not output the first detection signal.

[0171] (17) The electronic device according to (15) or (16), wherein the subtractor includes a first comparator that outputs the first output signal and a second comparator that outputs the second output signal, and further comprises a first capacitance element provided between the outputs of the first and second buffer circuits and one input terminal of the first comparator, and a second capacitance element provided between the outputs of the first and second buffer circuits and one input terminal of the second comparator, wherein the first threshold voltage is applied to the other input terminal of the first comparator and the second threshold voltage is applied to the other input terminal of the second comparator.

[0172] (18) A control method for a photodetector comprising: a light receiving unit that converts incident light into an electrical signal; a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit; a second buffer circuit; a first comparator; and a second comparator, wherein the first buffer circuit outputs a first detection signal corresponding to the voltage signal, or the second buffer circuit outputs a second detection signal corresponding to an arbitrary first pseudo-signal that does not depend on the voltage signal; a first output signal is output when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal; and a second output signal is output when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

[0173] Furthermore, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the gist of this disclosure. Also, the effects described herein are merely illustrative and not limiting, and other effects may exist.

[0174] 300 Event detection circuit 310 Logarithmic transformation circuit 320 Buffer 321 First buffer circuit 322 Second buffer circuit 330 Subtractor 331 First subtraction circuit 332 Second subtraction circuit 340 Quantizer 341 First quantization circuit 342 Second quantization circuit

Claims

1. A photodetector comprising: a light receiving unit that converts incident light into an electrical signal; a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; a second buffer circuit that outputs a second detection signal corresponding to an arbitrary first pseudo-signal that is independent of the voltage signal; and a subtractor that outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal, and outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

2. The photodetector according to claim 1, wherein when the first buffer circuit outputs the first detection signal, the second buffer circuit does not output the second detection signal, and when the second buffer circuit outputs the second detection signal, the first buffer circuit does not output the first detection signal.

3. The photodetector according to claim 1, wherein the subtractor includes a first comparator that outputs the first output signal and a second comparator that outputs the second output signal, and further comprises a first capacitive element provided between the outputs of the first and second buffer circuits and one input terminal of the first comparator, and a second capacitive element provided between the outputs of the first and second buffer circuits and one input terminal of the second comparator, wherein the first threshold voltage is applied to the other input terminal of the first comparator and the second threshold voltage is applied to the other input terminal of the second comparator.

4. The photodetector according to claim 1, further comprising a current source for supplying a constant current to the first and second buffer circuits, wherein the first buffer circuit includes a first transistor that receives the voltage signal at its gate and has one end connected to the first voltage source, and a second transistor that receives a first selection signal at its gate and has one end connected to the other end of the first transistor and the other end connected to an output node, and the second buffer circuit includes a third transistor that receives the first pseudo-signal at its gate and has one end connected to the first voltage source, and a fourth transistor that receives a second selection signal at its gate and has one end connected to the other end of the third transistor and the other end connected to an output node, and the current source is connected to the output node.

5. The photodetector according to claim 1, wherein the voltage of the first pseudo-signal is constant.

6. The photodetector according to claim 1, wherein the voltage of the first pseudo-signal changes in steps.

7. The photodetector according to claim 1, wherein the voltage of the first pseudo-signal changes to cross the voltage signal.

8. The photodetector according to claim 1, wherein the voltage of the first pseudo-signal changes substantially linearly.

9. The photodetector according to claim 8, wherein, in the inspection, the second buffer circuit outputs the second detection signal to the subtractor.

10. The photodetector according to claim 1, further comprising a third buffer circuit that outputs a third detection signal corresponding to an arbitrary second pseudo-signal independent of the voltage signal, wherein the subtractor outputs a first output signal when one of the first to third detection signals selected exceeds the first threshold voltage, and outputs a second output signal when one of the first to third detection signals selected falls below the second threshold voltage.

11. The photodetector according to claim 10, wherein when the first buffer circuit outputs the first detection signal, the second and third buffer circuits do not output the second and third detection signals; when the second buffer circuit outputs the second detection signal, the first and third buffer circuits do not output the first and third detection signals; and when the third buffer circuit outputs the third detection signal, the first and second buffer circuits do not output the first and third detection signals.

12. The photodetector according to claim 10, wherein the subtractor includes a first comparator that outputs the first output signal and a second comparator that outputs the second output signal, and further comprises a first capacitive element provided between the outputs of the first to third buffer circuits and one input terminal of the first comparator, and a second capacitive element provided between the outputs of the first to third buffer circuits and one input terminal of the second comparator, wherein the first threshold voltage is applied to the other input terminal of the first comparator and the second threshold voltage is applied to the other input terminal of the second comparator.

13. The photodetector according to claim 10, further comprising a current source for supplying a constant current to the first to third buffer circuits, wherein the first buffer circuit includes a first transistor that receives the voltage signal at its gate and has one end connected to the first voltage source, and a second transistor that receives the first selection signal at its gate, has one end connected to the other end of the first transistor and the other end connected to an output node, the second buffer circuit includes a third transistor that receives the first pseudo-signal at its gate and has one end connected to the first voltage source, and a fourth transistor that receives the second selection signal at its gate, has one end connected to the other end of the third transistor and the other end connected to an output node, the third buffer circuit includes a fifth transistor that receives the second pseudo-signal at its gate and has one end connected to the first voltage source, and a sixth transistor that receives the third selection signal at its gate, has one end connected to the other end of the fifth transistor and the other end connected to an output node, and the current source is connected to the output node.

14. The photodetector according to claim 10, wherein, in the inspection, the second and third buffer circuits alternately output the second and third detection signals to the subtractor.

15. An electronic device comprising a photodetector that includes: a light receiving unit that converts incident light into an electrical signal; a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit that outputs a first detection signal corresponding to the voltage signal; a second buffer circuit that outputs a second detection signal corresponding to an arbitrary first pseudo-signal that is independent of the voltage signal; and a subtractor that outputs a first output signal when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal, and outputs a second output signal when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

16. The electronic device according to claim 15, wherein when the first buffer circuit outputs the first detection signal, the second buffer circuit does not output the second detection signal, and when the second buffer circuit outputs the second detection signal, the first buffer circuit does not output the first detection signal.

17. The electronic device according to claim 15, wherein the subtractor includes a first comparator that outputs the first output signal and a second comparator that outputs the second output signal, and further comprises a first capacitance element provided between the outputs of the first and second buffer circuits and one input terminal of the first comparator, and a second capacitance element provided between the outputs of the first and second buffer circuits and one input terminal of the second comparator, wherein the first threshold voltage is applied to the other input terminal of the first comparator and the second threshold voltage is applied to the other input terminal of the second comparator.

18. A control method for a photodetector comprising: a light receiving unit that converts incident light into an electrical signal; a conversion circuit that converts the electrical signal into a voltage signal; a first buffer circuit; a second buffer circuit; and a subtractor, wherein the first buffer circuit outputs a first detection signal corresponding to the voltage signal, or the second buffer circuit outputs a second detection signal corresponding to an arbitrary first pseudo-signal independent of the voltage signal; a first output signal is output when the first or second detection signal exceeds a first threshold voltage higher than the first or second detection signal; and a second output signal is output when the first or second detection signal falls below a second threshold voltage lower than the first or second detection signal.

Images